Enum lief::assembly::arm::opcodes::Opcode

pub enum Opcode {
    PHI,
    INLINEASM,
    INLINEASM_BR,
    CFI_INSTRUCTION,
    EH_LABEL,
    GC_LABEL,
    ANNOTATION_LABEL,
    KILL,
    EXTRACT_SUBREG,
    INSERT_SUBREG,
    IMPLICIT_DEF,
    SUBREG_TO_REG,
    COPY_TO_REGCLASS,
    DBG_VALUE,
    DBG_VALUE_LIST,
    DBG_INSTR_REF,
    DBG_PHI,
    DBG_LABEL,
    REG_SEQUENCE,
    COPY,
    BUNDLE,
    LIFETIME_START,
    LIFETIME_END,
    PSEUDO_PROBE,
    ARITH_FENCE,
    STACKMAP,
    FENTRY_CALL,
    PATCHPOINT,
    LOAD_STACK_GUARD,
    PREALLOCATED_SETUP,
    PREALLOCATED_ARG,
    STATEPOINT,
    LOCAL_ESCAPE,
    FAULTING_OP,
    PATCHABLE_OP,
    PATCHABLE_FUNCTION_ENTER,
    PATCHABLE_RET,
    PATCHABLE_FUNCTION_EXIT,
    PATCHABLE_TAIL_CALL,
    PATCHABLE_EVENT_CALL,
    PATCHABLE_TYPED_EVENT_CALL,
    ICALL_BRANCH_FUNNEL,
    MEMBARRIER,
    JUMP_TABLE_DEBUG_INFO,
    CONVERGENCECTRL_ENTRY,
    CONVERGENCECTRL_ANCHOR,
    CONVERGENCECTRL_LOOP,
    CONVERGENCECTRL_GLUE,
    G_ASSERT_SEXT,
    G_ASSERT_ZEXT,
    G_ASSERT_ALIGN,
    G_ADD,
    G_SUB,
    G_MUL,
    G_SDIV,
    G_UDIV,
    G_SREM,
    G_UREM,
    G_SDIVREM,
    G_UDIVREM,
    G_AND,
    G_OR,
    G_XOR,
    G_IMPLICIT_DEF,
    G_PHI,
    G_FRAME_INDEX,
    G_GLOBAL_VALUE,
    G_PTRAUTH_GLOBAL_VALUE,
    G_CONSTANT_POOL,
    G_EXTRACT,
    G_UNMERGE_VALUES,
    G_INSERT,
    G_MERGE_VALUES,
    G_BUILD_VECTOR,
    G_BUILD_VECTOR_TRUNC,
    G_CONCAT_VECTORS,
    G_PTRTOINT,
    G_INTTOPTR,
    G_BITCAST,
    G_FREEZE,
    G_CONSTANT_FOLD_BARRIER,
    G_INTRINSIC_FPTRUNC_ROUND,
    G_INTRINSIC_TRUNC,
    G_INTRINSIC_ROUND,
    G_INTRINSIC_LRINT,
    G_INTRINSIC_LLRINT,
    G_INTRINSIC_ROUNDEVEN,
    G_READCYCLECOUNTER,
    G_READSTEADYCOUNTER,
    G_LOAD,
    G_SEXTLOAD,
    G_ZEXTLOAD,
    G_INDEXED_LOAD,
    G_INDEXED_SEXTLOAD,
    G_INDEXED_ZEXTLOAD,
    G_STORE,
    G_INDEXED_STORE,
    G_ATOMIC_CMPXCHG_WITH_SUCCESS,
    G_ATOMIC_CMPXCHG,
    G_ATOMICRMW_XCHG,
    G_ATOMICRMW_ADD,
    G_ATOMICRMW_SUB,
    G_ATOMICRMW_AND,
    G_ATOMICRMW_NAND,
    G_ATOMICRMW_OR,
    G_ATOMICRMW_XOR,
    G_ATOMICRMW_MAX,
    G_ATOMICRMW_MIN,
    G_ATOMICRMW_UMAX,
    G_ATOMICRMW_UMIN,
    G_ATOMICRMW_FADD,
    G_ATOMICRMW_FSUB,
    G_ATOMICRMW_FMAX,
    G_ATOMICRMW_FMIN,
    G_ATOMICRMW_UINC_WRAP,
    G_ATOMICRMW_UDEC_WRAP,
    G_FENCE,
    G_PREFETCH,
    G_BRCOND,
    G_BRINDIRECT,
    G_INVOKE_REGION_START,
    G_INTRINSIC,
    G_INTRINSIC_W_SIDE_EFFECTS,
    G_INTRINSIC_CONVERGENT,
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS,
    G_ANYEXT,
    G_TRUNC,
    G_CONSTANT,
    G_FCONSTANT,
    G_VASTART,
    G_VAARG,
    G_SEXT,
    G_SEXT_INREG,
    G_ZEXT,
    G_SHL,
    G_LSHR,
    G_ASHR,
    G_FSHL,
    G_FSHR,
    G_ROTR,
    G_ROTL,
    G_ICMP,
    G_FCMP,
    G_SCMP,
    G_UCMP,
    G_SELECT,
    G_UADDO,
    G_UADDE,
    G_USUBO,
    G_USUBE,
    G_SADDO,
    G_SADDE,
    G_SSUBO,
    G_SSUBE,
    G_UMULO,
    G_SMULO,
    G_UMULH,
    G_SMULH,
    G_UADDSAT,
    G_SADDSAT,
    G_USUBSAT,
    G_SSUBSAT,
    G_USHLSAT,
    G_SSHLSAT,
    G_SMULFIX,
    G_UMULFIX,
    G_SMULFIXSAT,
    G_UMULFIXSAT,
    G_SDIVFIX,
    G_UDIVFIX,
    G_SDIVFIXSAT,
    G_UDIVFIXSAT,
    G_FADD,
    G_FSUB,
    G_FMUL,
    G_FMA,
    G_FMAD,
    G_FDIV,
    G_FREM,
    G_FPOW,
    G_FPOWI,
    G_FEXP,
    G_FEXP2,
    G_FEXP10,
    G_FLOG,
    G_FLOG2,
    G_FLOG10,
    G_FLDEXP,
    G_FFREXP,
    G_FNEG,
    G_FPEXT,
    G_FPTRUNC,
    G_FPTOSI,
    G_FPTOUI,
    G_SITOFP,
    G_UITOFP,
    G_FABS,
    G_FCOPYSIGN,
    G_IS_FPCLASS,
    G_FCANONICALIZE,
    G_FMINNUM,
    G_FMAXNUM,
    G_FMINNUM_IEEE,
    G_FMAXNUM_IEEE,
    G_FMINIMUM,
    G_FMAXIMUM,
    G_GET_FPENV,
    G_SET_FPENV,
    G_RESET_FPENV,
    G_GET_FPMODE,
    G_SET_FPMODE,
    G_RESET_FPMODE,
    G_PTR_ADD,
    G_PTRMASK,
    G_SMIN,
    G_SMAX,
    G_UMIN,
    G_UMAX,
    G_ABS,
    G_LROUND,
    G_LLROUND,
    G_BR,
    G_BRJT,
    G_VSCALE,
    G_INSERT_SUBVECTOR,
    G_EXTRACT_SUBVECTOR,
    G_INSERT_VECTOR_ELT,
    G_EXTRACT_VECTOR_ELT,
    G_SHUFFLE_VECTOR,
    G_SPLAT_VECTOR,
    G_VECTOR_COMPRESS,
    G_CTTZ,
    G_CTTZ_ZERO_UNDEF,
    G_CTLZ,
    G_CTLZ_ZERO_UNDEF,
    G_CTPOP,
    G_BSWAP,
    G_BITREVERSE,
    G_FCEIL,
    G_FCOS,
    G_FSIN,
    G_FTAN,
    G_FACOS,
    G_FASIN,
    G_FATAN,
    G_FCOSH,
    G_FSINH,
    G_FTANH,
    G_FSQRT,
    G_FFLOOR,
    G_FRINT,
    G_FNEARBYINT,
    G_ADDRSPACE_CAST,
    G_BLOCK_ADDR,
    G_JUMP_TABLE,
    G_DYN_STACKALLOC,
    G_STACKSAVE,
    G_STACKRESTORE,
    G_STRICT_FADD,
    G_STRICT_FSUB,
    G_STRICT_FMUL,
    G_STRICT_FDIV,
    G_STRICT_FREM,
    G_STRICT_FMA,
    G_STRICT_FSQRT,
    G_STRICT_FLDEXP,
    G_READ_REGISTER,
    G_WRITE_REGISTER,
    G_MEMCPY,
    G_MEMCPY_INLINE,
    G_MEMMOVE,
    G_MEMSET,
    G_BZERO,
    G_TRAP,
    G_DEBUGTRAP,
    G_UBSANTRAP,
    G_VECREDUCE_SEQ_FADD,
    G_VECREDUCE_SEQ_FMUL,
    G_VECREDUCE_FADD,
    G_VECREDUCE_FMUL,
    G_VECREDUCE_FMAX,
    G_VECREDUCE_FMIN,
    G_VECREDUCE_FMAXIMUM,
    G_VECREDUCE_FMINIMUM,
    G_VECREDUCE_ADD,
    G_VECREDUCE_MUL,
    G_VECREDUCE_AND,
    G_VECREDUCE_OR,
    G_VECREDUCE_XOR,
    G_VECREDUCE_SMAX,
    G_VECREDUCE_SMIN,
    G_VECREDUCE_UMAX,
    G_VECREDUCE_UMIN,
    G_SBFX,
    G_UBFX,
    ABS,
    ADDSri,
    ADDSrr,
    ADDSrsi,
    ADDSrsr,
    ADJCALLSTACKDOWN,
    ADJCALLSTACKUP,
    ASRi,
    ASRr,
    B,
    BCCZi64,
    BCCi64,
    BLX_noip,
    BLX_pred_noip,
    BL_PUSHLR,
    BMOVPCB_CALL,
    BMOVPCRX_CALL,
    BR_JTadd,
    BR_JTm_i12,
    BR_JTm_rs,
    BR_JTr,
    BX_CALL,
    CMP_SWAP_16,
    CMP_SWAP_32,
    CMP_SWAP_64,
    CMP_SWAP_8,
    CONSTPOOL_ENTRY,
    COPY_STRUCT_BYVAL_I32,
    ITasm,
    Int_eh_sjlj_dispatchsetup,
    Int_eh_sjlj_longjmp,
    Int_eh_sjlj_setjmp,
    Int_eh_sjlj_setjmp_nofp,
    Int_eh_sjlj_setup_dispatch,
    JUMPTABLE_ADDRS,
    JUMPTABLE_INSTS,
    JUMPTABLE_TBB,
    JUMPTABLE_TBH,
    LDMIA_RET,
    LDRBT_POST,
    LDRConstPool,
    LDRHTii,
    LDRLIT_ga_abs,
    LDRLIT_ga_pcrel,
    LDRLIT_ga_pcrel_ldr,
    LDRSBTii,
    LDRSHTii,
    LDRT_POST,
    LEApcrel,
    LEApcrelJT,
    LOADDUAL,
    LSLi,
    LSLr,
    LSRi,
    LSRr,
    MEMCPY,
    MLAv5,
    MOVCCi,
    MOVCCi16,
    MOVCCi32imm,
    MOVCCr,
    MOVCCsi,
    MOVCCsr,
    MOVPCRX,
    MOVTi16_ga_pcrel,
    MOV_ga_pcrel,
    MOV_ga_pcrel_ldr,
    MOVi16_ga_pcrel,
    MOVi32imm,
    MOVsra_glue,
    MOVsrl_glue,
    MQPRCopy,
    MQQPRLoad,
    MQQPRStore,
    MQQQQPRLoad,
    MQQQQPRStore,
    MULv5,
    MVE_MEMCPYLOOPINST,
    MVE_MEMSETLOOPINST,
    MVNCCi,
    PICADD,
    PICLDR,
    PICLDRB,
    PICLDRH,
    PICLDRSB,
    PICLDRSH,
    PICSTR,
    PICSTRB,
    PICSTRH,
    PseudoARMInitUndefDPR_VFP2,
    PseudoARMInitUndefGPR,
    PseudoARMInitUndefMQPR,
    PseudoARMInitUndefSPR,
    RORi,
    RORr,
    RRX,
    RRXi,
    RSBSri,
    RSBSrsi,
    RSBSrsr,
    SEH_EpilogEnd,
    SEH_EpilogStart,
    SEH_Nop,
    SEH_Nop_Ret,
    SEH_PrologEnd,
    SEH_SaveFRegs,
    SEH_SaveLR,
    SEH_SaveRegs,
    SEH_SaveRegs_Ret,
    SEH_SaveSP,
    SEH_StackAlloc,
    SMLALv5,
    SMULLv5,
    SPACE,
    STOREDUAL,
    STRBT_POST,
    STRBi_preidx,
    STRBr_preidx,
    STRH_preidx,
    STRT_POST,
    STRi_preidx,
    STRr_preidx,
    SUBS_PC_LR,
    SUBSri,
    SUBSrr,
    SUBSrsi,
    SUBSrsr,
    SpeculationBarrierISBDSBEndBB,
    SpeculationBarrierSBEndBB,
    TAILJMPd,
    TAILJMPr,
    TAILJMPr4,
    TCRETURNdi,
    TCRETURNri,
    TCRETURNrinotr12,
    TPsoft,
    UMLALv5,
    UMULLv5,
    VLD1LNdAsm_16,
    VLD1LNdAsm_32,
    VLD1LNdAsm_8,
    VLD1LNdWB_fixed_Asm_16,
    VLD1LNdWB_fixed_Asm_32,
    VLD1LNdWB_fixed_Asm_8,
    VLD1LNdWB_register_Asm_16,
    VLD1LNdWB_register_Asm_32,
    VLD1LNdWB_register_Asm_8,
    VLD2LNdAsm_16,
    VLD2LNdAsm_32,
    VLD2LNdAsm_8,
    VLD2LNdWB_fixed_Asm_16,
    VLD2LNdWB_fixed_Asm_32,
    VLD2LNdWB_fixed_Asm_8,
    VLD2LNdWB_register_Asm_16,
    VLD2LNdWB_register_Asm_32,
    VLD2LNdWB_register_Asm_8,
    VLD2LNqAsm_16,
    VLD2LNqAsm_32,
    VLD2LNqWB_fixed_Asm_16,
    VLD2LNqWB_fixed_Asm_32,
    VLD2LNqWB_register_Asm_16,
    VLD2LNqWB_register_Asm_32,
    VLD3DUPdAsm_16,
    VLD3DUPdAsm_32,
    VLD3DUPdAsm_8,
    VLD3DUPdWB_fixed_Asm_16,
    VLD3DUPdWB_fixed_Asm_32,
    VLD3DUPdWB_fixed_Asm_8,
    VLD3DUPdWB_register_Asm_16,
    VLD3DUPdWB_register_Asm_32,
    VLD3DUPdWB_register_Asm_8,
    VLD3DUPqAsm_16,
    VLD3DUPqAsm_32,
    VLD3DUPqAsm_8,
    VLD3DUPqWB_fixed_Asm_16,
    VLD3DUPqWB_fixed_Asm_32,
    VLD3DUPqWB_fixed_Asm_8,
    VLD3DUPqWB_register_Asm_16,
    VLD3DUPqWB_register_Asm_32,
    VLD3DUPqWB_register_Asm_8,
    VLD3LNdAsm_16,
    VLD3LNdAsm_32,
    VLD3LNdAsm_8,
    VLD3LNdWB_fixed_Asm_16,
    VLD3LNdWB_fixed_Asm_32,
    VLD3LNdWB_fixed_Asm_8,
    VLD3LNdWB_register_Asm_16,
    VLD3LNdWB_register_Asm_32,
    VLD3LNdWB_register_Asm_8,
    VLD3LNqAsm_16,
    VLD3LNqAsm_32,
    VLD3LNqWB_fixed_Asm_16,
    VLD3LNqWB_fixed_Asm_32,
    VLD3LNqWB_register_Asm_16,
    VLD3LNqWB_register_Asm_32,
    VLD3dAsm_16,
    VLD3dAsm_32,
    VLD3dAsm_8,
    VLD3dWB_fixed_Asm_16,
    VLD3dWB_fixed_Asm_32,
    VLD3dWB_fixed_Asm_8,
    VLD3dWB_register_Asm_16,
    VLD3dWB_register_Asm_32,
    VLD3dWB_register_Asm_8,
    VLD3qAsm_16,
    VLD3qAsm_32,
    VLD3qAsm_8,
    VLD3qWB_fixed_Asm_16,
    VLD3qWB_fixed_Asm_32,
    VLD3qWB_fixed_Asm_8,
    VLD3qWB_register_Asm_16,
    VLD3qWB_register_Asm_32,
    VLD3qWB_register_Asm_8,
    VLD4DUPdAsm_16,
    VLD4DUPdAsm_32,
    VLD4DUPdAsm_8,
    VLD4DUPdWB_fixed_Asm_16,
    VLD4DUPdWB_fixed_Asm_32,
    VLD4DUPdWB_fixed_Asm_8,
    VLD4DUPdWB_register_Asm_16,
    VLD4DUPdWB_register_Asm_32,
    VLD4DUPdWB_register_Asm_8,
    VLD4DUPqAsm_16,
    VLD4DUPqAsm_32,
    VLD4DUPqAsm_8,
    VLD4DUPqWB_fixed_Asm_16,
    VLD4DUPqWB_fixed_Asm_32,
    VLD4DUPqWB_fixed_Asm_8,
    VLD4DUPqWB_register_Asm_16,
    VLD4DUPqWB_register_Asm_32,
    VLD4DUPqWB_register_Asm_8,
    VLD4LNdAsm_16,
    VLD4LNdAsm_32,
    VLD4LNdAsm_8,
    VLD4LNdWB_fixed_Asm_16,
    VLD4LNdWB_fixed_Asm_32,
    VLD4LNdWB_fixed_Asm_8,
    VLD4LNdWB_register_Asm_16,
    VLD4LNdWB_register_Asm_32,
    VLD4LNdWB_register_Asm_8,
    VLD4LNqAsm_16,
    VLD4LNqAsm_32,
    VLD4LNqWB_fixed_Asm_16,
    VLD4LNqWB_fixed_Asm_32,
    VLD4LNqWB_register_Asm_16,
    VLD4LNqWB_register_Asm_32,
    VLD4dAsm_16,
    VLD4dAsm_32,
    VLD4dAsm_8,
    VLD4dWB_fixed_Asm_16,
    VLD4dWB_fixed_Asm_32,
    VLD4dWB_fixed_Asm_8,
    VLD4dWB_register_Asm_16,
    VLD4dWB_register_Asm_32,
    VLD4dWB_register_Asm_8,
    VLD4qAsm_16,
    VLD4qAsm_32,
    VLD4qAsm_8,
    VLD4qWB_fixed_Asm_16,
    VLD4qWB_fixed_Asm_32,
    VLD4qWB_fixed_Asm_8,
    VLD4qWB_register_Asm_16,
    VLD4qWB_register_Asm_32,
    VLD4qWB_register_Asm_8,
    VMOVD0,
    VMOVDcc,
    VMOVHcc,
    VMOVQ0,
    VMOVScc,
    VST1LNdAsm_16,
    VST1LNdAsm_32,
    VST1LNdAsm_8,
    VST1LNdWB_fixed_Asm_16,
    VST1LNdWB_fixed_Asm_32,
    VST1LNdWB_fixed_Asm_8,
    VST1LNdWB_register_Asm_16,
    VST1LNdWB_register_Asm_32,
    VST1LNdWB_register_Asm_8,
    VST2LNdAsm_16,
    VST2LNdAsm_32,
    VST2LNdAsm_8,
    VST2LNdWB_fixed_Asm_16,
    VST2LNdWB_fixed_Asm_32,
    VST2LNdWB_fixed_Asm_8,
    VST2LNdWB_register_Asm_16,
    VST2LNdWB_register_Asm_32,
    VST2LNdWB_register_Asm_8,
    VST2LNqAsm_16,
    VST2LNqAsm_32,
    VST2LNqWB_fixed_Asm_16,
    VST2LNqWB_fixed_Asm_32,
    VST2LNqWB_register_Asm_16,
    VST2LNqWB_register_Asm_32,
    VST3LNdAsm_16,
    VST3LNdAsm_32,
    VST3LNdAsm_8,
    VST3LNdWB_fixed_Asm_16,
    VST3LNdWB_fixed_Asm_32,
    VST3LNdWB_fixed_Asm_8,
    VST3LNdWB_register_Asm_16,
    VST3LNdWB_register_Asm_32,
    VST3LNdWB_register_Asm_8,
    VST3LNqAsm_16,
    VST3LNqAsm_32,
    VST3LNqWB_fixed_Asm_16,
    VST3LNqWB_fixed_Asm_32,
    VST3LNqWB_register_Asm_16,
    VST3LNqWB_register_Asm_32,
    VST3dAsm_16,
    VST3dAsm_32,
    VST3dAsm_8,
    VST3dWB_fixed_Asm_16,
    VST3dWB_fixed_Asm_32,
    VST3dWB_fixed_Asm_8,
    VST3dWB_register_Asm_16,
    VST3dWB_register_Asm_32,
    VST3dWB_register_Asm_8,
    VST3qAsm_16,
    VST3qAsm_32,
    VST3qAsm_8,
    VST3qWB_fixed_Asm_16,
    VST3qWB_fixed_Asm_32,
    VST3qWB_fixed_Asm_8,
    VST3qWB_register_Asm_16,
    VST3qWB_register_Asm_32,
    VST3qWB_register_Asm_8,
    VST4LNdAsm_16,
    VST4LNdAsm_32,
    VST4LNdAsm_8,
    VST4LNdWB_fixed_Asm_16,
    VST4LNdWB_fixed_Asm_32,
    VST4LNdWB_fixed_Asm_8,
    VST4LNdWB_register_Asm_16,
    VST4LNdWB_register_Asm_32,
    VST4LNdWB_register_Asm_8,
    VST4LNqAsm_16,
    VST4LNqAsm_32,
    VST4LNqWB_fixed_Asm_16,
    VST4LNqWB_fixed_Asm_32,
    VST4LNqWB_register_Asm_16,
    VST4LNqWB_register_Asm_32,
    VST4dAsm_16,
    VST4dAsm_32,
    VST4dAsm_8,
    VST4dWB_fixed_Asm_16,
    VST4dWB_fixed_Asm_32,
    VST4dWB_fixed_Asm_8,
    VST4dWB_register_Asm_16,
    VST4dWB_register_Asm_32,
    VST4dWB_register_Asm_8,
    VST4qAsm_16,
    VST4qAsm_32,
    VST4qAsm_8,
    VST4qWB_fixed_Asm_16,
    VST4qWB_fixed_Asm_32,
    VST4qWB_fixed_Asm_8,
    VST4qWB_register_Asm_16,
    VST4qWB_register_Asm_32,
    VST4qWB_register_Asm_8,
    WIN__CHKSTK,
    WIN__DBZCHK,
    t2ABS,
    t2ADDSri,
    t2ADDSrr,
    t2ADDSrs,
    t2BF_LabelPseudo,
    t2BR_JT,
    t2CALL_BTI,
    t2DoLoopStart,
    t2DoLoopStartTP,
    t2LDMIA_RET,
    t2LDRB_OFFSET_imm,
    t2LDRB_POST_imm,
    t2LDRB_PRE_imm,
    t2LDRBpcrel,
    t2LDRConstPool,
    t2LDRH_OFFSET_imm,
    t2LDRH_POST_imm,
    t2LDRH_PRE_imm,
    t2LDRHpcrel,
    t2LDRLIT_ga_pcrel,
    t2LDRSB_OFFSET_imm,
    t2LDRSB_POST_imm,
    t2LDRSB_PRE_imm,
    t2LDRSBpcrel,
    t2LDRSH_OFFSET_imm,
    t2LDRSH_POST_imm,
    t2LDRSH_PRE_imm,
    t2LDRSHpcrel,
    t2LDR_POST_imm,
    t2LDR_PRE_imm,
    t2LDRpci_pic,
    t2LDRpcrel,
    t2LEApcrel,
    t2LEApcrelJT,
    t2LoopDec,
    t2LoopEnd,
    t2LoopEndDec,
    t2MOVCCasr,
    t2MOVCCi,
    t2MOVCCi16,
    t2MOVCCi32imm,
    t2MOVCClsl,
    t2MOVCClsr,
    t2MOVCCr,
    t2MOVCCror,
    t2MOVSsi,
    t2MOVSsr,
    t2MOVTi16_ga_pcrel,
    t2MOV_ga_pcrel,
    t2MOVi16_ga_pcrel,
    t2MOVi32imm,
    t2MOVsi,
    t2MOVsr,
    t2MVNCCi,
    t2RSBSri,
    t2RSBSrs,
    t2STRB_OFFSET_imm,
    t2STRB_POST_imm,
    t2STRB_PRE_imm,
    t2STRB_preidx,
    t2STRH_OFFSET_imm,
    t2STRH_POST_imm,
    t2STRH_PRE_imm,
    t2STRH_preidx,
    t2STR_POST_imm,
    t2STR_PRE_imm,
    t2STR_preidx,
    t2SUBSri,
    t2SUBSrr,
    t2SUBSrs,
    t2SpeculationBarrierISBDSBEndBB,
    t2SpeculationBarrierSBEndBB,
    t2TBB_JT,
    t2TBH_JT,
    t2WhileLoopSetup,
    t2WhileLoopStart,
    t2WhileLoopStartLR,
    t2WhileLoopStartTP,
    tADCS,
    tADDSi3,
    tADDSi8,
    tADDSrr,
    tADDframe,
    tADJCALLSTACKDOWN,
    tADJCALLSTACKUP,
    tBLXNS_CALL,
    tBLXr_noip,
    tBL_PUSHLR,
    tBRIND,
    tBR_JTr,
    tBXNS_RET,
    tBX_CALL,
    tBX_RET,
    tBX_RET_vararg,
    tBfar,
    tCMP_SWAP_16,
    tCMP_SWAP_32,
    tCMP_SWAP_8,
    tLDMIA_UPD,
    tLDRConstPool,
    tLDRLIT_ga_abs,
    tLDRLIT_ga_pcrel,
    tLDR_postidx,
    tLDRpci_pic,
    tLEApcrel,
    tLEApcrelJT,
    tLSLSri,
    tMOVCCr_pseudo,
    tMOVi32imm,
    tPOP_RET,
    tRSBS,
    tSBCS,
    tSUBSi3,
    tSUBSi8,
    tSUBSrr,
    tTAILJMPd,
    tTAILJMPdND,
    tTAILJMPr,
    tTBB_JT,
    tTBH_JT,
    tTPsoft,
    ADCri,
    ADCrr,
    ADCrsi,
    ADCrsr,
    ADDri,
    ADDrr,
    ADDrsi,
    ADDrsr,
    ADR,
    AESD,
    AESE,
    AESIMC,
    AESMC,
    ANDri,
    ANDrr,
    ANDrsi,
    ANDrsr,
    BF16VDOTI_VDOTD,
    BF16VDOTI_VDOTQ,
    BF16VDOTS_VDOTD,
    BF16VDOTS_VDOTQ,
    BF16_VCVT,
    BF16_VCVTB,
    BF16_VCVTT,
    BFC,
    BFI,
    BICri,
    BICrr,
    BICrsi,
    BICrsr,
    BKPT,
    BL,
    BLX,
    BLX_pred,
    BLXi,
    BL_pred,
    BX,
    BXJ,
    BX_RET,
    BX_pred,
    Bcc,
    CDE_CX1,
    CDE_CX1A,
    CDE_CX1D,
    CDE_CX1DA,
    CDE_CX2,
    CDE_CX2A,
    CDE_CX2D,
    CDE_CX2DA,
    CDE_CX3,
    CDE_CX3A,
    CDE_CX3D,
    CDE_CX3DA,
    CDE_VCX1A_fpdp,
    CDE_VCX1A_fpsp,
    CDE_VCX1A_vec,
    CDE_VCX1_fpdp,
    CDE_VCX1_fpsp,
    CDE_VCX1_vec,
    CDE_VCX2A_fpdp,
    CDE_VCX2A_fpsp,
    CDE_VCX2A_vec,
    CDE_VCX2_fpdp,
    CDE_VCX2_fpsp,
    CDE_VCX2_vec,
    CDE_VCX3A_fpdp,
    CDE_VCX3A_fpsp,
    CDE_VCX3A_vec,
    CDE_VCX3_fpdp,
    CDE_VCX3_fpsp,
    CDE_VCX3_vec,
    CDP,
    CDP2,
    CLREX,
    CLZ,
    CMNri,
    CMNzrr,
    CMNzrsi,
    CMNzrsr,
    CMPri,
    CMPrr,
    CMPrsi,
    CMPrsr,
    CPS1p,
    CPS2p,
    CPS3p,
    CRC32B,
    CRC32CB,
    CRC32CH,
    CRC32CW,
    CRC32H,
    CRC32W,
    DBG,
    DMB,
    DSB,
    EORri,
    EORrr,
    EORrsi,
    EORrsr,
    ERET,
    FCONSTD,
    FCONSTH,
    FCONSTS,
    FLDMXDB_UPD,
    FLDMXIA,
    FLDMXIA_UPD,
    FMSTAT,
    FSTMXDB_UPD,
    FSTMXIA,
    FSTMXIA_UPD,
    HINT,
    HLT,
    HVC,
    ISB,
    LDA,
    LDAB,
    LDAEX,
    LDAEXB,
    LDAEXD,
    LDAEXH,
    LDAH,
    LDC2L_OFFSET,
    LDC2L_OPTION,
    LDC2L_POST,
    LDC2L_PRE,
    LDC2_OFFSET,
    LDC2_OPTION,
    LDC2_POST,
    LDC2_PRE,
    LDCL_OFFSET,
    LDCL_OPTION,
    LDCL_POST,
    LDCL_PRE,
    LDC_OFFSET,
    LDC_OPTION,
    LDC_POST,
    LDC_PRE,
    LDMDA,
    LDMDA_UPD,
    LDMDB,
    LDMDB_UPD,
    LDMIA,
    LDMIA_UPD,
    LDMIB,
    LDMIB_UPD,
    LDRBT_POST_IMM,
    LDRBT_POST_REG,
    LDRB_POST_IMM,
    LDRB_POST_REG,
    LDRB_PRE_IMM,
    LDRB_PRE_REG,
    LDRBi12,
    LDRBrs,
    LDRD,
    LDRD_POST,
    LDRD_PRE,
    LDREX,
    LDREXB,
    LDREXD,
    LDREXH,
    LDRH,
    LDRHTi,
    LDRHTr,
    LDRH_POST,
    LDRH_PRE,
    LDRSB,
    LDRSBTi,
    LDRSBTr,
    LDRSB_POST,
    LDRSB_PRE,
    LDRSH,
    LDRSHTi,
    LDRSHTr,
    LDRSH_POST,
    LDRSH_PRE,
    LDRT_POST_IMM,
    LDRT_POST_REG,
    LDR_POST_IMM,
    LDR_POST_REG,
    LDR_PRE_IMM,
    LDR_PRE_REG,
    LDRcp,
    LDRi12,
    LDRrs,
    MCR,
    MCR2,
    MCRR,
    MCRR2,
    MLA,
    MLS,
    MOVPCLR,
    MOVTi16,
    MOVi,
    MOVi16,
    MOVr,
    MOVr_TC,
    MOVsi,
    MOVsr,
    MRC,
    MRC2,
    MRRC,
    MRRC2,
    MRS,
    MRSbanked,
    MRSsys,
    MSR,
    MSRbanked,
    MSRi,
    MUL,
    MVE_ASRLi,
    MVE_ASRLr,
    MVE_DLSTP_16,
    MVE_DLSTP_32,
    MVE_DLSTP_64,
    MVE_DLSTP_8,
    MVE_LCTP,
    MVE_LETP,
    MVE_LSLLi,
    MVE_LSLLr,
    MVE_LSRL,
    MVE_SQRSHR,
    MVE_SQRSHRL,
    MVE_SQSHL,
    MVE_SQSHLL,
    MVE_SRSHR,
    MVE_SRSHRL,
    MVE_UQRSHL,
    MVE_UQRSHLL,
    MVE_UQSHL,
    MVE_UQSHLL,
    MVE_URSHR,
    MVE_URSHRL,
    MVE_VABAVs16,
    MVE_VABAVs32,
    MVE_VABAVs8,
    MVE_VABAVu16,
    MVE_VABAVu32,
    MVE_VABAVu8,
    MVE_VABDf16,
    MVE_VABDf32,
    MVE_VABDs16,
    MVE_VABDs32,
    MVE_VABDs8,
    MVE_VABDu16,
    MVE_VABDu32,
    MVE_VABDu8,
    MVE_VABSf16,
    MVE_VABSf32,
    MVE_VABSs16,
    MVE_VABSs32,
    MVE_VABSs8,
    MVE_VADC,
    MVE_VADCI,
    MVE_VADDLVs32acc,
    MVE_VADDLVs32no_acc,
    MVE_VADDLVu32acc,
    MVE_VADDLVu32no_acc,
    MVE_VADDVs16acc,
    MVE_VADDVs16no_acc,
    MVE_VADDVs32acc,
    MVE_VADDVs32no_acc,
    MVE_VADDVs8acc,
    MVE_VADDVs8no_acc,
    MVE_VADDVu16acc,
    MVE_VADDVu16no_acc,
    MVE_VADDVu32acc,
    MVE_VADDVu32no_acc,
    MVE_VADDVu8acc,
    MVE_VADDVu8no_acc,
    MVE_VADD_qr_f16,
    MVE_VADD_qr_f32,
    MVE_VADD_qr_i16,
    MVE_VADD_qr_i32,
    MVE_VADD_qr_i8,
    MVE_VADDf16,
    MVE_VADDf32,
    MVE_VADDi16,
    MVE_VADDi32,
    MVE_VADDi8,
    MVE_VAND,
    MVE_VBIC,
    MVE_VBICimmi16,
    MVE_VBICimmi32,
    MVE_VBRSR16,
    MVE_VBRSR32,
    MVE_VBRSR8,
    MVE_VCADDf16,
    MVE_VCADDf32,
    MVE_VCADDi16,
    MVE_VCADDi32,
    MVE_VCADDi8,
    MVE_VCLSs16,
    MVE_VCLSs32,
    MVE_VCLSs8,
    MVE_VCLZs16,
    MVE_VCLZs32,
    MVE_VCLZs8,
    MVE_VCMLAf16,
    MVE_VCMLAf32,
    MVE_VCMPf16,
    MVE_VCMPf16r,
    MVE_VCMPf32,
    MVE_VCMPf32r,
    MVE_VCMPi16,
    MVE_VCMPi16r,
    MVE_VCMPi32,
    MVE_VCMPi32r,
    MVE_VCMPi8,
    MVE_VCMPi8r,
    MVE_VCMPs16,
    MVE_VCMPs16r,
    MVE_VCMPs32,
    MVE_VCMPs32r,
    MVE_VCMPs8,
    MVE_VCMPs8r,
    MVE_VCMPu16,
    MVE_VCMPu16r,
    MVE_VCMPu32,
    MVE_VCMPu32r,
    MVE_VCMPu8,
    MVE_VCMPu8r,
    MVE_VCMULf16,
    MVE_VCMULf32,
    MVE_VCTP16,
    MVE_VCTP32,
    MVE_VCTP64,
    MVE_VCTP8,
    MVE_VCVTf16f32bh,
    MVE_VCVTf16f32th,
    MVE_VCVTf16s16_fix,
    MVE_VCVTf16s16n,
    MVE_VCVTf16u16_fix,
    MVE_VCVTf16u16n,
    MVE_VCVTf32f16bh,
    MVE_VCVTf32f16th,
    MVE_VCVTf32s32_fix,
    MVE_VCVTf32s32n,
    MVE_VCVTf32u32_fix,
    MVE_VCVTf32u32n,
    MVE_VCVTs16f16_fix,
    MVE_VCVTs16f16a,
    MVE_VCVTs16f16m,
    MVE_VCVTs16f16n,
    MVE_VCVTs16f16p,
    MVE_VCVTs16f16z,
    MVE_VCVTs32f32_fix,
    MVE_VCVTs32f32a,
    MVE_VCVTs32f32m,
    MVE_VCVTs32f32n,
    MVE_VCVTs32f32p,
    MVE_VCVTs32f32z,
    MVE_VCVTu16f16_fix,
    MVE_VCVTu16f16a,
    MVE_VCVTu16f16m,
    MVE_VCVTu16f16n,
    MVE_VCVTu16f16p,
    MVE_VCVTu16f16z,
    MVE_VCVTu32f32_fix,
    MVE_VCVTu32f32a,
    MVE_VCVTu32f32m,
    MVE_VCVTu32f32n,
    MVE_VCVTu32f32p,
    MVE_VCVTu32f32z,
    MVE_VDDUPu16,
    MVE_VDDUPu32,
    MVE_VDDUPu8,
    MVE_VDUP16,
    MVE_VDUP32,
    MVE_VDUP8,
    MVE_VDWDUPu16,
    MVE_VDWDUPu32,
    MVE_VDWDUPu8,
    MVE_VEOR,
    MVE_VFMA_qr_Sf16,
    MVE_VFMA_qr_Sf32,
    MVE_VFMA_qr_f16,
    MVE_VFMA_qr_f32,
    MVE_VFMAf16,
    MVE_VFMAf32,
    MVE_VFMSf16,
    MVE_VFMSf32,
    MVE_VHADD_qr_s16,
    MVE_VHADD_qr_s32,
    MVE_VHADD_qr_s8,
    MVE_VHADD_qr_u16,
    MVE_VHADD_qr_u32,
    MVE_VHADD_qr_u8,
    MVE_VHADDs16,
    MVE_VHADDs32,
    MVE_VHADDs8,
    MVE_VHADDu16,
    MVE_VHADDu32,
    MVE_VHADDu8,
    MVE_VHCADDs16,
    MVE_VHCADDs32,
    MVE_VHCADDs8,
    MVE_VHSUB_qr_s16,
    MVE_VHSUB_qr_s32,
    MVE_VHSUB_qr_s8,
    MVE_VHSUB_qr_u16,
    MVE_VHSUB_qr_u32,
    MVE_VHSUB_qr_u8,
    MVE_VHSUBs16,
    MVE_VHSUBs32,
    MVE_VHSUBs8,
    MVE_VHSUBu16,
    MVE_VHSUBu32,
    MVE_VHSUBu8,
    MVE_VIDUPu16,
    MVE_VIDUPu32,
    MVE_VIDUPu8,
    MVE_VIWDUPu16,
    MVE_VIWDUPu32,
    MVE_VIWDUPu8,
    MVE_VLD20_16,
    MVE_VLD20_16_wb,
    MVE_VLD20_32,
    MVE_VLD20_32_wb,
    MVE_VLD20_8,
    MVE_VLD20_8_wb,
    MVE_VLD21_16,
    MVE_VLD21_16_wb,
    MVE_VLD21_32,
    MVE_VLD21_32_wb,
    MVE_VLD21_8,
    MVE_VLD21_8_wb,
    MVE_VLD40_16,
    MVE_VLD40_16_wb,
    MVE_VLD40_32,
    MVE_VLD40_32_wb,
    MVE_VLD40_8,
    MVE_VLD40_8_wb,
    MVE_VLD41_16,
    MVE_VLD41_16_wb,
    MVE_VLD41_32,
    MVE_VLD41_32_wb,
    MVE_VLD41_8,
    MVE_VLD41_8_wb,
    MVE_VLD42_16,
    MVE_VLD42_16_wb,
    MVE_VLD42_32,
    MVE_VLD42_32_wb,
    MVE_VLD42_8,
    MVE_VLD42_8_wb,
    MVE_VLD43_16,
    MVE_VLD43_16_wb,
    MVE_VLD43_32,
    MVE_VLD43_32_wb,
    MVE_VLD43_8,
    MVE_VLD43_8_wb,
    MVE_VLDRBS16,
    MVE_VLDRBS16_post,
    MVE_VLDRBS16_pre,
    MVE_VLDRBS16_rq,
    MVE_VLDRBS32,
    MVE_VLDRBS32_post,
    MVE_VLDRBS32_pre,
    MVE_VLDRBS32_rq,
    MVE_VLDRBU16,
    MVE_VLDRBU16_post,
    MVE_VLDRBU16_pre,
    MVE_VLDRBU16_rq,
    MVE_VLDRBU32,
    MVE_VLDRBU32_post,
    MVE_VLDRBU32_pre,
    MVE_VLDRBU32_rq,
    MVE_VLDRBU8,
    MVE_VLDRBU8_post,
    MVE_VLDRBU8_pre,
    MVE_VLDRBU8_rq,
    MVE_VLDRDU64_qi,
    MVE_VLDRDU64_qi_pre,
    MVE_VLDRDU64_rq,
    MVE_VLDRDU64_rq_u,
    MVE_VLDRHS32,
    MVE_VLDRHS32_post,
    MVE_VLDRHS32_pre,
    MVE_VLDRHS32_rq,
    MVE_VLDRHS32_rq_u,
    MVE_VLDRHU16,
    MVE_VLDRHU16_post,
    MVE_VLDRHU16_pre,
    MVE_VLDRHU16_rq,
    MVE_VLDRHU16_rq_u,
    MVE_VLDRHU32,
    MVE_VLDRHU32_post,
    MVE_VLDRHU32_pre,
    MVE_VLDRHU32_rq,
    MVE_VLDRHU32_rq_u,
    MVE_VLDRWU32,
    MVE_VLDRWU32_post,
    MVE_VLDRWU32_pre,
    MVE_VLDRWU32_qi,
    MVE_VLDRWU32_qi_pre,
    MVE_VLDRWU32_rq,
    MVE_VLDRWU32_rq_u,
    MVE_VMAXAVs16,
    MVE_VMAXAVs32,
    MVE_VMAXAVs8,
    MVE_VMAXAs16,
    MVE_VMAXAs32,
    MVE_VMAXAs8,
    MVE_VMAXNMAVf16,
    MVE_VMAXNMAVf32,
    MVE_VMAXNMAf16,
    MVE_VMAXNMAf32,
    MVE_VMAXNMVf16,
    MVE_VMAXNMVf32,
    MVE_VMAXNMf16,
    MVE_VMAXNMf32,
    MVE_VMAXVs16,
    MVE_VMAXVs32,
    MVE_VMAXVs8,
    MVE_VMAXVu16,
    MVE_VMAXVu32,
    MVE_VMAXVu8,
    MVE_VMAXs16,
    MVE_VMAXs32,
    MVE_VMAXs8,
    MVE_VMAXu16,
    MVE_VMAXu32,
    MVE_VMAXu8,
    MVE_VMINAVs16,
    MVE_VMINAVs32,
    MVE_VMINAVs8,
    MVE_VMINAs16,
    MVE_VMINAs32,
    MVE_VMINAs8,
    MVE_VMINNMAVf16,
    MVE_VMINNMAVf32,
    MVE_VMINNMAf16,
    MVE_VMINNMAf32,
    MVE_VMINNMVf16,
    MVE_VMINNMVf32,
    MVE_VMINNMf16,
    MVE_VMINNMf32,
    MVE_VMINVs16,
    MVE_VMINVs32,
    MVE_VMINVs8,
    MVE_VMINVu16,
    MVE_VMINVu32,
    MVE_VMINVu8,
    MVE_VMINs16,
    MVE_VMINs32,
    MVE_VMINs8,
    MVE_VMINu16,
    MVE_VMINu32,
    MVE_VMINu8,
    MVE_VMLADAVas16,
    MVE_VMLADAVas32,
    MVE_VMLADAVas8,
    MVE_VMLADAVau16,
    MVE_VMLADAVau32,
    MVE_VMLADAVau8,
    MVE_VMLADAVaxs16,
    MVE_VMLADAVaxs32,
    MVE_VMLADAVaxs8,
    MVE_VMLADAVs16,
    MVE_VMLADAVs32,
    MVE_VMLADAVs8,
    MVE_VMLADAVu16,
    MVE_VMLADAVu32,
    MVE_VMLADAVu8,
    MVE_VMLADAVxs16,
    MVE_VMLADAVxs32,
    MVE_VMLADAVxs8,
    MVE_VMLALDAVas16,
    MVE_VMLALDAVas32,
    MVE_VMLALDAVau16,
    MVE_VMLALDAVau32,
    MVE_VMLALDAVaxs16,
    MVE_VMLALDAVaxs32,
    MVE_VMLALDAVs16,
    MVE_VMLALDAVs32,
    MVE_VMLALDAVu16,
    MVE_VMLALDAVu32,
    MVE_VMLALDAVxs16,
    MVE_VMLALDAVxs32,
    MVE_VMLAS_qr_i16,
    MVE_VMLAS_qr_i32,
    MVE_VMLAS_qr_i8,
    MVE_VMLA_qr_i16,
    MVE_VMLA_qr_i32,
    MVE_VMLA_qr_i8,
    MVE_VMLSDAVas16,
    MVE_VMLSDAVas32,
    MVE_VMLSDAVas8,
    MVE_VMLSDAVaxs16,
    MVE_VMLSDAVaxs32,
    MVE_VMLSDAVaxs8,
    MVE_VMLSDAVs16,
    MVE_VMLSDAVs32,
    MVE_VMLSDAVs8,
    MVE_VMLSDAVxs16,
    MVE_VMLSDAVxs32,
    MVE_VMLSDAVxs8,
    MVE_VMLSLDAVas16,
    MVE_VMLSLDAVas32,
    MVE_VMLSLDAVaxs16,
    MVE_VMLSLDAVaxs32,
    MVE_VMLSLDAVs16,
    MVE_VMLSLDAVs32,
    MVE_VMLSLDAVxs16,
    MVE_VMLSLDAVxs32,
    MVE_VMOVLs16bh,
    MVE_VMOVLs16th,
    MVE_VMOVLs8bh,
    MVE_VMOVLs8th,
    MVE_VMOVLu16bh,
    MVE_VMOVLu16th,
    MVE_VMOVLu8bh,
    MVE_VMOVLu8th,
    MVE_VMOVNi16bh,
    MVE_VMOVNi16th,
    MVE_VMOVNi32bh,
    MVE_VMOVNi32th,
    MVE_VMOV_from_lane_32,
    MVE_VMOV_from_lane_s16,
    MVE_VMOV_from_lane_s8,
    MVE_VMOV_from_lane_u16,
    MVE_VMOV_from_lane_u8,
    MVE_VMOV_q_rr,
    MVE_VMOV_rr_q,
    MVE_VMOV_to_lane_16,
    MVE_VMOV_to_lane_32,
    MVE_VMOV_to_lane_8,
    MVE_VMOVimmf32,
    MVE_VMOVimmi16,
    MVE_VMOVimmi32,
    MVE_VMOVimmi64,
    MVE_VMOVimmi8,
    MVE_VMULHs16,
    MVE_VMULHs32,
    MVE_VMULHs8,
    MVE_VMULHu16,
    MVE_VMULHu32,
    MVE_VMULHu8,
    MVE_VMULLBp16,
    MVE_VMULLBp8,
    MVE_VMULLBs16,
    MVE_VMULLBs32,
    MVE_VMULLBs8,
    MVE_VMULLBu16,
    MVE_VMULLBu32,
    MVE_VMULLBu8,
    MVE_VMULLTp16,
    MVE_VMULLTp8,
    MVE_VMULLTs16,
    MVE_VMULLTs32,
    MVE_VMULLTs8,
    MVE_VMULLTu16,
    MVE_VMULLTu32,
    MVE_VMULLTu8,
    MVE_VMUL_qr_f16,
    MVE_VMUL_qr_f32,
    MVE_VMUL_qr_i16,
    MVE_VMUL_qr_i32,
    MVE_VMUL_qr_i8,
    MVE_VMULf16,
    MVE_VMULf32,
    MVE_VMULi16,
    MVE_VMULi32,
    MVE_VMULi8,
    MVE_VMVN,
    MVE_VMVNimmi16,
    MVE_VMVNimmi32,
    MVE_VNEGf16,
    MVE_VNEGf32,
    MVE_VNEGs16,
    MVE_VNEGs32,
    MVE_VNEGs8,
    MVE_VORN,
    MVE_VORR,
    MVE_VORRimmi16,
    MVE_VORRimmi32,
    MVE_VPNOT,
    MVE_VPSEL,
    MVE_VPST,
    MVE_VPTv16i8,
    MVE_VPTv16i8r,
    MVE_VPTv16s8,
    MVE_VPTv16s8r,
    MVE_VPTv16u8,
    MVE_VPTv16u8r,
    MVE_VPTv4f32,
    MVE_VPTv4f32r,
    MVE_VPTv4i32,
    MVE_VPTv4i32r,
    MVE_VPTv4s32,
    MVE_VPTv4s32r,
    MVE_VPTv4u32,
    MVE_VPTv4u32r,
    MVE_VPTv8f16,
    MVE_VPTv8f16r,
    MVE_VPTv8i16,
    MVE_VPTv8i16r,
    MVE_VPTv8s16,
    MVE_VPTv8s16r,
    MVE_VPTv8u16,
    MVE_VPTv8u16r,
    MVE_VQABSs16,
    MVE_VQABSs32,
    MVE_VQABSs8,
    MVE_VQADD_qr_s16,
    MVE_VQADD_qr_s32,
    MVE_VQADD_qr_s8,
    MVE_VQADD_qr_u16,
    MVE_VQADD_qr_u32,
    MVE_VQADD_qr_u8,
    MVE_VQADDs16,
    MVE_VQADDs32,
    MVE_VQADDs8,
    MVE_VQADDu16,
    MVE_VQADDu32,
    MVE_VQADDu8,
    MVE_VQDMLADHXs16,
    MVE_VQDMLADHXs32,
    MVE_VQDMLADHXs8,
    MVE_VQDMLADHs16,
    MVE_VQDMLADHs32,
    MVE_VQDMLADHs8,
    MVE_VQDMLAH_qrs16,
    MVE_VQDMLAH_qrs32,
    MVE_VQDMLAH_qrs8,
    MVE_VQDMLASH_qrs16,
    MVE_VQDMLASH_qrs32,
    MVE_VQDMLASH_qrs8,
    MVE_VQDMLSDHXs16,
    MVE_VQDMLSDHXs32,
    MVE_VQDMLSDHXs8,
    MVE_VQDMLSDHs16,
    MVE_VQDMLSDHs32,
    MVE_VQDMLSDHs8,
    MVE_VQDMULH_qr_s16,
    MVE_VQDMULH_qr_s32,
    MVE_VQDMULH_qr_s8,
    MVE_VQDMULHi16,
    MVE_VQDMULHi32,
    MVE_VQDMULHi8,
    MVE_VQDMULL_qr_s16bh,
    MVE_VQDMULL_qr_s16th,
    MVE_VQDMULL_qr_s32bh,
    MVE_VQDMULL_qr_s32th,
    MVE_VQDMULLs16bh,
    MVE_VQDMULLs16th,
    MVE_VQDMULLs32bh,
    MVE_VQDMULLs32th,
    MVE_VQMOVNs16bh,
    MVE_VQMOVNs16th,
    MVE_VQMOVNs32bh,
    MVE_VQMOVNs32th,
    MVE_VQMOVNu16bh,
    MVE_VQMOVNu16th,
    MVE_VQMOVNu32bh,
    MVE_VQMOVNu32th,
    MVE_VQMOVUNs16bh,
    MVE_VQMOVUNs16th,
    MVE_VQMOVUNs32bh,
    MVE_VQMOVUNs32th,
    MVE_VQNEGs16,
    MVE_VQNEGs32,
    MVE_VQNEGs8,
    MVE_VQRDMLADHXs16,
    MVE_VQRDMLADHXs32,
    MVE_VQRDMLADHXs8,
    MVE_VQRDMLADHs16,
    MVE_VQRDMLADHs32,
    MVE_VQRDMLADHs8,
    MVE_VQRDMLAH_qrs16,
    MVE_VQRDMLAH_qrs32,
    MVE_VQRDMLAH_qrs8,
    MVE_VQRDMLASH_qrs16,
    MVE_VQRDMLASH_qrs32,
    MVE_VQRDMLASH_qrs8,
    MVE_VQRDMLSDHXs16,
    MVE_VQRDMLSDHXs32,
    MVE_VQRDMLSDHXs8,
    MVE_VQRDMLSDHs16,
    MVE_VQRDMLSDHs32,
    MVE_VQRDMLSDHs8,
    MVE_VQRDMULH_qr_s16,
    MVE_VQRDMULH_qr_s32,
    MVE_VQRDMULH_qr_s8,
    MVE_VQRDMULHi16,
    MVE_VQRDMULHi32,
    MVE_VQRDMULHi8,
    MVE_VQRSHL_by_vecs16,
    MVE_VQRSHL_by_vecs32,
    MVE_VQRSHL_by_vecs8,
    MVE_VQRSHL_by_vecu16,
    MVE_VQRSHL_by_vecu32,
    MVE_VQRSHL_by_vecu8,
    MVE_VQRSHL_qrs16,
    MVE_VQRSHL_qrs32,
    MVE_VQRSHL_qrs8,
    MVE_VQRSHL_qru16,
    MVE_VQRSHL_qru32,
    MVE_VQRSHL_qru8,
    MVE_VQRSHRNbhs16,
    MVE_VQRSHRNbhs32,
    MVE_VQRSHRNbhu16,
    MVE_VQRSHRNbhu32,
    MVE_VQRSHRNths16,
    MVE_VQRSHRNths32,
    MVE_VQRSHRNthu16,
    MVE_VQRSHRNthu32,
    MVE_VQRSHRUNs16bh,
    MVE_VQRSHRUNs16th,
    MVE_VQRSHRUNs32bh,
    MVE_VQRSHRUNs32th,
    MVE_VQSHLU_imms16,
    MVE_VQSHLU_imms32,
    MVE_VQSHLU_imms8,
    MVE_VQSHL_by_vecs16,
    MVE_VQSHL_by_vecs32,
    MVE_VQSHL_by_vecs8,
    MVE_VQSHL_by_vecu16,
    MVE_VQSHL_by_vecu32,
    MVE_VQSHL_by_vecu8,
    MVE_VQSHL_qrs16,
    MVE_VQSHL_qrs32,
    MVE_VQSHL_qrs8,
    MVE_VQSHL_qru16,
    MVE_VQSHL_qru32,
    MVE_VQSHL_qru8,
    MVE_VQSHLimms16,
    MVE_VQSHLimms32,
    MVE_VQSHLimms8,
    MVE_VQSHLimmu16,
    MVE_VQSHLimmu32,
    MVE_VQSHLimmu8,
    MVE_VQSHRNbhs16,
    MVE_VQSHRNbhs32,
    MVE_VQSHRNbhu16,
    MVE_VQSHRNbhu32,
    MVE_VQSHRNths16,
    MVE_VQSHRNths32,
    MVE_VQSHRNthu16,
    MVE_VQSHRNthu32,
    MVE_VQSHRUNs16bh,
    MVE_VQSHRUNs16th,
    MVE_VQSHRUNs32bh,
    MVE_VQSHRUNs32th,
    MVE_VQSUB_qr_s16,
    MVE_VQSUB_qr_s32,
    MVE_VQSUB_qr_s8,
    MVE_VQSUB_qr_u16,
    MVE_VQSUB_qr_u32,
    MVE_VQSUB_qr_u8,
    MVE_VQSUBs16,
    MVE_VQSUBs32,
    MVE_VQSUBs8,
    MVE_VQSUBu16,
    MVE_VQSUBu32,
    MVE_VQSUBu8,
    MVE_VREV16_8,
    MVE_VREV32_16,
    MVE_VREV32_8,
    MVE_VREV64_16,
    MVE_VREV64_32,
    MVE_VREV64_8,
    MVE_VRHADDs16,
    MVE_VRHADDs32,
    MVE_VRHADDs8,
    MVE_VRHADDu16,
    MVE_VRHADDu32,
    MVE_VRHADDu8,
    MVE_VRINTf16A,
    MVE_VRINTf16M,
    MVE_VRINTf16N,
    MVE_VRINTf16P,
    MVE_VRINTf16X,
    MVE_VRINTf16Z,
    MVE_VRINTf32A,
    MVE_VRINTf32M,
    MVE_VRINTf32N,
    MVE_VRINTf32P,
    MVE_VRINTf32X,
    MVE_VRINTf32Z,
    MVE_VRMLALDAVHas32,
    MVE_VRMLALDAVHau32,
    MVE_VRMLALDAVHaxs32,
    MVE_VRMLALDAVHs32,
    MVE_VRMLALDAVHu32,
    MVE_VRMLALDAVHxs32,
    MVE_VRMLSLDAVHas32,
    MVE_VRMLSLDAVHaxs32,
    MVE_VRMLSLDAVHs32,
    MVE_VRMLSLDAVHxs32,
    MVE_VRMULHs16,
    MVE_VRMULHs32,
    MVE_VRMULHs8,
    MVE_VRMULHu16,
    MVE_VRMULHu32,
    MVE_VRMULHu8,
    MVE_VRSHL_by_vecs16,
    MVE_VRSHL_by_vecs32,
    MVE_VRSHL_by_vecs8,
    MVE_VRSHL_by_vecu16,
    MVE_VRSHL_by_vecu32,
    MVE_VRSHL_by_vecu8,
    MVE_VRSHL_qrs16,
    MVE_VRSHL_qrs32,
    MVE_VRSHL_qrs8,
    MVE_VRSHL_qru16,
    MVE_VRSHL_qru32,
    MVE_VRSHL_qru8,
    MVE_VRSHRNi16bh,
    MVE_VRSHRNi16th,
    MVE_VRSHRNi32bh,
    MVE_VRSHRNi32th,
    MVE_VRSHR_imms16,
    MVE_VRSHR_imms32,
    MVE_VRSHR_imms8,
    MVE_VRSHR_immu16,
    MVE_VRSHR_immu32,
    MVE_VRSHR_immu8,
    MVE_VSBC,
    MVE_VSBCI,
    MVE_VSHLC,
    MVE_VSHLL_imms16bh,
    MVE_VSHLL_imms16th,
    MVE_VSHLL_imms8bh,
    MVE_VSHLL_imms8th,
    MVE_VSHLL_immu16bh,
    MVE_VSHLL_immu16th,
    MVE_VSHLL_immu8bh,
    MVE_VSHLL_immu8th,
    MVE_VSHLL_lws16bh,
    MVE_VSHLL_lws16th,
    MVE_VSHLL_lws8bh,
    MVE_VSHLL_lws8th,
    MVE_VSHLL_lwu16bh,
    MVE_VSHLL_lwu16th,
    MVE_VSHLL_lwu8bh,
    MVE_VSHLL_lwu8th,
    MVE_VSHL_by_vecs16,
    MVE_VSHL_by_vecs32,
    MVE_VSHL_by_vecs8,
    MVE_VSHL_by_vecu16,
    MVE_VSHL_by_vecu32,
    MVE_VSHL_by_vecu8,
    MVE_VSHL_immi16,
    MVE_VSHL_immi32,
    MVE_VSHL_immi8,
    MVE_VSHL_qrs16,
    MVE_VSHL_qrs32,
    MVE_VSHL_qrs8,
    MVE_VSHL_qru16,
    MVE_VSHL_qru32,
    MVE_VSHL_qru8,
    MVE_VSHRNi16bh,
    MVE_VSHRNi16th,
    MVE_VSHRNi32bh,
    MVE_VSHRNi32th,
    MVE_VSHR_imms16,
    MVE_VSHR_imms32,
    MVE_VSHR_imms8,
    MVE_VSHR_immu16,
    MVE_VSHR_immu32,
    MVE_VSHR_immu8,
    MVE_VSLIimm16,
    MVE_VSLIimm32,
    MVE_VSLIimm8,
    MVE_VSRIimm16,
    MVE_VSRIimm32,
    MVE_VSRIimm8,
    MVE_VST20_16,
    MVE_VST20_16_wb,
    MVE_VST20_32,
    MVE_VST20_32_wb,
    MVE_VST20_8,
    MVE_VST20_8_wb,
    MVE_VST21_16,
    MVE_VST21_16_wb,
    MVE_VST21_32,
    MVE_VST21_32_wb,
    MVE_VST21_8,
    MVE_VST21_8_wb,
    MVE_VST40_16,
    MVE_VST40_16_wb,
    MVE_VST40_32,
    MVE_VST40_32_wb,
    MVE_VST40_8,
    MVE_VST40_8_wb,
    MVE_VST41_16,
    MVE_VST41_16_wb,
    MVE_VST41_32,
    MVE_VST41_32_wb,
    MVE_VST41_8,
    MVE_VST41_8_wb,
    MVE_VST42_16,
    MVE_VST42_16_wb,
    MVE_VST42_32,
    MVE_VST42_32_wb,
    MVE_VST42_8,
    MVE_VST42_8_wb,
    MVE_VST43_16,
    MVE_VST43_16_wb,
    MVE_VST43_32,
    MVE_VST43_32_wb,
    MVE_VST43_8,
    MVE_VST43_8_wb,
    MVE_VSTRB16,
    MVE_VSTRB16_post,
    MVE_VSTRB16_pre,
    MVE_VSTRB16_rq,
    MVE_VSTRB32,
    MVE_VSTRB32_post,
    MVE_VSTRB32_pre,
    MVE_VSTRB32_rq,
    MVE_VSTRB8_rq,
    MVE_VSTRBU8,
    MVE_VSTRBU8_post,
    MVE_VSTRBU8_pre,
    MVE_VSTRD64_qi,
    MVE_VSTRD64_qi_pre,
    MVE_VSTRD64_rq,
    MVE_VSTRD64_rq_u,
    MVE_VSTRH16_rq,
    MVE_VSTRH16_rq_u,
    MVE_VSTRH32,
    MVE_VSTRH32_post,
    MVE_VSTRH32_pre,
    MVE_VSTRH32_rq,
    MVE_VSTRH32_rq_u,
    MVE_VSTRHU16,
    MVE_VSTRHU16_post,
    MVE_VSTRHU16_pre,
    MVE_VSTRW32_qi,
    MVE_VSTRW32_qi_pre,
    MVE_VSTRW32_rq,
    MVE_VSTRW32_rq_u,
    MVE_VSTRWU32,
    MVE_VSTRWU32_post,
    MVE_VSTRWU32_pre,
    MVE_VSUB_qr_f16,
    MVE_VSUB_qr_f32,
    MVE_VSUB_qr_i16,
    MVE_VSUB_qr_i32,
    MVE_VSUB_qr_i8,
    MVE_VSUBf16,
    MVE_VSUBf32,
    MVE_VSUBi16,
    MVE_VSUBi32,
    MVE_VSUBi8,
    MVE_WLSTP_16,
    MVE_WLSTP_32,
    MVE_WLSTP_64,
    MVE_WLSTP_8,
    MVNi,
    MVNr,
    MVNsi,
    MVNsr,
    NEON_VMAXNMNDf,
    NEON_VMAXNMNDh,
    NEON_VMAXNMNQf,
    NEON_VMAXNMNQh,
    NEON_VMINNMNDf,
    NEON_VMINNMNDh,
    NEON_VMINNMNQf,
    NEON_VMINNMNQh,
    ORRri,
    ORRrr,
    ORRrsi,
    ORRrsr,
    PKHBT,
    PKHTB,
    PLDWi12,
    PLDWrs,
    PLDi12,
    PLDrs,
    PLIi12,
    PLIrs,
    QADD,
    QADD16,
    QADD8,
    QASX,
    QDADD,
    QDSUB,
    QSAX,
    QSUB,
    QSUB16,
    QSUB8,
    RBIT,
    REV,
    REV16,
    REVSH,
    RFEDA,
    RFEDA_UPD,
    RFEDB,
    RFEDB_UPD,
    RFEIA,
    RFEIA_UPD,
    RFEIB,
    RFEIB_UPD,
    RSBri,
    RSBrr,
    RSBrsi,
    RSBrsr,
    RSCri,
    RSCrr,
    RSCrsi,
    RSCrsr,
    SADD16,
    SADD8,
    SASX,
    SB,
    SBCri,
    SBCrr,
    SBCrsi,
    SBCrsr,
    SBFX,
    SDIV,
    SEL,
    SETEND,
    SETPAN,
    SHA1C,
    SHA1H,
    SHA1M,
    SHA1P,
    SHA1SU0,
    SHA1SU1,
    SHA256H,
    SHA256H2,
    SHA256SU0,
    SHA256SU1,
    SHADD16,
    SHADD8,
    SHASX,
    SHSAX,
    SHSUB16,
    SHSUB8,
    SMC,
    SMLABB,
    SMLABT,
    SMLAD,
    SMLADX,
    SMLAL,
    SMLALBB,
    SMLALBT,
    SMLALD,
    SMLALDX,
    SMLALTB,
    SMLALTT,
    SMLATB,
    SMLATT,
    SMLAWB,
    SMLAWT,
    SMLSD,
    SMLSDX,
    SMLSLD,
    SMLSLDX,
    SMMLA,
    SMMLAR,
    SMMLS,
    SMMLSR,
    SMMUL,
    SMMULR,
    SMUAD,
    SMUADX,
    SMULBB,
    SMULBT,
    SMULL,
    SMULTB,
    SMULTT,
    SMULWB,
    SMULWT,
    SMUSD,
    SMUSDX,
    SRSDA,
    SRSDA_UPD,
    SRSDB,
    SRSDB_UPD,
    SRSIA,
    SRSIA_UPD,
    SRSIB,
    SRSIB_UPD,
    SSAT,
    SSAT16,
    SSAX,
    SSUB16,
    SSUB8,
    STC2L_OFFSET,
    STC2L_OPTION,
    STC2L_POST,
    STC2L_PRE,
    STC2_OFFSET,
    STC2_OPTION,
    STC2_POST,
    STC2_PRE,
    STCL_OFFSET,
    STCL_OPTION,
    STCL_POST,
    STCL_PRE,
    STC_OFFSET,
    STC_OPTION,
    STC_POST,
    STC_PRE,
    STL,
    STLB,
    STLEX,
    STLEXB,
    STLEXD,
    STLEXH,
    STLH,
    STMDA,
    STMDA_UPD,
    STMDB,
    STMDB_UPD,
    STMIA,
    STMIA_UPD,
    STMIB,
    STMIB_UPD,
    STRBT_POST_IMM,
    STRBT_POST_REG,
    STRB_POST_IMM,
    STRB_POST_REG,
    STRB_PRE_IMM,
    STRB_PRE_REG,
    STRBi12,
    STRBrs,
    STRD,
    STRD_POST,
    STRD_PRE,
    STREX,
    STREXB,
    STREXD,
    STREXH,
    STRH,
    STRHTi,
    STRHTr,
    STRH_POST,
    STRH_PRE,
    STRT_POST_IMM,
    STRT_POST_REG,
    STR_POST_IMM,
    STR_POST_REG,
    STR_PRE_IMM,
    STR_PRE_REG,
    STRi12,
    STRrs,
    SUBri,
    SUBrr,
    SUBrsi,
    SUBrsr,
    SVC,
    SWP,
    SWPB,
    SXTAB,
    SXTAB16,
    SXTAH,
    SXTB,
    SXTB16,
    SXTH,
    TEQri,
    TEQrr,
    TEQrsi,
    TEQrsr,
    TRAP,
    TRAPNaCl,
    TSB,
    TSTri,
    TSTrr,
    TSTrsi,
    TSTrsr,
    UADD16,
    UADD8,
    UASX,
    UBFX,
    UDF,
    UDIV,
    UHADD16,
    UHADD8,
    UHASX,
    UHSAX,
    UHSUB16,
    UHSUB8,
    UMAAL,
    UMLAL,
    UMULL,
    UQADD16,
    UQADD8,
    UQASX,
    UQSAX,
    UQSUB16,
    UQSUB8,
    USAD8,
    USADA8,
    USAT,
    USAT16,
    USAX,
    USUB16,
    USUB8,
    UXTAB,
    UXTAB16,
    UXTAH,
    UXTB,
    UXTB16,
    UXTH,
    VABALsv2i64,
    VABALsv4i32,
    VABALsv8i16,
    VABALuv2i64,
    VABALuv4i32,
    VABALuv8i16,
    VABAsv16i8,
    VABAsv2i32,
    VABAsv4i16,
    VABAsv4i32,
    VABAsv8i16,
    VABAsv8i8,
    VABAuv16i8,
    VABAuv2i32,
    VABAuv4i16,
    VABAuv4i32,
    VABAuv8i16,
    VABAuv8i8,
    VABDLsv2i64,
    VABDLsv4i32,
    VABDLsv8i16,
    VABDLuv2i64,
    VABDLuv4i32,
    VABDLuv8i16,
    VABDfd,
    VABDfq,
    VABDhd,
    VABDhq,
    VABDsv16i8,
    VABDsv2i32,
    VABDsv4i16,
    VABDsv4i32,
    VABDsv8i16,
    VABDsv8i8,
    VABDuv16i8,
    VABDuv2i32,
    VABDuv4i16,
    VABDuv4i32,
    VABDuv8i16,
    VABDuv8i8,
    VABSD,
    VABSH,
    VABSS,
    VABSfd,
    VABSfq,
    VABShd,
    VABShq,
    VABSv16i8,
    VABSv2i32,
    VABSv4i16,
    VABSv4i32,
    VABSv8i16,
    VABSv8i8,
    VACGEfd,
    VACGEfq,
    VACGEhd,
    VACGEhq,
    VACGTfd,
    VACGTfq,
    VACGThd,
    VACGThq,
    VADDD,
    VADDH,
    VADDHNv2i32,
    VADDHNv4i16,
    VADDHNv8i8,
    VADDLsv2i64,
    VADDLsv4i32,
    VADDLsv8i16,
    VADDLuv2i64,
    VADDLuv4i32,
    VADDLuv8i16,
    VADDS,
    VADDWsv2i64,
    VADDWsv4i32,
    VADDWsv8i16,
    VADDWuv2i64,
    VADDWuv4i32,
    VADDWuv8i16,
    VADDfd,
    VADDfq,
    VADDhd,
    VADDhq,
    VADDv16i8,
    VADDv1i64,
    VADDv2i32,
    VADDv2i64,
    VADDv4i16,
    VADDv4i32,
    VADDv8i16,
    VADDv8i8,
    VANDd,
    VANDq,
    VBF16MALBQ,
    VBF16MALBQI,
    VBF16MALTQ,
    VBF16MALTQI,
    VBICd,
    VBICiv2i32,
    VBICiv4i16,
    VBICiv4i32,
    VBICiv8i16,
    VBICq,
    VBIFd,
    VBIFq,
    VBITd,
    VBITq,
    VBSLd,
    VBSLq,
    VBSPd,
    VBSPq,
    VCADDv2f32,
    VCADDv4f16,
    VCADDv4f32,
    VCADDv8f16,
    VCEQfd,
    VCEQfq,
    VCEQhd,
    VCEQhq,
    VCEQv16i8,
    VCEQv2i32,
    VCEQv4i16,
    VCEQv4i32,
    VCEQv8i16,
    VCEQv8i8,
    VCEQzv16i8,
    VCEQzv2f32,
    VCEQzv2i32,
    VCEQzv4f16,
    VCEQzv4f32,
    VCEQzv4i16,
    VCEQzv4i32,
    VCEQzv8f16,
    VCEQzv8i16,
    VCEQzv8i8,
    VCGEfd,
    VCGEfq,
    VCGEhd,
    VCGEhq,
    VCGEsv16i8,
    VCGEsv2i32,
    VCGEsv4i16,
    VCGEsv4i32,
    VCGEsv8i16,
    VCGEsv8i8,
    VCGEuv16i8,
    VCGEuv2i32,
    VCGEuv4i16,
    VCGEuv4i32,
    VCGEuv8i16,
    VCGEuv8i8,
    VCGEzv16i8,
    VCGEzv2f32,
    VCGEzv2i32,
    VCGEzv4f16,
    VCGEzv4f32,
    VCGEzv4i16,
    VCGEzv4i32,
    VCGEzv8f16,
    VCGEzv8i16,
    VCGEzv8i8,
    VCGTfd,
    VCGTfq,
    VCGThd,
    VCGThq,
    VCGTsv16i8,
    VCGTsv2i32,
    VCGTsv4i16,
    VCGTsv4i32,
    VCGTsv8i16,
    VCGTsv8i8,
    VCGTuv16i8,
    VCGTuv2i32,
    VCGTuv4i16,
    VCGTuv4i32,
    VCGTuv8i16,
    VCGTuv8i8,
    VCGTzv16i8,
    VCGTzv2f32,
    VCGTzv2i32,
    VCGTzv4f16,
    VCGTzv4f32,
    VCGTzv4i16,
    VCGTzv4i32,
    VCGTzv8f16,
    VCGTzv8i16,
    VCGTzv8i8,
    VCLEzv16i8,
    VCLEzv2f32,
    VCLEzv2i32,
    VCLEzv4f16,
    VCLEzv4f32,
    VCLEzv4i16,
    VCLEzv4i32,
    VCLEzv8f16,
    VCLEzv8i16,
    VCLEzv8i8,
    VCLSv16i8,
    VCLSv2i32,
    VCLSv4i16,
    VCLSv4i32,
    VCLSv8i16,
    VCLSv8i8,
    VCLTzv16i8,
    VCLTzv2f32,
    VCLTzv2i32,
    VCLTzv4f16,
    VCLTzv4f32,
    VCLTzv4i16,
    VCLTzv4i32,
    VCLTzv8f16,
    VCLTzv8i16,
    VCLTzv8i8,
    VCLZv16i8,
    VCLZv2i32,
    VCLZv4i16,
    VCLZv4i32,
    VCLZv8i16,
    VCLZv8i8,
    VCMLAv2f32,
    VCMLAv2f32_indexed,
    VCMLAv4f16,
    VCMLAv4f16_indexed,
    VCMLAv4f32,
    VCMLAv4f32_indexed,
    VCMLAv8f16,
    VCMLAv8f16_indexed,
    VCMPD,
    VCMPED,
    VCMPEH,
    VCMPES,
    VCMPEZD,
    VCMPEZH,
    VCMPEZS,
    VCMPH,
    VCMPS,
    VCMPZD,
    VCMPZH,
    VCMPZS,
    VCNTd,
    VCNTq,
    VCVTANSDf,
    VCVTANSDh,
    VCVTANSQf,
    VCVTANSQh,
    VCVTANUDf,
    VCVTANUDh,
    VCVTANUQf,
    VCVTANUQh,
    VCVTASD,
    VCVTASH,
    VCVTASS,
    VCVTAUD,
    VCVTAUH,
    VCVTAUS,
    VCVTBDH,
    VCVTBHD,
    VCVTBHS,
    VCVTBSH,
    VCVTDS,
    VCVTMNSDf,
    VCVTMNSDh,
    VCVTMNSQf,
    VCVTMNSQh,
    VCVTMNUDf,
    VCVTMNUDh,
    VCVTMNUQf,
    VCVTMNUQh,
    VCVTMSD,
    VCVTMSH,
    VCVTMSS,
    VCVTMUD,
    VCVTMUH,
    VCVTMUS,
    VCVTNNSDf,
    VCVTNNSDh,
    VCVTNNSQf,
    VCVTNNSQh,
    VCVTNNUDf,
    VCVTNNUDh,
    VCVTNNUQf,
    VCVTNNUQh,
    VCVTNSD,
    VCVTNSH,
    VCVTNSS,
    VCVTNUD,
    VCVTNUH,
    VCVTNUS,
    VCVTPNSDf,
    VCVTPNSDh,
    VCVTPNSQf,
    VCVTPNSQh,
    VCVTPNUDf,
    VCVTPNUDh,
    VCVTPNUQf,
    VCVTPNUQh,
    VCVTPSD,
    VCVTPSH,
    VCVTPSS,
    VCVTPUD,
    VCVTPUH,
    VCVTPUS,
    VCVTSD,
    VCVTTDH,
    VCVTTHD,
    VCVTTHS,
    VCVTTSH,
    VCVTf2h,
    VCVTf2sd,
    VCVTf2sq,
    VCVTf2ud,
    VCVTf2uq,
    VCVTf2xsd,
    VCVTf2xsq,
    VCVTf2xud,
    VCVTf2xuq,
    VCVTh2f,
    VCVTh2sd,
    VCVTh2sq,
    VCVTh2ud,
    VCVTh2uq,
    VCVTh2xsd,
    VCVTh2xsq,
    VCVTh2xud,
    VCVTh2xuq,
    VCVTs2fd,
    VCVTs2fq,
    VCVTs2hd,
    VCVTs2hq,
    VCVTu2fd,
    VCVTu2fq,
    VCVTu2hd,
    VCVTu2hq,
    VCVTxs2fd,
    VCVTxs2fq,
    VCVTxs2hd,
    VCVTxs2hq,
    VCVTxu2fd,
    VCVTxu2fq,
    VCVTxu2hd,
    VCVTxu2hq,
    VDIVD,
    VDIVH,
    VDIVS,
    VDUP16d,
    VDUP16q,
    VDUP32d,
    VDUP32q,
    VDUP8d,
    VDUP8q,
    VDUPLN16d,
    VDUPLN16q,
    VDUPLN32d,
    VDUPLN32q,
    VDUPLN8d,
    VDUPLN8q,
    VEORd,
    VEORq,
    VEXTd16,
    VEXTd32,
    VEXTd8,
    VEXTq16,
    VEXTq32,
    VEXTq64,
    VEXTq8,
    VFMAD,
    VFMAH,
    VFMALD,
    VFMALDI,
    VFMALQ,
    VFMALQI,
    VFMAS,
    VFMAfd,
    VFMAfq,
    VFMAhd,
    VFMAhq,
    VFMSD,
    VFMSH,
    VFMSLD,
    VFMSLDI,
    VFMSLQ,
    VFMSLQI,
    VFMSS,
    VFMSfd,
    VFMSfq,
    VFMShd,
    VFMShq,
    VFNMAD,
    VFNMAH,
    VFNMAS,
    VFNMSD,
    VFNMSH,
    VFNMSS,
    VFP_VMAXNMD,
    VFP_VMAXNMH,
    VFP_VMAXNMS,
    VFP_VMINNMD,
    VFP_VMINNMH,
    VFP_VMINNMS,
    VGETLNi32,
    VGETLNs16,
    VGETLNs8,
    VGETLNu16,
    VGETLNu8,
    VHADDsv16i8,
    VHADDsv2i32,
    VHADDsv4i16,
    VHADDsv4i32,
    VHADDsv8i16,
    VHADDsv8i8,
    VHADDuv16i8,
    VHADDuv2i32,
    VHADDuv4i16,
    VHADDuv4i32,
    VHADDuv8i16,
    VHADDuv8i8,
    VHSUBsv16i8,
    VHSUBsv2i32,
    VHSUBsv4i16,
    VHSUBsv4i32,
    VHSUBsv8i16,
    VHSUBsv8i8,
    VHSUBuv16i8,
    VHSUBuv2i32,
    VHSUBuv4i16,
    VHSUBuv4i32,
    VHSUBuv8i16,
    VHSUBuv8i8,
    VINSH,
    VJCVT,
    VLD1DUPd16,
    VLD1DUPd16wb_fixed,
    VLD1DUPd16wb_register,
    VLD1DUPd32,
    VLD1DUPd32wb_fixed,
    VLD1DUPd32wb_register,
    VLD1DUPd8,
    VLD1DUPd8wb_fixed,
    VLD1DUPd8wb_register,
    VLD1DUPq16,
    VLD1DUPq16wb_fixed,
    VLD1DUPq16wb_register,
    VLD1DUPq32,
    VLD1DUPq32wb_fixed,
    VLD1DUPq32wb_register,
    VLD1DUPq8,
    VLD1DUPq8wb_fixed,
    VLD1DUPq8wb_register,
    VLD1LNd16,
    VLD1LNd16_UPD,
    VLD1LNd32,
    VLD1LNd32_UPD,
    VLD1LNd8,
    VLD1LNd8_UPD,
    VLD1LNq16Pseudo,
    VLD1LNq16Pseudo_UPD,
    VLD1LNq32Pseudo,
    VLD1LNq32Pseudo_UPD,
    VLD1LNq8Pseudo,
    VLD1LNq8Pseudo_UPD,
    VLD1d16,
    VLD1d16Q,
    VLD1d16QPseudo,
    VLD1d16QPseudoWB_fixed,
    VLD1d16QPseudoWB_register,
    VLD1d16Qwb_fixed,
    VLD1d16Qwb_register,
    VLD1d16T,
    VLD1d16TPseudo,
    VLD1d16TPseudoWB_fixed,
    VLD1d16TPseudoWB_register,
    VLD1d16Twb_fixed,
    VLD1d16Twb_register,
    VLD1d16wb_fixed,
    VLD1d16wb_register,
    VLD1d32,
    VLD1d32Q,
    VLD1d32QPseudo,
    VLD1d32QPseudoWB_fixed,
    VLD1d32QPseudoWB_register,
    VLD1d32Qwb_fixed,
    VLD1d32Qwb_register,
    VLD1d32T,
    VLD1d32TPseudo,
    VLD1d32TPseudoWB_fixed,
    VLD1d32TPseudoWB_register,
    VLD1d32Twb_fixed,
    VLD1d32Twb_register,
    VLD1d32wb_fixed,
    VLD1d32wb_register,
    VLD1d64,
    VLD1d64Q,
    VLD1d64QPseudo,
    VLD1d64QPseudoWB_fixed,
    VLD1d64QPseudoWB_register,
    VLD1d64Qwb_fixed,
    VLD1d64Qwb_register,
    VLD1d64T,
    VLD1d64TPseudo,
    VLD1d64TPseudoWB_fixed,
    VLD1d64TPseudoWB_register,
    VLD1d64Twb_fixed,
    VLD1d64Twb_register,
    VLD1d64wb_fixed,
    VLD1d64wb_register,
    VLD1d8,
    VLD1d8Q,
    VLD1d8QPseudo,
    VLD1d8QPseudoWB_fixed,
    VLD1d8QPseudoWB_register,
    VLD1d8Qwb_fixed,
    VLD1d8Qwb_register,
    VLD1d8T,
    VLD1d8TPseudo,
    VLD1d8TPseudoWB_fixed,
    VLD1d8TPseudoWB_register,
    VLD1d8Twb_fixed,
    VLD1d8Twb_register,
    VLD1d8wb_fixed,
    VLD1d8wb_register,
    VLD1q16,
    VLD1q16HighQPseudo,
    VLD1q16HighQPseudo_UPD,
    VLD1q16HighTPseudo,
    VLD1q16HighTPseudo_UPD,
    VLD1q16LowQPseudo_UPD,
    VLD1q16LowTPseudo_UPD,
    VLD1q16wb_fixed,
    VLD1q16wb_register,
    VLD1q32,
    VLD1q32HighQPseudo,
    VLD1q32HighQPseudo_UPD,
    VLD1q32HighTPseudo,
    VLD1q32HighTPseudo_UPD,
    VLD1q32LowQPseudo_UPD,
    VLD1q32LowTPseudo_UPD,
    VLD1q32wb_fixed,
    VLD1q32wb_register,
    VLD1q64,
    VLD1q64HighQPseudo,
    VLD1q64HighQPseudo_UPD,
    VLD1q64HighTPseudo,
    VLD1q64HighTPseudo_UPD,
    VLD1q64LowQPseudo_UPD,
    VLD1q64LowTPseudo_UPD,
    VLD1q64wb_fixed,
    VLD1q64wb_register,
    VLD1q8,
    VLD1q8HighQPseudo,
    VLD1q8HighQPseudo_UPD,
    VLD1q8HighTPseudo,
    VLD1q8HighTPseudo_UPD,
    VLD1q8LowQPseudo_UPD,
    VLD1q8LowTPseudo_UPD,
    VLD1q8wb_fixed,
    VLD1q8wb_register,
    VLD2DUPd16,
    VLD2DUPd16wb_fixed,
    VLD2DUPd16wb_register,
    VLD2DUPd16x2,
    VLD2DUPd16x2wb_fixed,
    VLD2DUPd16x2wb_register,
    VLD2DUPd32,
    VLD2DUPd32wb_fixed,
    VLD2DUPd32wb_register,
    VLD2DUPd32x2,
    VLD2DUPd32x2wb_fixed,
    VLD2DUPd32x2wb_register,
    VLD2DUPd8,
    VLD2DUPd8wb_fixed,
    VLD2DUPd8wb_register,
    VLD2DUPd8x2,
    VLD2DUPd8x2wb_fixed,
    VLD2DUPd8x2wb_register,
    VLD2DUPq16EvenPseudo,
    VLD2DUPq16OddPseudo,
    VLD2DUPq16OddPseudoWB_fixed,
    VLD2DUPq16OddPseudoWB_register,
    VLD2DUPq32EvenPseudo,
    VLD2DUPq32OddPseudo,
    VLD2DUPq32OddPseudoWB_fixed,
    VLD2DUPq32OddPseudoWB_register,
    VLD2DUPq8EvenPseudo,
    VLD2DUPq8OddPseudo,
    VLD2DUPq8OddPseudoWB_fixed,
    VLD2DUPq8OddPseudoWB_register,
    VLD2LNd16,
    VLD2LNd16Pseudo,
    VLD2LNd16Pseudo_UPD,
    VLD2LNd16_UPD,
    VLD2LNd32,
    VLD2LNd32Pseudo,
    VLD2LNd32Pseudo_UPD,
    VLD2LNd32_UPD,
    VLD2LNd8,
    VLD2LNd8Pseudo,
    VLD2LNd8Pseudo_UPD,
    VLD2LNd8_UPD,
    VLD2LNq16,
    VLD2LNq16Pseudo,
    VLD2LNq16Pseudo_UPD,
    VLD2LNq16_UPD,
    VLD2LNq32,
    VLD2LNq32Pseudo,
    VLD2LNq32Pseudo_UPD,
    VLD2LNq32_UPD,
    VLD2b16,
    VLD2b16wb_fixed,
    VLD2b16wb_register,
    VLD2b32,
    VLD2b32wb_fixed,
    VLD2b32wb_register,
    VLD2b8,
    VLD2b8wb_fixed,
    VLD2b8wb_register,
    VLD2d16,
    VLD2d16wb_fixed,
    VLD2d16wb_register,
    VLD2d32,
    VLD2d32wb_fixed,
    VLD2d32wb_register,
    VLD2d8,
    VLD2d8wb_fixed,
    VLD2d8wb_register,
    VLD2q16,
    VLD2q16Pseudo,
    VLD2q16PseudoWB_fixed,
    VLD2q16PseudoWB_register,
    VLD2q16wb_fixed,
    VLD2q16wb_register,
    VLD2q32,
    VLD2q32Pseudo,
    VLD2q32PseudoWB_fixed,
    VLD2q32PseudoWB_register,
    VLD2q32wb_fixed,
    VLD2q32wb_register,
    VLD2q8,
    VLD2q8Pseudo,
    VLD2q8PseudoWB_fixed,
    VLD2q8PseudoWB_register,
    VLD2q8wb_fixed,
    VLD2q8wb_register,
    VLD3DUPd16,
    VLD3DUPd16Pseudo,
    VLD3DUPd16Pseudo_UPD,
    VLD3DUPd16_UPD,
    VLD3DUPd32,
    VLD3DUPd32Pseudo,
    VLD3DUPd32Pseudo_UPD,
    VLD3DUPd32_UPD,
    VLD3DUPd8,
    VLD3DUPd8Pseudo,
    VLD3DUPd8Pseudo_UPD,
    VLD3DUPd8_UPD,
    VLD3DUPq16,
    VLD3DUPq16EvenPseudo,
    VLD3DUPq16OddPseudo,
    VLD3DUPq16OddPseudo_UPD,
    VLD3DUPq16_UPD,
    VLD3DUPq32,
    VLD3DUPq32EvenPseudo,
    VLD3DUPq32OddPseudo,
    VLD3DUPq32OddPseudo_UPD,
    VLD3DUPq32_UPD,
    VLD3DUPq8,
    VLD3DUPq8EvenPseudo,
    VLD3DUPq8OddPseudo,
    VLD3DUPq8OddPseudo_UPD,
    VLD3DUPq8_UPD,
    VLD3LNd16,
    VLD3LNd16Pseudo,
    VLD3LNd16Pseudo_UPD,
    VLD3LNd16_UPD,
    VLD3LNd32,
    VLD3LNd32Pseudo,
    VLD3LNd32Pseudo_UPD,
    VLD3LNd32_UPD,
    VLD3LNd8,
    VLD3LNd8Pseudo,
    VLD3LNd8Pseudo_UPD,
    VLD3LNd8_UPD,
    VLD3LNq16,
    VLD3LNq16Pseudo,
    VLD3LNq16Pseudo_UPD,
    VLD3LNq16_UPD,
    VLD3LNq32,
    VLD3LNq32Pseudo,
    VLD3LNq32Pseudo_UPD,
    VLD3LNq32_UPD,
    VLD3d16,
    VLD3d16Pseudo,
    VLD3d16Pseudo_UPD,
    VLD3d16_UPD,
    VLD3d32,
    VLD3d32Pseudo,
    VLD3d32Pseudo_UPD,
    VLD3d32_UPD,
    VLD3d8,
    VLD3d8Pseudo,
    VLD3d8Pseudo_UPD,
    VLD3d8_UPD,
    VLD3q16,
    VLD3q16Pseudo_UPD,
    VLD3q16_UPD,
    VLD3q16oddPseudo,
    VLD3q16oddPseudo_UPD,
    VLD3q32,
    VLD3q32Pseudo_UPD,
    VLD3q32_UPD,
    VLD3q32oddPseudo,
    VLD3q32oddPseudo_UPD,
    VLD3q8,
    VLD3q8Pseudo_UPD,
    VLD3q8_UPD,
    VLD3q8oddPseudo,
    VLD3q8oddPseudo_UPD,
    VLD4DUPd16,
    VLD4DUPd16Pseudo,
    VLD4DUPd16Pseudo_UPD,
    VLD4DUPd16_UPD,
    VLD4DUPd32,
    VLD4DUPd32Pseudo,
    VLD4DUPd32Pseudo_UPD,
    VLD4DUPd32_UPD,
    VLD4DUPd8,
    VLD4DUPd8Pseudo,
    VLD4DUPd8Pseudo_UPD,
    VLD4DUPd8_UPD,
    VLD4DUPq16,
    VLD4DUPq16EvenPseudo,
    VLD4DUPq16OddPseudo,
    VLD4DUPq16OddPseudo_UPD,
    VLD4DUPq16_UPD,
    VLD4DUPq32,
    VLD4DUPq32EvenPseudo,
    VLD4DUPq32OddPseudo,
    VLD4DUPq32OddPseudo_UPD,
    VLD4DUPq32_UPD,
    VLD4DUPq8,
    VLD4DUPq8EvenPseudo,
    VLD4DUPq8OddPseudo,
    VLD4DUPq8OddPseudo_UPD,
    VLD4DUPq8_UPD,
    VLD4LNd16,
    VLD4LNd16Pseudo,
    VLD4LNd16Pseudo_UPD,
    VLD4LNd16_UPD,
    VLD4LNd32,
    VLD4LNd32Pseudo,
    VLD4LNd32Pseudo_UPD,
    VLD4LNd32_UPD,
    VLD4LNd8,
    VLD4LNd8Pseudo,
    VLD4LNd8Pseudo_UPD,
    VLD4LNd8_UPD,
    VLD4LNq16,
    VLD4LNq16Pseudo,
    VLD4LNq16Pseudo_UPD,
    VLD4LNq16_UPD,
    VLD4LNq32,
    VLD4LNq32Pseudo,
    VLD4LNq32Pseudo_UPD,
    VLD4LNq32_UPD,
    VLD4d16,
    VLD4d16Pseudo,
    VLD4d16Pseudo_UPD,
    VLD4d16_UPD,
    VLD4d32,
    VLD4d32Pseudo,
    VLD4d32Pseudo_UPD,
    VLD4d32_UPD,
    VLD4d8,
    VLD4d8Pseudo,
    VLD4d8Pseudo_UPD,
    VLD4d8_UPD,
    VLD4q16,
    VLD4q16Pseudo_UPD,
    VLD4q16_UPD,
    VLD4q16oddPseudo,
    VLD4q16oddPseudo_UPD,
    VLD4q32,
    VLD4q32Pseudo_UPD,
    VLD4q32_UPD,
    VLD4q32oddPseudo,
    VLD4q32oddPseudo_UPD,
    VLD4q8,
    VLD4q8Pseudo_UPD,
    VLD4q8_UPD,
    VLD4q8oddPseudo,
    VLD4q8oddPseudo_UPD,
    VLDMDDB_UPD,
    VLDMDIA,
    VLDMDIA_UPD,
    VLDMQIA,
    VLDMSDB_UPD,
    VLDMSIA,
    VLDMSIA_UPD,
    VLDRD,
    VLDRH,
    VLDRS,
    VLDR_FPCXTNS_off,
    VLDR_FPCXTNS_post,
    VLDR_FPCXTNS_pre,
    VLDR_FPCXTS_off,
    VLDR_FPCXTS_post,
    VLDR_FPCXTS_pre,
    VLDR_FPSCR_NZCVQC_off,
    VLDR_FPSCR_NZCVQC_post,
    VLDR_FPSCR_NZCVQC_pre,
    VLDR_FPSCR_off,
    VLDR_FPSCR_post,
    VLDR_FPSCR_pre,
    VLDR_P0_off,
    VLDR_P0_post,
    VLDR_P0_pre,
    VLDR_VPR_off,
    VLDR_VPR_post,
    VLDR_VPR_pre,
    VLLDM,
    VLLDM_T2,
    VLSTM,
    VLSTM_T2,
    VMAXfd,
    VMAXfq,
    VMAXhd,
    VMAXhq,
    VMAXsv16i8,
    VMAXsv2i32,
    VMAXsv4i16,
    VMAXsv4i32,
    VMAXsv8i16,
    VMAXsv8i8,
    VMAXuv16i8,
    VMAXuv2i32,
    VMAXuv4i16,
    VMAXuv4i32,
    VMAXuv8i16,
    VMAXuv8i8,
    VMINfd,
    VMINfq,
    VMINhd,
    VMINhq,
    VMINsv16i8,
    VMINsv2i32,
    VMINsv4i16,
    VMINsv4i32,
    VMINsv8i16,
    VMINsv8i8,
    VMINuv16i8,
    VMINuv2i32,
    VMINuv4i16,
    VMINuv4i32,
    VMINuv8i16,
    VMINuv8i8,
    VMLAD,
    VMLAH,
    VMLALslsv2i32,
    VMLALslsv4i16,
    VMLALsluv2i32,
    VMLALsluv4i16,
    VMLALsv2i64,
    VMLALsv4i32,
    VMLALsv8i16,
    VMLALuv2i64,
    VMLALuv4i32,
    VMLALuv8i16,
    VMLAS,
    VMLAfd,
    VMLAfq,
    VMLAhd,
    VMLAhq,
    VMLAslfd,
    VMLAslfq,
    VMLAslhd,
    VMLAslhq,
    VMLAslv2i32,
    VMLAslv4i16,
    VMLAslv4i32,
    VMLAslv8i16,
    VMLAv16i8,
    VMLAv2i32,
    VMLAv4i16,
    VMLAv4i32,
    VMLAv8i16,
    VMLAv8i8,
    VMLSD,
    VMLSH,
    VMLSLslsv2i32,
    VMLSLslsv4i16,
    VMLSLsluv2i32,
    VMLSLsluv4i16,
    VMLSLsv2i64,
    VMLSLsv4i32,
    VMLSLsv8i16,
    VMLSLuv2i64,
    VMLSLuv4i32,
    VMLSLuv8i16,
    VMLSS,
    VMLSfd,
    VMLSfq,
    VMLShd,
    VMLShq,
    VMLSslfd,
    VMLSslfq,
    VMLSslhd,
    VMLSslhq,
    VMLSslv2i32,
    VMLSslv4i16,
    VMLSslv4i32,
    VMLSslv8i16,
    VMLSv16i8,
    VMLSv2i32,
    VMLSv4i16,
    VMLSv4i32,
    VMLSv8i16,
    VMLSv8i8,
    VMMLA,
    VMOVD,
    VMOVDRR,
    VMOVH,
    VMOVHR,
    VMOVLsv2i64,
    VMOVLsv4i32,
    VMOVLsv8i16,
    VMOVLuv2i64,
    VMOVLuv4i32,
    VMOVLuv8i16,
    VMOVNv2i32,
    VMOVNv4i16,
    VMOVNv8i8,
    VMOVRH,
    VMOVRRD,
    VMOVRRS,
    VMOVRS,
    VMOVS,
    VMOVSR,
    VMOVSRR,
    VMOVv16i8,
    VMOVv1i64,
    VMOVv2f32,
    VMOVv2i32,
    VMOVv2i64,
    VMOVv4f32,
    VMOVv4i16,
    VMOVv4i32,
    VMOVv8i16,
    VMOVv8i8,
    VMRS,
    VMRS_FPCXTNS,
    VMRS_FPCXTS,
    VMRS_FPEXC,
    VMRS_FPINST,
    VMRS_FPINST2,
    VMRS_FPSCR_NZCVQC,
    VMRS_FPSID,
    VMRS_MVFR0,
    VMRS_MVFR1,
    VMRS_MVFR2,
    VMRS_P0,
    VMRS_VPR,
    VMSR,
    VMSR_FPCXTNS,
    VMSR_FPCXTS,
    VMSR_FPEXC,
    VMSR_FPINST,
    VMSR_FPINST2,
    VMSR_FPSCR_NZCVQC,
    VMSR_FPSID,
    VMSR_P0,
    VMSR_VPR,
    VMULD,
    VMULH,
    VMULLp64,
    VMULLp8,
    VMULLslsv2i32,
    VMULLslsv4i16,
    VMULLsluv2i32,
    VMULLsluv4i16,
    VMULLsv2i64,
    VMULLsv4i32,
    VMULLsv8i16,
    VMULLuv2i64,
    VMULLuv4i32,
    VMULLuv8i16,
    VMULS,
    VMULfd,
    VMULfq,
    VMULhd,
    VMULhq,
    VMULpd,
    VMULpq,
    VMULslfd,
    VMULslfq,
    VMULslhd,
    VMULslhq,
    VMULslv2i32,
    VMULslv4i16,
    VMULslv4i32,
    VMULslv8i16,
    VMULv16i8,
    VMULv2i32,
    VMULv4i16,
    VMULv4i32,
    VMULv8i16,
    VMULv8i8,
    VMVNd,
    VMVNq,
    VMVNv2i32,
    VMVNv4i16,
    VMVNv4i32,
    VMVNv8i16,
    VNEGD,
    VNEGH,
    VNEGS,
    VNEGf32q,
    VNEGfd,
    VNEGhd,
    VNEGhq,
    VNEGs16d,
    VNEGs16q,
    VNEGs32d,
    VNEGs32q,
    VNEGs8d,
    VNEGs8q,
    VNMLAD,
    VNMLAH,
    VNMLAS,
    VNMLSD,
    VNMLSH,
    VNMLSS,
    VNMULD,
    VNMULH,
    VNMULS,
    VORNd,
    VORNq,
    VORRd,
    VORRiv2i32,
    VORRiv4i16,
    VORRiv4i32,
    VORRiv8i16,
    VORRq,
    VPADALsv16i8,
    VPADALsv2i32,
    VPADALsv4i16,
    VPADALsv4i32,
    VPADALsv8i16,
    VPADALsv8i8,
    VPADALuv16i8,
    VPADALuv2i32,
    VPADALuv4i16,
    VPADALuv4i32,
    VPADALuv8i16,
    VPADALuv8i8,
    VPADDLsv16i8,
    VPADDLsv2i32,
    VPADDLsv4i16,
    VPADDLsv4i32,
    VPADDLsv8i16,
    VPADDLsv8i8,
    VPADDLuv16i8,
    VPADDLuv2i32,
    VPADDLuv4i16,
    VPADDLuv4i32,
    VPADDLuv8i16,
    VPADDLuv8i8,
    VPADDf,
    VPADDh,
    VPADDi16,
    VPADDi32,
    VPADDi8,
    VPMAXf,
    VPMAXh,
    VPMAXs16,
    VPMAXs32,
    VPMAXs8,
    VPMAXu16,
    VPMAXu32,
    VPMAXu8,
    VPMINf,
    VPMINh,
    VPMINs16,
    VPMINs32,
    VPMINs8,
    VPMINu16,
    VPMINu32,
    VPMINu8,
    VQABSv16i8,
    VQABSv2i32,
    VQABSv4i16,
    VQABSv4i32,
    VQABSv8i16,
    VQABSv8i8,
    VQADDsv16i8,
    VQADDsv1i64,
    VQADDsv2i32,
    VQADDsv2i64,
    VQADDsv4i16,
    VQADDsv4i32,
    VQADDsv8i16,
    VQADDsv8i8,
    VQADDuv16i8,
    VQADDuv1i64,
    VQADDuv2i32,
    VQADDuv2i64,
    VQADDuv4i16,
    VQADDuv4i32,
    VQADDuv8i16,
    VQADDuv8i8,
    VQDMLALslv2i32,
    VQDMLALslv4i16,
    VQDMLALv2i64,
    VQDMLALv4i32,
    VQDMLSLslv2i32,
    VQDMLSLslv4i16,
    VQDMLSLv2i64,
    VQDMLSLv4i32,
    VQDMULHslv2i32,
    VQDMULHslv4i16,
    VQDMULHslv4i32,
    VQDMULHslv8i16,
    VQDMULHv2i32,
    VQDMULHv4i16,
    VQDMULHv4i32,
    VQDMULHv8i16,
    VQDMULLslv2i32,
    VQDMULLslv4i16,
    VQDMULLv2i64,
    VQDMULLv4i32,
    VQMOVNsuv2i32,
    VQMOVNsuv4i16,
    VQMOVNsuv8i8,
    VQMOVNsv2i32,
    VQMOVNsv4i16,
    VQMOVNsv8i8,
    VQMOVNuv2i32,
    VQMOVNuv4i16,
    VQMOVNuv8i8,
    VQNEGv16i8,
    VQNEGv2i32,
    VQNEGv4i16,
    VQNEGv4i32,
    VQNEGv8i16,
    VQNEGv8i8,
    VQRDMLAHslv2i32,
    VQRDMLAHslv4i16,
    VQRDMLAHslv4i32,
    VQRDMLAHslv8i16,
    VQRDMLAHv2i32,
    VQRDMLAHv4i16,
    VQRDMLAHv4i32,
    VQRDMLAHv8i16,
    VQRDMLSHslv2i32,
    VQRDMLSHslv4i16,
    VQRDMLSHslv4i32,
    VQRDMLSHslv8i16,
    VQRDMLSHv2i32,
    VQRDMLSHv4i16,
    VQRDMLSHv4i32,
    VQRDMLSHv8i16,
    VQRDMULHslv2i32,
    VQRDMULHslv4i16,
    VQRDMULHslv4i32,
    VQRDMULHslv8i16,
    VQRDMULHv2i32,
    VQRDMULHv4i16,
    VQRDMULHv4i32,
    VQRDMULHv8i16,
    VQRSHLsv16i8,
    VQRSHLsv1i64,
    VQRSHLsv2i32,
    VQRSHLsv2i64,
    VQRSHLsv4i16,
    VQRSHLsv4i32,
    VQRSHLsv8i16,
    VQRSHLsv8i8,
    VQRSHLuv16i8,
    VQRSHLuv1i64,
    VQRSHLuv2i32,
    VQRSHLuv2i64,
    VQRSHLuv4i16,
    VQRSHLuv4i32,
    VQRSHLuv8i16,
    VQRSHLuv8i8,
    VQRSHRNsv2i32,
    VQRSHRNsv4i16,
    VQRSHRNsv8i8,
    VQRSHRNuv2i32,
    VQRSHRNuv4i16,
    VQRSHRNuv8i8,
    VQRSHRUNv2i32,
    VQRSHRUNv4i16,
    VQRSHRUNv8i8,
    VQSHLsiv16i8,
    VQSHLsiv1i64,
    VQSHLsiv2i32,
    VQSHLsiv2i64,
    VQSHLsiv4i16,
    VQSHLsiv4i32,
    VQSHLsiv8i16,
    VQSHLsiv8i8,
    VQSHLsuv16i8,
    VQSHLsuv1i64,
    VQSHLsuv2i32,
    VQSHLsuv2i64,
    VQSHLsuv4i16,
    VQSHLsuv4i32,
    VQSHLsuv8i16,
    VQSHLsuv8i8,
    VQSHLsv16i8,
    VQSHLsv1i64,
    VQSHLsv2i32,
    VQSHLsv2i64,
    VQSHLsv4i16,
    VQSHLsv4i32,
    VQSHLsv8i16,
    VQSHLsv8i8,
    VQSHLuiv16i8,
    VQSHLuiv1i64,
    VQSHLuiv2i32,
    VQSHLuiv2i64,
    VQSHLuiv4i16,
    VQSHLuiv4i32,
    VQSHLuiv8i16,
    VQSHLuiv8i8,
    VQSHLuv16i8,
    VQSHLuv1i64,
    VQSHLuv2i32,
    VQSHLuv2i64,
    VQSHLuv4i16,
    VQSHLuv4i32,
    VQSHLuv8i16,
    VQSHLuv8i8,
    VQSHRNsv2i32,
    VQSHRNsv4i16,
    VQSHRNsv8i8,
    VQSHRNuv2i32,
    VQSHRNuv4i16,
    VQSHRNuv8i8,
    VQSHRUNv2i32,
    VQSHRUNv4i16,
    VQSHRUNv8i8,
    VQSUBsv16i8,
    VQSUBsv1i64,
    VQSUBsv2i32,
    VQSUBsv2i64,
    VQSUBsv4i16,
    VQSUBsv4i32,
    VQSUBsv8i16,
    VQSUBsv8i8,
    VQSUBuv16i8,
    VQSUBuv1i64,
    VQSUBuv2i32,
    VQSUBuv2i64,
    VQSUBuv4i16,
    VQSUBuv4i32,
    VQSUBuv8i16,
    VQSUBuv8i8,
    VRADDHNv2i32,
    VRADDHNv4i16,
    VRADDHNv8i8,
    VRECPEd,
    VRECPEfd,
    VRECPEfq,
    VRECPEhd,
    VRECPEhq,
    VRECPEq,
    VRECPSfd,
    VRECPSfq,
    VRECPShd,
    VRECPShq,
    VREV16d8,
    VREV16q8,
    VREV32d16,
    VREV32d8,
    VREV32q16,
    VREV32q8,
    VREV64d16,
    VREV64d32,
    VREV64d8,
    VREV64q16,
    VREV64q32,
    VREV64q8,
    VRHADDsv16i8,
    VRHADDsv2i32,
    VRHADDsv4i16,
    VRHADDsv4i32,
    VRHADDsv8i16,
    VRHADDsv8i8,
    VRHADDuv16i8,
    VRHADDuv2i32,
    VRHADDuv4i16,
    VRHADDuv4i32,
    VRHADDuv8i16,
    VRHADDuv8i8,
    VRINTAD,
    VRINTAH,
    VRINTANDf,
    VRINTANDh,
    VRINTANQf,
    VRINTANQh,
    VRINTAS,
    VRINTMD,
    VRINTMH,
    VRINTMNDf,
    VRINTMNDh,
    VRINTMNQf,
    VRINTMNQh,
    VRINTMS,
    VRINTND,
    VRINTNH,
    VRINTNNDf,
    VRINTNNDh,
    VRINTNNQf,
    VRINTNNQh,
    VRINTNS,
    VRINTPD,
    VRINTPH,
    VRINTPNDf,
    VRINTPNDh,
    VRINTPNQf,
    VRINTPNQh,
    VRINTPS,
    VRINTRD,
    VRINTRH,
    VRINTRS,
    VRINTXD,
    VRINTXH,
    VRINTXNDf,
    VRINTXNDh,
    VRINTXNQf,
    VRINTXNQh,
    VRINTXS,
    VRINTZD,
    VRINTZH,
    VRINTZNDf,
    VRINTZNDh,
    VRINTZNQf,
    VRINTZNQh,
    VRINTZS,
    VRSHLsv16i8,
    VRSHLsv1i64,
    VRSHLsv2i32,
    VRSHLsv2i64,
    VRSHLsv4i16,
    VRSHLsv4i32,
    VRSHLsv8i16,
    VRSHLsv8i8,
    VRSHLuv16i8,
    VRSHLuv1i64,
    VRSHLuv2i32,
    VRSHLuv2i64,
    VRSHLuv4i16,
    VRSHLuv4i32,
    VRSHLuv8i16,
    VRSHLuv8i8,
    VRSHRNv2i32,
    VRSHRNv4i16,
    VRSHRNv8i8,
    VRSHRsv16i8,
    VRSHRsv1i64,
    VRSHRsv2i32,
    VRSHRsv2i64,
    VRSHRsv4i16,
    VRSHRsv4i32,
    VRSHRsv8i16,
    VRSHRsv8i8,
    VRSHRuv16i8,
    VRSHRuv1i64,
    VRSHRuv2i32,
    VRSHRuv2i64,
    VRSHRuv4i16,
    VRSHRuv4i32,
    VRSHRuv8i16,
    VRSHRuv8i8,
    VRSQRTEd,
    VRSQRTEfd,
    VRSQRTEfq,
    VRSQRTEhd,
    VRSQRTEhq,
    VRSQRTEq,
    VRSQRTSfd,
    VRSQRTSfq,
    VRSQRTShd,
    VRSQRTShq,
    VRSRAsv16i8,
    VRSRAsv1i64,
    VRSRAsv2i32,
    VRSRAsv2i64,
    VRSRAsv4i16,
    VRSRAsv4i32,
    VRSRAsv8i16,
    VRSRAsv8i8,
    VRSRAuv16i8,
    VRSRAuv1i64,
    VRSRAuv2i32,
    VRSRAuv2i64,
    VRSRAuv4i16,
    VRSRAuv4i32,
    VRSRAuv8i16,
    VRSRAuv8i8,
    VRSUBHNv2i32,
    VRSUBHNv4i16,
    VRSUBHNv8i8,
    VSCCLRMD,
    VSCCLRMS,
    VSDOTD,
    VSDOTDI,
    VSDOTQ,
    VSDOTQI,
    VSELEQD,
    VSELEQH,
    VSELEQS,
    VSELGED,
    VSELGEH,
    VSELGES,
    VSELGTD,
    VSELGTH,
    VSELGTS,
    VSELVSD,
    VSELVSH,
    VSELVSS,
    VSETLNi16,
    VSETLNi32,
    VSETLNi8,
    VSHLLi16,
    VSHLLi32,
    VSHLLi8,
    VSHLLsv2i64,
    VSHLLsv4i32,
    VSHLLsv8i16,
    VSHLLuv2i64,
    VSHLLuv4i32,
    VSHLLuv8i16,
    VSHLiv16i8,
    VSHLiv1i64,
    VSHLiv2i32,
    VSHLiv2i64,
    VSHLiv4i16,
    VSHLiv4i32,
    VSHLiv8i16,
    VSHLiv8i8,
    VSHLsv16i8,
    VSHLsv1i64,
    VSHLsv2i32,
    VSHLsv2i64,
    VSHLsv4i16,
    VSHLsv4i32,
    VSHLsv8i16,
    VSHLsv8i8,
    VSHLuv16i8,
    VSHLuv1i64,
    VSHLuv2i32,
    VSHLuv2i64,
    VSHLuv4i16,
    VSHLuv4i32,
    VSHLuv8i16,
    VSHLuv8i8,
    VSHRNv2i32,
    VSHRNv4i16,
    VSHRNv8i8,
    VSHRsv16i8,
    VSHRsv1i64,
    VSHRsv2i32,
    VSHRsv2i64,
    VSHRsv4i16,
    VSHRsv4i32,
    VSHRsv8i16,
    VSHRsv8i8,
    VSHRuv16i8,
    VSHRuv1i64,
    VSHRuv2i32,
    VSHRuv2i64,
    VSHRuv4i16,
    VSHRuv4i32,
    VSHRuv8i16,
    VSHRuv8i8,
    VSHTOD,
    VSHTOH,
    VSHTOS,
    VSITOD,
    VSITOH,
    VSITOS,
    VSLIv16i8,
    VSLIv1i64,
    VSLIv2i32,
    VSLIv2i64,
    VSLIv4i16,
    VSLIv4i32,
    VSLIv8i16,
    VSLIv8i8,
    VSLTOD,
    VSLTOH,
    VSLTOS,
    VSMMLA,
    VSQRTD,
    VSQRTH,
    VSQRTS,
    VSRAsv16i8,
    VSRAsv1i64,
    VSRAsv2i32,
    VSRAsv2i64,
    VSRAsv4i16,
    VSRAsv4i32,
    VSRAsv8i16,
    VSRAsv8i8,
    VSRAuv16i8,
    VSRAuv1i64,
    VSRAuv2i32,
    VSRAuv2i64,
    VSRAuv4i16,
    VSRAuv4i32,
    VSRAuv8i16,
    VSRAuv8i8,
    VSRIv16i8,
    VSRIv1i64,
    VSRIv2i32,
    VSRIv2i64,
    VSRIv4i16,
    VSRIv4i32,
    VSRIv8i16,
    VSRIv8i8,
    VST1LNd16,
    VST1LNd16_UPD,
    VST1LNd32,
    VST1LNd32_UPD,
    VST1LNd8,
    VST1LNd8_UPD,
    VST1LNq16Pseudo,
    VST1LNq16Pseudo_UPD,
    VST1LNq32Pseudo,
    VST1LNq32Pseudo_UPD,
    VST1LNq8Pseudo,
    VST1LNq8Pseudo_UPD,
    VST1d16,
    VST1d16Q,
    VST1d16QPseudo,
    VST1d16QPseudoWB_fixed,
    VST1d16QPseudoWB_register,
    VST1d16Qwb_fixed,
    VST1d16Qwb_register,
    VST1d16T,
    VST1d16TPseudo,
    VST1d16TPseudoWB_fixed,
    VST1d16TPseudoWB_register,
    VST1d16Twb_fixed,
    VST1d16Twb_register,
    VST1d16wb_fixed,
    VST1d16wb_register,
    VST1d32,
    VST1d32Q,
    VST1d32QPseudo,
    VST1d32QPseudoWB_fixed,
    VST1d32QPseudoWB_register,
    VST1d32Qwb_fixed,
    VST1d32Qwb_register,
    VST1d32T,
    VST1d32TPseudo,
    VST1d32TPseudoWB_fixed,
    VST1d32TPseudoWB_register,
    VST1d32Twb_fixed,
    VST1d32Twb_register,
    VST1d32wb_fixed,
    VST1d32wb_register,
    VST1d64,
    VST1d64Q,
    VST1d64QPseudo,
    VST1d64QPseudoWB_fixed,
    VST1d64QPseudoWB_register,
    VST1d64Qwb_fixed,
    VST1d64Qwb_register,
    VST1d64T,
    VST1d64TPseudo,
    VST1d64TPseudoWB_fixed,
    VST1d64TPseudoWB_register,
    VST1d64Twb_fixed,
    VST1d64Twb_register,
    VST1d64wb_fixed,
    VST1d64wb_register,
    VST1d8,
    VST1d8Q,
    VST1d8QPseudo,
    VST1d8QPseudoWB_fixed,
    VST1d8QPseudoWB_register,
    VST1d8Qwb_fixed,
    VST1d8Qwb_register,
    VST1d8T,
    VST1d8TPseudo,
    VST1d8TPseudoWB_fixed,
    VST1d8TPseudoWB_register,
    VST1d8Twb_fixed,
    VST1d8Twb_register,
    VST1d8wb_fixed,
    VST1d8wb_register,
    VST1q16,
    VST1q16HighQPseudo,
    VST1q16HighQPseudo_UPD,
    VST1q16HighTPseudo,
    VST1q16HighTPseudo_UPD,
    VST1q16LowQPseudo_UPD,
    VST1q16LowTPseudo_UPD,
    VST1q16wb_fixed,
    VST1q16wb_register,
    VST1q32,
    VST1q32HighQPseudo,
    VST1q32HighQPseudo_UPD,
    VST1q32HighTPseudo,
    VST1q32HighTPseudo_UPD,
    VST1q32LowQPseudo_UPD,
    VST1q32LowTPseudo_UPD,
    VST1q32wb_fixed,
    VST1q32wb_register,
    VST1q64,
    VST1q64HighQPseudo,
    VST1q64HighQPseudo_UPD,
    VST1q64HighTPseudo,
    VST1q64HighTPseudo_UPD,
    VST1q64LowQPseudo_UPD,
    VST1q64LowTPseudo_UPD,
    VST1q64wb_fixed,
    VST1q64wb_register,
    VST1q8,
    VST1q8HighQPseudo,
    VST1q8HighQPseudo_UPD,
    VST1q8HighTPseudo,
    VST1q8HighTPseudo_UPD,
    VST1q8LowQPseudo_UPD,
    VST1q8LowTPseudo_UPD,
    VST1q8wb_fixed,
    VST1q8wb_register,
    VST2LNd16,
    VST2LNd16Pseudo,
    VST2LNd16Pseudo_UPD,
    VST2LNd16_UPD,
    VST2LNd32,
    VST2LNd32Pseudo,
    VST2LNd32Pseudo_UPD,
    VST2LNd32_UPD,
    VST2LNd8,
    VST2LNd8Pseudo,
    VST2LNd8Pseudo_UPD,
    VST2LNd8_UPD,
    VST2LNq16,
    VST2LNq16Pseudo,
    VST2LNq16Pseudo_UPD,
    VST2LNq16_UPD,
    VST2LNq32,
    VST2LNq32Pseudo,
    VST2LNq32Pseudo_UPD,
    VST2LNq32_UPD,
    VST2b16,
    VST2b16wb_fixed,
    VST2b16wb_register,
    VST2b32,
    VST2b32wb_fixed,
    VST2b32wb_register,
    VST2b8,
    VST2b8wb_fixed,
    VST2b8wb_register,
    VST2d16,
    VST2d16wb_fixed,
    VST2d16wb_register,
    VST2d32,
    VST2d32wb_fixed,
    VST2d32wb_register,
    VST2d8,
    VST2d8wb_fixed,
    VST2d8wb_register,
    VST2q16,
    VST2q16Pseudo,
    VST2q16PseudoWB_fixed,
    VST2q16PseudoWB_register,
    VST2q16wb_fixed,
    VST2q16wb_register,
    VST2q32,
    VST2q32Pseudo,
    VST2q32PseudoWB_fixed,
    VST2q32PseudoWB_register,
    VST2q32wb_fixed,
    VST2q32wb_register,
    VST2q8,
    VST2q8Pseudo,
    VST2q8PseudoWB_fixed,
    VST2q8PseudoWB_register,
    VST2q8wb_fixed,
    VST2q8wb_register,
    VST3LNd16,
    VST3LNd16Pseudo,
    VST3LNd16Pseudo_UPD,
    VST3LNd16_UPD,
    VST3LNd32,
    VST3LNd32Pseudo,
    VST3LNd32Pseudo_UPD,
    VST3LNd32_UPD,
    VST3LNd8,
    VST3LNd8Pseudo,
    VST3LNd8Pseudo_UPD,
    VST3LNd8_UPD,
    VST3LNq16,
    VST3LNq16Pseudo,
    VST3LNq16Pseudo_UPD,
    VST3LNq16_UPD,
    VST3LNq32,
    VST3LNq32Pseudo,
    VST3LNq32Pseudo_UPD,
    VST3LNq32_UPD,
    VST3d16,
    VST3d16Pseudo,
    VST3d16Pseudo_UPD,
    VST3d16_UPD,
    VST3d32,
    VST3d32Pseudo,
    VST3d32Pseudo_UPD,
    VST3d32_UPD,
    VST3d8,
    VST3d8Pseudo,
    VST3d8Pseudo_UPD,
    VST3d8_UPD,
    VST3q16,
    VST3q16Pseudo_UPD,
    VST3q16_UPD,
    VST3q16oddPseudo,
    VST3q16oddPseudo_UPD,
    VST3q32,
    VST3q32Pseudo_UPD,
    VST3q32_UPD,
    VST3q32oddPseudo,
    VST3q32oddPseudo_UPD,
    VST3q8,
    VST3q8Pseudo_UPD,
    VST3q8_UPD,
    VST3q8oddPseudo,
    VST3q8oddPseudo_UPD,
    VST4LNd16,
    VST4LNd16Pseudo,
    VST4LNd16Pseudo_UPD,
    VST4LNd16_UPD,
    VST4LNd32,
    VST4LNd32Pseudo,
    VST4LNd32Pseudo_UPD,
    VST4LNd32_UPD,
    VST4LNd8,
    VST4LNd8Pseudo,
    VST4LNd8Pseudo_UPD,
    VST4LNd8_UPD,
    VST4LNq16,
    VST4LNq16Pseudo,
    VST4LNq16Pseudo_UPD,
    VST4LNq16_UPD,
    VST4LNq32,
    VST4LNq32Pseudo,
    VST4LNq32Pseudo_UPD,
    VST4LNq32_UPD,
    VST4d16,
    VST4d16Pseudo,
    VST4d16Pseudo_UPD,
    VST4d16_UPD,
    VST4d32,
    VST4d32Pseudo,
    VST4d32Pseudo_UPD,
    VST4d32_UPD,
    VST4d8,
    VST4d8Pseudo,
    VST4d8Pseudo_UPD,
    VST4d8_UPD,
    VST4q16,
    VST4q16Pseudo_UPD,
    VST4q16_UPD,
    VST4q16oddPseudo,
    VST4q16oddPseudo_UPD,
    VST4q32,
    VST4q32Pseudo_UPD,
    VST4q32_UPD,
    VST4q32oddPseudo,
    VST4q32oddPseudo_UPD,
    VST4q8,
    VST4q8Pseudo_UPD,
    VST4q8_UPD,
    VST4q8oddPseudo,
    VST4q8oddPseudo_UPD,
    VSTMDDB_UPD,
    VSTMDIA,
    VSTMDIA_UPD,
    VSTMQIA,
    VSTMSDB_UPD,
    VSTMSIA,
    VSTMSIA_UPD,
    VSTRD,
    VSTRH,
    VSTRS,
    VSTR_FPCXTNS_off,
    VSTR_FPCXTNS_post,
    VSTR_FPCXTNS_pre,
    VSTR_FPCXTS_off,
    VSTR_FPCXTS_post,
    VSTR_FPCXTS_pre,
    VSTR_FPSCR_NZCVQC_off,
    VSTR_FPSCR_NZCVQC_post,
    VSTR_FPSCR_NZCVQC_pre,
    VSTR_FPSCR_off,
    VSTR_FPSCR_post,
    VSTR_FPSCR_pre,
    VSTR_P0_off,
    VSTR_P0_post,
    VSTR_P0_pre,
    VSTR_VPR_off,
    VSTR_VPR_post,
    VSTR_VPR_pre,
    VSUBD,
    VSUBH,
    VSUBHNv2i32,
    VSUBHNv4i16,
    VSUBHNv8i8,
    VSUBLsv2i64,
    VSUBLsv4i32,
    VSUBLsv8i16,
    VSUBLuv2i64,
    VSUBLuv4i32,
    VSUBLuv8i16,
    VSUBS,
    VSUBWsv2i64,
    VSUBWsv4i32,
    VSUBWsv8i16,
    VSUBWuv2i64,
    VSUBWuv4i32,
    VSUBWuv8i16,
    VSUBfd,
    VSUBfq,
    VSUBhd,
    VSUBhq,
    VSUBv16i8,
    VSUBv1i64,
    VSUBv2i32,
    VSUBv2i64,
    VSUBv4i16,
    VSUBv4i32,
    VSUBv8i16,
    VSUBv8i8,
    VSUDOTDI,
    VSUDOTQI,
    VSWPd,
    VSWPq,
    VTBL1,
    VTBL2,
    VTBL3,
    VTBL3Pseudo,
    VTBL4,
    VTBL4Pseudo,
    VTBX1,
    VTBX2,
    VTBX3,
    VTBX3Pseudo,
    VTBX4,
    VTBX4Pseudo,
    VTOSHD,
    VTOSHH,
    VTOSHS,
    VTOSIRD,
    VTOSIRH,
    VTOSIRS,
    VTOSIZD,
    VTOSIZH,
    VTOSIZS,
    VTOSLD,
    VTOSLH,
    VTOSLS,
    VTOUHD,
    VTOUHH,
    VTOUHS,
    VTOUIRD,
    VTOUIRH,
    VTOUIRS,
    VTOUIZD,
    VTOUIZH,
    VTOUIZS,
    VTOULD,
    VTOULH,
    VTOULS,
    VTRNd16,
    VTRNd32,
    VTRNd8,
    VTRNq16,
    VTRNq32,
    VTRNq8,
    VTSTv16i8,
    VTSTv2i32,
    VTSTv4i16,
    VTSTv4i32,
    VTSTv8i16,
    VTSTv8i8,
    VUDOTD,
    VUDOTDI,
    VUDOTQ,
    VUDOTQI,
    VUHTOD,
    VUHTOH,
    VUHTOS,
    VUITOD,
    VUITOH,
    VUITOS,
    VULTOD,
    VULTOH,
    VULTOS,
    VUMMLA,
    VUSDOTD,
    VUSDOTDI,
    VUSDOTQ,
    VUSDOTQI,
    VUSMMLA,
    VUZPd16,
    VUZPd8,
    VUZPq16,
    VUZPq32,
    VUZPq8,
    VZIPd16,
    VZIPd8,
    VZIPq16,
    VZIPq32,
    VZIPq8,
    sysLDMDA,
    sysLDMDA_UPD,
    sysLDMDB,
    sysLDMDB_UPD,
    sysLDMIA,
    sysLDMIA_UPD,
    sysLDMIB,
    sysLDMIB_UPD,
    sysSTMDA,
    sysSTMDA_UPD,
    sysSTMDB,
    sysSTMDB_UPD,
    sysSTMIA,
    sysSTMIA_UPD,
    sysSTMIB,
    sysSTMIB_UPD,
    t2ADCri,
    t2ADCrr,
    t2ADCrs,
    t2ADDri,
    t2ADDri12,
    t2ADDrr,
    t2ADDrs,
    t2ADDspImm,
    t2ADDspImm12,
    t2ADR,
    t2ANDri,
    t2ANDrr,
    t2ANDrs,
    t2ASRri,
    t2ASRrr,
    t2AUT,
    t2AUTG,
    t2B,
    t2BFC,
    t2BFI,
    t2BFLi,
    t2BFLr,
    t2BFi,
    t2BFic,
    t2BFr,
    t2BICri,
    t2BICrr,
    t2BICrs,
    t2BTI,
    t2BXAUT,
    t2BXJ,
    t2Bcc,
    t2CDP,
    t2CDP2,
    t2CLREX,
    t2CLRM,
    t2CLZ,
    t2CMNri,
    t2CMNzrr,
    t2CMNzrs,
    t2CMPri,
    t2CMPrr,
    t2CMPrs,
    t2CPS1p,
    t2CPS2p,
    t2CPS3p,
    t2CRC32B,
    t2CRC32CB,
    t2CRC32CH,
    t2CRC32CW,
    t2CRC32H,
    t2CRC32W,
    t2CSEL,
    t2CSINC,
    t2CSINV,
    t2CSNEG,
    t2DBG,
    t2DCPS1,
    t2DCPS2,
    t2DCPS3,
    t2DLS,
    t2DMB,
    t2DSB,
    t2EORri,
    t2EORrr,
    t2EORrs,
    t2HINT,
    t2HVC,
    t2ISB,
    t2IT,
    t2Int_eh_sjlj_setjmp,
    t2Int_eh_sjlj_setjmp_nofp,
    t2LDA,
    t2LDAB,
    t2LDAEX,
    t2LDAEXB,
    t2LDAEXD,
    t2LDAEXH,
    t2LDAH,
    t2LDC2L_OFFSET,
    t2LDC2L_OPTION,
    t2LDC2L_POST,
    t2LDC2L_PRE,
    t2LDC2_OFFSET,
    t2LDC2_OPTION,
    t2LDC2_POST,
    t2LDC2_PRE,
    t2LDCL_OFFSET,
    t2LDCL_OPTION,
    t2LDCL_POST,
    t2LDCL_PRE,
    t2LDC_OFFSET,
    t2LDC_OPTION,
    t2LDC_POST,
    t2LDC_PRE,
    t2LDMDB,
    t2LDMDB_UPD,
    t2LDMIA,
    t2LDMIA_UPD,
    t2LDRBT,
    t2LDRB_POST,
    t2LDRB_PRE,
    t2LDRBi12,
    t2LDRBi8,
    t2LDRBpci,
    t2LDRBs,
    t2LDRD_POST,
    t2LDRD_PRE,
    t2LDRDi8,
    t2LDREX,
    t2LDREXB,
    t2LDREXD,
    t2LDREXH,
    t2LDRHT,
    t2LDRH_POST,
    t2LDRH_PRE,
    t2LDRHi12,
    t2LDRHi8,
    t2LDRHpci,
    t2LDRHs,
    t2LDRSBT,
    t2LDRSB_POST,
    t2LDRSB_PRE,
    t2LDRSBi12,
    t2LDRSBi8,
    t2LDRSBpci,
    t2LDRSBs,
    t2LDRSHT,
    t2LDRSH_POST,
    t2LDRSH_PRE,
    t2LDRSHi12,
    t2LDRSHi8,
    t2LDRSHpci,
    t2LDRSHs,
    t2LDRT,
    t2LDR_POST,
    t2LDR_PRE,
    t2LDRi12,
    t2LDRi8,
    t2LDRpci,
    t2LDRs,
    t2LE,
    t2LEUpdate,
    t2LSLri,
    t2LSLrr,
    t2LSRri,
    t2LSRrr,
    t2MCR,
    t2MCR2,
    t2MCRR,
    t2MCRR2,
    t2MLA,
    t2MLS,
    t2MOVTi16,
    t2MOVi,
    t2MOVi16,
    t2MOVr,
    t2MOVsra_glue,
    t2MOVsrl_glue,
    t2MRC,
    t2MRC2,
    t2MRRC,
    t2MRRC2,
    t2MRS_AR,
    t2MRS_M,
    t2MRSbanked,
    t2MRSsys_AR,
    t2MSR_AR,
    t2MSR_M,
    t2MSRbanked,
    t2MUL,
    t2MVNi,
    t2MVNr,
    t2MVNs,
    t2ORNri,
    t2ORNrr,
    t2ORNrs,
    t2ORRri,
    t2ORRrr,
    t2ORRrs,
    t2PAC,
    t2PACBTI,
    t2PACG,
    t2PKHBT,
    t2PKHTB,
    t2PLDWi12,
    t2PLDWi8,
    t2PLDWs,
    t2PLDi12,
    t2PLDi8,
    t2PLDpci,
    t2PLDs,
    t2PLIi12,
    t2PLIi8,
    t2PLIpci,
    t2PLIs,
    t2QADD,
    t2QADD16,
    t2QADD8,
    t2QASX,
    t2QDADD,
    t2QDSUB,
    t2QSAX,
    t2QSUB,
    t2QSUB16,
    t2QSUB8,
    t2RBIT,
    t2REV,
    t2REV16,
    t2REVSH,
    t2RFEDB,
    t2RFEDBW,
    t2RFEIA,
    t2RFEIAW,
    t2RORri,
    t2RORrr,
    t2RRX,
    t2RSBri,
    t2RSBrr,
    t2RSBrs,
    t2SADD16,
    t2SADD8,
    t2SASX,
    t2SB,
    t2SBCri,
    t2SBCrr,
    t2SBCrs,
    t2SBFX,
    t2SDIV,
    t2SEL,
    t2SETPAN,
    t2SG,
    t2SHADD16,
    t2SHADD8,
    t2SHASX,
    t2SHSAX,
    t2SHSUB16,
    t2SHSUB8,
    t2SMC,
    t2SMLABB,
    t2SMLABT,
    t2SMLAD,
    t2SMLADX,
    t2SMLAL,
    t2SMLALBB,
    t2SMLALBT,
    t2SMLALD,
    t2SMLALDX,
    t2SMLALTB,
    t2SMLALTT,
    t2SMLATB,
    t2SMLATT,
    t2SMLAWB,
    t2SMLAWT,
    t2SMLSD,
    t2SMLSDX,
    t2SMLSLD,
    t2SMLSLDX,
    t2SMMLA,
    t2SMMLAR,
    t2SMMLS,
    t2SMMLSR,
    t2SMMUL,
    t2SMMULR,
    t2SMUAD,
    t2SMUADX,
    t2SMULBB,
    t2SMULBT,
    t2SMULL,
    t2SMULTB,
    t2SMULTT,
    t2SMULWB,
    t2SMULWT,
    t2SMUSD,
    t2SMUSDX,
    t2SRSDB,
    t2SRSDB_UPD,
    t2SRSIA,
    t2SRSIA_UPD,
    t2SSAT,
    t2SSAT16,
    t2SSAX,
    t2SSUB16,
    t2SSUB8,
    t2STC2L_OFFSET,
    t2STC2L_OPTION,
    t2STC2L_POST,
    t2STC2L_PRE,
    t2STC2_OFFSET,
    t2STC2_OPTION,
    t2STC2_POST,
    t2STC2_PRE,
    t2STCL_OFFSET,
    t2STCL_OPTION,
    t2STCL_POST,
    t2STCL_PRE,
    t2STC_OFFSET,
    t2STC_OPTION,
    t2STC_POST,
    t2STC_PRE,
    t2STL,
    t2STLB,
    t2STLEX,
    t2STLEXB,
    t2STLEXD,
    t2STLEXH,
    t2STLH,
    t2STMDB,
    t2STMDB_UPD,
    t2STMIA,
    t2STMIA_UPD,
    t2STRBT,
    t2STRB_POST,
    t2STRB_PRE,
    t2STRBi12,
    t2STRBi8,
    t2STRBs,
    t2STRD_POST,
    t2STRD_PRE,
    t2STRDi8,
    t2STREX,
    t2STREXB,
    t2STREXD,
    t2STREXH,
    t2STRHT,
    t2STRH_POST,
    t2STRH_PRE,
    t2STRHi12,
    t2STRHi8,
    t2STRHs,
    t2STRT,
    t2STR_POST,
    t2STR_PRE,
    t2STRi12,
    t2STRi8,
    t2STRs,
    t2SUBS_PC_LR,
    t2SUBri,
    t2SUBri12,
    t2SUBrr,
    t2SUBrs,
    t2SUBspImm,
    t2SUBspImm12,
    t2SXTAB,
    t2SXTAB16,
    t2SXTAH,
    t2SXTB,
    t2SXTB16,
    t2SXTH,
    t2TBB,
    t2TBH,
    t2TEQri,
    t2TEQrr,
    t2TEQrs,
    t2TSB,
    t2TSTri,
    t2TSTrr,
    t2TSTrs,
    t2TT,
    t2TTA,
    t2TTAT,
    t2TTT,
    t2UADD16,
    t2UADD8,
    t2UASX,
    t2UBFX,
    t2UDF,
    t2UDIV,
    t2UHADD16,
    t2UHADD8,
    t2UHASX,
    t2UHSAX,
    t2UHSUB16,
    t2UHSUB8,
    t2UMAAL,
    t2UMLAL,
    t2UMULL,
    t2UQADD16,
    t2UQADD8,
    t2UQASX,
    t2UQSAX,
    t2UQSUB16,
    t2UQSUB8,
    t2USAD8,
    t2USADA8,
    t2USAT,
    t2USAT16,
    t2USAX,
    t2USUB16,
    t2USUB8,
    t2UXTAB,
    t2UXTAB16,
    t2UXTAH,
    t2UXTB,
    t2UXTB16,
    t2UXTH,
    t2WLS,
    tADC,
    tADDhirr,
    tADDi3,
    tADDi8,
    tADDrSP,
    tADDrSPi,
    tADDrr,
    tADDspi,
    tADDspr,
    tADR,
    tAND,
    tASRri,
    tASRrr,
    tB,
    tBIC,
    tBKPT,
    tBL,
    tBLXNSr,
    tBLXi,
    tBLXr,
    tBX,
    tBXNS,
    tBcc,
    tCBNZ,
    tCBZ,
    tCMNz,
    tCMPhir,
    tCMPi8,
    tCMPr,
    tCPS,
    tEOR,
    tHINT,
    tHLT,
    tInt_WIN_eh_sjlj_longjmp,
    tInt_eh_sjlj_longjmp,
    tInt_eh_sjlj_setjmp,
    tLDMIA,
    tLDRBi,
    tLDRBr,
    tLDRHi,
    tLDRHr,
    tLDRSB,
    tLDRSH,
    tLDRi,
    tLDRpci,
    tLDRr,
    tLDRspi,
    tLSLri,
    tLSLrr,
    tLSRri,
    tLSRrr,
    tMOVSr,
    tMOVi8,
    tMOVr,
    tMUL,
    tMVN,
    tORR,
    tPICADD,
    tPOP,
    tPUSH,
    tREV,
    tREV16,
    tREVSH,
    tROR,
    tRSB,
    tSBC,
    tSETEND,
    tSTMIA_UPD,
    tSTRBi,
    tSTRBr,
    tSTRHi,
    tSTRHr,
    tSTRi,
    tSTRr,
    tSTRspi,
    tSUBi3,
    tSUBi8,
    tSUBrr,
    tSUBspi,
    tSVC,
    tSXTB,
    tSXTH,
    tTRAP,
    tTST,
    tUDF,
    tUXTB,
    tUXTH,
    t__brkdiv0,
    INSTRUCTION_LIST_END,
    UNKNOWN(u64),
}

Variants

PHI

INLINEASM

INLINEASM_BR

CFI_INSTRUCTION

EH_LABEL

GC_LABEL

ANNOTATION_LABEL

KILL

EXTRACT_SUBREG

INSERT_SUBREG

IMPLICIT_DEF

SUBREG_TO_REG

COPY_TO_REGCLASS

DBG_VALUE

DBG_VALUE_LIST

DBG_INSTR_REF

DBG_PHI

DBG_LABEL

REG_SEQUENCE

COPY

BUNDLE

LIFETIME_START

LIFETIME_END

PSEUDO_PROBE

ARITH_FENCE

STACKMAP

FENTRY_CALL

PATCHPOINT

LOAD_STACK_GUARD

PREALLOCATED_SETUP

PREALLOCATED_ARG

STATEPOINT

LOCAL_ESCAPE

FAULTING_OP

PATCHABLE_OP

PATCHABLE_FUNCTION_ENTER

PATCHABLE_RET

PATCHABLE_FUNCTION_EXIT

PATCHABLE_TAIL_CALL

PATCHABLE_EVENT_CALL

PATCHABLE_TYPED_EVENT_CALL

ICALL_BRANCH_FUNNEL

MEMBARRIER

JUMP_TABLE_DEBUG_INFO

CONVERGENCECTRL_ENTRY

CONVERGENCECTRL_ANCHOR

CONVERGENCECTRL_LOOP

CONVERGENCECTRL_GLUE

G_ASSERT_SEXT

G_ASSERT_ZEXT

G_ASSERT_ALIGN

G_ADD

G_SUB

G_MUL

G_SDIV

G_UDIV

G_SREM

G_UREM

G_SDIVREM

G_UDIVREM

G_AND

G_OR

G_XOR

G_IMPLICIT_DEF

G_PHI

G_FRAME_INDEX

G_GLOBAL_VALUE

G_PTRAUTH_GLOBAL_VALUE

G_CONSTANT_POOL

G_EXTRACT

G_UNMERGE_VALUES

G_INSERT

G_MERGE_VALUES

G_BUILD_VECTOR

G_BUILD_VECTOR_TRUNC

G_CONCAT_VECTORS

G_PTRTOINT

G_INTTOPTR

G_BITCAST

G_FREEZE

G_CONSTANT_FOLD_BARRIER

G_INTRINSIC_FPTRUNC_ROUND

G_INTRINSIC_TRUNC

G_INTRINSIC_ROUND

G_INTRINSIC_LRINT

G_INTRINSIC_LLRINT

G_INTRINSIC_ROUNDEVEN

G_READCYCLECOUNTER

G_READSTEADYCOUNTER

G_LOAD

G_SEXTLOAD

G_ZEXTLOAD

G_INDEXED_LOAD

G_INDEXED_SEXTLOAD

G_INDEXED_ZEXTLOAD

G_STORE

G_INDEXED_STORE

G_ATOMIC_CMPXCHG_WITH_SUCCESS

G_ATOMIC_CMPXCHG

G_ATOMICRMW_XCHG

G_ATOMICRMW_ADD

G_ATOMICRMW_SUB

G_ATOMICRMW_AND

G_ATOMICRMW_NAND

G_ATOMICRMW_OR

G_ATOMICRMW_XOR

G_ATOMICRMW_MAX

G_ATOMICRMW_MIN

G_ATOMICRMW_UMAX

G_ATOMICRMW_UMIN

G_ATOMICRMW_FADD

G_ATOMICRMW_FSUB

G_ATOMICRMW_FMAX

G_ATOMICRMW_FMIN

G_ATOMICRMW_UINC_WRAP

G_ATOMICRMW_UDEC_WRAP

G_FENCE

G_PREFETCH

G_BRCOND

G_BRINDIRECT

G_INVOKE_REGION_START

G_INTRINSIC

G_INTRINSIC_W_SIDE_EFFECTS

G_INTRINSIC_CONVERGENT

G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS

G_ANYEXT

G_TRUNC

G_CONSTANT

G_FCONSTANT

G_VASTART

G_VAARG

G_SEXT

G_SEXT_INREG

G_ZEXT

G_SHL

G_LSHR

G_ASHR

G_FSHL

G_FSHR

G_ROTR

G_ROTL

G_ICMP

G_FCMP

G_SCMP

G_UCMP

G_SELECT

G_UADDO

G_UADDE

G_USUBO

G_USUBE

G_SADDO

G_SADDE

G_SSUBO

G_SSUBE

G_UMULO

G_SMULO

G_UMULH

G_SMULH

G_UADDSAT

G_SADDSAT

G_USUBSAT

G_SSUBSAT

G_USHLSAT

G_SSHLSAT

G_SMULFIX

G_UMULFIX

G_SMULFIXSAT

G_UMULFIXSAT

G_SDIVFIX

G_UDIVFIX

G_SDIVFIXSAT

G_UDIVFIXSAT

G_FADD

G_FSUB

G_FMUL

G_FMA

G_FMAD

G_FDIV

G_FREM

G_FPOW

G_FPOWI

G_FEXP

G_FEXP2

G_FEXP10

G_FLOG

G_FLOG2

G_FLOG10

G_FLDEXP

G_FFREXP

G_FNEG

G_FPEXT

G_FPTRUNC

G_FPTOSI

G_FPTOUI

G_SITOFP

G_UITOFP

G_FABS

G_FCOPYSIGN

G_IS_FPCLASS

G_FCANONICALIZE

G_FMINNUM

G_FMAXNUM

G_FMINNUM_IEEE

G_FMAXNUM_IEEE

G_FMINIMUM

G_FMAXIMUM

G_GET_FPENV

G_SET_FPENV

G_RESET_FPENV

G_GET_FPMODE

G_SET_FPMODE

G_RESET_FPMODE

G_PTR_ADD

G_PTRMASK

G_SMIN

G_SMAX

G_UMIN

G_UMAX

G_ABS

G_LROUND

G_LLROUND

G_BR

G_BRJT

G_VSCALE

G_INSERT_SUBVECTOR

G_EXTRACT_SUBVECTOR

G_INSERT_VECTOR_ELT

G_EXTRACT_VECTOR_ELT

G_SHUFFLE_VECTOR

G_SPLAT_VECTOR

G_VECTOR_COMPRESS

G_CTTZ

G_CTTZ_ZERO_UNDEF

G_CTLZ

G_CTLZ_ZERO_UNDEF

G_CTPOP

G_BSWAP

G_BITREVERSE

G_FCEIL

G_FCOS

G_FSIN

G_FTAN

G_FACOS

G_FASIN

G_FATAN

G_FCOSH

G_FSINH

G_FTANH

G_FSQRT

G_FFLOOR

G_FRINT

G_FNEARBYINT

G_ADDRSPACE_CAST

G_BLOCK_ADDR

G_JUMP_TABLE

G_DYN_STACKALLOC

G_STACKSAVE

G_STACKRESTORE

G_STRICT_FADD

G_STRICT_FSUB

G_STRICT_FMUL

G_STRICT_FDIV

G_STRICT_FREM

G_STRICT_FMA

G_STRICT_FSQRT

G_STRICT_FLDEXP

G_READ_REGISTER

G_WRITE_REGISTER

G_MEMCPY

G_MEMCPY_INLINE

G_MEMMOVE

G_MEMSET

G_BZERO

G_TRAP

G_DEBUGTRAP

G_UBSANTRAP

G_VECREDUCE_SEQ_FADD

G_VECREDUCE_SEQ_FMUL

G_VECREDUCE_FADD

G_VECREDUCE_FMUL

G_VECREDUCE_FMAX

G_VECREDUCE_FMIN

G_VECREDUCE_FMAXIMUM

G_VECREDUCE_FMINIMUM

G_VECREDUCE_ADD

G_VECREDUCE_MUL

G_VECREDUCE_AND

G_VECREDUCE_OR

G_VECREDUCE_XOR

G_VECREDUCE_SMAX

G_VECREDUCE_SMIN

G_VECREDUCE_UMAX

G_VECREDUCE_UMIN

G_SBFX

G_UBFX

ABS

ADDSri

ADDSrr

ADDSrsi

ADDSrsr

ADJCALLSTACKDOWN

ADJCALLSTACKUP

ASRi

ASRr

B

BCCZi64

BCCi64

BLX_noip

BLX_pred_noip

BL_PUSHLR

BMOVPCB_CALL

BMOVPCRX_CALL

BR_JTadd

BR_JTm_i12

BR_JTm_rs

BR_JTr

BX_CALL

CMP_SWAP_16

CMP_SWAP_32

CMP_SWAP_64

CMP_SWAP_8

CONSTPOOL_ENTRY

COPY_STRUCT_BYVAL_I32

ITasm

Int_eh_sjlj_dispatchsetup

Int_eh_sjlj_longjmp

Int_eh_sjlj_setjmp

Int_eh_sjlj_setjmp_nofp

Int_eh_sjlj_setup_dispatch

JUMPTABLE_ADDRS

JUMPTABLE_INSTS

JUMPTABLE_TBB

JUMPTABLE_TBH

LDMIA_RET

LDRBT_POST

LDRConstPool

LDRHTii

LDRLIT_ga_abs

LDRLIT_ga_pcrel

LDRLIT_ga_pcrel_ldr

LDRSBTii

LDRSHTii

LDRT_POST

LEApcrel

LEApcrelJT

LOADDUAL

LSLi

LSLr

LSRi

LSRr

MEMCPY

MLAv5

MOVCCi

MOVCCi16

MOVCCi32imm

MOVCCr

MOVCCsi

MOVCCsr

MOVPCRX

MOVTi16_ga_pcrel

MOV_ga_pcrel

MOV_ga_pcrel_ldr

MOVi16_ga_pcrel

MOVi32imm

MOVsra_glue

MOVsrl_glue

MQPRCopy

MQQPRLoad

MQQPRStore

MQQQQPRLoad

MQQQQPRStore

MULv5

MVE_MEMCPYLOOPINST

MVE_MEMSETLOOPINST

MVNCCi

PICADD

PICLDR

PICLDRB

PICLDRH

PICLDRSB

PICLDRSH

PICSTR

PICSTRB

PICSTRH

PseudoARMInitUndefDPR_VFP2

PseudoARMInitUndefGPR

PseudoARMInitUndefMQPR

PseudoARMInitUndefSPR

RORi

RORr

RRX

RRXi

RSBSri

RSBSrsi

RSBSrsr

SEH_EpilogEnd

SEH_EpilogStart

SEH_Nop

SEH_Nop_Ret

SEH_PrologEnd

SEH_SaveFRegs

SEH_SaveLR

SEH_SaveRegs

SEH_SaveRegs_Ret

SEH_SaveSP

SEH_StackAlloc

SMLALv5

SMULLv5

SPACE

STOREDUAL

STRBT_POST

STRBi_preidx

STRBr_preidx

STRH_preidx

STRT_POST

STRi_preidx

STRr_preidx

SUBS_PC_LR

SUBSri

SUBSrr

SUBSrsi

SUBSrsr

SpeculationBarrierISBDSBEndBB

SpeculationBarrierSBEndBB

TAILJMPd

TAILJMPr

TAILJMPr4

TCRETURNdi

TCRETURNri

TCRETURNrinotr12

TPsoft

UMLALv5

UMULLv5

VLD1LNdAsm_16

VLD1LNdAsm_32

VLD1LNdAsm_8

VLD1LNdWB_fixed_Asm_16

VLD1LNdWB_fixed_Asm_32

VLD1LNdWB_fixed_Asm_8

VLD1LNdWB_register_Asm_16

VLD1LNdWB_register_Asm_32

VLD1LNdWB_register_Asm_8

VLD2LNdAsm_16

VLD2LNdAsm_32

VLD2LNdAsm_8

VLD2LNdWB_fixed_Asm_16

VLD2LNdWB_fixed_Asm_32

VLD2LNdWB_fixed_Asm_8

VLD2LNdWB_register_Asm_16

VLD2LNdWB_register_Asm_32

VLD2LNdWB_register_Asm_8

VLD2LNqAsm_16

VLD2LNqAsm_32

VLD2LNqWB_fixed_Asm_16

VLD2LNqWB_fixed_Asm_32

VLD2LNqWB_register_Asm_16

VLD2LNqWB_register_Asm_32

VLD3DUPdAsm_16

VLD3DUPdAsm_32

VLD3DUPdAsm_8

VLD3DUPdWB_fixed_Asm_16

VLD3DUPdWB_fixed_Asm_32

VLD3DUPdWB_fixed_Asm_8

VLD3DUPdWB_register_Asm_16

VLD3DUPdWB_register_Asm_32

VLD3DUPdWB_register_Asm_8

VLD3DUPqAsm_16

VLD3DUPqAsm_32

VLD3DUPqAsm_8

VLD3DUPqWB_fixed_Asm_16

VLD3DUPqWB_fixed_Asm_32

VLD3DUPqWB_fixed_Asm_8

VLD3DUPqWB_register_Asm_16

VLD3DUPqWB_register_Asm_32

VLD3DUPqWB_register_Asm_8

VLD3LNdAsm_16

VLD3LNdAsm_32

VLD3LNdAsm_8

VLD3LNdWB_fixed_Asm_16

VLD3LNdWB_fixed_Asm_32

VLD3LNdWB_fixed_Asm_8

VLD3LNdWB_register_Asm_16

VLD3LNdWB_register_Asm_32

VLD3LNdWB_register_Asm_8

VLD3LNqAsm_16

VLD3LNqAsm_32

VLD3LNqWB_fixed_Asm_16

VLD3LNqWB_fixed_Asm_32

VLD3LNqWB_register_Asm_16

VLD3LNqWB_register_Asm_32

VLD3dAsm_16

VLD3dAsm_32

VLD3dAsm_8

VLD3dWB_fixed_Asm_16

VLD3dWB_fixed_Asm_32

VLD3dWB_fixed_Asm_8

VLD3dWB_register_Asm_16

VLD3dWB_register_Asm_32

VLD3dWB_register_Asm_8

VLD3qAsm_16

VLD3qAsm_32

VLD3qAsm_8

VLD3qWB_fixed_Asm_16

VLD3qWB_fixed_Asm_32

VLD3qWB_fixed_Asm_8

VLD3qWB_register_Asm_16

VLD3qWB_register_Asm_32

VLD3qWB_register_Asm_8

VLD4DUPdAsm_16

VLD4DUPdAsm_32

VLD4DUPdAsm_8

VLD4DUPdWB_fixed_Asm_16

VLD4DUPdWB_fixed_Asm_32

VLD4DUPdWB_fixed_Asm_8

VLD4DUPdWB_register_Asm_16

VLD4DUPdWB_register_Asm_32

VLD4DUPdWB_register_Asm_8

VLD4DUPqAsm_16

VLD4DUPqAsm_32

VLD4DUPqAsm_8

VLD4DUPqWB_fixed_Asm_16

VLD4DUPqWB_fixed_Asm_32

VLD4DUPqWB_fixed_Asm_8

VLD4DUPqWB_register_Asm_16

VLD4DUPqWB_register_Asm_32

VLD4DUPqWB_register_Asm_8

VLD4LNdAsm_16

VLD4LNdAsm_32

VLD4LNdAsm_8

VLD4LNdWB_fixed_Asm_16

VLD4LNdWB_fixed_Asm_32

VLD4LNdWB_fixed_Asm_8

VLD4LNdWB_register_Asm_16

VLD4LNdWB_register_Asm_32

VLD4LNdWB_register_Asm_8

VLD4LNqAsm_16

VLD4LNqAsm_32

VLD4LNqWB_fixed_Asm_16

VLD4LNqWB_fixed_Asm_32

VLD4LNqWB_register_Asm_16

VLD4LNqWB_register_Asm_32

VLD4dAsm_16

VLD4dAsm_32

VLD4dAsm_8

VLD4dWB_fixed_Asm_16

VLD4dWB_fixed_Asm_32

VLD4dWB_fixed_Asm_8

VLD4dWB_register_Asm_16

VLD4dWB_register_Asm_32

VLD4dWB_register_Asm_8

VLD4qAsm_16

VLD4qAsm_32

VLD4qAsm_8

VLD4qWB_fixed_Asm_16

VLD4qWB_fixed_Asm_32

VLD4qWB_fixed_Asm_8

VLD4qWB_register_Asm_16

VLD4qWB_register_Asm_32

VLD4qWB_register_Asm_8

VMOVD0

VMOVDcc

VMOVHcc

VMOVQ0

VMOVScc

VST1LNdAsm_16

VST1LNdAsm_32

VST1LNdAsm_8

VST1LNdWB_fixed_Asm_16

VST1LNdWB_fixed_Asm_32

VST1LNdWB_fixed_Asm_8

VST1LNdWB_register_Asm_16

VST1LNdWB_register_Asm_32

VST1LNdWB_register_Asm_8

VST2LNdAsm_16

VST2LNdAsm_32

VST2LNdAsm_8

VST2LNdWB_fixed_Asm_16

VST2LNdWB_fixed_Asm_32

VST2LNdWB_fixed_Asm_8

VST2LNdWB_register_Asm_16

VST2LNdWB_register_Asm_32

VST2LNdWB_register_Asm_8

VST2LNqAsm_16

VST2LNqAsm_32

VST2LNqWB_fixed_Asm_16

VST2LNqWB_fixed_Asm_32

VST2LNqWB_register_Asm_16

VST2LNqWB_register_Asm_32

VST3LNdAsm_16

VST3LNdAsm_32

VST3LNdAsm_8

VST3LNdWB_fixed_Asm_16

VST3LNdWB_fixed_Asm_32

VST3LNdWB_fixed_Asm_8

VST3LNdWB_register_Asm_16

VST3LNdWB_register_Asm_32

VST3LNdWB_register_Asm_8

VST3LNqAsm_16

VST3LNqAsm_32

VST3LNqWB_fixed_Asm_16

VST3LNqWB_fixed_Asm_32

VST3LNqWB_register_Asm_16

VST3LNqWB_register_Asm_32

VST3dAsm_16

VST3dAsm_32

VST3dAsm_8

VST3dWB_fixed_Asm_16

VST3dWB_fixed_Asm_32

VST3dWB_fixed_Asm_8

VST3dWB_register_Asm_16

VST3dWB_register_Asm_32

VST3dWB_register_Asm_8

VST3qAsm_16

VST3qAsm_32

VST3qAsm_8

VST3qWB_fixed_Asm_16

VST3qWB_fixed_Asm_32

VST3qWB_fixed_Asm_8

VST3qWB_register_Asm_16

VST3qWB_register_Asm_32

VST3qWB_register_Asm_8

VST4LNdAsm_16

VST4LNdAsm_32

VST4LNdAsm_8

VST4LNdWB_fixed_Asm_16

VST4LNdWB_fixed_Asm_32

VST4LNdWB_fixed_Asm_8

VST4LNdWB_register_Asm_16

VST4LNdWB_register_Asm_32

VST4LNdWB_register_Asm_8

VST4LNqAsm_16

VST4LNqAsm_32

VST4LNqWB_fixed_Asm_16

VST4LNqWB_fixed_Asm_32

VST4LNqWB_register_Asm_16

VST4LNqWB_register_Asm_32

VST4dAsm_16

VST4dAsm_32

VST4dAsm_8

VST4dWB_fixed_Asm_16

VST4dWB_fixed_Asm_32

VST4dWB_fixed_Asm_8

VST4dWB_register_Asm_16

VST4dWB_register_Asm_32

VST4dWB_register_Asm_8

VST4qAsm_16

VST4qAsm_32

VST4qAsm_8

VST4qWB_fixed_Asm_16

VST4qWB_fixed_Asm_32

VST4qWB_fixed_Asm_8

VST4qWB_register_Asm_16

VST4qWB_register_Asm_32

VST4qWB_register_Asm_8

WIN__CHKSTK

WIN__DBZCHK

t2ABS

t2ADDSri

t2ADDSrr

t2ADDSrs

t2BF_LabelPseudo

t2BR_JT

t2CALL_BTI

t2DoLoopStart

t2DoLoopStartTP

t2LDMIA_RET

t2LDRB_OFFSET_imm

t2LDRB_POST_imm

t2LDRB_PRE_imm

t2LDRBpcrel

t2LDRConstPool

t2LDRH_OFFSET_imm

t2LDRH_POST_imm

t2LDRH_PRE_imm

t2LDRHpcrel

t2LDRLIT_ga_pcrel

t2LDRSB_OFFSET_imm

t2LDRSB_POST_imm

t2LDRSB_PRE_imm

t2LDRSBpcrel

t2LDRSH_OFFSET_imm

t2LDRSH_POST_imm

t2LDRSH_PRE_imm

t2LDRSHpcrel

t2LDR_POST_imm

t2LDR_PRE_imm

t2LDRpci_pic

t2LDRpcrel

t2LEApcrel

t2LEApcrelJT

t2LoopDec

t2LoopEnd

t2LoopEndDec

t2MOVCCasr

t2MOVCCi

t2MOVCCi16

t2MOVCCi32imm

t2MOVCClsl

t2MOVCClsr

t2MOVCCr

t2MOVCCror

t2MOVSsi

t2MOVSsr

t2MOVTi16_ga_pcrel

t2MOV_ga_pcrel

t2MOVi16_ga_pcrel

t2MOVi32imm

t2MOVsi

t2MOVsr

t2MVNCCi

t2RSBSri

t2RSBSrs

t2STRB_OFFSET_imm

t2STRB_POST_imm

t2STRB_PRE_imm

t2STRB_preidx

t2STRH_OFFSET_imm

t2STRH_POST_imm

t2STRH_PRE_imm

t2STRH_preidx

t2STR_POST_imm

t2STR_PRE_imm

t2STR_preidx

t2SUBSri

t2SUBSrr

t2SUBSrs

t2SpeculationBarrierISBDSBEndBB

t2SpeculationBarrierSBEndBB

t2TBB_JT

t2TBH_JT

t2WhileLoopSetup

t2WhileLoopStart

t2WhileLoopStartLR

t2WhileLoopStartTP

tADCS

tADDSi3

tADDSi8

tADDSrr

tADDframe

tADJCALLSTACKDOWN

tADJCALLSTACKUP

tBLXNS_CALL

tBLXr_noip

tBL_PUSHLR

tBRIND

tBR_JTr

tBXNS_RET

tBX_CALL

tBX_RET

tBX_RET_vararg

tBfar

tCMP_SWAP_16

tCMP_SWAP_32

tCMP_SWAP_8

tLDMIA_UPD

tLDRConstPool

tLDRLIT_ga_abs

tLDRLIT_ga_pcrel

tLDR_postidx

tLDRpci_pic

tLEApcrel

tLEApcrelJT

tLSLSri

tMOVCCr_pseudo

tMOVi32imm

tPOP_RET

tRSBS

tSBCS

tSUBSi3

tSUBSi8

tSUBSrr

tTAILJMPd

tTAILJMPdND

tTAILJMPr

tTBB_JT

tTBH_JT

tTPsoft

ADCri

ADCrr

ADCrsi

ADCrsr

ADDri

ADDrr

ADDrsi

ADDrsr

ADR

AESD

AESE

AESIMC

AESMC

ANDri

ANDrr

ANDrsi

ANDrsr

BF16VDOTI_VDOTD

BF16VDOTI_VDOTQ

BF16VDOTS_VDOTD

BF16VDOTS_VDOTQ

BF16_VCVT

BF16_VCVTB

BF16_VCVTT

BFC

BFI

BICri

BICrr

BICrsi

BICrsr

BKPT

BL

BLX

BLX_pred

BLXi

BL_pred

BX

BXJ

BX_RET

BX_pred

Bcc

CDE_CX1

CDE_CX1A

CDE_CX1D

CDE_CX1DA

CDE_CX2

CDE_CX2A

CDE_CX2D

CDE_CX2DA

CDE_CX3

CDE_CX3A

CDE_CX3D

CDE_CX3DA

CDE_VCX1A_fpdp

CDE_VCX1A_fpsp

CDE_VCX1A_vec

CDE_VCX1_fpdp

CDE_VCX1_fpsp

CDE_VCX1_vec

CDE_VCX2A_fpdp

CDE_VCX2A_fpsp

CDE_VCX2A_vec

CDE_VCX2_fpdp

CDE_VCX2_fpsp

CDE_VCX2_vec

CDE_VCX3A_fpdp

CDE_VCX3A_fpsp

CDE_VCX3A_vec

CDE_VCX3_fpdp

CDE_VCX3_fpsp

CDE_VCX3_vec

CDP

CDP2

CLREX

CLZ

CMNri

CMNzrr

CMNzrsi

CMNzrsr

CMPri

CMPrr

CMPrsi

CMPrsr

CPS1p

CPS2p

CPS3p

CRC32B

CRC32CB

CRC32CH

CRC32CW

CRC32H

CRC32W

DBG

DMB

DSB

EORri

EORrr

EORrsi

EORrsr

ERET

FCONSTD

FCONSTH

FCONSTS

FLDMXDB_UPD

FLDMXIA

FLDMXIA_UPD

FMSTAT

FSTMXDB_UPD

FSTMXIA

FSTMXIA_UPD

HINT

HLT

HVC

ISB

LDA

LDAB

LDAEX

LDAEXB

LDAEXD

LDAEXH

LDAH

LDC2L_OFFSET

LDC2L_OPTION

LDC2L_POST

LDC2L_PRE

LDC2_OFFSET

LDC2_OPTION

LDC2_POST

LDC2_PRE

LDCL_OFFSET

LDCL_OPTION

LDCL_POST

LDCL_PRE

LDC_OFFSET

LDC_OPTION

LDC_POST

LDC_PRE

LDMDA

LDMDA_UPD

LDMDB

LDMDB_UPD

LDMIA

LDMIA_UPD

LDMIB

LDMIB_UPD

LDRBT_POST_IMM

LDRBT_POST_REG

LDRB_POST_IMM

LDRB_POST_REG

LDRB_PRE_IMM

LDRB_PRE_REG

LDRBi12

LDRBrs

LDRD

LDRD_POST

LDRD_PRE

LDREX

LDREXB

LDREXD

LDREXH

LDRH

LDRHTi

LDRHTr

LDRH_POST

LDRH_PRE

LDRSB

LDRSBTi

LDRSBTr

LDRSB_POST

LDRSB_PRE

LDRSH

LDRSHTi

LDRSHTr

LDRSH_POST

LDRSH_PRE

LDRT_POST_IMM

LDRT_POST_REG

LDR_POST_IMM

LDR_POST_REG

LDR_PRE_IMM

LDR_PRE_REG

LDRcp

LDRi12

LDRrs

MCR

MCR2

MCRR

MCRR2

MLA

MLS

MOVPCLR

MOVTi16

MOVi

MOVi16

MOVr

MOVr_TC

MOVsi

MOVsr

MRC

MRC2

MRRC

MRRC2

MRS

MRSbanked

MRSsys

MSR

MSRbanked

MSRi

MUL

MVE_ASRLi

MVE_ASRLr

MVE_DLSTP_16

MVE_DLSTP_32

MVE_DLSTP_64

MVE_DLSTP_8

MVE_LCTP

MVE_LETP

MVE_LSLLi

MVE_LSLLr

MVE_LSRL

MVE_SQRSHR

MVE_SQRSHRL

MVE_SQSHL

MVE_SQSHLL

MVE_SRSHR

MVE_SRSHRL

MVE_UQRSHL

MVE_UQRSHLL

MVE_UQSHL

MVE_UQSHLL

MVE_URSHR

MVE_URSHRL

MVE_VABAVs16

MVE_VABAVs32

MVE_VABAVs8

MVE_VABAVu16

MVE_VABAVu32

MVE_VABAVu8

MVE_VABDf16

MVE_VABDf32

MVE_VABDs16

MVE_VABDs32

MVE_VABDs8

MVE_VABDu16

MVE_VABDu32

MVE_VABDu8

MVE_VABSf16

MVE_VABSf32

MVE_VABSs16

MVE_VABSs32

MVE_VABSs8

MVE_VADC

MVE_VADCI

MVE_VADDLVs32acc

MVE_VADDLVs32no_acc

MVE_VADDLVu32acc

MVE_VADDLVu32no_acc

MVE_VADDVs16acc

MVE_VADDVs16no_acc

MVE_VADDVs32acc

MVE_VADDVs32no_acc

MVE_VADDVs8acc

MVE_VADDVs8no_acc

MVE_VADDVu16acc

MVE_VADDVu16no_acc

MVE_VADDVu32acc

MVE_VADDVu32no_acc

MVE_VADDVu8acc

MVE_VADDVu8no_acc

MVE_VADD_qr_f16

MVE_VADD_qr_f32

MVE_VADD_qr_i16

MVE_VADD_qr_i32

MVE_VADD_qr_i8

MVE_VADDf16

MVE_VADDf32

MVE_VADDi16

MVE_VADDi32

MVE_VADDi8

MVE_VAND

MVE_VBIC

MVE_VBICimmi16

MVE_VBICimmi32

MVE_VBRSR16

MVE_VBRSR32

MVE_VBRSR8

MVE_VCADDf16

MVE_VCADDf32

MVE_VCADDi16

MVE_VCADDi32

MVE_VCADDi8

MVE_VCLSs16

MVE_VCLSs32

MVE_VCLSs8

MVE_VCLZs16

MVE_VCLZs32

MVE_VCLZs8

MVE_VCMLAf16

MVE_VCMLAf32

MVE_VCMPf16

MVE_VCMPf16r

MVE_VCMPf32

MVE_VCMPf32r

MVE_VCMPi16

MVE_VCMPi16r

MVE_VCMPi32

MVE_VCMPi32r

MVE_VCMPi8

MVE_VCMPi8r

MVE_VCMPs16

MVE_VCMPs16r

MVE_VCMPs32

MVE_VCMPs32r

MVE_VCMPs8

MVE_VCMPs8r

MVE_VCMPu16

MVE_VCMPu16r

MVE_VCMPu32

MVE_VCMPu32r

MVE_VCMPu8

MVE_VCMPu8r

MVE_VCMULf16

MVE_VCMULf32

MVE_VCTP16

MVE_VCTP32

MVE_VCTP64

MVE_VCTP8

MVE_VCVTf16f32bh

MVE_VCVTf16f32th

MVE_VCVTf16s16_fix

MVE_VCVTf16s16n

MVE_VCVTf16u16_fix

MVE_VCVTf16u16n

MVE_VCVTf32f16bh

MVE_VCVTf32f16th

MVE_VCVTf32s32_fix

MVE_VCVTf32s32n

MVE_VCVTf32u32_fix

MVE_VCVTf32u32n

MVE_VCVTs16f16_fix

MVE_VCVTs16f16a

MVE_VCVTs16f16m

MVE_VCVTs16f16n

MVE_VCVTs16f16p

MVE_VCVTs16f16z

MVE_VCVTs32f32_fix

MVE_VCVTs32f32a

MVE_VCVTs32f32m

MVE_VCVTs32f32n

MVE_VCVTs32f32p

MVE_VCVTs32f32z

MVE_VCVTu16f16_fix

MVE_VCVTu16f16a

MVE_VCVTu16f16m

MVE_VCVTu16f16n

MVE_VCVTu16f16p

MVE_VCVTu16f16z

MVE_VCVTu32f32_fix

MVE_VCVTu32f32a

MVE_VCVTu32f32m

MVE_VCVTu32f32n

MVE_VCVTu32f32p

MVE_VCVTu32f32z

MVE_VDDUPu16

MVE_VDDUPu32

MVE_VDDUPu8

MVE_VDUP16

MVE_VDUP32

MVE_VDUP8

MVE_VDWDUPu16

MVE_VDWDUPu32

MVE_VDWDUPu8

MVE_VEOR

MVE_VFMA_qr_Sf16

MVE_VFMA_qr_Sf32

MVE_VFMA_qr_f16

MVE_VFMA_qr_f32

MVE_VFMAf16

MVE_VFMAf32

MVE_VFMSf16

MVE_VFMSf32

MVE_VHADD_qr_s16

MVE_VHADD_qr_s32

MVE_VHADD_qr_s8

MVE_VHADD_qr_u16

MVE_VHADD_qr_u32

MVE_VHADD_qr_u8

MVE_VHADDs16

MVE_VHADDs32

MVE_VHADDs8

MVE_VHADDu16

MVE_VHADDu32

MVE_VHADDu8

MVE_VHCADDs16

MVE_VHCADDs32

MVE_VHCADDs8

MVE_VHSUB_qr_s16

MVE_VHSUB_qr_s32

MVE_VHSUB_qr_s8

MVE_VHSUB_qr_u16

MVE_VHSUB_qr_u32

MVE_VHSUB_qr_u8

MVE_VHSUBs16

MVE_VHSUBs32

MVE_VHSUBs8

MVE_VHSUBu16

MVE_VHSUBu32

MVE_VHSUBu8

MVE_VIDUPu16

MVE_VIDUPu32

MVE_VIDUPu8

MVE_VIWDUPu16

MVE_VIWDUPu32

MVE_VIWDUPu8

MVE_VLD20_16

MVE_VLD20_16_wb

MVE_VLD20_32

MVE_VLD20_32_wb

MVE_VLD20_8

MVE_VLD20_8_wb

MVE_VLD21_16

MVE_VLD21_16_wb

MVE_VLD21_32

MVE_VLD21_32_wb

MVE_VLD21_8

MVE_VLD21_8_wb

MVE_VLD40_16

MVE_VLD40_16_wb

MVE_VLD40_32

MVE_VLD40_32_wb

MVE_VLD40_8

MVE_VLD40_8_wb

MVE_VLD41_16

MVE_VLD41_16_wb

MVE_VLD41_32

MVE_VLD41_32_wb

MVE_VLD41_8

MVE_VLD41_8_wb

MVE_VLD42_16

MVE_VLD42_16_wb

MVE_VLD42_32

MVE_VLD42_32_wb

MVE_VLD42_8

MVE_VLD42_8_wb

MVE_VLD43_16

MVE_VLD43_16_wb

MVE_VLD43_32

MVE_VLD43_32_wb

MVE_VLD43_8

MVE_VLD43_8_wb

MVE_VLDRBS16

MVE_VLDRBS16_post

MVE_VLDRBS16_pre

MVE_VLDRBS16_rq

MVE_VLDRBS32

MVE_VLDRBS32_post

MVE_VLDRBS32_pre

MVE_VLDRBS32_rq

MVE_VLDRBU16

MVE_VLDRBU16_post

MVE_VLDRBU16_pre

MVE_VLDRBU16_rq

MVE_VLDRBU32

MVE_VLDRBU32_post

MVE_VLDRBU32_pre

MVE_VLDRBU32_rq

MVE_VLDRBU8

MVE_VLDRBU8_post

MVE_VLDRBU8_pre

MVE_VLDRBU8_rq

MVE_VLDRDU64_qi

MVE_VLDRDU64_qi_pre

MVE_VLDRDU64_rq

MVE_VLDRDU64_rq_u

MVE_VLDRHS32

MVE_VLDRHS32_post

MVE_VLDRHS32_pre

MVE_VLDRHS32_rq

MVE_VLDRHS32_rq_u

MVE_VLDRHU16

MVE_VLDRHU16_post

MVE_VLDRHU16_pre

MVE_VLDRHU16_rq

MVE_VLDRHU16_rq_u

MVE_VLDRHU32

MVE_VLDRHU32_post

MVE_VLDRHU32_pre

MVE_VLDRHU32_rq

MVE_VLDRHU32_rq_u

MVE_VLDRWU32

MVE_VLDRWU32_post

MVE_VLDRWU32_pre

MVE_VLDRWU32_qi

MVE_VLDRWU32_qi_pre

MVE_VLDRWU32_rq

MVE_VLDRWU32_rq_u

MVE_VMAXAVs16

MVE_VMAXAVs32

MVE_VMAXAVs8

MVE_VMAXAs16

MVE_VMAXAs32

MVE_VMAXAs8

MVE_VMAXNMAVf16

MVE_VMAXNMAVf32

MVE_VMAXNMAf16

MVE_VMAXNMAf32

MVE_VMAXNMVf16

MVE_VMAXNMVf32

MVE_VMAXNMf16

MVE_VMAXNMf32

MVE_VMAXVs16

MVE_VMAXVs32

MVE_VMAXVs8

MVE_VMAXVu16

MVE_VMAXVu32

MVE_VMAXVu8

MVE_VMAXs16

MVE_VMAXs32

MVE_VMAXs8

MVE_VMAXu16

MVE_VMAXu32

MVE_VMAXu8

MVE_VMINAVs16

MVE_VMINAVs32

MVE_VMINAVs8

MVE_VMINAs16

MVE_VMINAs32

MVE_VMINAs8

MVE_VMINNMAVf16

MVE_VMINNMAVf32

MVE_VMINNMAf16

MVE_VMINNMAf32

MVE_VMINNMVf16

MVE_VMINNMVf32

MVE_VMINNMf16

MVE_VMINNMf32

MVE_VMINVs16

MVE_VMINVs32

MVE_VMINVs8

MVE_VMINVu16

MVE_VMINVu32

MVE_VMINVu8

MVE_VMINs16

MVE_VMINs32

MVE_VMINs8

MVE_VMINu16

MVE_VMINu32

MVE_VMINu8

MVE_VMLADAVas16

MVE_VMLADAVas32

MVE_VMLADAVas8

MVE_VMLADAVau16

MVE_VMLADAVau32

MVE_VMLADAVau8

MVE_VMLADAVaxs16

MVE_VMLADAVaxs32

MVE_VMLADAVaxs8

MVE_VMLADAVs16

MVE_VMLADAVs32

MVE_VMLADAVs8

MVE_VMLADAVu16

MVE_VMLADAVu32

MVE_VMLADAVu8

MVE_VMLADAVxs16

MVE_VMLADAVxs32

MVE_VMLADAVxs8

MVE_VMLALDAVas16

MVE_VMLALDAVas32

MVE_VMLALDAVau16

MVE_VMLALDAVau32

MVE_VMLALDAVaxs16

MVE_VMLALDAVaxs32

MVE_VMLALDAVs16

MVE_VMLALDAVs32

MVE_VMLALDAVu16

MVE_VMLALDAVu32

MVE_VMLALDAVxs16

MVE_VMLALDAVxs32

MVE_VMLAS_qr_i16

MVE_VMLAS_qr_i32

MVE_VMLAS_qr_i8

MVE_VMLA_qr_i16

MVE_VMLA_qr_i32

MVE_VMLA_qr_i8

MVE_VMLSDAVas16

MVE_VMLSDAVas32

MVE_VMLSDAVas8

MVE_VMLSDAVaxs16

MVE_VMLSDAVaxs32

MVE_VMLSDAVaxs8

MVE_VMLSDAVs16

MVE_VMLSDAVs32

MVE_VMLSDAVs8

MVE_VMLSDAVxs16

MVE_VMLSDAVxs32

MVE_VMLSDAVxs8

MVE_VMLSLDAVas16

MVE_VMLSLDAVas32

MVE_VMLSLDAVaxs16

MVE_VMLSLDAVaxs32

MVE_VMLSLDAVs16

MVE_VMLSLDAVs32

MVE_VMLSLDAVxs16

MVE_VMLSLDAVxs32

MVE_VMOVLs16bh

MVE_VMOVLs16th

MVE_VMOVLs8bh

MVE_VMOVLs8th

MVE_VMOVLu16bh

MVE_VMOVLu16th

MVE_VMOVLu8bh

MVE_VMOVLu8th

MVE_VMOVNi16bh

MVE_VMOVNi16th

MVE_VMOVNi32bh

MVE_VMOVNi32th

MVE_VMOV_from_lane_32

MVE_VMOV_from_lane_s16

MVE_VMOV_from_lane_s8

MVE_VMOV_from_lane_u16

MVE_VMOV_from_lane_u8

MVE_VMOV_q_rr

MVE_VMOV_rr_q

MVE_VMOV_to_lane_16

MVE_VMOV_to_lane_32

MVE_VMOV_to_lane_8

MVE_VMOVimmf32

MVE_VMOVimmi16

MVE_VMOVimmi32

MVE_VMOVimmi64

MVE_VMOVimmi8

MVE_VMULHs16

MVE_VMULHs32

MVE_VMULHs8

MVE_VMULHu16

MVE_VMULHu32

MVE_VMULHu8

MVE_VMULLBp16

MVE_VMULLBp8

MVE_VMULLBs16

MVE_VMULLBs32

MVE_VMULLBs8

MVE_VMULLBu16

MVE_VMULLBu32

MVE_VMULLBu8

MVE_VMULLTp16

MVE_VMULLTp8

MVE_VMULLTs16

MVE_VMULLTs32

MVE_VMULLTs8

MVE_VMULLTu16

MVE_VMULLTu32

MVE_VMULLTu8

MVE_VMUL_qr_f16

MVE_VMUL_qr_f32

MVE_VMUL_qr_i16

MVE_VMUL_qr_i32

MVE_VMUL_qr_i8

MVE_VMULf16

MVE_VMULf32

MVE_VMULi16

MVE_VMULi32

MVE_VMULi8

MVE_VMVN

MVE_VMVNimmi16

MVE_VMVNimmi32

MVE_VNEGf16

MVE_VNEGf32

MVE_VNEGs16

MVE_VNEGs32

MVE_VNEGs8

MVE_VORN

MVE_VORR

MVE_VORRimmi16

MVE_VORRimmi32

MVE_VPNOT

MVE_VPSEL

MVE_VPST

MVE_VPTv16i8

MVE_VPTv16i8r

MVE_VPTv16s8

MVE_VPTv16s8r

MVE_VPTv16u8

MVE_VPTv16u8r

MVE_VPTv4f32

MVE_VPTv4f32r

MVE_VPTv4i32

MVE_VPTv4i32r

MVE_VPTv4s32

MVE_VPTv4s32r

MVE_VPTv4u32

MVE_VPTv4u32r

MVE_VPTv8f16

MVE_VPTv8f16r

MVE_VPTv8i16

MVE_VPTv8i16r

MVE_VPTv8s16

MVE_VPTv8s16r

MVE_VPTv8u16

MVE_VPTv8u16r

MVE_VQABSs16

MVE_VQABSs32

MVE_VQABSs8

MVE_VQADD_qr_s16

MVE_VQADD_qr_s32

MVE_VQADD_qr_s8

MVE_VQADD_qr_u16

MVE_VQADD_qr_u32

MVE_VQADD_qr_u8

MVE_VQADDs16

MVE_VQADDs32

MVE_VQADDs8

MVE_VQADDu16

MVE_VQADDu32

MVE_VQADDu8

MVE_VQDMLADHXs16

MVE_VQDMLADHXs32

MVE_VQDMLADHXs8

MVE_VQDMLADHs16

MVE_VQDMLADHs32

MVE_VQDMLADHs8

MVE_VQDMLAH_qrs16

MVE_VQDMLAH_qrs32

MVE_VQDMLAH_qrs8

MVE_VQDMLASH_qrs16

MVE_VQDMLASH_qrs32

MVE_VQDMLASH_qrs8

MVE_VQDMLSDHXs16

MVE_VQDMLSDHXs32

MVE_VQDMLSDHXs8

MVE_VQDMLSDHs16

MVE_VQDMLSDHs32

MVE_VQDMLSDHs8

MVE_VQDMULH_qr_s16

MVE_VQDMULH_qr_s32

MVE_VQDMULH_qr_s8

MVE_VQDMULHi16

MVE_VQDMULHi32

MVE_VQDMULHi8

MVE_VQDMULL_qr_s16bh

MVE_VQDMULL_qr_s16th

MVE_VQDMULL_qr_s32bh

MVE_VQDMULL_qr_s32th

MVE_VQDMULLs16bh

MVE_VQDMULLs16th

MVE_VQDMULLs32bh

MVE_VQDMULLs32th

MVE_VQMOVNs16bh

MVE_VQMOVNs16th

MVE_VQMOVNs32bh

MVE_VQMOVNs32th

MVE_VQMOVNu16bh

MVE_VQMOVNu16th

MVE_VQMOVNu32bh

MVE_VQMOVNu32th

MVE_VQMOVUNs16bh

MVE_VQMOVUNs16th

MVE_VQMOVUNs32bh

MVE_VQMOVUNs32th

MVE_VQNEGs16

MVE_VQNEGs32

MVE_VQNEGs8

MVE_VQRDMLADHXs16

MVE_VQRDMLADHXs32

MVE_VQRDMLADHXs8

MVE_VQRDMLADHs16

MVE_VQRDMLADHs32

MVE_VQRDMLADHs8

MVE_VQRDMLAH_qrs16

MVE_VQRDMLAH_qrs32

MVE_VQRDMLAH_qrs8

MVE_VQRDMLASH_qrs16

MVE_VQRDMLASH_qrs32

MVE_VQRDMLASH_qrs8

MVE_VQRDMLSDHXs16

MVE_VQRDMLSDHXs32

MVE_VQRDMLSDHXs8

MVE_VQRDMLSDHs16

MVE_VQRDMLSDHs32

MVE_VQRDMLSDHs8

MVE_VQRDMULH_qr_s16

MVE_VQRDMULH_qr_s32

MVE_VQRDMULH_qr_s8

MVE_VQRDMULHi16

MVE_VQRDMULHi32

MVE_VQRDMULHi8

MVE_VQRSHL_by_vecs16

MVE_VQRSHL_by_vecs32

MVE_VQRSHL_by_vecs8

MVE_VQRSHL_by_vecu16

MVE_VQRSHL_by_vecu32

MVE_VQRSHL_by_vecu8

MVE_VQRSHL_qrs16

MVE_VQRSHL_qrs32

MVE_VQRSHL_qrs8

MVE_VQRSHL_qru16

MVE_VQRSHL_qru32

MVE_VQRSHL_qru8

MVE_VQRSHRNbhs16

MVE_VQRSHRNbhs32

MVE_VQRSHRNbhu16

MVE_VQRSHRNbhu32

MVE_VQRSHRNths16

MVE_VQRSHRNths32

MVE_VQRSHRNthu16

MVE_VQRSHRNthu32

MVE_VQRSHRUNs16bh

MVE_VQRSHRUNs16th

MVE_VQRSHRUNs32bh

MVE_VQRSHRUNs32th

MVE_VQSHLU_imms16

MVE_VQSHLU_imms32

MVE_VQSHLU_imms8

MVE_VQSHL_by_vecs16

MVE_VQSHL_by_vecs32

MVE_VQSHL_by_vecs8

MVE_VQSHL_by_vecu16

MVE_VQSHL_by_vecu32

MVE_VQSHL_by_vecu8

MVE_VQSHL_qrs16

MVE_VQSHL_qrs32

MVE_VQSHL_qrs8

MVE_VQSHL_qru16

MVE_VQSHL_qru32

MVE_VQSHL_qru8

MVE_VQSHLimms16

MVE_VQSHLimms32

MVE_VQSHLimms8

MVE_VQSHLimmu16

MVE_VQSHLimmu32

MVE_VQSHLimmu8

MVE_VQSHRNbhs16

MVE_VQSHRNbhs32

MVE_VQSHRNbhu16

MVE_VQSHRNbhu32

MVE_VQSHRNths16

MVE_VQSHRNths32

MVE_VQSHRNthu16

MVE_VQSHRNthu32

MVE_VQSHRUNs16bh

MVE_VQSHRUNs16th

MVE_VQSHRUNs32bh

MVE_VQSHRUNs32th

MVE_VQSUB_qr_s16

MVE_VQSUB_qr_s32

MVE_VQSUB_qr_s8

MVE_VQSUB_qr_u16

MVE_VQSUB_qr_u32

MVE_VQSUB_qr_u8

MVE_VQSUBs16

MVE_VQSUBs32

MVE_VQSUBs8

MVE_VQSUBu16

MVE_VQSUBu32

MVE_VQSUBu8

MVE_VREV16_8

MVE_VREV32_16

MVE_VREV32_8

MVE_VREV64_16

MVE_VREV64_32

MVE_VREV64_8

MVE_VRHADDs16

MVE_VRHADDs32

MVE_VRHADDs8

MVE_VRHADDu16

MVE_VRHADDu32

MVE_VRHADDu8

MVE_VRINTf16A

MVE_VRINTf16M

MVE_VRINTf16N

MVE_VRINTf16P

MVE_VRINTf16X

MVE_VRINTf16Z

MVE_VRINTf32A

MVE_VRINTf32M

MVE_VRINTf32N

MVE_VRINTf32P

MVE_VRINTf32X

MVE_VRINTf32Z

MVE_VRMLALDAVHas32

MVE_VRMLALDAVHau32

MVE_VRMLALDAVHaxs32

MVE_VRMLALDAVHs32

MVE_VRMLALDAVHu32

MVE_VRMLALDAVHxs32

MVE_VRMLSLDAVHas32

MVE_VRMLSLDAVHaxs32

MVE_VRMLSLDAVHs32

MVE_VRMLSLDAVHxs32

MVE_VRMULHs16

MVE_VRMULHs32

MVE_VRMULHs8

MVE_VRMULHu16

MVE_VRMULHu32

MVE_VRMULHu8

MVE_VRSHL_by_vecs16

MVE_VRSHL_by_vecs32

MVE_VRSHL_by_vecs8

MVE_VRSHL_by_vecu16

MVE_VRSHL_by_vecu32

MVE_VRSHL_by_vecu8

MVE_VRSHL_qrs16

MVE_VRSHL_qrs32

MVE_VRSHL_qrs8

MVE_VRSHL_qru16

MVE_VRSHL_qru32

MVE_VRSHL_qru8

MVE_VRSHRNi16bh

MVE_VRSHRNi16th

MVE_VRSHRNi32bh

MVE_VRSHRNi32th

MVE_VRSHR_imms16

MVE_VRSHR_imms32

MVE_VRSHR_imms8

MVE_VRSHR_immu16

MVE_VRSHR_immu32

MVE_VRSHR_immu8

MVE_VSBC

MVE_VSBCI

MVE_VSHLC

MVE_VSHLL_imms16bh

MVE_VSHLL_imms16th

MVE_VSHLL_imms8bh

MVE_VSHLL_imms8th

MVE_VSHLL_immu16bh

MVE_VSHLL_immu16th

MVE_VSHLL_immu8bh

MVE_VSHLL_immu8th

MVE_VSHLL_lws16bh

MVE_VSHLL_lws16th

MVE_VSHLL_lws8bh

MVE_VSHLL_lws8th

MVE_VSHLL_lwu16bh

MVE_VSHLL_lwu16th

MVE_VSHLL_lwu8bh

MVE_VSHLL_lwu8th

MVE_VSHL_by_vecs16

MVE_VSHL_by_vecs32

MVE_VSHL_by_vecs8

MVE_VSHL_by_vecu16

MVE_VSHL_by_vecu32

MVE_VSHL_by_vecu8

MVE_VSHL_immi16

MVE_VSHL_immi32

MVE_VSHL_immi8

MVE_VSHL_qrs16

MVE_VSHL_qrs32

MVE_VSHL_qrs8

MVE_VSHL_qru16

MVE_VSHL_qru32

MVE_VSHL_qru8

MVE_VSHRNi16bh

MVE_VSHRNi16th

MVE_VSHRNi32bh

MVE_VSHRNi32th

MVE_VSHR_imms16

MVE_VSHR_imms32

MVE_VSHR_imms8

MVE_VSHR_immu16

MVE_VSHR_immu32

MVE_VSHR_immu8

MVE_VSLIimm16

MVE_VSLIimm32

MVE_VSLIimm8

MVE_VSRIimm16

MVE_VSRIimm32

MVE_VSRIimm8

MVE_VST20_16

MVE_VST20_16_wb

MVE_VST20_32

MVE_VST20_32_wb

MVE_VST20_8

MVE_VST20_8_wb

MVE_VST21_16

MVE_VST21_16_wb

MVE_VST21_32

MVE_VST21_32_wb

MVE_VST21_8

MVE_VST21_8_wb

MVE_VST40_16

MVE_VST40_16_wb

MVE_VST40_32

MVE_VST40_32_wb

MVE_VST40_8

MVE_VST40_8_wb

MVE_VST41_16

MVE_VST41_16_wb

MVE_VST41_32

MVE_VST41_32_wb

MVE_VST41_8

MVE_VST41_8_wb

MVE_VST42_16

MVE_VST42_16_wb

MVE_VST42_32

MVE_VST42_32_wb

MVE_VST42_8

MVE_VST42_8_wb

MVE_VST43_16

MVE_VST43_16_wb

MVE_VST43_32

MVE_VST43_32_wb

MVE_VST43_8

MVE_VST43_8_wb

MVE_VSTRB16

MVE_VSTRB16_post

MVE_VSTRB16_pre

MVE_VSTRB16_rq

MVE_VSTRB32

MVE_VSTRB32_post

MVE_VSTRB32_pre

MVE_VSTRB32_rq

MVE_VSTRB8_rq

MVE_VSTRBU8

MVE_VSTRBU8_post

MVE_VSTRBU8_pre

MVE_VSTRD64_qi

MVE_VSTRD64_qi_pre

MVE_VSTRD64_rq

MVE_VSTRD64_rq_u

MVE_VSTRH16_rq

MVE_VSTRH16_rq_u

MVE_VSTRH32

MVE_VSTRH32_post

MVE_VSTRH32_pre

MVE_VSTRH32_rq

MVE_VSTRH32_rq_u

MVE_VSTRHU16

MVE_VSTRHU16_post

MVE_VSTRHU16_pre

MVE_VSTRW32_qi

MVE_VSTRW32_qi_pre

MVE_VSTRW32_rq

MVE_VSTRW32_rq_u

MVE_VSTRWU32

MVE_VSTRWU32_post

MVE_VSTRWU32_pre

MVE_VSUB_qr_f16

MVE_VSUB_qr_f32

MVE_VSUB_qr_i16

MVE_VSUB_qr_i32

MVE_VSUB_qr_i8

MVE_VSUBf16

MVE_VSUBf32

MVE_VSUBi16

MVE_VSUBi32

MVE_VSUBi8

MVE_WLSTP_16

MVE_WLSTP_32

MVE_WLSTP_64

MVE_WLSTP_8

MVNi

MVNr

MVNsi

MVNsr

NEON_VMAXNMNDf

NEON_VMAXNMNDh

NEON_VMAXNMNQf

NEON_VMAXNMNQh

NEON_VMINNMNDf

NEON_VMINNMNDh

NEON_VMINNMNQf

NEON_VMINNMNQh

ORRri

ORRrr

ORRrsi

ORRrsr

PKHBT

PKHTB

PLDWi12

PLDWrs

PLDi12

PLDrs

PLIi12

PLIrs

QADD

QADD16

QADD8

QASX

QDADD

QDSUB

QSAX

QSUB

QSUB16

QSUB8

RBIT

REV

REV16

REVSH

RFEDA

RFEDA_UPD

RFEDB

RFEDB_UPD

RFEIA

RFEIA_UPD

RFEIB

RFEIB_UPD

RSBri

RSBrr

RSBrsi

RSBrsr

RSCri

RSCrr

RSCrsi

RSCrsr

SADD16

SADD8

SASX

SB

SBCri

SBCrr

SBCrsi

SBCrsr

SBFX

SDIV

SEL

SETEND

SETPAN

SHA1C

SHA1H

SHA1M

SHA1P

SHA1SU0

SHA1SU1

SHA256H

SHA256H2

SHA256SU0

SHA256SU1

SHADD16

SHADD8

SHASX

SHSAX

SHSUB16

SHSUB8

SMC

SMLABB

SMLABT

SMLAD

SMLADX

SMLAL

SMLALBB

SMLALBT

SMLALD

SMLALDX

SMLALTB

SMLALTT

SMLATB

SMLATT

SMLAWB

SMLAWT

SMLSD

SMLSDX

SMLSLD

SMLSLDX

SMMLA

SMMLAR

SMMLS

SMMLSR

SMMUL

SMMULR

SMUAD

SMUADX

SMULBB

SMULBT

SMULL

SMULTB

SMULTT

SMULWB

SMULWT

SMUSD

SMUSDX

SRSDA

SRSDA_UPD

SRSDB

SRSDB_UPD

SRSIA

SRSIA_UPD

SRSIB

SRSIB_UPD

SSAT

SSAT16

SSAX

SSUB16

SSUB8

STC2L_OFFSET

STC2L_OPTION

STC2L_POST

STC2L_PRE

STC2_OFFSET

STC2_OPTION

STC2_POST

STC2_PRE

STCL_OFFSET

STCL_OPTION

STCL_POST

STCL_PRE

STC_OFFSET

STC_OPTION

STC_POST

STC_PRE

STL

STLB

STLEX

STLEXB

STLEXD

STLEXH

STLH

STMDA

STMDA_UPD

STMDB

STMDB_UPD

STMIA

STMIA_UPD

STMIB

STMIB_UPD

STRBT_POST_IMM

STRBT_POST_REG

STRB_POST_IMM

STRB_POST_REG

STRB_PRE_IMM

STRB_PRE_REG

STRBi12

STRBrs

STRD

STRD_POST

STRD_PRE

STREX

STREXB

STREXD

STREXH

STRH

STRHTi

STRHTr

STRH_POST

STRH_PRE

STRT_POST_IMM

STRT_POST_REG

STR_POST_IMM

STR_POST_REG

STR_PRE_IMM

STR_PRE_REG

STRi12

STRrs

SUBri

SUBrr

SUBrsi

SUBrsr

SVC

SWP

SWPB

SXTAB

SXTAB16

SXTAH

SXTB

SXTB16

SXTH

TEQri

TEQrr

TEQrsi

TEQrsr

TRAP

TRAPNaCl

TSB

TSTri

TSTrr

TSTrsi

TSTrsr

UADD16

UADD8

UASX

UBFX

UDF

UDIV

UHADD16

UHADD8

UHASX

UHSAX

UHSUB16

UHSUB8

UMAAL

UMLAL

UMULL

UQADD16

UQADD8

UQASX

UQSAX

UQSUB16

UQSUB8

USAD8

USADA8

USAT

USAT16

USAX

USUB16

USUB8

UXTAB

UXTAB16

UXTAH

UXTB

UXTB16

UXTH

VABALsv2i64

VABALsv4i32

VABALsv8i16

VABALuv2i64

VABALuv4i32

VABALuv8i16

VABAsv16i8

VABAsv2i32

VABAsv4i16

VABAsv4i32

VABAsv8i16

VABAsv8i8

VABAuv16i8

VABAuv2i32

VABAuv4i16

VABAuv4i32

VABAuv8i16

VABAuv8i8

VABDLsv2i64

VABDLsv4i32

VABDLsv8i16

VABDLuv2i64

VABDLuv4i32

VABDLuv8i16

VABDfd

VABDfq

VABDhd

VABDhq

VABDsv16i8

VABDsv2i32

VABDsv4i16

VABDsv4i32

VABDsv8i16

VABDsv8i8

VABDuv16i8

VABDuv2i32

VABDuv4i16

VABDuv4i32

VABDuv8i16

VABDuv8i8

VABSD

VABSH

VABSS

VABSfd

VABSfq

VABShd

VABShq

VABSv16i8

VABSv2i32

VABSv4i16

VABSv4i32

VABSv8i16

VABSv8i8

VACGEfd

VACGEfq

VACGEhd

VACGEhq

VACGTfd

VACGTfq

VACGThd

VACGThq

VADDD

VADDH

VADDHNv2i32

VADDHNv4i16

VADDHNv8i8

VADDLsv2i64

VADDLsv4i32

VADDLsv8i16

VADDLuv2i64

VADDLuv4i32

VADDLuv8i16

VADDS

VADDWsv2i64

VADDWsv4i32

VADDWsv8i16

VADDWuv2i64

VADDWuv4i32

VADDWuv8i16

VADDfd

VADDfq

VADDhd

VADDhq

VADDv16i8

VADDv1i64

VADDv2i32

VADDv2i64

VADDv4i16

VADDv4i32

VADDv8i16

VADDv8i8

VANDd

VANDq

VBF16MALBQ

VBF16MALBQI

VBF16MALTQ

VBF16MALTQI

VBICd

VBICiv2i32

VBICiv4i16

VBICiv4i32

VBICiv8i16

VBICq

VBIFd

VBIFq

VBITd

VBITq

VBSLd

VBSLq

VBSPd

VBSPq

VCADDv2f32

VCADDv4f16

VCADDv4f32

VCADDv8f16

VCEQfd

VCEQfq

VCEQhd

VCEQhq

VCEQv16i8

VCEQv2i32

VCEQv4i16

VCEQv4i32

VCEQv8i16

VCEQv8i8

VCEQzv16i8

VCEQzv2f32

VCEQzv2i32

VCEQzv4f16

VCEQzv4f32

VCEQzv4i16

VCEQzv4i32

VCEQzv8f16

VCEQzv8i16

VCEQzv8i8

VCGEfd

VCGEfq

VCGEhd

VCGEhq

VCGEsv16i8

VCGEsv2i32

VCGEsv4i16

VCGEsv4i32

VCGEsv8i16

VCGEsv8i8

VCGEuv16i8

VCGEuv2i32

VCGEuv4i16

VCGEuv4i32

VCGEuv8i16

VCGEuv8i8

VCGEzv16i8

VCGEzv2f32

VCGEzv2i32

VCGEzv4f16

VCGEzv4f32

VCGEzv4i16

VCGEzv4i32

VCGEzv8f16

VCGEzv8i16

VCGEzv8i8

VCGTfd

VCGTfq

VCGThd

VCGThq

VCGTsv16i8

VCGTsv2i32

VCGTsv4i16

VCGTsv4i32

VCGTsv8i16

VCGTsv8i8

VCGTuv16i8

VCGTuv2i32

VCGTuv4i16

VCGTuv4i32

VCGTuv8i16

VCGTuv8i8

VCGTzv16i8

VCGTzv2f32

VCGTzv2i32

VCGTzv4f16

VCGTzv4f32

VCGTzv4i16

VCGTzv4i32

VCGTzv8f16

VCGTzv8i16

VCGTzv8i8

VCLEzv16i8

VCLEzv2f32

VCLEzv2i32

VCLEzv4f16

VCLEzv4f32

VCLEzv4i16

VCLEzv4i32

VCLEzv8f16

VCLEzv8i16

VCLEzv8i8

VCLSv16i8

VCLSv2i32

VCLSv4i16

VCLSv4i32

VCLSv8i16

VCLSv8i8

VCLTzv16i8

VCLTzv2f32

VCLTzv2i32

VCLTzv4f16

VCLTzv4f32

VCLTzv4i16

VCLTzv4i32

VCLTzv8f16

VCLTzv8i16

VCLTzv8i8

VCLZv16i8

VCLZv2i32

VCLZv4i16

VCLZv4i32

VCLZv8i16

VCLZv8i8

VCMLAv2f32

VCMLAv2f32_indexed

VCMLAv4f16

VCMLAv4f16_indexed

VCMLAv4f32

VCMLAv4f32_indexed

VCMLAv8f16

VCMLAv8f16_indexed

VCMPD

VCMPED

VCMPEH

VCMPES

VCMPEZD

VCMPEZH

VCMPEZS

VCMPH

VCMPS

VCMPZD

VCMPZH

VCMPZS

VCNTd

VCNTq

VCVTANSDf

VCVTANSDh

VCVTANSQf

VCVTANSQh

VCVTANUDf

VCVTANUDh

VCVTANUQf

VCVTANUQh

VCVTASD

VCVTASH

VCVTASS

VCVTAUD

VCVTAUH

VCVTAUS

VCVTBDH

VCVTBHD

VCVTBHS

VCVTBSH

VCVTDS

VCVTMNSDf

VCVTMNSDh

VCVTMNSQf

VCVTMNSQh

VCVTMNUDf

VCVTMNUDh

VCVTMNUQf

VCVTMNUQh

VCVTMSD

VCVTMSH

VCVTMSS

VCVTMUD

VCVTMUH

VCVTMUS

VCVTNNSDf

VCVTNNSDh

VCVTNNSQf

VCVTNNSQh

VCVTNNUDf

VCVTNNUDh

VCVTNNUQf

VCVTNNUQh

VCVTNSD

VCVTNSH

VCVTNSS

VCVTNUD

VCVTNUH

VCVTNUS

VCVTPNSDf

VCVTPNSDh

VCVTPNSQf

VCVTPNSQh

VCVTPNUDf

VCVTPNUDh

VCVTPNUQf

VCVTPNUQh

VCVTPSD

VCVTPSH

VCVTPSS

VCVTPUD

VCVTPUH

VCVTPUS

VCVTSD

VCVTTDH

VCVTTHD

VCVTTHS

VCVTTSH

VCVTf2h

VCVTf2sd

VCVTf2sq

VCVTf2ud

VCVTf2uq

VCVTf2xsd

VCVTf2xsq

VCVTf2xud

VCVTf2xuq

VCVTh2f

VCVTh2sd

VCVTh2sq

VCVTh2ud

VCVTh2uq

VCVTh2xsd

VCVTh2xsq

VCVTh2xud

VCVTh2xuq

VCVTs2fd

VCVTs2fq

VCVTs2hd

VCVTs2hq

VCVTu2fd

VCVTu2fq

VCVTu2hd

VCVTu2hq

VCVTxs2fd

VCVTxs2fq

VCVTxs2hd

VCVTxs2hq

VCVTxu2fd

VCVTxu2fq

VCVTxu2hd

VCVTxu2hq

VDIVD

VDIVH

VDIVS

VDUP16d

VDUP16q

VDUP32d

VDUP32q

VDUP8d

VDUP8q

VDUPLN16d

VDUPLN16q

VDUPLN32d

VDUPLN32q

VDUPLN8d

VDUPLN8q

VEORd

VEORq

VEXTd16

VEXTd32

VEXTd8

VEXTq16

VEXTq32

VEXTq64

VEXTq8

VFMAD

VFMAH

VFMALD

VFMALDI

VFMALQ

VFMALQI

VFMAS

VFMAfd

VFMAfq

VFMAhd

VFMAhq

VFMSD

VFMSH

VFMSLD

VFMSLDI

VFMSLQ

VFMSLQI

VFMSS

VFMSfd

VFMSfq

VFMShd

VFMShq

VFNMAD

VFNMAH

VFNMAS

VFNMSD

VFNMSH

VFNMSS

VFP_VMAXNMD

VFP_VMAXNMH

VFP_VMAXNMS

VFP_VMINNMD

VFP_VMINNMH

VFP_VMINNMS

VGETLNi32

VGETLNs16

VGETLNs8

VGETLNu16

VGETLNu8

VHADDsv16i8

VHADDsv2i32

VHADDsv4i16

VHADDsv4i32

VHADDsv8i16

VHADDsv8i8

VHADDuv16i8

VHADDuv2i32

VHADDuv4i16

VHADDuv4i32

VHADDuv8i16

VHADDuv8i8

VHSUBsv16i8

VHSUBsv2i32

VHSUBsv4i16

VHSUBsv4i32

VHSUBsv8i16

VHSUBsv8i8

VHSUBuv16i8

VHSUBuv2i32

VHSUBuv4i16

VHSUBuv4i32

VHSUBuv8i16

VHSUBuv8i8

VINSH

VJCVT

VLD1DUPd16

VLD1DUPd16wb_fixed

VLD1DUPd16wb_register

VLD1DUPd32

VLD1DUPd32wb_fixed

VLD1DUPd32wb_register

VLD1DUPd8

VLD1DUPd8wb_fixed

VLD1DUPd8wb_register

VLD1DUPq16

VLD1DUPq16wb_fixed

VLD1DUPq16wb_register

VLD1DUPq32

VLD1DUPq32wb_fixed

VLD1DUPq32wb_register

VLD1DUPq8

VLD1DUPq8wb_fixed

VLD1DUPq8wb_register

VLD1LNd16

VLD1LNd16_UPD

VLD1LNd32

VLD1LNd32_UPD

VLD1LNd8

VLD1LNd8_UPD

VLD1LNq16Pseudo

VLD1LNq16Pseudo_UPD

VLD1LNq32Pseudo

VLD1LNq32Pseudo_UPD

VLD1LNq8Pseudo

VLD1LNq8Pseudo_UPD

VLD1d16

VLD1d16Q

VLD1d16QPseudo

VLD1d16QPseudoWB_fixed

VLD1d16QPseudoWB_register

VLD1d16Qwb_fixed

VLD1d16Qwb_register

VLD1d16T

VLD1d16TPseudo

VLD1d16TPseudoWB_fixed

VLD1d16TPseudoWB_register

VLD1d16Twb_fixed

VLD1d16Twb_register

VLD1d16wb_fixed

VLD1d16wb_register

VLD1d32

VLD1d32Q

VLD1d32QPseudo

VLD1d32QPseudoWB_fixed

VLD1d32QPseudoWB_register

VLD1d32Qwb_fixed

VLD1d32Qwb_register

VLD1d32T

VLD1d32TPseudo

VLD1d32TPseudoWB_fixed

VLD1d32TPseudoWB_register

VLD1d32Twb_fixed

VLD1d32Twb_register

VLD1d32wb_fixed

VLD1d32wb_register

VLD1d64

VLD1d64Q

VLD1d64QPseudo

VLD1d64QPseudoWB_fixed

VLD1d64QPseudoWB_register

VLD1d64Qwb_fixed

VLD1d64Qwb_register

VLD1d64T

VLD1d64TPseudo

VLD1d64TPseudoWB_fixed

VLD1d64TPseudoWB_register

VLD1d64Twb_fixed

VLD1d64Twb_register

VLD1d64wb_fixed

VLD1d64wb_register

VLD1d8

VLD1d8Q

VLD1d8QPseudo

VLD1d8QPseudoWB_fixed

VLD1d8QPseudoWB_register

VLD1d8Qwb_fixed

VLD1d8Qwb_register

VLD1d8T

VLD1d8TPseudo

VLD1d8TPseudoWB_fixed

VLD1d8TPseudoWB_register

VLD1d8Twb_fixed

VLD1d8Twb_register

VLD1d8wb_fixed

VLD1d8wb_register

VLD1q16

VLD1q16HighQPseudo

VLD1q16HighQPseudo_UPD

VLD1q16HighTPseudo

VLD1q16HighTPseudo_UPD

VLD1q16LowQPseudo_UPD

VLD1q16LowTPseudo_UPD

VLD1q16wb_fixed

VLD1q16wb_register

VLD1q32

VLD1q32HighQPseudo

VLD1q32HighQPseudo_UPD

VLD1q32HighTPseudo

VLD1q32HighTPseudo_UPD

VLD1q32LowQPseudo_UPD

VLD1q32LowTPseudo_UPD

VLD1q32wb_fixed

VLD1q32wb_register

VLD1q64

VLD1q64HighQPseudo

VLD1q64HighQPseudo_UPD

VLD1q64HighTPseudo

VLD1q64HighTPseudo_UPD

VLD1q64LowQPseudo_UPD

VLD1q64LowTPseudo_UPD

VLD1q64wb_fixed

VLD1q64wb_register

VLD1q8

VLD1q8HighQPseudo

VLD1q8HighQPseudo_UPD

VLD1q8HighTPseudo

VLD1q8HighTPseudo_UPD

VLD1q8LowQPseudo_UPD

VLD1q8LowTPseudo_UPD

VLD1q8wb_fixed

VLD1q8wb_register

VLD2DUPd16

VLD2DUPd16wb_fixed

VLD2DUPd16wb_register

VLD2DUPd16x2

VLD2DUPd16x2wb_fixed

VLD2DUPd16x2wb_register

VLD2DUPd32

VLD2DUPd32wb_fixed

VLD2DUPd32wb_register

VLD2DUPd32x2

VLD2DUPd32x2wb_fixed

VLD2DUPd32x2wb_register

VLD2DUPd8

VLD2DUPd8wb_fixed

VLD2DUPd8wb_register

VLD2DUPd8x2

VLD2DUPd8x2wb_fixed

VLD2DUPd8x2wb_register

VLD2DUPq16EvenPseudo

VLD2DUPq16OddPseudo

VLD2DUPq16OddPseudoWB_fixed

VLD2DUPq16OddPseudoWB_register

VLD2DUPq32EvenPseudo

VLD2DUPq32OddPseudo

VLD2DUPq32OddPseudoWB_fixed

VLD2DUPq32OddPseudoWB_register

VLD2DUPq8EvenPseudo

VLD2DUPq8OddPseudo

VLD2DUPq8OddPseudoWB_fixed

VLD2DUPq8OddPseudoWB_register

VLD2LNd16

VLD2LNd16Pseudo

VLD2LNd16Pseudo_UPD

VLD2LNd16_UPD

VLD2LNd32

VLD2LNd32Pseudo

VLD2LNd32Pseudo_UPD

VLD2LNd32_UPD

VLD2LNd8

VLD2LNd8Pseudo

VLD2LNd8Pseudo_UPD

VLD2LNd8_UPD

VLD2LNq16

VLD2LNq16Pseudo

VLD2LNq16Pseudo_UPD

VLD2LNq16_UPD

VLD2LNq32

VLD2LNq32Pseudo

VLD2LNq32Pseudo_UPD

VLD2LNq32_UPD

VLD2b16

VLD2b16wb_fixed

VLD2b16wb_register

VLD2b32

VLD2b32wb_fixed

VLD2b32wb_register

VLD2b8

VLD2b8wb_fixed

VLD2b8wb_register

VLD2d16

VLD2d16wb_fixed

VLD2d16wb_register

VLD2d32

VLD2d32wb_fixed

VLD2d32wb_register

VLD2d8

VLD2d8wb_fixed

VLD2d8wb_register

VLD2q16

VLD2q16Pseudo

VLD2q16PseudoWB_fixed

VLD2q16PseudoWB_register

VLD2q16wb_fixed

VLD2q16wb_register

VLD2q32

VLD2q32Pseudo

VLD2q32PseudoWB_fixed

VLD2q32PseudoWB_register

VLD2q32wb_fixed

VLD2q32wb_register

VLD2q8

VLD2q8Pseudo

VLD2q8PseudoWB_fixed

VLD2q8PseudoWB_register

VLD2q8wb_fixed

VLD2q8wb_register

VLD3DUPd16

VLD3DUPd16Pseudo

VLD3DUPd16Pseudo_UPD

VLD3DUPd16_UPD

VLD3DUPd32

VLD3DUPd32Pseudo

VLD3DUPd32Pseudo_UPD

VLD3DUPd32_UPD

VLD3DUPd8

VLD3DUPd8Pseudo

VLD3DUPd8Pseudo_UPD

VLD3DUPd8_UPD

VLD3DUPq16

VLD3DUPq16EvenPseudo

VLD3DUPq16OddPseudo

VLD3DUPq16OddPseudo_UPD

VLD3DUPq16_UPD

VLD3DUPq32

VLD3DUPq32EvenPseudo

VLD3DUPq32OddPseudo

VLD3DUPq32OddPseudo_UPD

VLD3DUPq32_UPD

VLD3DUPq8

VLD3DUPq8EvenPseudo

VLD3DUPq8OddPseudo

VLD3DUPq8OddPseudo_UPD

VLD3DUPq8_UPD

VLD3LNd16

VLD3LNd16Pseudo

VLD3LNd16Pseudo_UPD

VLD3LNd16_UPD

VLD3LNd32

VLD3LNd32Pseudo

VLD3LNd32Pseudo_UPD

VLD3LNd32_UPD

VLD3LNd8

VLD3LNd8Pseudo

VLD3LNd8Pseudo_UPD

VLD3LNd8_UPD

VLD3LNq16

VLD3LNq16Pseudo

VLD3LNq16Pseudo_UPD

VLD3LNq16_UPD

VLD3LNq32

VLD3LNq32Pseudo

VLD3LNq32Pseudo_UPD

VLD3LNq32_UPD

VLD3d16

VLD3d16Pseudo

VLD3d16Pseudo_UPD

VLD3d16_UPD

VLD3d32

VLD3d32Pseudo

VLD3d32Pseudo_UPD

VLD3d32_UPD

VLD3d8

VLD3d8Pseudo

VLD3d8Pseudo_UPD

VLD3d8_UPD

VLD3q16

VLD3q16Pseudo_UPD

VLD3q16_UPD

VLD3q16oddPseudo

VLD3q16oddPseudo_UPD

VLD3q32

VLD3q32Pseudo_UPD

VLD3q32_UPD

VLD3q32oddPseudo

VLD3q32oddPseudo_UPD

VLD3q8

VLD3q8Pseudo_UPD

VLD3q8_UPD

VLD3q8oddPseudo

VLD3q8oddPseudo_UPD

VLD4DUPd16

VLD4DUPd16Pseudo

VLD4DUPd16Pseudo_UPD

VLD4DUPd16_UPD

VLD4DUPd32

VLD4DUPd32Pseudo

VLD4DUPd32Pseudo_UPD

VLD4DUPd32_UPD

VLD4DUPd8

VLD4DUPd8Pseudo

VLD4DUPd8Pseudo_UPD

VLD4DUPd8_UPD

VLD4DUPq16

VLD4DUPq16EvenPseudo

VLD4DUPq16OddPseudo

VLD4DUPq16OddPseudo_UPD

VLD4DUPq16_UPD

VLD4DUPq32

VLD4DUPq32EvenPseudo

VLD4DUPq32OddPseudo

VLD4DUPq32OddPseudo_UPD

VLD4DUPq32_UPD

VLD4DUPq8

VLD4DUPq8EvenPseudo

VLD4DUPq8OddPseudo

VLD4DUPq8OddPseudo_UPD

VLD4DUPq8_UPD

VLD4LNd16

VLD4LNd16Pseudo

VLD4LNd16Pseudo_UPD

VLD4LNd16_UPD

VLD4LNd32

VLD4LNd32Pseudo

VLD4LNd32Pseudo_UPD

VLD4LNd32_UPD

VLD4LNd8

VLD4LNd8Pseudo

VLD4LNd8Pseudo_UPD

VLD4LNd8_UPD

VLD4LNq16

VLD4LNq16Pseudo

VLD4LNq16Pseudo_UPD

VLD4LNq16_UPD

VLD4LNq32

VLD4LNq32Pseudo

VLD4LNq32Pseudo_UPD

VLD4LNq32_UPD

VLD4d16

VLD4d16Pseudo

VLD4d16Pseudo_UPD

VLD4d16_UPD

VLD4d32

VLD4d32Pseudo

VLD4d32Pseudo_UPD

VLD4d32_UPD

VLD4d8

VLD4d8Pseudo

VLD4d8Pseudo_UPD

VLD4d8_UPD

VLD4q16

VLD4q16Pseudo_UPD

VLD4q16_UPD

VLD4q16oddPseudo

VLD4q16oddPseudo_UPD

VLD4q32

VLD4q32Pseudo_UPD

VLD4q32_UPD

VLD4q32oddPseudo

VLD4q32oddPseudo_UPD

VLD4q8

VLD4q8Pseudo_UPD

VLD4q8_UPD

VLD4q8oddPseudo

VLD4q8oddPseudo_UPD

VLDMDDB_UPD

VLDMDIA

VLDMDIA_UPD

VLDMQIA

VLDMSDB_UPD

VLDMSIA

VLDMSIA_UPD

VLDRD

VLDRH

VLDRS

VLDR_FPCXTNS_off

VLDR_FPCXTNS_post

VLDR_FPCXTNS_pre

VLDR_FPCXTS_off

VLDR_FPCXTS_post

VLDR_FPCXTS_pre

VLDR_FPSCR_NZCVQC_off

VLDR_FPSCR_NZCVQC_post

VLDR_FPSCR_NZCVQC_pre

VLDR_FPSCR_off

VLDR_FPSCR_post

VLDR_FPSCR_pre

VLDR_P0_off

VLDR_P0_post

VLDR_P0_pre

VLDR_VPR_off

VLDR_VPR_post

VLDR_VPR_pre

VLLDM

VLLDM_T2

VLSTM

VLSTM_T2

VMAXfd

VMAXfq

VMAXhd

VMAXhq

VMAXsv16i8

VMAXsv2i32

VMAXsv4i16

VMAXsv4i32

VMAXsv8i16

VMAXsv8i8

VMAXuv16i8

VMAXuv2i32

VMAXuv4i16

VMAXuv4i32

VMAXuv8i16

VMAXuv8i8

VMINfd

VMINfq

VMINhd

VMINhq

VMINsv16i8

VMINsv2i32

VMINsv4i16

VMINsv4i32

VMINsv8i16

VMINsv8i8

VMINuv16i8

VMINuv2i32

VMINuv4i16

VMINuv4i32

VMINuv8i16

VMINuv8i8

VMLAD

VMLAH

VMLALslsv2i32

VMLALslsv4i16

VMLALsluv2i32

VMLALsluv4i16

VMLALsv2i64

VMLALsv4i32

VMLALsv8i16

VMLALuv2i64

VMLALuv4i32

VMLALuv8i16

VMLAS

VMLAfd

VMLAfq

VMLAhd

VMLAhq

VMLAslfd

VMLAslfq

VMLAslhd

VMLAslhq

VMLAslv2i32

VMLAslv4i16

VMLAslv4i32

VMLAslv8i16

VMLAv16i8

VMLAv2i32

VMLAv4i16

VMLAv4i32

VMLAv8i16

VMLAv8i8

VMLSD

VMLSH

VMLSLslsv2i32

VMLSLslsv4i16

VMLSLsluv2i32

VMLSLsluv4i16

VMLSLsv2i64

VMLSLsv4i32

VMLSLsv8i16

VMLSLuv2i64

VMLSLuv4i32

VMLSLuv8i16

VMLSS

VMLSfd

VMLSfq

VMLShd

VMLShq

VMLSslfd

VMLSslfq

VMLSslhd

VMLSslhq

VMLSslv2i32

VMLSslv4i16

VMLSslv4i32

VMLSslv8i16

VMLSv16i8

VMLSv2i32

VMLSv4i16

VMLSv4i32

VMLSv8i16

VMLSv8i8

VMMLA

VMOVD

VMOVDRR

VMOVH

VMOVHR

VMOVLsv2i64

VMOVLsv4i32

VMOVLsv8i16

VMOVLuv2i64

VMOVLuv4i32

VMOVLuv8i16

VMOVNv2i32

VMOVNv4i16

VMOVNv8i8

VMOVRH

VMOVRRD

VMOVRRS

VMOVRS

VMOVS

VMOVSR

VMOVSRR

VMOVv16i8

VMOVv1i64

VMOVv2f32

VMOVv2i32

VMOVv2i64

VMOVv4f32

VMOVv4i16

VMOVv4i32

VMOVv8i16

VMOVv8i8

VMRS

VMRS_FPCXTNS

VMRS_FPCXTS

VMRS_FPEXC

VMRS_FPINST

VMRS_FPINST2

VMRS_FPSCR_NZCVQC

VMRS_FPSID

VMRS_MVFR0

VMRS_MVFR1

VMRS_MVFR2

VMRS_P0

VMRS_VPR

VMSR

VMSR_FPCXTNS

VMSR_FPCXTS

VMSR_FPEXC

VMSR_FPINST

VMSR_FPINST2

VMSR_FPSCR_NZCVQC

VMSR_FPSID

VMSR_P0

VMSR_VPR

VMULD

VMULH

VMULLp64

VMULLp8

VMULLslsv2i32

VMULLslsv4i16

VMULLsluv2i32

VMULLsluv4i16

VMULLsv2i64

VMULLsv4i32

VMULLsv8i16

VMULLuv2i64

VMULLuv4i32

VMULLuv8i16

VMULS

VMULfd

VMULfq

VMULhd

VMULhq

VMULpd

VMULpq

VMULslfd

VMULslfq

VMULslhd

VMULslhq

VMULslv2i32

VMULslv4i16

VMULslv4i32

VMULslv8i16

VMULv16i8

VMULv2i32

VMULv4i16

VMULv4i32

VMULv8i16

VMULv8i8

VMVNd

VMVNq

VMVNv2i32

VMVNv4i16

VMVNv4i32

VMVNv8i16

VNEGD

VNEGH

VNEGS

VNEGf32q

VNEGfd

VNEGhd

VNEGhq

VNEGs16d

VNEGs16q

VNEGs32d

VNEGs32q

VNEGs8d

VNEGs8q

VNMLAD

VNMLAH

VNMLAS

VNMLSD

VNMLSH

VNMLSS

VNMULD

VNMULH

VNMULS

VORNd

VORNq

VORRd

VORRiv2i32

VORRiv4i16

VORRiv4i32

VORRiv8i16

VORRq

VPADALsv16i8

VPADALsv2i32

VPADALsv4i16

VPADALsv4i32

VPADALsv8i16

VPADALsv8i8

VPADALuv16i8

VPADALuv2i32

VPADALuv4i16

VPADALuv4i32

VPADALuv8i16

VPADALuv8i8

VPADDLsv16i8

VPADDLsv2i32

VPADDLsv4i16

VPADDLsv4i32

VPADDLsv8i16

VPADDLsv8i8

VPADDLuv16i8

VPADDLuv2i32

VPADDLuv4i16

VPADDLuv4i32

VPADDLuv8i16

VPADDLuv8i8

VPADDf

VPADDh

VPADDi16

VPADDi32

VPADDi8

VPMAXf

VPMAXh

VPMAXs16

VPMAXs32

VPMAXs8

VPMAXu16

VPMAXu32

VPMAXu8

VPMINf

VPMINh

VPMINs16

VPMINs32

VPMINs8

VPMINu16

VPMINu32

VPMINu8

VQABSv16i8

VQABSv2i32

VQABSv4i16

VQABSv4i32

VQABSv8i16

VQABSv8i8

VQADDsv16i8

VQADDsv1i64

VQADDsv2i32

VQADDsv2i64

VQADDsv4i16

VQADDsv4i32

VQADDsv8i16

VQADDsv8i8

VQADDuv16i8

VQADDuv1i64

VQADDuv2i32

VQADDuv2i64

VQADDuv4i16

VQADDuv4i32

VQADDuv8i16

VQADDuv8i8

VQDMLALslv2i32

VQDMLALslv4i16

VQDMLALv2i64

VQDMLALv4i32

VQDMLSLslv2i32

VQDMLSLslv4i16

VQDMLSLv2i64

VQDMLSLv4i32

VQDMULHslv2i32

VQDMULHslv4i16

VQDMULHslv4i32

VQDMULHslv8i16

VQDMULHv2i32

VQDMULHv4i16

VQDMULHv4i32

VQDMULHv8i16

VQDMULLslv2i32

VQDMULLslv4i16

VQDMULLv2i64

VQDMULLv4i32

VQMOVNsuv2i32

VQMOVNsuv4i16

VQMOVNsuv8i8

VQMOVNsv2i32

VQMOVNsv4i16

VQMOVNsv8i8

VQMOVNuv2i32

VQMOVNuv4i16

VQMOVNuv8i8

VQNEGv16i8

VQNEGv2i32

VQNEGv4i16

VQNEGv4i32

VQNEGv8i16

VQNEGv8i8

VQRDMLAHslv2i32

VQRDMLAHslv4i16

VQRDMLAHslv4i32

VQRDMLAHslv8i16

VQRDMLAHv2i32

VQRDMLAHv4i16

VQRDMLAHv4i32

VQRDMLAHv8i16

VQRDMLSHslv2i32

VQRDMLSHslv4i16

VQRDMLSHslv4i32

VQRDMLSHslv8i16

VQRDMLSHv2i32

VQRDMLSHv4i16

VQRDMLSHv4i32

VQRDMLSHv8i16

VQRDMULHslv2i32

VQRDMULHslv4i16

VQRDMULHslv4i32

VQRDMULHslv8i16

VQRDMULHv2i32

VQRDMULHv4i16

VQRDMULHv4i32

VQRDMULHv8i16

VQRSHLsv16i8

VQRSHLsv1i64

VQRSHLsv2i32

VQRSHLsv2i64

VQRSHLsv4i16

VQRSHLsv4i32

VQRSHLsv8i16

VQRSHLsv8i8

VQRSHLuv16i8

VQRSHLuv1i64

VQRSHLuv2i32

VQRSHLuv2i64

VQRSHLuv4i16

VQRSHLuv4i32

VQRSHLuv8i16

VQRSHLuv8i8

VQRSHRNsv2i32

VQRSHRNsv4i16

VQRSHRNsv8i8

VQRSHRNuv2i32

VQRSHRNuv4i16

VQRSHRNuv8i8

VQRSHRUNv2i32

VQRSHRUNv4i16

VQRSHRUNv8i8

VQSHLsiv16i8

VQSHLsiv1i64

VQSHLsiv2i32

VQSHLsiv2i64

VQSHLsiv4i16

VQSHLsiv4i32

VQSHLsiv8i16

VQSHLsiv8i8

VQSHLsuv16i8

VQSHLsuv1i64

VQSHLsuv2i32

VQSHLsuv2i64

VQSHLsuv4i16

VQSHLsuv4i32

VQSHLsuv8i16

VQSHLsuv8i8

VQSHLsv16i8

VQSHLsv1i64

VQSHLsv2i32

VQSHLsv2i64

VQSHLsv4i16

VQSHLsv4i32

VQSHLsv8i16

VQSHLsv8i8

VQSHLuiv16i8

VQSHLuiv1i64

VQSHLuiv2i32

VQSHLuiv2i64

VQSHLuiv4i16

VQSHLuiv4i32

VQSHLuiv8i16

VQSHLuiv8i8

VQSHLuv16i8

VQSHLuv1i64

VQSHLuv2i32

VQSHLuv2i64

VQSHLuv4i16

VQSHLuv4i32

VQSHLuv8i16

VQSHLuv8i8

VQSHRNsv2i32

VQSHRNsv4i16

VQSHRNsv8i8

VQSHRNuv2i32

VQSHRNuv4i16

VQSHRNuv8i8

VQSHRUNv2i32

VQSHRUNv4i16

VQSHRUNv8i8

VQSUBsv16i8

VQSUBsv1i64

VQSUBsv2i32

VQSUBsv2i64

VQSUBsv4i16

VQSUBsv4i32

VQSUBsv8i16

VQSUBsv8i8

VQSUBuv16i8

VQSUBuv1i64

VQSUBuv2i32

VQSUBuv2i64

VQSUBuv4i16

VQSUBuv4i32

VQSUBuv8i16

VQSUBuv8i8

VRADDHNv2i32

VRADDHNv4i16

VRADDHNv8i8

VRECPEd

VRECPEfd

VRECPEfq

VRECPEhd

VRECPEhq

VRECPEq

VRECPSfd

VRECPSfq

VRECPShd

VRECPShq

VREV16d8

VREV16q8

VREV32d16

VREV32d8

VREV32q16

VREV32q8

VREV64d16

VREV64d32

VREV64d8

VREV64q16

VREV64q32

VREV64q8

VRHADDsv16i8

VRHADDsv2i32

VRHADDsv4i16

VRHADDsv4i32

VRHADDsv8i16

VRHADDsv8i8

VRHADDuv16i8

VRHADDuv2i32

VRHADDuv4i16

VRHADDuv4i32

VRHADDuv8i16

VRHADDuv8i8

VRINTAD

VRINTAH

VRINTANDf

VRINTANDh

VRINTANQf

VRINTANQh

VRINTAS

VRINTMD

VRINTMH

VRINTMNDf

VRINTMNDh

VRINTMNQf

VRINTMNQh

VRINTMS

VRINTND

VRINTNH

VRINTNNDf

VRINTNNDh

VRINTNNQf

VRINTNNQh

VRINTNS

VRINTPD

VRINTPH

VRINTPNDf

VRINTPNDh

VRINTPNQf

VRINTPNQh

VRINTPS

VRINTRD

VRINTRH

VRINTRS

VRINTXD

VRINTXH

VRINTXNDf

VRINTXNDh

VRINTXNQf

VRINTXNQh

VRINTXS

VRINTZD

VRINTZH

VRINTZNDf

VRINTZNDh

VRINTZNQf

VRINTZNQh

VRINTZS

VRSHLsv16i8

VRSHLsv1i64

VRSHLsv2i32

VRSHLsv2i64

VRSHLsv4i16

VRSHLsv4i32

VRSHLsv8i16

VRSHLsv8i8

VRSHLuv16i8

VRSHLuv1i64

VRSHLuv2i32

VRSHLuv2i64

VRSHLuv4i16

VRSHLuv4i32

VRSHLuv8i16

VRSHLuv8i8

VRSHRNv2i32

VRSHRNv4i16

VRSHRNv8i8

VRSHRsv16i8

VRSHRsv1i64

VRSHRsv2i32

VRSHRsv2i64

VRSHRsv4i16

VRSHRsv4i32

VRSHRsv8i16

VRSHRsv8i8

VRSHRuv16i8

VRSHRuv1i64

VRSHRuv2i32

VRSHRuv2i64

VRSHRuv4i16

VRSHRuv4i32

VRSHRuv8i16

VRSHRuv8i8

VRSQRTEd

VRSQRTEfd

VRSQRTEfq

VRSQRTEhd

VRSQRTEhq

VRSQRTEq

VRSQRTSfd

VRSQRTSfq

VRSQRTShd

VRSQRTShq

VRSRAsv16i8

VRSRAsv1i64

VRSRAsv2i32

VRSRAsv2i64

VRSRAsv4i16

VRSRAsv4i32

VRSRAsv8i16

VRSRAsv8i8

VRSRAuv16i8

VRSRAuv1i64

VRSRAuv2i32

VRSRAuv2i64

VRSRAuv4i16

VRSRAuv4i32

VRSRAuv8i16

VRSRAuv8i8

VRSUBHNv2i32

VRSUBHNv4i16

VRSUBHNv8i8

VSCCLRMD

VSCCLRMS

VSDOTD

VSDOTDI

VSDOTQ

VSDOTQI

VSELEQD

VSELEQH

VSELEQS

VSELGED

VSELGEH

VSELGES

VSELGTD

VSELGTH

VSELGTS

VSELVSD

VSELVSH

VSELVSS

VSETLNi16

VSETLNi32

VSETLNi8

VSHLLi16

VSHLLi32

VSHLLi8

VSHLLsv2i64

VSHLLsv4i32

VSHLLsv8i16

VSHLLuv2i64

VSHLLuv4i32

VSHLLuv8i16

VSHLiv16i8

VSHLiv1i64

VSHLiv2i32

VSHLiv2i64

VSHLiv4i16

VSHLiv4i32

VSHLiv8i16

VSHLiv8i8

VSHLsv16i8

VSHLsv1i64

VSHLsv2i32

VSHLsv2i64

VSHLsv4i16

VSHLsv4i32

VSHLsv8i16

VSHLsv8i8

VSHLuv16i8

VSHLuv1i64

VSHLuv2i32

VSHLuv2i64

VSHLuv4i16

VSHLuv4i32

VSHLuv8i16

VSHLuv8i8

VSHRNv2i32

VSHRNv4i16

VSHRNv8i8

VSHRsv16i8

VSHRsv1i64

VSHRsv2i32

VSHRsv2i64

VSHRsv4i16

VSHRsv4i32

VSHRsv8i16

VSHRsv8i8

VSHRuv16i8

VSHRuv1i64

VSHRuv2i32

VSHRuv2i64

VSHRuv4i16

VSHRuv4i32

VSHRuv8i16

VSHRuv8i8

VSHTOD

VSHTOH

VSHTOS

VSITOD

VSITOH

VSITOS

VSLIv16i8

VSLIv1i64

VSLIv2i32

VSLIv2i64

VSLIv4i16

VSLIv4i32

VSLIv8i16

VSLIv8i8

VSLTOD

VSLTOH

VSLTOS

VSMMLA

VSQRTD

VSQRTH

VSQRTS

VSRAsv16i8

VSRAsv1i64

VSRAsv2i32

VSRAsv2i64

VSRAsv4i16

VSRAsv4i32

VSRAsv8i16

VSRAsv8i8

VSRAuv16i8

VSRAuv1i64

VSRAuv2i32

VSRAuv2i64

VSRAuv4i16

VSRAuv4i32

VSRAuv8i16

VSRAuv8i8

VSRIv16i8

VSRIv1i64

VSRIv2i32

VSRIv2i64

VSRIv4i16

VSRIv4i32

VSRIv8i16

VSRIv8i8

VST1LNd16

VST1LNd16_UPD

VST1LNd32

VST1LNd32_UPD

VST1LNd8

VST1LNd8_UPD

VST1LNq16Pseudo

VST1LNq16Pseudo_UPD

VST1LNq32Pseudo

VST1LNq32Pseudo_UPD

VST1LNq8Pseudo

VST1LNq8Pseudo_UPD

VST1d16

VST1d16Q

VST1d16QPseudo

VST1d16QPseudoWB_fixed

VST1d16QPseudoWB_register

VST1d16Qwb_fixed

VST1d16Qwb_register

VST1d16T

VST1d16TPseudo

VST1d16TPseudoWB_fixed

VST1d16TPseudoWB_register

VST1d16Twb_fixed

VST1d16Twb_register

VST1d16wb_fixed

VST1d16wb_register

VST1d32

VST1d32Q

VST1d32QPseudo

VST1d32QPseudoWB_fixed

VST1d32QPseudoWB_register

VST1d32Qwb_fixed

VST1d32Qwb_register

VST1d32T

VST1d32TPseudo

VST1d32TPseudoWB_fixed

VST1d32TPseudoWB_register

VST1d32Twb_fixed

VST1d32Twb_register

VST1d32wb_fixed

VST1d32wb_register

VST1d64

VST1d64Q

VST1d64QPseudo

VST1d64QPseudoWB_fixed

VST1d64QPseudoWB_register

VST1d64Qwb_fixed

VST1d64Qwb_register

VST1d64T

VST1d64TPseudo

VST1d64TPseudoWB_fixed

VST1d64TPseudoWB_register

VST1d64Twb_fixed

VST1d64Twb_register

VST1d64wb_fixed

VST1d64wb_register

VST1d8

VST1d8Q

VST1d8QPseudo

VST1d8QPseudoWB_fixed

VST1d8QPseudoWB_register

VST1d8Qwb_fixed

VST1d8Qwb_register

VST1d8T

VST1d8TPseudo

VST1d8TPseudoWB_fixed

VST1d8TPseudoWB_register

VST1d8Twb_fixed

VST1d8Twb_register

VST1d8wb_fixed

VST1d8wb_register

VST1q16

VST1q16HighQPseudo

VST1q16HighQPseudo_UPD

VST1q16HighTPseudo

VST1q16HighTPseudo_UPD

VST1q16LowQPseudo_UPD

VST1q16LowTPseudo_UPD

VST1q16wb_fixed

VST1q16wb_register

VST1q32

VST1q32HighQPseudo

VST1q32HighQPseudo_UPD

VST1q32HighTPseudo

VST1q32HighTPseudo_UPD

VST1q32LowQPseudo_UPD

VST1q32LowTPseudo_UPD

VST1q32wb_fixed

VST1q32wb_register

VST1q64

VST1q64HighQPseudo

VST1q64HighQPseudo_UPD

VST1q64HighTPseudo

VST1q64HighTPseudo_UPD

VST1q64LowQPseudo_UPD

VST1q64LowTPseudo_UPD

VST1q64wb_fixed

VST1q64wb_register

VST1q8

VST1q8HighQPseudo

VST1q8HighQPseudo_UPD

VST1q8HighTPseudo

VST1q8HighTPseudo_UPD

VST1q8LowQPseudo_UPD

VST1q8LowTPseudo_UPD

VST1q8wb_fixed

VST1q8wb_register

VST2LNd16

VST2LNd16Pseudo

VST2LNd16Pseudo_UPD

VST2LNd16_UPD

VST2LNd32

VST2LNd32Pseudo

VST2LNd32Pseudo_UPD

VST2LNd32_UPD

VST2LNd8

VST2LNd8Pseudo

VST2LNd8Pseudo_UPD

VST2LNd8_UPD

VST2LNq16

VST2LNq16Pseudo

VST2LNq16Pseudo_UPD

VST2LNq16_UPD

VST2LNq32

VST2LNq32Pseudo

VST2LNq32Pseudo_UPD

VST2LNq32_UPD

VST2b16

VST2b16wb_fixed

VST2b16wb_register

VST2b32

VST2b32wb_fixed

VST2b32wb_register

VST2b8

VST2b8wb_fixed

VST2b8wb_register

VST2d16

VST2d16wb_fixed

VST2d16wb_register

VST2d32

VST2d32wb_fixed

VST2d32wb_register

VST2d8

VST2d8wb_fixed

VST2d8wb_register

VST2q16

VST2q16Pseudo

VST2q16PseudoWB_fixed

VST2q16PseudoWB_register

VST2q16wb_fixed

VST2q16wb_register

VST2q32

VST2q32Pseudo

VST2q32PseudoWB_fixed

VST2q32PseudoWB_register

VST2q32wb_fixed

VST2q32wb_register

VST2q8

VST2q8Pseudo

VST2q8PseudoWB_fixed

VST2q8PseudoWB_register

VST2q8wb_fixed

VST2q8wb_register

VST3LNd16

VST3LNd16Pseudo

VST3LNd16Pseudo_UPD

VST3LNd16_UPD

VST3LNd32

VST3LNd32Pseudo

VST3LNd32Pseudo_UPD

VST3LNd32_UPD

VST3LNd8

VST3LNd8Pseudo

VST3LNd8Pseudo_UPD

VST3LNd8_UPD

VST3LNq16

VST3LNq16Pseudo

VST3LNq16Pseudo_UPD

VST3LNq16_UPD

VST3LNq32

VST3LNq32Pseudo

VST3LNq32Pseudo_UPD

VST3LNq32_UPD

VST3d16

VST3d16Pseudo

VST3d16Pseudo_UPD

VST3d16_UPD

VST3d32

VST3d32Pseudo

VST3d32Pseudo_UPD

VST3d32_UPD

VST3d8

VST3d8Pseudo

VST3d8Pseudo_UPD

VST3d8_UPD

VST3q16

VST3q16Pseudo_UPD

VST3q16_UPD

VST3q16oddPseudo

VST3q16oddPseudo_UPD

VST3q32

VST3q32Pseudo_UPD

VST3q32_UPD

VST3q32oddPseudo

VST3q32oddPseudo_UPD

VST3q8

VST3q8Pseudo_UPD

VST3q8_UPD

VST3q8oddPseudo

VST3q8oddPseudo_UPD

VST4LNd16

VST4LNd16Pseudo

VST4LNd16Pseudo_UPD

VST4LNd16_UPD

VST4LNd32

VST4LNd32Pseudo

VST4LNd32Pseudo_UPD

VST4LNd32_UPD

VST4LNd8

VST4LNd8Pseudo

VST4LNd8Pseudo_UPD

VST4LNd8_UPD

VST4LNq16

VST4LNq16Pseudo

VST4LNq16Pseudo_UPD

VST4LNq16_UPD

VST4LNq32

VST4LNq32Pseudo

VST4LNq32Pseudo_UPD

VST4LNq32_UPD

VST4d16

VST4d16Pseudo

VST4d16Pseudo_UPD

VST4d16_UPD

VST4d32

VST4d32Pseudo

VST4d32Pseudo_UPD

VST4d32_UPD

VST4d8

VST4d8Pseudo

VST4d8Pseudo_UPD

VST4d8_UPD

VST4q16

VST4q16Pseudo_UPD

VST4q16_UPD

VST4q16oddPseudo

VST4q16oddPseudo_UPD

VST4q32

VST4q32Pseudo_UPD

VST4q32_UPD

VST4q32oddPseudo

VST4q32oddPseudo_UPD

VST4q8

VST4q8Pseudo_UPD

VST4q8_UPD

VST4q8oddPseudo

VST4q8oddPseudo_UPD

VSTMDDB_UPD

VSTMDIA

VSTMDIA_UPD

VSTMQIA

VSTMSDB_UPD

VSTMSIA

VSTMSIA_UPD

VSTRD

VSTRH

VSTRS

VSTR_FPCXTNS_off

VSTR_FPCXTNS_post

VSTR_FPCXTNS_pre

VSTR_FPCXTS_off

VSTR_FPCXTS_post

VSTR_FPCXTS_pre

VSTR_FPSCR_NZCVQC_off

VSTR_FPSCR_NZCVQC_post

VSTR_FPSCR_NZCVQC_pre

VSTR_FPSCR_off

VSTR_FPSCR_post

VSTR_FPSCR_pre

VSTR_P0_off

VSTR_P0_post

VSTR_P0_pre

VSTR_VPR_off

VSTR_VPR_post

VSTR_VPR_pre

VSUBD

VSUBH

VSUBHNv2i32

VSUBHNv4i16

VSUBHNv8i8

VSUBLsv2i64

VSUBLsv4i32

VSUBLsv8i16

VSUBLuv2i64

VSUBLuv4i32

VSUBLuv8i16

VSUBS

VSUBWsv2i64

VSUBWsv4i32

VSUBWsv8i16

VSUBWuv2i64

VSUBWuv4i32

VSUBWuv8i16

VSUBfd

VSUBfq

VSUBhd

VSUBhq

VSUBv16i8

VSUBv1i64

VSUBv2i32

VSUBv2i64

VSUBv4i16

VSUBv4i32

VSUBv8i16

VSUBv8i8

VSUDOTDI

VSUDOTQI

VSWPd

VSWPq

VTBL1

VTBL2

VTBL3

VTBL3Pseudo

VTBL4

VTBL4Pseudo

VTBX1

VTBX2

VTBX3

VTBX3Pseudo

VTBX4

VTBX4Pseudo

VTOSHD

VTOSHH

VTOSHS

VTOSIRD

VTOSIRH

VTOSIRS

VTOSIZD

VTOSIZH

VTOSIZS

VTOSLD

VTOSLH

VTOSLS

VTOUHD

VTOUHH

VTOUHS

VTOUIRD

VTOUIRH

VTOUIRS

VTOUIZD

VTOUIZH

VTOUIZS

VTOULD

VTOULH

VTOULS

VTRNd16

VTRNd32

VTRNd8

VTRNq16

VTRNq32

VTRNq8

VTSTv16i8

VTSTv2i32

VTSTv4i16

VTSTv4i32

VTSTv8i16

VTSTv8i8

VUDOTD

VUDOTDI

VUDOTQ

VUDOTQI

VUHTOD

VUHTOH

VUHTOS

VUITOD

VUITOH

VUITOS

VULTOD

VULTOH

VULTOS

VUMMLA

VUSDOTD

VUSDOTDI

VUSDOTQ

VUSDOTQI

VUSMMLA

VUZPd16

VUZPd8

VUZPq16

VUZPq32

VUZPq8

VZIPd16

VZIPd8

VZIPq16

VZIPq32

VZIPq8

sysLDMDA

sysLDMDA_UPD

sysLDMDB

sysLDMDB_UPD

sysLDMIA

sysLDMIA_UPD

sysLDMIB

sysLDMIB_UPD

sysSTMDA

sysSTMDA_UPD

sysSTMDB

sysSTMDB_UPD

sysSTMIA

sysSTMIA_UPD

sysSTMIB

sysSTMIB_UPD

t2ADCri

t2ADCrr

t2ADCrs

t2ADDri

t2ADDri12

t2ADDrr

t2ADDrs

t2ADDspImm

t2ADDspImm12

t2ADR

t2ANDri

t2ANDrr

t2ANDrs

t2ASRri

t2ASRrr

t2AUT

t2AUTG

t2B

t2BFC

t2BFI

t2BFLi

t2BFLr

t2BFi

t2BFic

t2BFr

t2BICri

t2BICrr

t2BICrs

t2BTI

t2BXAUT

t2BXJ

t2Bcc

t2CDP

t2CDP2

t2CLREX

t2CLRM

t2CLZ

t2CMNri

t2CMNzrr

t2CMNzrs

t2CMPri

t2CMPrr

t2CMPrs

t2CPS1p

t2CPS2p

t2CPS3p

t2CRC32B

t2CRC32CB

t2CRC32CH

t2CRC32CW

t2CRC32H

t2CRC32W

t2CSEL

t2CSINC

t2CSINV

t2CSNEG

t2DBG

t2DCPS1

t2DCPS2

t2DCPS3

t2DLS

t2DMB

t2DSB

t2EORri

t2EORrr

t2EORrs

t2HINT

t2HVC

t2ISB

t2IT

t2Int_eh_sjlj_setjmp

t2Int_eh_sjlj_setjmp_nofp

t2LDA

t2LDAB

t2LDAEX

t2LDAEXB

t2LDAEXD

t2LDAEXH

t2LDAH

t2LDC2L_OFFSET

t2LDC2L_OPTION

t2LDC2L_POST

t2LDC2L_PRE

t2LDC2_OFFSET

t2LDC2_OPTION

t2LDC2_POST

t2LDC2_PRE

t2LDCL_OFFSET

t2LDCL_OPTION

t2LDCL_POST

t2LDCL_PRE

t2LDC_OFFSET

t2LDC_OPTION

t2LDC_POST

t2LDC_PRE

t2LDMDB

t2LDMDB_UPD

t2LDMIA

t2LDMIA_UPD

t2LDRBT

t2LDRB_POST

t2LDRB_PRE

t2LDRBi12

t2LDRBi8

t2LDRBpci

t2LDRBs

t2LDRD_POST

t2LDRD_PRE

t2LDRDi8

t2LDREX

t2LDREXB

t2LDREXD

t2LDREXH

t2LDRHT

t2LDRH_POST

t2LDRH_PRE

t2LDRHi12

t2LDRHi8

t2LDRHpci

t2LDRHs

t2LDRSBT

t2LDRSB_POST

t2LDRSB_PRE

t2LDRSBi12

t2LDRSBi8

t2LDRSBpci

t2LDRSBs

t2LDRSHT

t2LDRSH_POST

t2LDRSH_PRE

t2LDRSHi12

t2LDRSHi8

t2LDRSHpci

t2LDRSHs

t2LDRT

t2LDR_POST

t2LDR_PRE

t2LDRi12

t2LDRi8

t2LDRpci

t2LDRs

t2LE

t2LEUpdate

t2LSLri

t2LSLrr

t2LSRri

t2LSRrr

t2MCR

t2MCR2

t2MCRR

t2MCRR2

t2MLA

t2MLS

t2MOVTi16

t2MOVi

t2MOVi16

t2MOVr

t2MOVsra_glue

t2MOVsrl_glue

t2MRC

t2MRC2

t2MRRC

t2MRRC2

t2MRS_AR

t2MRS_M

t2MRSbanked

t2MRSsys_AR

t2MSR_AR

t2MSR_M

t2MSRbanked

t2MUL

t2MVNi

t2MVNr

t2MVNs

t2ORNri

t2ORNrr

t2ORNrs

t2ORRri

t2ORRrr

t2ORRrs

t2PAC

t2PACBTI

t2PACG

t2PKHBT

t2PKHTB

t2PLDWi12

t2PLDWi8

t2PLDWs

t2PLDi12

t2PLDi8

t2PLDpci

t2PLDs

t2PLIi12

t2PLIi8

t2PLIpci

t2PLIs

t2QADD

t2QADD16

t2QADD8

t2QASX

t2QDADD

t2QDSUB

t2QSAX

t2QSUB

t2QSUB16

t2QSUB8

t2RBIT

t2REV

t2REV16

t2REVSH

t2RFEDB

t2RFEDBW

t2RFEIA

t2RFEIAW

t2RORri

t2RORrr

t2RRX

t2RSBri

t2RSBrr

t2RSBrs

t2SADD16

t2SADD8

t2SASX

t2SB

t2SBCri

t2SBCrr

t2SBCrs

t2SBFX

t2SDIV

t2SEL

t2SETPAN

t2SG

t2SHADD16

t2SHADD8

t2SHASX

t2SHSAX

t2SHSUB16

t2SHSUB8

t2SMC

t2SMLABB

t2SMLABT

t2SMLAD

t2SMLADX

t2SMLAL

t2SMLALBB

t2SMLALBT

t2SMLALD

t2SMLALDX

t2SMLALTB

t2SMLALTT

t2SMLATB

t2SMLATT

t2SMLAWB

t2SMLAWT

t2SMLSD

t2SMLSDX

t2SMLSLD

t2SMLSLDX

t2SMMLA

t2SMMLAR

t2SMMLS

t2SMMLSR

t2SMMUL

t2SMMULR

t2SMUAD

t2SMUADX

t2SMULBB

t2SMULBT

t2SMULL

t2SMULTB

t2SMULTT

t2SMULWB

t2SMULWT

t2SMUSD

t2SMUSDX

t2SRSDB

t2SRSDB_UPD

t2SRSIA

t2SRSIA_UPD

t2SSAT

t2SSAT16

t2SSAX

t2SSUB16

t2SSUB8

t2STC2L_OFFSET

t2STC2L_OPTION

t2STC2L_POST

t2STC2L_PRE

t2STC2_OFFSET

t2STC2_OPTION

t2STC2_POST

t2STC2_PRE

t2STCL_OFFSET

t2STCL_OPTION

t2STCL_POST

t2STCL_PRE

t2STC_OFFSET

t2STC_OPTION

t2STC_POST

t2STC_PRE

t2STL

t2STLB

t2STLEX

t2STLEXB

t2STLEXD

t2STLEXH

t2STLH

t2STMDB

t2STMDB_UPD

t2STMIA

t2STMIA_UPD

t2STRBT

t2STRB_POST

t2STRB_PRE

t2STRBi12

t2STRBi8

t2STRBs

t2STRD_POST

t2STRD_PRE

t2STRDi8

t2STREX

t2STREXB

t2STREXD

t2STREXH

t2STRHT

t2STRH_POST

t2STRH_PRE

t2STRHi12

t2STRHi8

t2STRHs

t2STRT

t2STR_POST

t2STR_PRE

t2STRi12

t2STRi8

t2STRs

t2SUBS_PC_LR

t2SUBri

t2SUBri12

t2SUBrr

t2SUBrs

t2SUBspImm

t2SUBspImm12

t2SXTAB

t2SXTAB16

t2SXTAH

t2SXTB

t2SXTB16

t2SXTH

t2TBB

t2TBH

t2TEQri

t2TEQrr

t2TEQrs

t2TSB

t2TSTri

t2TSTrr

t2TSTrs

t2TT

t2TTA

t2TTAT

t2TTT

t2UADD16

t2UADD8

t2UASX

t2UBFX

t2UDF

t2UDIV

t2UHADD16

t2UHADD8

t2UHASX

t2UHSAX

t2UHSUB16

t2UHSUB8

t2UMAAL

t2UMLAL

t2UMULL

t2UQADD16

t2UQADD8

t2UQASX

t2UQSAX

t2UQSUB16

t2UQSUB8

t2USAD8

t2USADA8

t2USAT

t2USAT16

t2USAX

t2USUB16

t2USUB8

t2UXTAB

t2UXTAB16

t2UXTAH

t2UXTB

t2UXTB16

t2UXTH

t2WLS

tADC

tADDhirr

tADDi3

tADDi8

tADDrSP

tADDrSPi

tADDrr

tADDspi

tADDspr

tADR

tAND

tASRri

tASRrr

tB

tBIC

tBKPT

tBL

tBLXNSr

tBLXi

tBLXr

tBX

tBXNS

tBcc

tCBNZ

tCBZ

tCMNz

tCMPhir

tCMPi8

tCMPr

tCPS

tEOR

tHINT

tHLT

tInt_WIN_eh_sjlj_longjmp

tInt_eh_sjlj_longjmp

tInt_eh_sjlj_setjmp

tLDMIA

tLDRBi

tLDRBr

tLDRHi

tLDRHr

tLDRSB

tLDRSH

tLDRi

tLDRpci

tLDRr

tLDRspi

tLSLri

tLSLrr

tLSRri

tLSRrr

tMOVSr

tMOVi8

tMOVr

tMUL

tMVN

tORR

tPICADD

tPOP

tPUSH

tREV

tREV16

tREVSH

tROR

tRSB

tSBC

tSETEND

tSTMIA_UPD

tSTRBi

tSTRBr

tSTRHi

tSTRHr

tSTRi

tSTRr

tSTRspi

tSUBi3

tSUBi8

tSUBrr

tSUBspi

tSVC

tSXTB

tSXTH

tTRAP

tTST

tUDF

tUXTB

tUXTH

t__brkdiv0

INSTRUCTION_LIST_END

UNKNOWN(u64)

Trait Implementations

impl Clone for Opcode

fn clone(&self) -> Opcode

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Opcode

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl From<u64> for Opcode

fn from(value: u64) -> Self

Converts to this type from the input type.

impl Hash for Opcode

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl Ord for Opcode

fn cmp(&self, other: &Opcode) -> Ordering

This method returns an Ordering between self and other.

fn max(self, other: Self) -> Selfwhere Self: Sized,

Compares and returns the maximum of two values.

fn min(self, other: Self) -> Selfwhere Self: Sized,

Compares and returns the minimum of two values.

fn clamp(self, min: Self, max: Self) -> Selfwhere Self: Sized + PartialOrd<Self>,

Restrict a value to a certain interval.

impl PartialEq<Opcode> for Opcode

fn eq(&self, other: &Opcode) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl PartialOrd<Opcode> for Opcode

fn partial_cmp(&self, other: &Opcode) -> Option<Ordering>

This method returns an ordering between self and other values if one exists.

fn lt(&self, other: &Rhs) -> bool

This method tests less than (for self and other) and is used by the < operator.

fn le(&self, other: &Rhs) -> bool

This method tests less than or equal to (for self and other) and is used by the <= operator.

fn gt(&self, other: &Rhs) -> bool

This method tests greater than (for self and other) and is used by the > operator.

fn ge(&self, other: &Rhs) -> bool

This method tests greater than or equal to (for self and other) and is used by the >= operator.

impl Copy for Opcode

impl Eq for Opcode

impl StructuralEq for Opcode

impl StructuralPartialEq for Opcode