Line data Source code
1 : #[allow(non_camel_case_types)]
2 0 : #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
3 : pub enum Opcode {
4 : PHI,
5 : INLINEASM,
6 : INLINEASM_BR,
7 : CFI_INSTRUCTION,
8 : EH_LABEL,
9 : GC_LABEL,
10 : ANNOTATION_LABEL,
11 : KILL,
12 : EXTRACT_SUBREG,
13 : INSERT_SUBREG,
14 : IMPLICIT_DEF,
15 : SUBREG_TO_REG,
16 : COPY_TO_REGCLASS,
17 : DBG_VALUE,
18 : DBG_VALUE_LIST,
19 : DBG_INSTR_REF,
20 : DBG_PHI,
21 : DBG_LABEL,
22 : REG_SEQUENCE,
23 : COPY,
24 : BUNDLE,
25 : LIFETIME_START,
26 : LIFETIME_END,
27 : PSEUDO_PROBE,
28 : ARITH_FENCE,
29 : STACKMAP,
30 : FENTRY_CALL,
31 : PATCHPOINT,
32 : LOAD_STACK_GUARD,
33 : PREALLOCATED_SETUP,
34 : PREALLOCATED_ARG,
35 : STATEPOINT,
36 : LOCAL_ESCAPE,
37 : FAULTING_OP,
38 : PATCHABLE_OP,
39 : PATCHABLE_FUNCTION_ENTER,
40 : PATCHABLE_RET,
41 : PATCHABLE_FUNCTION_EXIT,
42 : PATCHABLE_TAIL_CALL,
43 : PATCHABLE_EVENT_CALL,
44 : PATCHABLE_TYPED_EVENT_CALL,
45 : ICALL_BRANCH_FUNNEL,
46 : MEMBARRIER,
47 : JUMP_TABLE_DEBUG_INFO,
48 : CONVERGENCECTRL_ENTRY,
49 : CONVERGENCECTRL_ANCHOR,
50 : CONVERGENCECTRL_LOOP,
51 : CONVERGENCECTRL_GLUE,
52 : G_ASSERT_SEXT,
53 : G_ASSERT_ZEXT,
54 : G_ASSERT_ALIGN,
55 : G_ADD,
56 : G_SUB,
57 : G_MUL,
58 : G_SDIV,
59 : G_UDIV,
60 : G_SREM,
61 : G_UREM,
62 : G_SDIVREM,
63 : G_UDIVREM,
64 : G_AND,
65 : G_OR,
66 : G_XOR,
67 : G_IMPLICIT_DEF,
68 : G_PHI,
69 : G_FRAME_INDEX,
70 : G_GLOBAL_VALUE,
71 : G_PTRAUTH_GLOBAL_VALUE,
72 : G_CONSTANT_POOL,
73 : G_EXTRACT,
74 : G_UNMERGE_VALUES,
75 : G_INSERT,
76 : G_MERGE_VALUES,
77 : G_BUILD_VECTOR,
78 : G_BUILD_VECTOR_TRUNC,
79 : G_CONCAT_VECTORS,
80 : G_PTRTOINT,
81 : G_INTTOPTR,
82 : G_BITCAST,
83 : G_FREEZE,
84 : G_CONSTANT_FOLD_BARRIER,
85 : G_INTRINSIC_FPTRUNC_ROUND,
86 : G_INTRINSIC_TRUNC,
87 : G_INTRINSIC_ROUND,
88 : G_INTRINSIC_LRINT,
89 : G_INTRINSIC_LLRINT,
90 : G_INTRINSIC_ROUNDEVEN,
91 : G_READCYCLECOUNTER,
92 : G_READSTEADYCOUNTER,
93 : G_LOAD,
94 : G_SEXTLOAD,
95 : G_ZEXTLOAD,
96 : G_INDEXED_LOAD,
97 : G_INDEXED_SEXTLOAD,
98 : G_INDEXED_ZEXTLOAD,
99 : G_STORE,
100 : G_INDEXED_STORE,
101 : G_ATOMIC_CMPXCHG_WITH_SUCCESS,
102 : G_ATOMIC_CMPXCHG,
103 : G_ATOMICRMW_XCHG,
104 : G_ATOMICRMW_ADD,
105 : G_ATOMICRMW_SUB,
106 : G_ATOMICRMW_AND,
107 : G_ATOMICRMW_NAND,
108 : G_ATOMICRMW_OR,
109 : G_ATOMICRMW_XOR,
110 : G_ATOMICRMW_MAX,
111 : G_ATOMICRMW_MIN,
112 : G_ATOMICRMW_UMAX,
113 : G_ATOMICRMW_UMIN,
114 : G_ATOMICRMW_FADD,
115 : G_ATOMICRMW_FSUB,
116 : G_ATOMICRMW_FMAX,
117 : G_ATOMICRMW_FMIN,
118 : G_ATOMICRMW_UINC_WRAP,
119 : G_ATOMICRMW_UDEC_WRAP,
120 : G_FENCE,
121 : G_PREFETCH,
122 : G_BRCOND,
123 : G_BRINDIRECT,
124 : G_INVOKE_REGION_START,
125 : G_INTRINSIC,
126 : G_INTRINSIC_W_SIDE_EFFECTS,
127 : G_INTRINSIC_CONVERGENT,
128 : G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS,
129 : G_ANYEXT,
130 : G_TRUNC,
131 : G_CONSTANT,
132 : G_FCONSTANT,
133 : G_VASTART,
134 : G_VAARG,
135 : G_SEXT,
136 : G_SEXT_INREG,
137 : G_ZEXT,
138 : G_SHL,
139 : G_LSHR,
140 : G_ASHR,
141 : G_FSHL,
142 : G_FSHR,
143 : G_ROTR,
144 : G_ROTL,
145 : G_ICMP,
146 : G_FCMP,
147 : G_SCMP,
148 : G_UCMP,
149 : G_SELECT,
150 : G_UADDO,
151 : G_UADDE,
152 : G_USUBO,
153 : G_USUBE,
154 : G_SADDO,
155 : G_SADDE,
156 : G_SSUBO,
157 : G_SSUBE,
158 : G_UMULO,
159 : G_SMULO,
160 : G_UMULH,
161 : G_SMULH,
162 : G_UADDSAT,
163 : G_SADDSAT,
164 : G_USUBSAT,
165 : G_SSUBSAT,
166 : G_USHLSAT,
167 : G_SSHLSAT,
168 : G_SMULFIX,
169 : G_UMULFIX,
170 : G_SMULFIXSAT,
171 : G_UMULFIXSAT,
172 : G_SDIVFIX,
173 : G_UDIVFIX,
174 : G_SDIVFIXSAT,
175 : G_UDIVFIXSAT,
176 : G_FADD,
177 : G_FSUB,
178 : G_FMUL,
179 : G_FMA,
180 : G_FMAD,
181 : G_FDIV,
182 : G_FREM,
183 : G_FPOW,
184 : G_FPOWI,
185 : G_FEXP,
186 : G_FEXP2,
187 : G_FEXP10,
188 : G_FLOG,
189 : G_FLOG2,
190 : G_FLOG10,
191 : G_FLDEXP,
192 : G_FFREXP,
193 : G_FNEG,
194 : G_FPEXT,
195 : G_FPTRUNC,
196 : G_FPTOSI,
197 : G_FPTOUI,
198 : G_SITOFP,
199 : G_UITOFP,
200 : G_FABS,
201 : G_FCOPYSIGN,
202 : G_IS_FPCLASS,
203 : G_FCANONICALIZE,
204 : G_FMINNUM,
205 : G_FMAXNUM,
206 : G_FMINNUM_IEEE,
207 : G_FMAXNUM_IEEE,
208 : G_FMINIMUM,
209 : G_FMAXIMUM,
210 : G_GET_FPENV,
211 : G_SET_FPENV,
212 : G_RESET_FPENV,
213 : G_GET_FPMODE,
214 : G_SET_FPMODE,
215 : G_RESET_FPMODE,
216 : G_PTR_ADD,
217 : G_PTRMASK,
218 : G_SMIN,
219 : G_SMAX,
220 : G_UMIN,
221 : G_UMAX,
222 : G_ABS,
223 : G_LROUND,
224 : G_LLROUND,
225 : G_BR,
226 : G_BRJT,
227 : G_VSCALE,
228 : G_INSERT_SUBVECTOR,
229 : G_EXTRACT_SUBVECTOR,
230 : G_INSERT_VECTOR_ELT,
231 : G_EXTRACT_VECTOR_ELT,
232 : G_SHUFFLE_VECTOR,
233 : G_SPLAT_VECTOR,
234 : G_VECTOR_COMPRESS,
235 : G_CTTZ,
236 : G_CTTZ_ZERO_UNDEF,
237 : G_CTLZ,
238 : G_CTLZ_ZERO_UNDEF,
239 : G_CTPOP,
240 : G_BSWAP,
241 : G_BITREVERSE,
242 : G_FCEIL,
243 : G_FCOS,
244 : G_FSIN,
245 : G_FTAN,
246 : G_FACOS,
247 : G_FASIN,
248 : G_FATAN,
249 : G_FCOSH,
250 : G_FSINH,
251 : G_FTANH,
252 : G_FSQRT,
253 : G_FFLOOR,
254 : G_FRINT,
255 : G_FNEARBYINT,
256 : G_ADDRSPACE_CAST,
257 : G_BLOCK_ADDR,
258 : G_JUMP_TABLE,
259 : G_DYN_STACKALLOC,
260 : G_STACKSAVE,
261 : G_STACKRESTORE,
262 : G_STRICT_FADD,
263 : G_STRICT_FSUB,
264 : G_STRICT_FMUL,
265 : G_STRICT_FDIV,
266 : G_STRICT_FREM,
267 : G_STRICT_FMA,
268 : G_STRICT_FSQRT,
269 : G_STRICT_FLDEXP,
270 : G_READ_REGISTER,
271 : G_WRITE_REGISTER,
272 : G_MEMCPY,
273 : G_MEMCPY_INLINE,
274 : G_MEMMOVE,
275 : G_MEMSET,
276 : G_BZERO,
277 : G_TRAP,
278 : G_DEBUGTRAP,
279 : G_UBSANTRAP,
280 : G_VECREDUCE_SEQ_FADD,
281 : G_VECREDUCE_SEQ_FMUL,
282 : G_VECREDUCE_FADD,
283 : G_VECREDUCE_FMUL,
284 : G_VECREDUCE_FMAX,
285 : G_VECREDUCE_FMIN,
286 : G_VECREDUCE_FMAXIMUM,
287 : G_VECREDUCE_FMINIMUM,
288 : G_VECREDUCE_ADD,
289 : G_VECREDUCE_MUL,
290 : G_VECREDUCE_AND,
291 : G_VECREDUCE_OR,
292 : G_VECREDUCE_XOR,
293 : G_VECREDUCE_SMAX,
294 : G_VECREDUCE_SMIN,
295 : G_VECREDUCE_UMAX,
296 : G_VECREDUCE_UMIN,
297 : G_SBFX,
298 : G_UBFX,
299 : ADJCALLSTACKDOWN,
300 : ADJCALLSTACKUP,
301 : BuildPairF64Pseudo,
302 : G_FCLASS,
303 : G_READ_VLENB,
304 : G_SPLAT_VECTOR_SPLIT_I64_VL,
305 : G_VMCLR_VL,
306 : G_VMSET_VL,
307 : HWASAN_CHECK_MEMACCESS_SHORTGRANULES,
308 : KCFI_CHECK,
309 : PseudoAddTPRel,
310 : PseudoAtomicLoadNand32,
311 : PseudoAtomicLoadNand64,
312 : PseudoBR,
313 : PseudoBRIND,
314 : PseudoBRINDNonX7,
315 : PseudoBRINDX7,
316 : PseudoCALL,
317 : PseudoCALLIndirect,
318 : PseudoCALLIndirectNonX7,
319 : PseudoCALLReg,
320 : PseudoCCADD,
321 : PseudoCCADDI,
322 : PseudoCCADDIW,
323 : PseudoCCADDW,
324 : PseudoCCAND,
325 : PseudoCCANDI,
326 : PseudoCCANDN,
327 : PseudoCCMOVGPR,
328 : PseudoCCMOVGPRNoX0,
329 : PseudoCCOR,
330 : PseudoCCORI,
331 : PseudoCCORN,
332 : PseudoCCSLL,
333 : PseudoCCSLLI,
334 : PseudoCCSLLIW,
335 : PseudoCCSLLW,
336 : PseudoCCSRA,
337 : PseudoCCSRAI,
338 : PseudoCCSRAIW,
339 : PseudoCCSRAW,
340 : PseudoCCSRL,
341 : PseudoCCSRLI,
342 : PseudoCCSRLIW,
343 : PseudoCCSRLW,
344 : PseudoCCSUB,
345 : PseudoCCSUBW,
346 : PseudoCCXNOR,
347 : PseudoCCXOR,
348 : PseudoCCXORI,
349 : PseudoCmpXchg32,
350 : PseudoCmpXchg64,
351 : PseudoFLD,
352 : PseudoFLH,
353 : PseudoFLW,
354 : PseudoFROUND_D,
355 : PseudoFROUND_D_IN32X,
356 : PseudoFROUND_D_INX,
357 : PseudoFROUND_H,
358 : PseudoFROUND_H_INX,
359 : PseudoFROUND_S,
360 : PseudoFROUND_S_INX,
361 : PseudoFSD,
362 : PseudoFSH,
363 : PseudoFSW,
364 : PseudoJump,
365 : PseudoLA,
366 : PseudoLAImm,
367 : PseudoLA_TLSDESC,
368 : PseudoLA_TLS_GD,
369 : PseudoLA_TLS_IE,
370 : PseudoLB,
371 : PseudoLBU,
372 : PseudoLD,
373 : PseudoLGA,
374 : PseudoLH,
375 : PseudoLHU,
376 : PseudoLI,
377 : PseudoLLA,
378 : PseudoLLAImm,
379 : PseudoLW,
380 : PseudoLWU,
381 : PseudoLongBEQ,
382 : PseudoLongBGE,
383 : PseudoLongBGEU,
384 : PseudoLongBLT,
385 : PseudoLongBLTU,
386 : PseudoLongBNE,
387 : PseudoMaskedAtomicLoadAdd32,
388 : PseudoMaskedAtomicLoadMax32,
389 : PseudoMaskedAtomicLoadMin32,
390 : PseudoMaskedAtomicLoadNand32,
391 : PseudoMaskedAtomicLoadSub32,
392 : PseudoMaskedAtomicLoadUMax32,
393 : PseudoMaskedAtomicLoadUMin32,
394 : PseudoMaskedAtomicSwap32,
395 : PseudoMaskedCmpXchg32,
396 : PseudoMovAddr,
397 : PseudoMovImm,
398 : PseudoQuietFLE_D,
399 : PseudoQuietFLE_D_IN32X,
400 : PseudoQuietFLE_D_INX,
401 : PseudoQuietFLE_H,
402 : PseudoQuietFLE_H_INX,
403 : PseudoQuietFLE_S,
404 : PseudoQuietFLE_S_INX,
405 : PseudoQuietFLT_D,
406 : PseudoQuietFLT_D_IN32X,
407 : PseudoQuietFLT_D_INX,
408 : PseudoQuietFLT_H,
409 : PseudoQuietFLT_H_INX,
410 : PseudoQuietFLT_S,
411 : PseudoQuietFLT_S_INX,
412 : PseudoRET,
413 : PseudoRV32ZdinxLD,
414 : PseudoRV32ZdinxSD,
415 : PseudoRVVInitUndefM1,
416 : PseudoRVVInitUndefM2,
417 : PseudoRVVInitUndefM4,
418 : PseudoRVVInitUndefM8,
419 : PseudoReadVL,
420 : PseudoReadVLENB,
421 : PseudoSB,
422 : PseudoSD,
423 : PseudoSEXT_B,
424 : PseudoSEXT_H,
425 : PseudoSH,
426 : PseudoSW,
427 : PseudoTAIL,
428 : PseudoTAILIndirect,
429 : PseudoTAILIndirectNonX7,
430 : PseudoTHVdotVMAQASU_VV_M1,
431 : PseudoTHVdotVMAQASU_VV_M1_MASK,
432 : PseudoTHVdotVMAQASU_VV_M2,
433 : PseudoTHVdotVMAQASU_VV_M2_MASK,
434 : PseudoTHVdotVMAQASU_VV_M4,
435 : PseudoTHVdotVMAQASU_VV_M4_MASK,
436 : PseudoTHVdotVMAQASU_VV_M8,
437 : PseudoTHVdotVMAQASU_VV_M8_MASK,
438 : PseudoTHVdotVMAQASU_VV_MF2,
439 : PseudoTHVdotVMAQASU_VV_MF2_MASK,
440 : PseudoTHVdotVMAQASU_VX_M1,
441 : PseudoTHVdotVMAQASU_VX_M1_MASK,
442 : PseudoTHVdotVMAQASU_VX_M2,
443 : PseudoTHVdotVMAQASU_VX_M2_MASK,
444 : PseudoTHVdotVMAQASU_VX_M4,
445 : PseudoTHVdotVMAQASU_VX_M4_MASK,
446 : PseudoTHVdotVMAQASU_VX_M8,
447 : PseudoTHVdotVMAQASU_VX_M8_MASK,
448 : PseudoTHVdotVMAQASU_VX_MF2,
449 : PseudoTHVdotVMAQASU_VX_MF2_MASK,
450 : PseudoTHVdotVMAQAUS_VX_M1,
451 : PseudoTHVdotVMAQAUS_VX_M1_MASK,
452 : PseudoTHVdotVMAQAUS_VX_M2,
453 : PseudoTHVdotVMAQAUS_VX_M2_MASK,
454 : PseudoTHVdotVMAQAUS_VX_M4,
455 : PseudoTHVdotVMAQAUS_VX_M4_MASK,
456 : PseudoTHVdotVMAQAUS_VX_M8,
457 : PseudoTHVdotVMAQAUS_VX_M8_MASK,
458 : PseudoTHVdotVMAQAUS_VX_MF2,
459 : PseudoTHVdotVMAQAUS_VX_MF2_MASK,
460 : PseudoTHVdotVMAQAU_VV_M1,
461 : PseudoTHVdotVMAQAU_VV_M1_MASK,
462 : PseudoTHVdotVMAQAU_VV_M2,
463 : PseudoTHVdotVMAQAU_VV_M2_MASK,
464 : PseudoTHVdotVMAQAU_VV_M4,
465 : PseudoTHVdotVMAQAU_VV_M4_MASK,
466 : PseudoTHVdotVMAQAU_VV_M8,
467 : PseudoTHVdotVMAQAU_VV_M8_MASK,
468 : PseudoTHVdotVMAQAU_VV_MF2,
469 : PseudoTHVdotVMAQAU_VV_MF2_MASK,
470 : PseudoTHVdotVMAQAU_VX_M1,
471 : PseudoTHVdotVMAQAU_VX_M1_MASK,
472 : PseudoTHVdotVMAQAU_VX_M2,
473 : PseudoTHVdotVMAQAU_VX_M2_MASK,
474 : PseudoTHVdotVMAQAU_VX_M4,
475 : PseudoTHVdotVMAQAU_VX_M4_MASK,
476 : PseudoTHVdotVMAQAU_VX_M8,
477 : PseudoTHVdotVMAQAU_VX_M8_MASK,
478 : PseudoTHVdotVMAQAU_VX_MF2,
479 : PseudoTHVdotVMAQAU_VX_MF2_MASK,
480 : PseudoTHVdotVMAQA_VV_M1,
481 : PseudoTHVdotVMAQA_VV_M1_MASK,
482 : PseudoTHVdotVMAQA_VV_M2,
483 : PseudoTHVdotVMAQA_VV_M2_MASK,
484 : PseudoTHVdotVMAQA_VV_M4,
485 : PseudoTHVdotVMAQA_VV_M4_MASK,
486 : PseudoTHVdotVMAQA_VV_M8,
487 : PseudoTHVdotVMAQA_VV_M8_MASK,
488 : PseudoTHVdotVMAQA_VV_MF2,
489 : PseudoTHVdotVMAQA_VV_MF2_MASK,
490 : PseudoTHVdotVMAQA_VX_M1,
491 : PseudoTHVdotVMAQA_VX_M1_MASK,
492 : PseudoTHVdotVMAQA_VX_M2,
493 : PseudoTHVdotVMAQA_VX_M2_MASK,
494 : PseudoTHVdotVMAQA_VX_M4,
495 : PseudoTHVdotVMAQA_VX_M4_MASK,
496 : PseudoTHVdotVMAQA_VX_M8,
497 : PseudoTHVdotVMAQA_VX_M8_MASK,
498 : PseudoTHVdotVMAQA_VX_MF2,
499 : PseudoTHVdotVMAQA_VX_MF2_MASK,
500 : PseudoTLSDESCCall,
501 : PseudoVAADDU_VV_M1,
502 : PseudoVAADDU_VV_M1_MASK,
503 : PseudoVAADDU_VV_M2,
504 : PseudoVAADDU_VV_M2_MASK,
505 : PseudoVAADDU_VV_M4,
506 : PseudoVAADDU_VV_M4_MASK,
507 : PseudoVAADDU_VV_M8,
508 : PseudoVAADDU_VV_M8_MASK,
509 : PseudoVAADDU_VV_MF2,
510 : PseudoVAADDU_VV_MF2_MASK,
511 : PseudoVAADDU_VV_MF4,
512 : PseudoVAADDU_VV_MF4_MASK,
513 : PseudoVAADDU_VV_MF8,
514 : PseudoVAADDU_VV_MF8_MASK,
515 : PseudoVAADDU_VX_M1,
516 : PseudoVAADDU_VX_M1_MASK,
517 : PseudoVAADDU_VX_M2,
518 : PseudoVAADDU_VX_M2_MASK,
519 : PseudoVAADDU_VX_M4,
520 : PseudoVAADDU_VX_M4_MASK,
521 : PseudoVAADDU_VX_M8,
522 : PseudoVAADDU_VX_M8_MASK,
523 : PseudoVAADDU_VX_MF2,
524 : PseudoVAADDU_VX_MF2_MASK,
525 : PseudoVAADDU_VX_MF4,
526 : PseudoVAADDU_VX_MF4_MASK,
527 : PseudoVAADDU_VX_MF8,
528 : PseudoVAADDU_VX_MF8_MASK,
529 : PseudoVAADD_VV_M1,
530 : PseudoVAADD_VV_M1_MASK,
531 : PseudoVAADD_VV_M2,
532 : PseudoVAADD_VV_M2_MASK,
533 : PseudoVAADD_VV_M4,
534 : PseudoVAADD_VV_M4_MASK,
535 : PseudoVAADD_VV_M8,
536 : PseudoVAADD_VV_M8_MASK,
537 : PseudoVAADD_VV_MF2,
538 : PseudoVAADD_VV_MF2_MASK,
539 : PseudoVAADD_VV_MF4,
540 : PseudoVAADD_VV_MF4_MASK,
541 : PseudoVAADD_VV_MF8,
542 : PseudoVAADD_VV_MF8_MASK,
543 : PseudoVAADD_VX_M1,
544 : PseudoVAADD_VX_M1_MASK,
545 : PseudoVAADD_VX_M2,
546 : PseudoVAADD_VX_M2_MASK,
547 : PseudoVAADD_VX_M4,
548 : PseudoVAADD_VX_M4_MASK,
549 : PseudoVAADD_VX_M8,
550 : PseudoVAADD_VX_M8_MASK,
551 : PseudoVAADD_VX_MF2,
552 : PseudoVAADD_VX_MF2_MASK,
553 : PseudoVAADD_VX_MF4,
554 : PseudoVAADD_VX_MF4_MASK,
555 : PseudoVAADD_VX_MF8,
556 : PseudoVAADD_VX_MF8_MASK,
557 : PseudoVADC_VIM_M1,
558 : PseudoVADC_VIM_M2,
559 : PseudoVADC_VIM_M4,
560 : PseudoVADC_VIM_M8,
561 : PseudoVADC_VIM_MF2,
562 : PseudoVADC_VIM_MF4,
563 : PseudoVADC_VIM_MF8,
564 : PseudoVADC_VVM_M1,
565 : PseudoVADC_VVM_M2,
566 : PseudoVADC_VVM_M4,
567 : PseudoVADC_VVM_M8,
568 : PseudoVADC_VVM_MF2,
569 : PseudoVADC_VVM_MF4,
570 : PseudoVADC_VVM_MF8,
571 : PseudoVADC_VXM_M1,
572 : PseudoVADC_VXM_M2,
573 : PseudoVADC_VXM_M4,
574 : PseudoVADC_VXM_M8,
575 : PseudoVADC_VXM_MF2,
576 : PseudoVADC_VXM_MF4,
577 : PseudoVADC_VXM_MF8,
578 : PseudoVADD_VI_M1,
579 : PseudoVADD_VI_M1_MASK,
580 : PseudoVADD_VI_M2,
581 : PseudoVADD_VI_M2_MASK,
582 : PseudoVADD_VI_M4,
583 : PseudoVADD_VI_M4_MASK,
584 : PseudoVADD_VI_M8,
585 : PseudoVADD_VI_M8_MASK,
586 : PseudoVADD_VI_MF2,
587 : PseudoVADD_VI_MF2_MASK,
588 : PseudoVADD_VI_MF4,
589 : PseudoVADD_VI_MF4_MASK,
590 : PseudoVADD_VI_MF8,
591 : PseudoVADD_VI_MF8_MASK,
592 : PseudoVADD_VV_M1,
593 : PseudoVADD_VV_M1_MASK,
594 : PseudoVADD_VV_M2,
595 : PseudoVADD_VV_M2_MASK,
596 : PseudoVADD_VV_M4,
597 : PseudoVADD_VV_M4_MASK,
598 : PseudoVADD_VV_M8,
599 : PseudoVADD_VV_M8_MASK,
600 : PseudoVADD_VV_MF2,
601 : PseudoVADD_VV_MF2_MASK,
602 : PseudoVADD_VV_MF4,
603 : PseudoVADD_VV_MF4_MASK,
604 : PseudoVADD_VV_MF8,
605 : PseudoVADD_VV_MF8_MASK,
606 : PseudoVADD_VX_M1,
607 : PseudoVADD_VX_M1_MASK,
608 : PseudoVADD_VX_M2,
609 : PseudoVADD_VX_M2_MASK,
610 : PseudoVADD_VX_M4,
611 : PseudoVADD_VX_M4_MASK,
612 : PseudoVADD_VX_M8,
613 : PseudoVADD_VX_M8_MASK,
614 : PseudoVADD_VX_MF2,
615 : PseudoVADD_VX_MF2_MASK,
616 : PseudoVADD_VX_MF4,
617 : PseudoVADD_VX_MF4_MASK,
618 : PseudoVADD_VX_MF8,
619 : PseudoVADD_VX_MF8_MASK,
620 : PseudoVAESDF_VS_M1_M1,
621 : PseudoVAESDF_VS_M1_MF2,
622 : PseudoVAESDF_VS_M1_MF4,
623 : PseudoVAESDF_VS_M1_MF8,
624 : PseudoVAESDF_VS_M2_M1,
625 : PseudoVAESDF_VS_M2_M2,
626 : PseudoVAESDF_VS_M2_MF2,
627 : PseudoVAESDF_VS_M2_MF4,
628 : PseudoVAESDF_VS_M2_MF8,
629 : PseudoVAESDF_VS_M4_M1,
630 : PseudoVAESDF_VS_M4_M2,
631 : PseudoVAESDF_VS_M4_M4,
632 : PseudoVAESDF_VS_M4_MF2,
633 : PseudoVAESDF_VS_M4_MF4,
634 : PseudoVAESDF_VS_M4_MF8,
635 : PseudoVAESDF_VS_M8_M1,
636 : PseudoVAESDF_VS_M8_M2,
637 : PseudoVAESDF_VS_M8_M4,
638 : PseudoVAESDF_VS_M8_MF2,
639 : PseudoVAESDF_VS_M8_MF4,
640 : PseudoVAESDF_VS_M8_MF8,
641 : PseudoVAESDF_VS_MF2_MF2,
642 : PseudoVAESDF_VS_MF2_MF4,
643 : PseudoVAESDF_VS_MF2_MF8,
644 : PseudoVAESDF_VV_M1,
645 : PseudoVAESDF_VV_M2,
646 : PseudoVAESDF_VV_M4,
647 : PseudoVAESDF_VV_M8,
648 : PseudoVAESDF_VV_MF2,
649 : PseudoVAESDM_VS_M1_M1,
650 : PseudoVAESDM_VS_M1_MF2,
651 : PseudoVAESDM_VS_M1_MF4,
652 : PseudoVAESDM_VS_M1_MF8,
653 : PseudoVAESDM_VS_M2_M1,
654 : PseudoVAESDM_VS_M2_M2,
655 : PseudoVAESDM_VS_M2_MF2,
656 : PseudoVAESDM_VS_M2_MF4,
657 : PseudoVAESDM_VS_M2_MF8,
658 : PseudoVAESDM_VS_M4_M1,
659 : PseudoVAESDM_VS_M4_M2,
660 : PseudoVAESDM_VS_M4_M4,
661 : PseudoVAESDM_VS_M4_MF2,
662 : PseudoVAESDM_VS_M4_MF4,
663 : PseudoVAESDM_VS_M4_MF8,
664 : PseudoVAESDM_VS_M8_M1,
665 : PseudoVAESDM_VS_M8_M2,
666 : PseudoVAESDM_VS_M8_M4,
667 : PseudoVAESDM_VS_M8_MF2,
668 : PseudoVAESDM_VS_M8_MF4,
669 : PseudoVAESDM_VS_M8_MF8,
670 : PseudoVAESDM_VS_MF2_MF2,
671 : PseudoVAESDM_VS_MF2_MF4,
672 : PseudoVAESDM_VS_MF2_MF8,
673 : PseudoVAESDM_VV_M1,
674 : PseudoVAESDM_VV_M2,
675 : PseudoVAESDM_VV_M4,
676 : PseudoVAESDM_VV_M8,
677 : PseudoVAESDM_VV_MF2,
678 : PseudoVAESEF_VS_M1_M1,
679 : PseudoVAESEF_VS_M1_MF2,
680 : PseudoVAESEF_VS_M1_MF4,
681 : PseudoVAESEF_VS_M1_MF8,
682 : PseudoVAESEF_VS_M2_M1,
683 : PseudoVAESEF_VS_M2_M2,
684 : PseudoVAESEF_VS_M2_MF2,
685 : PseudoVAESEF_VS_M2_MF4,
686 : PseudoVAESEF_VS_M2_MF8,
687 : PseudoVAESEF_VS_M4_M1,
688 : PseudoVAESEF_VS_M4_M2,
689 : PseudoVAESEF_VS_M4_M4,
690 : PseudoVAESEF_VS_M4_MF2,
691 : PseudoVAESEF_VS_M4_MF4,
692 : PseudoVAESEF_VS_M4_MF8,
693 : PseudoVAESEF_VS_M8_M1,
694 : PseudoVAESEF_VS_M8_M2,
695 : PseudoVAESEF_VS_M8_M4,
696 : PseudoVAESEF_VS_M8_MF2,
697 : PseudoVAESEF_VS_M8_MF4,
698 : PseudoVAESEF_VS_M8_MF8,
699 : PseudoVAESEF_VS_MF2_MF2,
700 : PseudoVAESEF_VS_MF2_MF4,
701 : PseudoVAESEF_VS_MF2_MF8,
702 : PseudoVAESEF_VV_M1,
703 : PseudoVAESEF_VV_M2,
704 : PseudoVAESEF_VV_M4,
705 : PseudoVAESEF_VV_M8,
706 : PseudoVAESEF_VV_MF2,
707 : PseudoVAESEM_VS_M1_M1,
708 : PseudoVAESEM_VS_M1_MF2,
709 : PseudoVAESEM_VS_M1_MF4,
710 : PseudoVAESEM_VS_M1_MF8,
711 : PseudoVAESEM_VS_M2_M1,
712 : PseudoVAESEM_VS_M2_M2,
713 : PseudoVAESEM_VS_M2_MF2,
714 : PseudoVAESEM_VS_M2_MF4,
715 : PseudoVAESEM_VS_M2_MF8,
716 : PseudoVAESEM_VS_M4_M1,
717 : PseudoVAESEM_VS_M4_M2,
718 : PseudoVAESEM_VS_M4_M4,
719 : PseudoVAESEM_VS_M4_MF2,
720 : PseudoVAESEM_VS_M4_MF4,
721 : PseudoVAESEM_VS_M4_MF8,
722 : PseudoVAESEM_VS_M8_M1,
723 : PseudoVAESEM_VS_M8_M2,
724 : PseudoVAESEM_VS_M8_M4,
725 : PseudoVAESEM_VS_M8_MF2,
726 : PseudoVAESEM_VS_M8_MF4,
727 : PseudoVAESEM_VS_M8_MF8,
728 : PseudoVAESEM_VS_MF2_MF2,
729 : PseudoVAESEM_VS_MF2_MF4,
730 : PseudoVAESEM_VS_MF2_MF8,
731 : PseudoVAESEM_VV_M1,
732 : PseudoVAESEM_VV_M2,
733 : PseudoVAESEM_VV_M4,
734 : PseudoVAESEM_VV_M8,
735 : PseudoVAESEM_VV_MF2,
736 : PseudoVAESKF1_VI_M1,
737 : PseudoVAESKF1_VI_M2,
738 : PseudoVAESKF1_VI_M4,
739 : PseudoVAESKF1_VI_M8,
740 : PseudoVAESKF1_VI_MF2,
741 : PseudoVAESKF2_VI_M1,
742 : PseudoVAESKF2_VI_M2,
743 : PseudoVAESKF2_VI_M4,
744 : PseudoVAESKF2_VI_M8,
745 : PseudoVAESKF2_VI_MF2,
746 : PseudoVAESZ_VS_M1_M1,
747 : PseudoVAESZ_VS_M1_MF2,
748 : PseudoVAESZ_VS_M1_MF4,
749 : PseudoVAESZ_VS_M1_MF8,
750 : PseudoVAESZ_VS_M2_M1,
751 : PseudoVAESZ_VS_M2_M2,
752 : PseudoVAESZ_VS_M2_MF2,
753 : PseudoVAESZ_VS_M2_MF4,
754 : PseudoVAESZ_VS_M2_MF8,
755 : PseudoVAESZ_VS_M4_M1,
756 : PseudoVAESZ_VS_M4_M2,
757 : PseudoVAESZ_VS_M4_M4,
758 : PseudoVAESZ_VS_M4_MF2,
759 : PseudoVAESZ_VS_M4_MF4,
760 : PseudoVAESZ_VS_M4_MF8,
761 : PseudoVAESZ_VS_M8_M1,
762 : PseudoVAESZ_VS_M8_M2,
763 : PseudoVAESZ_VS_M8_M4,
764 : PseudoVAESZ_VS_M8_MF2,
765 : PseudoVAESZ_VS_M8_MF4,
766 : PseudoVAESZ_VS_M8_MF8,
767 : PseudoVAESZ_VS_MF2_MF2,
768 : PseudoVAESZ_VS_MF2_MF4,
769 : PseudoVAESZ_VS_MF2_MF8,
770 : PseudoVANDN_VV_M1,
771 : PseudoVANDN_VV_M1_MASK,
772 : PseudoVANDN_VV_M2,
773 : PseudoVANDN_VV_M2_MASK,
774 : PseudoVANDN_VV_M4,
775 : PseudoVANDN_VV_M4_MASK,
776 : PseudoVANDN_VV_M8,
777 : PseudoVANDN_VV_M8_MASK,
778 : PseudoVANDN_VV_MF2,
779 : PseudoVANDN_VV_MF2_MASK,
780 : PseudoVANDN_VV_MF4,
781 : PseudoVANDN_VV_MF4_MASK,
782 : PseudoVANDN_VV_MF8,
783 : PseudoVANDN_VV_MF8_MASK,
784 : PseudoVANDN_VX_M1,
785 : PseudoVANDN_VX_M1_MASK,
786 : PseudoVANDN_VX_M2,
787 : PseudoVANDN_VX_M2_MASK,
788 : PseudoVANDN_VX_M4,
789 : PseudoVANDN_VX_M4_MASK,
790 : PseudoVANDN_VX_M8,
791 : PseudoVANDN_VX_M8_MASK,
792 : PseudoVANDN_VX_MF2,
793 : PseudoVANDN_VX_MF2_MASK,
794 : PseudoVANDN_VX_MF4,
795 : PseudoVANDN_VX_MF4_MASK,
796 : PseudoVANDN_VX_MF8,
797 : PseudoVANDN_VX_MF8_MASK,
798 : PseudoVAND_VI_M1,
799 : PseudoVAND_VI_M1_MASK,
800 : PseudoVAND_VI_M2,
801 : PseudoVAND_VI_M2_MASK,
802 : PseudoVAND_VI_M4,
803 : PseudoVAND_VI_M4_MASK,
804 : PseudoVAND_VI_M8,
805 : PseudoVAND_VI_M8_MASK,
806 : PseudoVAND_VI_MF2,
807 : PseudoVAND_VI_MF2_MASK,
808 : PseudoVAND_VI_MF4,
809 : PseudoVAND_VI_MF4_MASK,
810 : PseudoVAND_VI_MF8,
811 : PseudoVAND_VI_MF8_MASK,
812 : PseudoVAND_VV_M1,
813 : PseudoVAND_VV_M1_MASK,
814 : PseudoVAND_VV_M2,
815 : PseudoVAND_VV_M2_MASK,
816 : PseudoVAND_VV_M4,
817 : PseudoVAND_VV_M4_MASK,
818 : PseudoVAND_VV_M8,
819 : PseudoVAND_VV_M8_MASK,
820 : PseudoVAND_VV_MF2,
821 : PseudoVAND_VV_MF2_MASK,
822 : PseudoVAND_VV_MF4,
823 : PseudoVAND_VV_MF4_MASK,
824 : PseudoVAND_VV_MF8,
825 : PseudoVAND_VV_MF8_MASK,
826 : PseudoVAND_VX_M1,
827 : PseudoVAND_VX_M1_MASK,
828 : PseudoVAND_VX_M2,
829 : PseudoVAND_VX_M2_MASK,
830 : PseudoVAND_VX_M4,
831 : PseudoVAND_VX_M4_MASK,
832 : PseudoVAND_VX_M8,
833 : PseudoVAND_VX_M8_MASK,
834 : PseudoVAND_VX_MF2,
835 : PseudoVAND_VX_MF2_MASK,
836 : PseudoVAND_VX_MF4,
837 : PseudoVAND_VX_MF4_MASK,
838 : PseudoVAND_VX_MF8,
839 : PseudoVAND_VX_MF8_MASK,
840 : PseudoVASUBU_VV_M1,
841 : PseudoVASUBU_VV_M1_MASK,
842 : PseudoVASUBU_VV_M2,
843 : PseudoVASUBU_VV_M2_MASK,
844 : PseudoVASUBU_VV_M4,
845 : PseudoVASUBU_VV_M4_MASK,
846 : PseudoVASUBU_VV_M8,
847 : PseudoVASUBU_VV_M8_MASK,
848 : PseudoVASUBU_VV_MF2,
849 : PseudoVASUBU_VV_MF2_MASK,
850 : PseudoVASUBU_VV_MF4,
851 : PseudoVASUBU_VV_MF4_MASK,
852 : PseudoVASUBU_VV_MF8,
853 : PseudoVASUBU_VV_MF8_MASK,
854 : PseudoVASUBU_VX_M1,
855 : PseudoVASUBU_VX_M1_MASK,
856 : PseudoVASUBU_VX_M2,
857 : PseudoVASUBU_VX_M2_MASK,
858 : PseudoVASUBU_VX_M4,
859 : PseudoVASUBU_VX_M4_MASK,
860 : PseudoVASUBU_VX_M8,
861 : PseudoVASUBU_VX_M8_MASK,
862 : PseudoVASUBU_VX_MF2,
863 : PseudoVASUBU_VX_MF2_MASK,
864 : PseudoVASUBU_VX_MF4,
865 : PseudoVASUBU_VX_MF4_MASK,
866 : PseudoVASUBU_VX_MF8,
867 : PseudoVASUBU_VX_MF8_MASK,
868 : PseudoVASUB_VV_M1,
869 : PseudoVASUB_VV_M1_MASK,
870 : PseudoVASUB_VV_M2,
871 : PseudoVASUB_VV_M2_MASK,
872 : PseudoVASUB_VV_M4,
873 : PseudoVASUB_VV_M4_MASK,
874 : PseudoVASUB_VV_M8,
875 : PseudoVASUB_VV_M8_MASK,
876 : PseudoVASUB_VV_MF2,
877 : PseudoVASUB_VV_MF2_MASK,
878 : PseudoVASUB_VV_MF4,
879 : PseudoVASUB_VV_MF4_MASK,
880 : PseudoVASUB_VV_MF8,
881 : PseudoVASUB_VV_MF8_MASK,
882 : PseudoVASUB_VX_M1,
883 : PseudoVASUB_VX_M1_MASK,
884 : PseudoVASUB_VX_M2,
885 : PseudoVASUB_VX_M2_MASK,
886 : PseudoVASUB_VX_M4,
887 : PseudoVASUB_VX_M4_MASK,
888 : PseudoVASUB_VX_M8,
889 : PseudoVASUB_VX_M8_MASK,
890 : PseudoVASUB_VX_MF2,
891 : PseudoVASUB_VX_MF2_MASK,
892 : PseudoVASUB_VX_MF4,
893 : PseudoVASUB_VX_MF4_MASK,
894 : PseudoVASUB_VX_MF8,
895 : PseudoVASUB_VX_MF8_MASK,
896 : PseudoVBREV8_V_M1,
897 : PseudoVBREV8_V_M1_MASK,
898 : PseudoVBREV8_V_M2,
899 : PseudoVBREV8_V_M2_MASK,
900 : PseudoVBREV8_V_M4,
901 : PseudoVBREV8_V_M4_MASK,
902 : PseudoVBREV8_V_M8,
903 : PseudoVBREV8_V_M8_MASK,
904 : PseudoVBREV8_V_MF2,
905 : PseudoVBREV8_V_MF2_MASK,
906 : PseudoVBREV8_V_MF4,
907 : PseudoVBREV8_V_MF4_MASK,
908 : PseudoVBREV8_V_MF8,
909 : PseudoVBREV8_V_MF8_MASK,
910 : PseudoVBREV_V_M1,
911 : PseudoVBREV_V_M1_MASK,
912 : PseudoVBREV_V_M2,
913 : PseudoVBREV_V_M2_MASK,
914 : PseudoVBREV_V_M4,
915 : PseudoVBREV_V_M4_MASK,
916 : PseudoVBREV_V_M8,
917 : PseudoVBREV_V_M8_MASK,
918 : PseudoVBREV_V_MF2,
919 : PseudoVBREV_V_MF2_MASK,
920 : PseudoVBREV_V_MF4,
921 : PseudoVBREV_V_MF4_MASK,
922 : PseudoVBREV_V_MF8,
923 : PseudoVBREV_V_MF8_MASK,
924 : PseudoVCLMULH_VV_M1,
925 : PseudoVCLMULH_VV_M1_MASK,
926 : PseudoVCLMULH_VV_M2,
927 : PseudoVCLMULH_VV_M2_MASK,
928 : PseudoVCLMULH_VV_M4,
929 : PseudoVCLMULH_VV_M4_MASK,
930 : PseudoVCLMULH_VV_M8,
931 : PseudoVCLMULH_VV_M8_MASK,
932 : PseudoVCLMULH_VV_MF2,
933 : PseudoVCLMULH_VV_MF2_MASK,
934 : PseudoVCLMULH_VV_MF4,
935 : PseudoVCLMULH_VV_MF4_MASK,
936 : PseudoVCLMULH_VV_MF8,
937 : PseudoVCLMULH_VV_MF8_MASK,
938 : PseudoVCLMULH_VX_M1,
939 : PseudoVCLMULH_VX_M1_MASK,
940 : PseudoVCLMULH_VX_M2,
941 : PseudoVCLMULH_VX_M2_MASK,
942 : PseudoVCLMULH_VX_M4,
943 : PseudoVCLMULH_VX_M4_MASK,
944 : PseudoVCLMULH_VX_M8,
945 : PseudoVCLMULH_VX_M8_MASK,
946 : PseudoVCLMULH_VX_MF2,
947 : PseudoVCLMULH_VX_MF2_MASK,
948 : PseudoVCLMULH_VX_MF4,
949 : PseudoVCLMULH_VX_MF4_MASK,
950 : PseudoVCLMULH_VX_MF8,
951 : PseudoVCLMULH_VX_MF8_MASK,
952 : PseudoVCLMUL_VV_M1,
953 : PseudoVCLMUL_VV_M1_MASK,
954 : PseudoVCLMUL_VV_M2,
955 : PseudoVCLMUL_VV_M2_MASK,
956 : PseudoVCLMUL_VV_M4,
957 : PseudoVCLMUL_VV_M4_MASK,
958 : PseudoVCLMUL_VV_M8,
959 : PseudoVCLMUL_VV_M8_MASK,
960 : PseudoVCLMUL_VV_MF2,
961 : PseudoVCLMUL_VV_MF2_MASK,
962 : PseudoVCLMUL_VV_MF4,
963 : PseudoVCLMUL_VV_MF4_MASK,
964 : PseudoVCLMUL_VV_MF8,
965 : PseudoVCLMUL_VV_MF8_MASK,
966 : PseudoVCLMUL_VX_M1,
967 : PseudoVCLMUL_VX_M1_MASK,
968 : PseudoVCLMUL_VX_M2,
969 : PseudoVCLMUL_VX_M2_MASK,
970 : PseudoVCLMUL_VX_M4,
971 : PseudoVCLMUL_VX_M4_MASK,
972 : PseudoVCLMUL_VX_M8,
973 : PseudoVCLMUL_VX_M8_MASK,
974 : PseudoVCLMUL_VX_MF2,
975 : PseudoVCLMUL_VX_MF2_MASK,
976 : PseudoVCLMUL_VX_MF4,
977 : PseudoVCLMUL_VX_MF4_MASK,
978 : PseudoVCLMUL_VX_MF8,
979 : PseudoVCLMUL_VX_MF8_MASK,
980 : PseudoVCLZ_V_M1,
981 : PseudoVCLZ_V_M1_MASK,
982 : PseudoVCLZ_V_M2,
983 : PseudoVCLZ_V_M2_MASK,
984 : PseudoVCLZ_V_M4,
985 : PseudoVCLZ_V_M4_MASK,
986 : PseudoVCLZ_V_M8,
987 : PseudoVCLZ_V_M8_MASK,
988 : PseudoVCLZ_V_MF2,
989 : PseudoVCLZ_V_MF2_MASK,
990 : PseudoVCLZ_V_MF4,
991 : PseudoVCLZ_V_MF4_MASK,
992 : PseudoVCLZ_V_MF8,
993 : PseudoVCLZ_V_MF8_MASK,
994 : PseudoVCOMPRESS_VM_M1_E16,
995 : PseudoVCOMPRESS_VM_M1_E32,
996 : PseudoVCOMPRESS_VM_M1_E64,
997 : PseudoVCOMPRESS_VM_M1_E8,
998 : PseudoVCOMPRESS_VM_M2_E16,
999 : PseudoVCOMPRESS_VM_M2_E32,
1000 : PseudoVCOMPRESS_VM_M2_E64,
1001 : PseudoVCOMPRESS_VM_M2_E8,
1002 : PseudoVCOMPRESS_VM_M4_E16,
1003 : PseudoVCOMPRESS_VM_M4_E32,
1004 : PseudoVCOMPRESS_VM_M4_E64,
1005 : PseudoVCOMPRESS_VM_M4_E8,
1006 : PseudoVCOMPRESS_VM_M8_E16,
1007 : PseudoVCOMPRESS_VM_M8_E32,
1008 : PseudoVCOMPRESS_VM_M8_E64,
1009 : PseudoVCOMPRESS_VM_M8_E8,
1010 : PseudoVCOMPRESS_VM_MF2_E16,
1011 : PseudoVCOMPRESS_VM_MF2_E32,
1012 : PseudoVCOMPRESS_VM_MF2_E8,
1013 : PseudoVCOMPRESS_VM_MF4_E16,
1014 : PseudoVCOMPRESS_VM_MF4_E8,
1015 : PseudoVCOMPRESS_VM_MF8_E8,
1016 : PseudoVCPOP_M_B1,
1017 : PseudoVCPOP_M_B16,
1018 : PseudoVCPOP_M_B16_MASK,
1019 : PseudoVCPOP_M_B1_MASK,
1020 : PseudoVCPOP_M_B2,
1021 : PseudoVCPOP_M_B2_MASK,
1022 : PseudoVCPOP_M_B32,
1023 : PseudoVCPOP_M_B32_MASK,
1024 : PseudoVCPOP_M_B4,
1025 : PseudoVCPOP_M_B4_MASK,
1026 : PseudoVCPOP_M_B64,
1027 : PseudoVCPOP_M_B64_MASK,
1028 : PseudoVCPOP_M_B8,
1029 : PseudoVCPOP_M_B8_MASK,
1030 : PseudoVCPOP_V_M1,
1031 : PseudoVCPOP_V_M1_MASK,
1032 : PseudoVCPOP_V_M2,
1033 : PseudoVCPOP_V_M2_MASK,
1034 : PseudoVCPOP_V_M4,
1035 : PseudoVCPOP_V_M4_MASK,
1036 : PseudoVCPOP_V_M8,
1037 : PseudoVCPOP_V_M8_MASK,
1038 : PseudoVCPOP_V_MF2,
1039 : PseudoVCPOP_V_MF2_MASK,
1040 : PseudoVCPOP_V_MF4,
1041 : PseudoVCPOP_V_MF4_MASK,
1042 : PseudoVCPOP_V_MF8,
1043 : PseudoVCPOP_V_MF8_MASK,
1044 : PseudoVCTZ_V_M1,
1045 : PseudoVCTZ_V_M1_MASK,
1046 : PseudoVCTZ_V_M2,
1047 : PseudoVCTZ_V_M2_MASK,
1048 : PseudoVCTZ_V_M4,
1049 : PseudoVCTZ_V_M4_MASK,
1050 : PseudoVCTZ_V_M8,
1051 : PseudoVCTZ_V_M8_MASK,
1052 : PseudoVCTZ_V_MF2,
1053 : PseudoVCTZ_V_MF2_MASK,
1054 : PseudoVCTZ_V_MF4,
1055 : PseudoVCTZ_V_MF4_MASK,
1056 : PseudoVCTZ_V_MF8,
1057 : PseudoVCTZ_V_MF8_MASK,
1058 : PseudoVC_FPR16VV_SE_M1,
1059 : PseudoVC_FPR16VV_SE_M2,
1060 : PseudoVC_FPR16VV_SE_M4,
1061 : PseudoVC_FPR16VV_SE_M8,
1062 : PseudoVC_FPR16VV_SE_MF2,
1063 : PseudoVC_FPR16VV_SE_MF4,
1064 : PseudoVC_FPR16VW_SE_M1,
1065 : PseudoVC_FPR16VW_SE_M2,
1066 : PseudoVC_FPR16VW_SE_M4,
1067 : PseudoVC_FPR16VW_SE_M8,
1068 : PseudoVC_FPR16VW_SE_MF2,
1069 : PseudoVC_FPR16VW_SE_MF4,
1070 : PseudoVC_FPR16V_SE_M1,
1071 : PseudoVC_FPR16V_SE_M2,
1072 : PseudoVC_FPR16V_SE_M4,
1073 : PseudoVC_FPR16V_SE_M8,
1074 : PseudoVC_FPR16V_SE_MF2,
1075 : PseudoVC_FPR16V_SE_MF4,
1076 : PseudoVC_FPR32VV_SE_M1,
1077 : PseudoVC_FPR32VV_SE_M2,
1078 : PseudoVC_FPR32VV_SE_M4,
1079 : PseudoVC_FPR32VV_SE_M8,
1080 : PseudoVC_FPR32VV_SE_MF2,
1081 : PseudoVC_FPR32VW_SE_M1,
1082 : PseudoVC_FPR32VW_SE_M2,
1083 : PseudoVC_FPR32VW_SE_M4,
1084 : PseudoVC_FPR32VW_SE_M8,
1085 : PseudoVC_FPR32VW_SE_MF2,
1086 : PseudoVC_FPR32V_SE_M1,
1087 : PseudoVC_FPR32V_SE_M2,
1088 : PseudoVC_FPR32V_SE_M4,
1089 : PseudoVC_FPR32V_SE_M8,
1090 : PseudoVC_FPR32V_SE_MF2,
1091 : PseudoVC_FPR64VV_SE_M1,
1092 : PseudoVC_FPR64VV_SE_M2,
1093 : PseudoVC_FPR64VV_SE_M4,
1094 : PseudoVC_FPR64VV_SE_M8,
1095 : PseudoVC_FPR64V_SE_M1,
1096 : PseudoVC_FPR64V_SE_M2,
1097 : PseudoVC_FPR64V_SE_M4,
1098 : PseudoVC_FPR64V_SE_M8,
1099 : PseudoVC_IVV_SE_M1,
1100 : PseudoVC_IVV_SE_M2,
1101 : PseudoVC_IVV_SE_M4,
1102 : PseudoVC_IVV_SE_M8,
1103 : PseudoVC_IVV_SE_MF2,
1104 : PseudoVC_IVV_SE_MF4,
1105 : PseudoVC_IVV_SE_MF8,
1106 : PseudoVC_IVW_SE_M1,
1107 : PseudoVC_IVW_SE_M2,
1108 : PseudoVC_IVW_SE_M4,
1109 : PseudoVC_IVW_SE_MF2,
1110 : PseudoVC_IVW_SE_MF4,
1111 : PseudoVC_IVW_SE_MF8,
1112 : PseudoVC_IV_SE_M1,
1113 : PseudoVC_IV_SE_M2,
1114 : PseudoVC_IV_SE_M4,
1115 : PseudoVC_IV_SE_M8,
1116 : PseudoVC_IV_SE_MF2,
1117 : PseudoVC_IV_SE_MF4,
1118 : PseudoVC_IV_SE_MF8,
1119 : PseudoVC_I_SE_M1,
1120 : PseudoVC_I_SE_M2,
1121 : PseudoVC_I_SE_M4,
1122 : PseudoVC_I_SE_M8,
1123 : PseudoVC_I_SE_MF2,
1124 : PseudoVC_I_SE_MF4,
1125 : PseudoVC_I_SE_MF8,
1126 : PseudoVC_VVV_SE_M1,
1127 : PseudoVC_VVV_SE_M2,
1128 : PseudoVC_VVV_SE_M4,
1129 : PseudoVC_VVV_SE_M8,
1130 : PseudoVC_VVV_SE_MF2,
1131 : PseudoVC_VVV_SE_MF4,
1132 : PseudoVC_VVV_SE_MF8,
1133 : PseudoVC_VVW_SE_M1,
1134 : PseudoVC_VVW_SE_M2,
1135 : PseudoVC_VVW_SE_M4,
1136 : PseudoVC_VVW_SE_MF2,
1137 : PseudoVC_VVW_SE_MF4,
1138 : PseudoVC_VVW_SE_MF8,
1139 : PseudoVC_VV_SE_M1,
1140 : PseudoVC_VV_SE_M2,
1141 : PseudoVC_VV_SE_M4,
1142 : PseudoVC_VV_SE_M8,
1143 : PseudoVC_VV_SE_MF2,
1144 : PseudoVC_VV_SE_MF4,
1145 : PseudoVC_VV_SE_MF8,
1146 : PseudoVC_V_FPR16VV_M1,
1147 : PseudoVC_V_FPR16VV_M2,
1148 : PseudoVC_V_FPR16VV_M4,
1149 : PseudoVC_V_FPR16VV_M8,
1150 : PseudoVC_V_FPR16VV_MF2,
1151 : PseudoVC_V_FPR16VV_MF4,
1152 : PseudoVC_V_FPR16VV_SE_M1,
1153 : PseudoVC_V_FPR16VV_SE_M2,
1154 : PseudoVC_V_FPR16VV_SE_M4,
1155 : PseudoVC_V_FPR16VV_SE_M8,
1156 : PseudoVC_V_FPR16VV_SE_MF2,
1157 : PseudoVC_V_FPR16VV_SE_MF4,
1158 : PseudoVC_V_FPR16VW_M1,
1159 : PseudoVC_V_FPR16VW_M2,
1160 : PseudoVC_V_FPR16VW_M4,
1161 : PseudoVC_V_FPR16VW_M8,
1162 : PseudoVC_V_FPR16VW_MF2,
1163 : PseudoVC_V_FPR16VW_MF4,
1164 : PseudoVC_V_FPR16VW_SE_M1,
1165 : PseudoVC_V_FPR16VW_SE_M2,
1166 : PseudoVC_V_FPR16VW_SE_M4,
1167 : PseudoVC_V_FPR16VW_SE_M8,
1168 : PseudoVC_V_FPR16VW_SE_MF2,
1169 : PseudoVC_V_FPR16VW_SE_MF4,
1170 : PseudoVC_V_FPR16V_M1,
1171 : PseudoVC_V_FPR16V_M2,
1172 : PseudoVC_V_FPR16V_M4,
1173 : PseudoVC_V_FPR16V_M8,
1174 : PseudoVC_V_FPR16V_MF2,
1175 : PseudoVC_V_FPR16V_MF4,
1176 : PseudoVC_V_FPR16V_SE_M1,
1177 : PseudoVC_V_FPR16V_SE_M2,
1178 : PseudoVC_V_FPR16V_SE_M4,
1179 : PseudoVC_V_FPR16V_SE_M8,
1180 : PseudoVC_V_FPR16V_SE_MF2,
1181 : PseudoVC_V_FPR16V_SE_MF4,
1182 : PseudoVC_V_FPR32VV_M1,
1183 : PseudoVC_V_FPR32VV_M2,
1184 : PseudoVC_V_FPR32VV_M4,
1185 : PseudoVC_V_FPR32VV_M8,
1186 : PseudoVC_V_FPR32VV_MF2,
1187 : PseudoVC_V_FPR32VV_SE_M1,
1188 : PseudoVC_V_FPR32VV_SE_M2,
1189 : PseudoVC_V_FPR32VV_SE_M4,
1190 : PseudoVC_V_FPR32VV_SE_M8,
1191 : PseudoVC_V_FPR32VV_SE_MF2,
1192 : PseudoVC_V_FPR32VW_M1,
1193 : PseudoVC_V_FPR32VW_M2,
1194 : PseudoVC_V_FPR32VW_M4,
1195 : PseudoVC_V_FPR32VW_M8,
1196 : PseudoVC_V_FPR32VW_MF2,
1197 : PseudoVC_V_FPR32VW_SE_M1,
1198 : PseudoVC_V_FPR32VW_SE_M2,
1199 : PseudoVC_V_FPR32VW_SE_M4,
1200 : PseudoVC_V_FPR32VW_SE_M8,
1201 : PseudoVC_V_FPR32VW_SE_MF2,
1202 : PseudoVC_V_FPR32V_M1,
1203 : PseudoVC_V_FPR32V_M2,
1204 : PseudoVC_V_FPR32V_M4,
1205 : PseudoVC_V_FPR32V_M8,
1206 : PseudoVC_V_FPR32V_MF2,
1207 : PseudoVC_V_FPR32V_SE_M1,
1208 : PseudoVC_V_FPR32V_SE_M2,
1209 : PseudoVC_V_FPR32V_SE_M4,
1210 : PseudoVC_V_FPR32V_SE_M8,
1211 : PseudoVC_V_FPR32V_SE_MF2,
1212 : PseudoVC_V_FPR64VV_M1,
1213 : PseudoVC_V_FPR64VV_M2,
1214 : PseudoVC_V_FPR64VV_M4,
1215 : PseudoVC_V_FPR64VV_M8,
1216 : PseudoVC_V_FPR64VV_SE_M1,
1217 : PseudoVC_V_FPR64VV_SE_M2,
1218 : PseudoVC_V_FPR64VV_SE_M4,
1219 : PseudoVC_V_FPR64VV_SE_M8,
1220 : PseudoVC_V_FPR64V_M1,
1221 : PseudoVC_V_FPR64V_M2,
1222 : PseudoVC_V_FPR64V_M4,
1223 : PseudoVC_V_FPR64V_M8,
1224 : PseudoVC_V_FPR64V_SE_M1,
1225 : PseudoVC_V_FPR64V_SE_M2,
1226 : PseudoVC_V_FPR64V_SE_M4,
1227 : PseudoVC_V_FPR64V_SE_M8,
1228 : PseudoVC_V_IVV_M1,
1229 : PseudoVC_V_IVV_M2,
1230 : PseudoVC_V_IVV_M4,
1231 : PseudoVC_V_IVV_M8,
1232 : PseudoVC_V_IVV_MF2,
1233 : PseudoVC_V_IVV_MF4,
1234 : PseudoVC_V_IVV_MF8,
1235 : PseudoVC_V_IVV_SE_M1,
1236 : PseudoVC_V_IVV_SE_M2,
1237 : PseudoVC_V_IVV_SE_M4,
1238 : PseudoVC_V_IVV_SE_M8,
1239 : PseudoVC_V_IVV_SE_MF2,
1240 : PseudoVC_V_IVV_SE_MF4,
1241 : PseudoVC_V_IVV_SE_MF8,
1242 : PseudoVC_V_IVW_M1,
1243 : PseudoVC_V_IVW_M2,
1244 : PseudoVC_V_IVW_M4,
1245 : PseudoVC_V_IVW_MF2,
1246 : PseudoVC_V_IVW_MF4,
1247 : PseudoVC_V_IVW_MF8,
1248 : PseudoVC_V_IVW_SE_M1,
1249 : PseudoVC_V_IVW_SE_M2,
1250 : PseudoVC_V_IVW_SE_M4,
1251 : PseudoVC_V_IVW_SE_MF2,
1252 : PseudoVC_V_IVW_SE_MF4,
1253 : PseudoVC_V_IVW_SE_MF8,
1254 : PseudoVC_V_IV_M1,
1255 : PseudoVC_V_IV_M2,
1256 : PseudoVC_V_IV_M4,
1257 : PseudoVC_V_IV_M8,
1258 : PseudoVC_V_IV_MF2,
1259 : PseudoVC_V_IV_MF4,
1260 : PseudoVC_V_IV_MF8,
1261 : PseudoVC_V_IV_SE_M1,
1262 : PseudoVC_V_IV_SE_M2,
1263 : PseudoVC_V_IV_SE_M4,
1264 : PseudoVC_V_IV_SE_M8,
1265 : PseudoVC_V_IV_SE_MF2,
1266 : PseudoVC_V_IV_SE_MF4,
1267 : PseudoVC_V_IV_SE_MF8,
1268 : PseudoVC_V_I_M1,
1269 : PseudoVC_V_I_M2,
1270 : PseudoVC_V_I_M4,
1271 : PseudoVC_V_I_M8,
1272 : PseudoVC_V_I_MF2,
1273 : PseudoVC_V_I_MF4,
1274 : PseudoVC_V_I_MF8,
1275 : PseudoVC_V_I_SE_M1,
1276 : PseudoVC_V_I_SE_M2,
1277 : PseudoVC_V_I_SE_M4,
1278 : PseudoVC_V_I_SE_M8,
1279 : PseudoVC_V_I_SE_MF2,
1280 : PseudoVC_V_I_SE_MF4,
1281 : PseudoVC_V_I_SE_MF8,
1282 : PseudoVC_V_VVV_M1,
1283 : PseudoVC_V_VVV_M2,
1284 : PseudoVC_V_VVV_M4,
1285 : PseudoVC_V_VVV_M8,
1286 : PseudoVC_V_VVV_MF2,
1287 : PseudoVC_V_VVV_MF4,
1288 : PseudoVC_V_VVV_MF8,
1289 : PseudoVC_V_VVV_SE_M1,
1290 : PseudoVC_V_VVV_SE_M2,
1291 : PseudoVC_V_VVV_SE_M4,
1292 : PseudoVC_V_VVV_SE_M8,
1293 : PseudoVC_V_VVV_SE_MF2,
1294 : PseudoVC_V_VVV_SE_MF4,
1295 : PseudoVC_V_VVV_SE_MF8,
1296 : PseudoVC_V_VVW_M1,
1297 : PseudoVC_V_VVW_M2,
1298 : PseudoVC_V_VVW_M4,
1299 : PseudoVC_V_VVW_MF2,
1300 : PseudoVC_V_VVW_MF4,
1301 : PseudoVC_V_VVW_MF8,
1302 : PseudoVC_V_VVW_SE_M1,
1303 : PseudoVC_V_VVW_SE_M2,
1304 : PseudoVC_V_VVW_SE_M4,
1305 : PseudoVC_V_VVW_SE_MF2,
1306 : PseudoVC_V_VVW_SE_MF4,
1307 : PseudoVC_V_VVW_SE_MF8,
1308 : PseudoVC_V_VV_M1,
1309 : PseudoVC_V_VV_M2,
1310 : PseudoVC_V_VV_M4,
1311 : PseudoVC_V_VV_M8,
1312 : PseudoVC_V_VV_MF2,
1313 : PseudoVC_V_VV_MF4,
1314 : PseudoVC_V_VV_MF8,
1315 : PseudoVC_V_VV_SE_M1,
1316 : PseudoVC_V_VV_SE_M2,
1317 : PseudoVC_V_VV_SE_M4,
1318 : PseudoVC_V_VV_SE_M8,
1319 : PseudoVC_V_VV_SE_MF2,
1320 : PseudoVC_V_VV_SE_MF4,
1321 : PseudoVC_V_VV_SE_MF8,
1322 : PseudoVC_V_XVV_M1,
1323 : PseudoVC_V_XVV_M2,
1324 : PseudoVC_V_XVV_M4,
1325 : PseudoVC_V_XVV_M8,
1326 : PseudoVC_V_XVV_MF2,
1327 : PseudoVC_V_XVV_MF4,
1328 : PseudoVC_V_XVV_MF8,
1329 : PseudoVC_V_XVV_SE_M1,
1330 : PseudoVC_V_XVV_SE_M2,
1331 : PseudoVC_V_XVV_SE_M4,
1332 : PseudoVC_V_XVV_SE_M8,
1333 : PseudoVC_V_XVV_SE_MF2,
1334 : PseudoVC_V_XVV_SE_MF4,
1335 : PseudoVC_V_XVV_SE_MF8,
1336 : PseudoVC_V_XVW_M1,
1337 : PseudoVC_V_XVW_M2,
1338 : PseudoVC_V_XVW_M4,
1339 : PseudoVC_V_XVW_MF2,
1340 : PseudoVC_V_XVW_MF4,
1341 : PseudoVC_V_XVW_MF8,
1342 : PseudoVC_V_XVW_SE_M1,
1343 : PseudoVC_V_XVW_SE_M2,
1344 : PseudoVC_V_XVW_SE_M4,
1345 : PseudoVC_V_XVW_SE_MF2,
1346 : PseudoVC_V_XVW_SE_MF4,
1347 : PseudoVC_V_XVW_SE_MF8,
1348 : PseudoVC_V_XV_M1,
1349 : PseudoVC_V_XV_M2,
1350 : PseudoVC_V_XV_M4,
1351 : PseudoVC_V_XV_M8,
1352 : PseudoVC_V_XV_MF2,
1353 : PseudoVC_V_XV_MF4,
1354 : PseudoVC_V_XV_MF8,
1355 : PseudoVC_V_XV_SE_M1,
1356 : PseudoVC_V_XV_SE_M2,
1357 : PseudoVC_V_XV_SE_M4,
1358 : PseudoVC_V_XV_SE_M8,
1359 : PseudoVC_V_XV_SE_MF2,
1360 : PseudoVC_V_XV_SE_MF4,
1361 : PseudoVC_V_XV_SE_MF8,
1362 : PseudoVC_V_X_M1,
1363 : PseudoVC_V_X_M2,
1364 : PseudoVC_V_X_M4,
1365 : PseudoVC_V_X_M8,
1366 : PseudoVC_V_X_MF2,
1367 : PseudoVC_V_X_MF4,
1368 : PseudoVC_V_X_MF8,
1369 : PseudoVC_V_X_SE_M1,
1370 : PseudoVC_V_X_SE_M2,
1371 : PseudoVC_V_X_SE_M4,
1372 : PseudoVC_V_X_SE_M8,
1373 : PseudoVC_V_X_SE_MF2,
1374 : PseudoVC_V_X_SE_MF4,
1375 : PseudoVC_V_X_SE_MF8,
1376 : PseudoVC_XVV_SE_M1,
1377 : PseudoVC_XVV_SE_M2,
1378 : PseudoVC_XVV_SE_M4,
1379 : PseudoVC_XVV_SE_M8,
1380 : PseudoVC_XVV_SE_MF2,
1381 : PseudoVC_XVV_SE_MF4,
1382 : PseudoVC_XVV_SE_MF8,
1383 : PseudoVC_XVW_SE_M1,
1384 : PseudoVC_XVW_SE_M2,
1385 : PseudoVC_XVW_SE_M4,
1386 : PseudoVC_XVW_SE_MF2,
1387 : PseudoVC_XVW_SE_MF4,
1388 : PseudoVC_XVW_SE_MF8,
1389 : PseudoVC_XV_SE_M1,
1390 : PseudoVC_XV_SE_M2,
1391 : PseudoVC_XV_SE_M4,
1392 : PseudoVC_XV_SE_M8,
1393 : PseudoVC_XV_SE_MF2,
1394 : PseudoVC_XV_SE_MF4,
1395 : PseudoVC_XV_SE_MF8,
1396 : PseudoVC_X_SE_M1,
1397 : PseudoVC_X_SE_M2,
1398 : PseudoVC_X_SE_M4,
1399 : PseudoVC_X_SE_M8,
1400 : PseudoVC_X_SE_MF2,
1401 : PseudoVC_X_SE_MF4,
1402 : PseudoVC_X_SE_MF8,
1403 : PseudoVDIVU_VV_M1_E16,
1404 : PseudoVDIVU_VV_M1_E16_MASK,
1405 : PseudoVDIVU_VV_M1_E32,
1406 : PseudoVDIVU_VV_M1_E32_MASK,
1407 : PseudoVDIVU_VV_M1_E64,
1408 : PseudoVDIVU_VV_M1_E64_MASK,
1409 : PseudoVDIVU_VV_M1_E8,
1410 : PseudoVDIVU_VV_M1_E8_MASK,
1411 : PseudoVDIVU_VV_M2_E16,
1412 : PseudoVDIVU_VV_M2_E16_MASK,
1413 : PseudoVDIVU_VV_M2_E32,
1414 : PseudoVDIVU_VV_M2_E32_MASK,
1415 : PseudoVDIVU_VV_M2_E64,
1416 : PseudoVDIVU_VV_M2_E64_MASK,
1417 : PseudoVDIVU_VV_M2_E8,
1418 : PseudoVDIVU_VV_M2_E8_MASK,
1419 : PseudoVDIVU_VV_M4_E16,
1420 : PseudoVDIVU_VV_M4_E16_MASK,
1421 : PseudoVDIVU_VV_M4_E32,
1422 : PseudoVDIVU_VV_M4_E32_MASK,
1423 : PseudoVDIVU_VV_M4_E64,
1424 : PseudoVDIVU_VV_M4_E64_MASK,
1425 : PseudoVDIVU_VV_M4_E8,
1426 : PseudoVDIVU_VV_M4_E8_MASK,
1427 : PseudoVDIVU_VV_M8_E16,
1428 : PseudoVDIVU_VV_M8_E16_MASK,
1429 : PseudoVDIVU_VV_M8_E32,
1430 : PseudoVDIVU_VV_M8_E32_MASK,
1431 : PseudoVDIVU_VV_M8_E64,
1432 : PseudoVDIVU_VV_M8_E64_MASK,
1433 : PseudoVDIVU_VV_M8_E8,
1434 : PseudoVDIVU_VV_M8_E8_MASK,
1435 : PseudoVDIVU_VV_MF2_E16,
1436 : PseudoVDIVU_VV_MF2_E16_MASK,
1437 : PseudoVDIVU_VV_MF2_E32,
1438 : PseudoVDIVU_VV_MF2_E32_MASK,
1439 : PseudoVDIVU_VV_MF2_E8,
1440 : PseudoVDIVU_VV_MF2_E8_MASK,
1441 : PseudoVDIVU_VV_MF4_E16,
1442 : PseudoVDIVU_VV_MF4_E16_MASK,
1443 : PseudoVDIVU_VV_MF4_E8,
1444 : PseudoVDIVU_VV_MF4_E8_MASK,
1445 : PseudoVDIVU_VV_MF8_E8,
1446 : PseudoVDIVU_VV_MF8_E8_MASK,
1447 : PseudoVDIVU_VX_M1_E16,
1448 : PseudoVDIVU_VX_M1_E16_MASK,
1449 : PseudoVDIVU_VX_M1_E32,
1450 : PseudoVDIVU_VX_M1_E32_MASK,
1451 : PseudoVDIVU_VX_M1_E64,
1452 : PseudoVDIVU_VX_M1_E64_MASK,
1453 : PseudoVDIVU_VX_M1_E8,
1454 : PseudoVDIVU_VX_M1_E8_MASK,
1455 : PseudoVDIVU_VX_M2_E16,
1456 : PseudoVDIVU_VX_M2_E16_MASK,
1457 : PseudoVDIVU_VX_M2_E32,
1458 : PseudoVDIVU_VX_M2_E32_MASK,
1459 : PseudoVDIVU_VX_M2_E64,
1460 : PseudoVDIVU_VX_M2_E64_MASK,
1461 : PseudoVDIVU_VX_M2_E8,
1462 : PseudoVDIVU_VX_M2_E8_MASK,
1463 : PseudoVDIVU_VX_M4_E16,
1464 : PseudoVDIVU_VX_M4_E16_MASK,
1465 : PseudoVDIVU_VX_M4_E32,
1466 : PseudoVDIVU_VX_M4_E32_MASK,
1467 : PseudoVDIVU_VX_M4_E64,
1468 : PseudoVDIVU_VX_M4_E64_MASK,
1469 : PseudoVDIVU_VX_M4_E8,
1470 : PseudoVDIVU_VX_M4_E8_MASK,
1471 : PseudoVDIVU_VX_M8_E16,
1472 : PseudoVDIVU_VX_M8_E16_MASK,
1473 : PseudoVDIVU_VX_M8_E32,
1474 : PseudoVDIVU_VX_M8_E32_MASK,
1475 : PseudoVDIVU_VX_M8_E64,
1476 : PseudoVDIVU_VX_M8_E64_MASK,
1477 : PseudoVDIVU_VX_M8_E8,
1478 : PseudoVDIVU_VX_M8_E8_MASK,
1479 : PseudoVDIVU_VX_MF2_E16,
1480 : PseudoVDIVU_VX_MF2_E16_MASK,
1481 : PseudoVDIVU_VX_MF2_E32,
1482 : PseudoVDIVU_VX_MF2_E32_MASK,
1483 : PseudoVDIVU_VX_MF2_E8,
1484 : PseudoVDIVU_VX_MF2_E8_MASK,
1485 : PseudoVDIVU_VX_MF4_E16,
1486 : PseudoVDIVU_VX_MF4_E16_MASK,
1487 : PseudoVDIVU_VX_MF4_E8,
1488 : PseudoVDIVU_VX_MF4_E8_MASK,
1489 : PseudoVDIVU_VX_MF8_E8,
1490 : PseudoVDIVU_VX_MF8_E8_MASK,
1491 : PseudoVDIV_VV_M1_E16,
1492 : PseudoVDIV_VV_M1_E16_MASK,
1493 : PseudoVDIV_VV_M1_E32,
1494 : PseudoVDIV_VV_M1_E32_MASK,
1495 : PseudoVDIV_VV_M1_E64,
1496 : PseudoVDIV_VV_M1_E64_MASK,
1497 : PseudoVDIV_VV_M1_E8,
1498 : PseudoVDIV_VV_M1_E8_MASK,
1499 : PseudoVDIV_VV_M2_E16,
1500 : PseudoVDIV_VV_M2_E16_MASK,
1501 : PseudoVDIV_VV_M2_E32,
1502 : PseudoVDIV_VV_M2_E32_MASK,
1503 : PseudoVDIV_VV_M2_E64,
1504 : PseudoVDIV_VV_M2_E64_MASK,
1505 : PseudoVDIV_VV_M2_E8,
1506 : PseudoVDIV_VV_M2_E8_MASK,
1507 : PseudoVDIV_VV_M4_E16,
1508 : PseudoVDIV_VV_M4_E16_MASK,
1509 : PseudoVDIV_VV_M4_E32,
1510 : PseudoVDIV_VV_M4_E32_MASK,
1511 : PseudoVDIV_VV_M4_E64,
1512 : PseudoVDIV_VV_M4_E64_MASK,
1513 : PseudoVDIV_VV_M4_E8,
1514 : PseudoVDIV_VV_M4_E8_MASK,
1515 : PseudoVDIV_VV_M8_E16,
1516 : PseudoVDIV_VV_M8_E16_MASK,
1517 : PseudoVDIV_VV_M8_E32,
1518 : PseudoVDIV_VV_M8_E32_MASK,
1519 : PseudoVDIV_VV_M8_E64,
1520 : PseudoVDIV_VV_M8_E64_MASK,
1521 : PseudoVDIV_VV_M8_E8,
1522 : PseudoVDIV_VV_M8_E8_MASK,
1523 : PseudoVDIV_VV_MF2_E16,
1524 : PseudoVDIV_VV_MF2_E16_MASK,
1525 : PseudoVDIV_VV_MF2_E32,
1526 : PseudoVDIV_VV_MF2_E32_MASK,
1527 : PseudoVDIV_VV_MF2_E8,
1528 : PseudoVDIV_VV_MF2_E8_MASK,
1529 : PseudoVDIV_VV_MF4_E16,
1530 : PseudoVDIV_VV_MF4_E16_MASK,
1531 : PseudoVDIV_VV_MF4_E8,
1532 : PseudoVDIV_VV_MF4_E8_MASK,
1533 : PseudoVDIV_VV_MF8_E8,
1534 : PseudoVDIV_VV_MF8_E8_MASK,
1535 : PseudoVDIV_VX_M1_E16,
1536 : PseudoVDIV_VX_M1_E16_MASK,
1537 : PseudoVDIV_VX_M1_E32,
1538 : PseudoVDIV_VX_M1_E32_MASK,
1539 : PseudoVDIV_VX_M1_E64,
1540 : PseudoVDIV_VX_M1_E64_MASK,
1541 : PseudoVDIV_VX_M1_E8,
1542 : PseudoVDIV_VX_M1_E8_MASK,
1543 : PseudoVDIV_VX_M2_E16,
1544 : PseudoVDIV_VX_M2_E16_MASK,
1545 : PseudoVDIV_VX_M2_E32,
1546 : PseudoVDIV_VX_M2_E32_MASK,
1547 : PseudoVDIV_VX_M2_E64,
1548 : PseudoVDIV_VX_M2_E64_MASK,
1549 : PseudoVDIV_VX_M2_E8,
1550 : PseudoVDIV_VX_M2_E8_MASK,
1551 : PseudoVDIV_VX_M4_E16,
1552 : PseudoVDIV_VX_M4_E16_MASK,
1553 : PseudoVDIV_VX_M4_E32,
1554 : PseudoVDIV_VX_M4_E32_MASK,
1555 : PseudoVDIV_VX_M4_E64,
1556 : PseudoVDIV_VX_M4_E64_MASK,
1557 : PseudoVDIV_VX_M4_E8,
1558 : PseudoVDIV_VX_M4_E8_MASK,
1559 : PseudoVDIV_VX_M8_E16,
1560 : PseudoVDIV_VX_M8_E16_MASK,
1561 : PseudoVDIV_VX_M8_E32,
1562 : PseudoVDIV_VX_M8_E32_MASK,
1563 : PseudoVDIV_VX_M8_E64,
1564 : PseudoVDIV_VX_M8_E64_MASK,
1565 : PseudoVDIV_VX_M8_E8,
1566 : PseudoVDIV_VX_M8_E8_MASK,
1567 : PseudoVDIV_VX_MF2_E16,
1568 : PseudoVDIV_VX_MF2_E16_MASK,
1569 : PseudoVDIV_VX_MF2_E32,
1570 : PseudoVDIV_VX_MF2_E32_MASK,
1571 : PseudoVDIV_VX_MF2_E8,
1572 : PseudoVDIV_VX_MF2_E8_MASK,
1573 : PseudoVDIV_VX_MF4_E16,
1574 : PseudoVDIV_VX_MF4_E16_MASK,
1575 : PseudoVDIV_VX_MF4_E8,
1576 : PseudoVDIV_VX_MF4_E8_MASK,
1577 : PseudoVDIV_VX_MF8_E8,
1578 : PseudoVDIV_VX_MF8_E8_MASK,
1579 : PseudoVFADD_VFPR16_M1_E16,
1580 : PseudoVFADD_VFPR16_M1_E16_MASK,
1581 : PseudoVFADD_VFPR16_M2_E16,
1582 : PseudoVFADD_VFPR16_M2_E16_MASK,
1583 : PseudoVFADD_VFPR16_M4_E16,
1584 : PseudoVFADD_VFPR16_M4_E16_MASK,
1585 : PseudoVFADD_VFPR16_M8_E16,
1586 : PseudoVFADD_VFPR16_M8_E16_MASK,
1587 : PseudoVFADD_VFPR16_MF2_E16,
1588 : PseudoVFADD_VFPR16_MF2_E16_MASK,
1589 : PseudoVFADD_VFPR16_MF4_E16,
1590 : PseudoVFADD_VFPR16_MF4_E16_MASK,
1591 : PseudoVFADD_VFPR32_M1_E32,
1592 : PseudoVFADD_VFPR32_M1_E32_MASK,
1593 : PseudoVFADD_VFPR32_M2_E32,
1594 : PseudoVFADD_VFPR32_M2_E32_MASK,
1595 : PseudoVFADD_VFPR32_M4_E32,
1596 : PseudoVFADD_VFPR32_M4_E32_MASK,
1597 : PseudoVFADD_VFPR32_M8_E32,
1598 : PseudoVFADD_VFPR32_M8_E32_MASK,
1599 : PseudoVFADD_VFPR32_MF2_E32,
1600 : PseudoVFADD_VFPR32_MF2_E32_MASK,
1601 : PseudoVFADD_VFPR64_M1_E64,
1602 : PseudoVFADD_VFPR64_M1_E64_MASK,
1603 : PseudoVFADD_VFPR64_M2_E64,
1604 : PseudoVFADD_VFPR64_M2_E64_MASK,
1605 : PseudoVFADD_VFPR64_M4_E64,
1606 : PseudoVFADD_VFPR64_M4_E64_MASK,
1607 : PseudoVFADD_VFPR64_M8_E64,
1608 : PseudoVFADD_VFPR64_M8_E64_MASK,
1609 : PseudoVFADD_VV_M1_E16,
1610 : PseudoVFADD_VV_M1_E16_MASK,
1611 : PseudoVFADD_VV_M1_E32,
1612 : PseudoVFADD_VV_M1_E32_MASK,
1613 : PseudoVFADD_VV_M1_E64,
1614 : PseudoVFADD_VV_M1_E64_MASK,
1615 : PseudoVFADD_VV_M2_E16,
1616 : PseudoVFADD_VV_M2_E16_MASK,
1617 : PseudoVFADD_VV_M2_E32,
1618 : PseudoVFADD_VV_M2_E32_MASK,
1619 : PseudoVFADD_VV_M2_E64,
1620 : PseudoVFADD_VV_M2_E64_MASK,
1621 : PseudoVFADD_VV_M4_E16,
1622 : PseudoVFADD_VV_M4_E16_MASK,
1623 : PseudoVFADD_VV_M4_E32,
1624 : PseudoVFADD_VV_M4_E32_MASK,
1625 : PseudoVFADD_VV_M4_E64,
1626 : PseudoVFADD_VV_M4_E64_MASK,
1627 : PseudoVFADD_VV_M8_E16,
1628 : PseudoVFADD_VV_M8_E16_MASK,
1629 : PseudoVFADD_VV_M8_E32,
1630 : PseudoVFADD_VV_M8_E32_MASK,
1631 : PseudoVFADD_VV_M8_E64,
1632 : PseudoVFADD_VV_M8_E64_MASK,
1633 : PseudoVFADD_VV_MF2_E16,
1634 : PseudoVFADD_VV_MF2_E16_MASK,
1635 : PseudoVFADD_VV_MF2_E32,
1636 : PseudoVFADD_VV_MF2_E32_MASK,
1637 : PseudoVFADD_VV_MF4_E16,
1638 : PseudoVFADD_VV_MF4_E16_MASK,
1639 : PseudoVFCLASS_V_M1,
1640 : PseudoVFCLASS_V_M1_MASK,
1641 : PseudoVFCLASS_V_M2,
1642 : PseudoVFCLASS_V_M2_MASK,
1643 : PseudoVFCLASS_V_M4,
1644 : PseudoVFCLASS_V_M4_MASK,
1645 : PseudoVFCLASS_V_M8,
1646 : PseudoVFCLASS_V_M8_MASK,
1647 : PseudoVFCLASS_V_MF2,
1648 : PseudoVFCLASS_V_MF2_MASK,
1649 : PseudoVFCLASS_V_MF4,
1650 : PseudoVFCLASS_V_MF4_MASK,
1651 : PseudoVFCVT_F_XU_V_M1_E16,
1652 : PseudoVFCVT_F_XU_V_M1_E16_MASK,
1653 : PseudoVFCVT_F_XU_V_M1_E32,
1654 : PseudoVFCVT_F_XU_V_M1_E32_MASK,
1655 : PseudoVFCVT_F_XU_V_M1_E64,
1656 : PseudoVFCVT_F_XU_V_M1_E64_MASK,
1657 : PseudoVFCVT_F_XU_V_M2_E16,
1658 : PseudoVFCVT_F_XU_V_M2_E16_MASK,
1659 : PseudoVFCVT_F_XU_V_M2_E32,
1660 : PseudoVFCVT_F_XU_V_M2_E32_MASK,
1661 : PseudoVFCVT_F_XU_V_M2_E64,
1662 : PseudoVFCVT_F_XU_V_M2_E64_MASK,
1663 : PseudoVFCVT_F_XU_V_M4_E16,
1664 : PseudoVFCVT_F_XU_V_M4_E16_MASK,
1665 : PseudoVFCVT_F_XU_V_M4_E32,
1666 : PseudoVFCVT_F_XU_V_M4_E32_MASK,
1667 : PseudoVFCVT_F_XU_V_M4_E64,
1668 : PseudoVFCVT_F_XU_V_M4_E64_MASK,
1669 : PseudoVFCVT_F_XU_V_M8_E16,
1670 : PseudoVFCVT_F_XU_V_M8_E16_MASK,
1671 : PseudoVFCVT_F_XU_V_M8_E32,
1672 : PseudoVFCVT_F_XU_V_M8_E32_MASK,
1673 : PseudoVFCVT_F_XU_V_M8_E64,
1674 : PseudoVFCVT_F_XU_V_M8_E64_MASK,
1675 : PseudoVFCVT_F_XU_V_MF2_E16,
1676 : PseudoVFCVT_F_XU_V_MF2_E16_MASK,
1677 : PseudoVFCVT_F_XU_V_MF2_E32,
1678 : PseudoVFCVT_F_XU_V_MF2_E32_MASK,
1679 : PseudoVFCVT_F_XU_V_MF4_E16,
1680 : PseudoVFCVT_F_XU_V_MF4_E16_MASK,
1681 : PseudoVFCVT_F_X_V_M1_E16,
1682 : PseudoVFCVT_F_X_V_M1_E16_MASK,
1683 : PseudoVFCVT_F_X_V_M1_E32,
1684 : PseudoVFCVT_F_X_V_M1_E32_MASK,
1685 : PseudoVFCVT_F_X_V_M1_E64,
1686 : PseudoVFCVT_F_X_V_M1_E64_MASK,
1687 : PseudoVFCVT_F_X_V_M2_E16,
1688 : PseudoVFCVT_F_X_V_M2_E16_MASK,
1689 : PseudoVFCVT_F_X_V_M2_E32,
1690 : PseudoVFCVT_F_X_V_M2_E32_MASK,
1691 : PseudoVFCVT_F_X_V_M2_E64,
1692 : PseudoVFCVT_F_X_V_M2_E64_MASK,
1693 : PseudoVFCVT_F_X_V_M4_E16,
1694 : PseudoVFCVT_F_X_V_M4_E16_MASK,
1695 : PseudoVFCVT_F_X_V_M4_E32,
1696 : PseudoVFCVT_F_X_V_M4_E32_MASK,
1697 : PseudoVFCVT_F_X_V_M4_E64,
1698 : PseudoVFCVT_F_X_V_M4_E64_MASK,
1699 : PseudoVFCVT_F_X_V_M8_E16,
1700 : PseudoVFCVT_F_X_V_M8_E16_MASK,
1701 : PseudoVFCVT_F_X_V_M8_E32,
1702 : PseudoVFCVT_F_X_V_M8_E32_MASK,
1703 : PseudoVFCVT_F_X_V_M8_E64,
1704 : PseudoVFCVT_F_X_V_M8_E64_MASK,
1705 : PseudoVFCVT_F_X_V_MF2_E16,
1706 : PseudoVFCVT_F_X_V_MF2_E16_MASK,
1707 : PseudoVFCVT_F_X_V_MF2_E32,
1708 : PseudoVFCVT_F_X_V_MF2_E32_MASK,
1709 : PseudoVFCVT_F_X_V_MF4_E16,
1710 : PseudoVFCVT_F_X_V_MF4_E16_MASK,
1711 : PseudoVFCVT_RM_F_XU_V_M1_E16,
1712 : PseudoVFCVT_RM_F_XU_V_M1_E16_MASK,
1713 : PseudoVFCVT_RM_F_XU_V_M1_E32,
1714 : PseudoVFCVT_RM_F_XU_V_M1_E32_MASK,
1715 : PseudoVFCVT_RM_F_XU_V_M1_E64,
1716 : PseudoVFCVT_RM_F_XU_V_M1_E64_MASK,
1717 : PseudoVFCVT_RM_F_XU_V_M2_E16,
1718 : PseudoVFCVT_RM_F_XU_V_M2_E16_MASK,
1719 : PseudoVFCVT_RM_F_XU_V_M2_E32,
1720 : PseudoVFCVT_RM_F_XU_V_M2_E32_MASK,
1721 : PseudoVFCVT_RM_F_XU_V_M2_E64,
1722 : PseudoVFCVT_RM_F_XU_V_M2_E64_MASK,
1723 : PseudoVFCVT_RM_F_XU_V_M4_E16,
1724 : PseudoVFCVT_RM_F_XU_V_M4_E16_MASK,
1725 : PseudoVFCVT_RM_F_XU_V_M4_E32,
1726 : PseudoVFCVT_RM_F_XU_V_M4_E32_MASK,
1727 : PseudoVFCVT_RM_F_XU_V_M4_E64,
1728 : PseudoVFCVT_RM_F_XU_V_M4_E64_MASK,
1729 : PseudoVFCVT_RM_F_XU_V_M8_E16,
1730 : PseudoVFCVT_RM_F_XU_V_M8_E16_MASK,
1731 : PseudoVFCVT_RM_F_XU_V_M8_E32,
1732 : PseudoVFCVT_RM_F_XU_V_M8_E32_MASK,
1733 : PseudoVFCVT_RM_F_XU_V_M8_E64,
1734 : PseudoVFCVT_RM_F_XU_V_M8_E64_MASK,
1735 : PseudoVFCVT_RM_F_XU_V_MF2_E16,
1736 : PseudoVFCVT_RM_F_XU_V_MF2_E16_MASK,
1737 : PseudoVFCVT_RM_F_XU_V_MF2_E32,
1738 : PseudoVFCVT_RM_F_XU_V_MF2_E32_MASK,
1739 : PseudoVFCVT_RM_F_XU_V_MF4_E16,
1740 : PseudoVFCVT_RM_F_XU_V_MF4_E16_MASK,
1741 : PseudoVFCVT_RM_F_X_V_M1_E16,
1742 : PseudoVFCVT_RM_F_X_V_M1_E16_MASK,
1743 : PseudoVFCVT_RM_F_X_V_M1_E32,
1744 : PseudoVFCVT_RM_F_X_V_M1_E32_MASK,
1745 : PseudoVFCVT_RM_F_X_V_M1_E64,
1746 : PseudoVFCVT_RM_F_X_V_M1_E64_MASK,
1747 : PseudoVFCVT_RM_F_X_V_M2_E16,
1748 : PseudoVFCVT_RM_F_X_V_M2_E16_MASK,
1749 : PseudoVFCVT_RM_F_X_V_M2_E32,
1750 : PseudoVFCVT_RM_F_X_V_M2_E32_MASK,
1751 : PseudoVFCVT_RM_F_X_V_M2_E64,
1752 : PseudoVFCVT_RM_F_X_V_M2_E64_MASK,
1753 : PseudoVFCVT_RM_F_X_V_M4_E16,
1754 : PseudoVFCVT_RM_F_X_V_M4_E16_MASK,
1755 : PseudoVFCVT_RM_F_X_V_M4_E32,
1756 : PseudoVFCVT_RM_F_X_V_M4_E32_MASK,
1757 : PseudoVFCVT_RM_F_X_V_M4_E64,
1758 : PseudoVFCVT_RM_F_X_V_M4_E64_MASK,
1759 : PseudoVFCVT_RM_F_X_V_M8_E16,
1760 : PseudoVFCVT_RM_F_X_V_M8_E16_MASK,
1761 : PseudoVFCVT_RM_F_X_V_M8_E32,
1762 : PseudoVFCVT_RM_F_X_V_M8_E32_MASK,
1763 : PseudoVFCVT_RM_F_X_V_M8_E64,
1764 : PseudoVFCVT_RM_F_X_V_M8_E64_MASK,
1765 : PseudoVFCVT_RM_F_X_V_MF2_E16,
1766 : PseudoVFCVT_RM_F_X_V_MF2_E16_MASK,
1767 : PseudoVFCVT_RM_F_X_V_MF2_E32,
1768 : PseudoVFCVT_RM_F_X_V_MF2_E32_MASK,
1769 : PseudoVFCVT_RM_F_X_V_MF4_E16,
1770 : PseudoVFCVT_RM_F_X_V_MF4_E16_MASK,
1771 : PseudoVFCVT_RM_XU_F_V_M1,
1772 : PseudoVFCVT_RM_XU_F_V_M1_MASK,
1773 : PseudoVFCVT_RM_XU_F_V_M2,
1774 : PseudoVFCVT_RM_XU_F_V_M2_MASK,
1775 : PseudoVFCVT_RM_XU_F_V_M4,
1776 : PseudoVFCVT_RM_XU_F_V_M4_MASK,
1777 : PseudoVFCVT_RM_XU_F_V_M8,
1778 : PseudoVFCVT_RM_XU_F_V_M8_MASK,
1779 : PseudoVFCVT_RM_XU_F_V_MF2,
1780 : PseudoVFCVT_RM_XU_F_V_MF2_MASK,
1781 : PseudoVFCVT_RM_XU_F_V_MF4,
1782 : PseudoVFCVT_RM_XU_F_V_MF4_MASK,
1783 : PseudoVFCVT_RM_X_F_V_M1,
1784 : PseudoVFCVT_RM_X_F_V_M1_MASK,
1785 : PseudoVFCVT_RM_X_F_V_M2,
1786 : PseudoVFCVT_RM_X_F_V_M2_MASK,
1787 : PseudoVFCVT_RM_X_F_V_M4,
1788 : PseudoVFCVT_RM_X_F_V_M4_MASK,
1789 : PseudoVFCVT_RM_X_F_V_M8,
1790 : PseudoVFCVT_RM_X_F_V_M8_MASK,
1791 : PseudoVFCVT_RM_X_F_V_MF2,
1792 : PseudoVFCVT_RM_X_F_V_MF2_MASK,
1793 : PseudoVFCVT_RM_X_F_V_MF4,
1794 : PseudoVFCVT_RM_X_F_V_MF4_MASK,
1795 : PseudoVFCVT_RTZ_XU_F_V_M1,
1796 : PseudoVFCVT_RTZ_XU_F_V_M1_MASK,
1797 : PseudoVFCVT_RTZ_XU_F_V_M2,
1798 : PseudoVFCVT_RTZ_XU_F_V_M2_MASK,
1799 : PseudoVFCVT_RTZ_XU_F_V_M4,
1800 : PseudoVFCVT_RTZ_XU_F_V_M4_MASK,
1801 : PseudoVFCVT_RTZ_XU_F_V_M8,
1802 : PseudoVFCVT_RTZ_XU_F_V_M8_MASK,
1803 : PseudoVFCVT_RTZ_XU_F_V_MF2,
1804 : PseudoVFCVT_RTZ_XU_F_V_MF2_MASK,
1805 : PseudoVFCVT_RTZ_XU_F_V_MF4,
1806 : PseudoVFCVT_RTZ_XU_F_V_MF4_MASK,
1807 : PseudoVFCVT_RTZ_X_F_V_M1,
1808 : PseudoVFCVT_RTZ_X_F_V_M1_MASK,
1809 : PseudoVFCVT_RTZ_X_F_V_M2,
1810 : PseudoVFCVT_RTZ_X_F_V_M2_MASK,
1811 : PseudoVFCVT_RTZ_X_F_V_M4,
1812 : PseudoVFCVT_RTZ_X_F_V_M4_MASK,
1813 : PseudoVFCVT_RTZ_X_F_V_M8,
1814 : PseudoVFCVT_RTZ_X_F_V_M8_MASK,
1815 : PseudoVFCVT_RTZ_X_F_V_MF2,
1816 : PseudoVFCVT_RTZ_X_F_V_MF2_MASK,
1817 : PseudoVFCVT_RTZ_X_F_V_MF4,
1818 : PseudoVFCVT_RTZ_X_F_V_MF4_MASK,
1819 : PseudoVFCVT_XU_F_V_M1,
1820 : PseudoVFCVT_XU_F_V_M1_MASK,
1821 : PseudoVFCVT_XU_F_V_M2,
1822 : PseudoVFCVT_XU_F_V_M2_MASK,
1823 : PseudoVFCVT_XU_F_V_M4,
1824 : PseudoVFCVT_XU_F_V_M4_MASK,
1825 : PseudoVFCVT_XU_F_V_M8,
1826 : PseudoVFCVT_XU_F_V_M8_MASK,
1827 : PseudoVFCVT_XU_F_V_MF2,
1828 : PseudoVFCVT_XU_F_V_MF2_MASK,
1829 : PseudoVFCVT_XU_F_V_MF4,
1830 : PseudoVFCVT_XU_F_V_MF4_MASK,
1831 : PseudoVFCVT_X_F_V_M1,
1832 : PseudoVFCVT_X_F_V_M1_MASK,
1833 : PseudoVFCVT_X_F_V_M2,
1834 : PseudoVFCVT_X_F_V_M2_MASK,
1835 : PseudoVFCVT_X_F_V_M4,
1836 : PseudoVFCVT_X_F_V_M4_MASK,
1837 : PseudoVFCVT_X_F_V_M8,
1838 : PseudoVFCVT_X_F_V_M8_MASK,
1839 : PseudoVFCVT_X_F_V_MF2,
1840 : PseudoVFCVT_X_F_V_MF2_MASK,
1841 : PseudoVFCVT_X_F_V_MF4,
1842 : PseudoVFCVT_X_F_V_MF4_MASK,
1843 : PseudoVFDIV_VFPR16_M1_E16,
1844 : PseudoVFDIV_VFPR16_M1_E16_MASK,
1845 : PseudoVFDIV_VFPR16_M2_E16,
1846 : PseudoVFDIV_VFPR16_M2_E16_MASK,
1847 : PseudoVFDIV_VFPR16_M4_E16,
1848 : PseudoVFDIV_VFPR16_M4_E16_MASK,
1849 : PseudoVFDIV_VFPR16_M8_E16,
1850 : PseudoVFDIV_VFPR16_M8_E16_MASK,
1851 : PseudoVFDIV_VFPR16_MF2_E16,
1852 : PseudoVFDIV_VFPR16_MF2_E16_MASK,
1853 : PseudoVFDIV_VFPR16_MF4_E16,
1854 : PseudoVFDIV_VFPR16_MF4_E16_MASK,
1855 : PseudoVFDIV_VFPR32_M1_E32,
1856 : PseudoVFDIV_VFPR32_M1_E32_MASK,
1857 : PseudoVFDIV_VFPR32_M2_E32,
1858 : PseudoVFDIV_VFPR32_M2_E32_MASK,
1859 : PseudoVFDIV_VFPR32_M4_E32,
1860 : PseudoVFDIV_VFPR32_M4_E32_MASK,
1861 : PseudoVFDIV_VFPR32_M8_E32,
1862 : PseudoVFDIV_VFPR32_M8_E32_MASK,
1863 : PseudoVFDIV_VFPR32_MF2_E32,
1864 : PseudoVFDIV_VFPR32_MF2_E32_MASK,
1865 : PseudoVFDIV_VFPR64_M1_E64,
1866 : PseudoVFDIV_VFPR64_M1_E64_MASK,
1867 : PseudoVFDIV_VFPR64_M2_E64,
1868 : PseudoVFDIV_VFPR64_M2_E64_MASK,
1869 : PseudoVFDIV_VFPR64_M4_E64,
1870 : PseudoVFDIV_VFPR64_M4_E64_MASK,
1871 : PseudoVFDIV_VFPR64_M8_E64,
1872 : PseudoVFDIV_VFPR64_M8_E64_MASK,
1873 : PseudoVFDIV_VV_M1_E16,
1874 : PseudoVFDIV_VV_M1_E16_MASK,
1875 : PseudoVFDIV_VV_M1_E32,
1876 : PseudoVFDIV_VV_M1_E32_MASK,
1877 : PseudoVFDIV_VV_M1_E64,
1878 : PseudoVFDIV_VV_M1_E64_MASK,
1879 : PseudoVFDIV_VV_M2_E16,
1880 : PseudoVFDIV_VV_M2_E16_MASK,
1881 : PseudoVFDIV_VV_M2_E32,
1882 : PseudoVFDIV_VV_M2_E32_MASK,
1883 : PseudoVFDIV_VV_M2_E64,
1884 : PseudoVFDIV_VV_M2_E64_MASK,
1885 : PseudoVFDIV_VV_M4_E16,
1886 : PseudoVFDIV_VV_M4_E16_MASK,
1887 : PseudoVFDIV_VV_M4_E32,
1888 : PseudoVFDIV_VV_M4_E32_MASK,
1889 : PseudoVFDIV_VV_M4_E64,
1890 : PseudoVFDIV_VV_M4_E64_MASK,
1891 : PseudoVFDIV_VV_M8_E16,
1892 : PseudoVFDIV_VV_M8_E16_MASK,
1893 : PseudoVFDIV_VV_M8_E32,
1894 : PseudoVFDIV_VV_M8_E32_MASK,
1895 : PseudoVFDIV_VV_M8_E64,
1896 : PseudoVFDIV_VV_M8_E64_MASK,
1897 : PseudoVFDIV_VV_MF2_E16,
1898 : PseudoVFDIV_VV_MF2_E16_MASK,
1899 : PseudoVFDIV_VV_MF2_E32,
1900 : PseudoVFDIV_VV_MF2_E32_MASK,
1901 : PseudoVFDIV_VV_MF4_E16,
1902 : PseudoVFDIV_VV_MF4_E16_MASK,
1903 : PseudoVFIRST_M_B1,
1904 : PseudoVFIRST_M_B16,
1905 : PseudoVFIRST_M_B16_MASK,
1906 : PseudoVFIRST_M_B1_MASK,
1907 : PseudoVFIRST_M_B2,
1908 : PseudoVFIRST_M_B2_MASK,
1909 : PseudoVFIRST_M_B32,
1910 : PseudoVFIRST_M_B32_MASK,
1911 : PseudoVFIRST_M_B4,
1912 : PseudoVFIRST_M_B4_MASK,
1913 : PseudoVFIRST_M_B64,
1914 : PseudoVFIRST_M_B64_MASK,
1915 : PseudoVFIRST_M_B8,
1916 : PseudoVFIRST_M_B8_MASK,
1917 : PseudoVFMACC_VFPR16_M1_E16,
1918 : PseudoVFMACC_VFPR16_M1_E16_MASK,
1919 : PseudoVFMACC_VFPR16_M2_E16,
1920 : PseudoVFMACC_VFPR16_M2_E16_MASK,
1921 : PseudoVFMACC_VFPR16_M4_E16,
1922 : PseudoVFMACC_VFPR16_M4_E16_MASK,
1923 : PseudoVFMACC_VFPR16_M8_E16,
1924 : PseudoVFMACC_VFPR16_M8_E16_MASK,
1925 : PseudoVFMACC_VFPR16_MF2_E16,
1926 : PseudoVFMACC_VFPR16_MF2_E16_MASK,
1927 : PseudoVFMACC_VFPR16_MF4_E16,
1928 : PseudoVFMACC_VFPR16_MF4_E16_MASK,
1929 : PseudoVFMACC_VFPR32_M1_E32,
1930 : PseudoVFMACC_VFPR32_M1_E32_MASK,
1931 : PseudoVFMACC_VFPR32_M2_E32,
1932 : PseudoVFMACC_VFPR32_M2_E32_MASK,
1933 : PseudoVFMACC_VFPR32_M4_E32,
1934 : PseudoVFMACC_VFPR32_M4_E32_MASK,
1935 : PseudoVFMACC_VFPR32_M8_E32,
1936 : PseudoVFMACC_VFPR32_M8_E32_MASK,
1937 : PseudoVFMACC_VFPR32_MF2_E32,
1938 : PseudoVFMACC_VFPR32_MF2_E32_MASK,
1939 : PseudoVFMACC_VFPR64_M1_E64,
1940 : PseudoVFMACC_VFPR64_M1_E64_MASK,
1941 : PseudoVFMACC_VFPR64_M2_E64,
1942 : PseudoVFMACC_VFPR64_M2_E64_MASK,
1943 : PseudoVFMACC_VFPR64_M4_E64,
1944 : PseudoVFMACC_VFPR64_M4_E64_MASK,
1945 : PseudoVFMACC_VFPR64_M8_E64,
1946 : PseudoVFMACC_VFPR64_M8_E64_MASK,
1947 : PseudoVFMACC_VV_M1_E16,
1948 : PseudoVFMACC_VV_M1_E16_MASK,
1949 : PseudoVFMACC_VV_M1_E32,
1950 : PseudoVFMACC_VV_M1_E32_MASK,
1951 : PseudoVFMACC_VV_M1_E64,
1952 : PseudoVFMACC_VV_M1_E64_MASK,
1953 : PseudoVFMACC_VV_M2_E16,
1954 : PseudoVFMACC_VV_M2_E16_MASK,
1955 : PseudoVFMACC_VV_M2_E32,
1956 : PseudoVFMACC_VV_M2_E32_MASK,
1957 : PseudoVFMACC_VV_M2_E64,
1958 : PseudoVFMACC_VV_M2_E64_MASK,
1959 : PseudoVFMACC_VV_M4_E16,
1960 : PseudoVFMACC_VV_M4_E16_MASK,
1961 : PseudoVFMACC_VV_M4_E32,
1962 : PseudoVFMACC_VV_M4_E32_MASK,
1963 : PseudoVFMACC_VV_M4_E64,
1964 : PseudoVFMACC_VV_M4_E64_MASK,
1965 : PseudoVFMACC_VV_M8_E16,
1966 : PseudoVFMACC_VV_M8_E16_MASK,
1967 : PseudoVFMACC_VV_M8_E32,
1968 : PseudoVFMACC_VV_M8_E32_MASK,
1969 : PseudoVFMACC_VV_M8_E64,
1970 : PseudoVFMACC_VV_M8_E64_MASK,
1971 : PseudoVFMACC_VV_MF2_E16,
1972 : PseudoVFMACC_VV_MF2_E16_MASK,
1973 : PseudoVFMACC_VV_MF2_E32,
1974 : PseudoVFMACC_VV_MF2_E32_MASK,
1975 : PseudoVFMACC_VV_MF4_E16,
1976 : PseudoVFMACC_VV_MF4_E16_MASK,
1977 : PseudoVFMADD_VFPR16_M1_E16,
1978 : PseudoVFMADD_VFPR16_M1_E16_MASK,
1979 : PseudoVFMADD_VFPR16_M2_E16,
1980 : PseudoVFMADD_VFPR16_M2_E16_MASK,
1981 : PseudoVFMADD_VFPR16_M4_E16,
1982 : PseudoVFMADD_VFPR16_M4_E16_MASK,
1983 : PseudoVFMADD_VFPR16_M8_E16,
1984 : PseudoVFMADD_VFPR16_M8_E16_MASK,
1985 : PseudoVFMADD_VFPR16_MF2_E16,
1986 : PseudoVFMADD_VFPR16_MF2_E16_MASK,
1987 : PseudoVFMADD_VFPR16_MF4_E16,
1988 : PseudoVFMADD_VFPR16_MF4_E16_MASK,
1989 : PseudoVFMADD_VFPR32_M1_E32,
1990 : PseudoVFMADD_VFPR32_M1_E32_MASK,
1991 : PseudoVFMADD_VFPR32_M2_E32,
1992 : PseudoVFMADD_VFPR32_M2_E32_MASK,
1993 : PseudoVFMADD_VFPR32_M4_E32,
1994 : PseudoVFMADD_VFPR32_M4_E32_MASK,
1995 : PseudoVFMADD_VFPR32_M8_E32,
1996 : PseudoVFMADD_VFPR32_M8_E32_MASK,
1997 : PseudoVFMADD_VFPR32_MF2_E32,
1998 : PseudoVFMADD_VFPR32_MF2_E32_MASK,
1999 : PseudoVFMADD_VFPR64_M1_E64,
2000 : PseudoVFMADD_VFPR64_M1_E64_MASK,
2001 : PseudoVFMADD_VFPR64_M2_E64,
2002 : PseudoVFMADD_VFPR64_M2_E64_MASK,
2003 : PseudoVFMADD_VFPR64_M4_E64,
2004 : PseudoVFMADD_VFPR64_M4_E64_MASK,
2005 : PseudoVFMADD_VFPR64_M8_E64,
2006 : PseudoVFMADD_VFPR64_M8_E64_MASK,
2007 : PseudoVFMADD_VV_M1_E16,
2008 : PseudoVFMADD_VV_M1_E16_MASK,
2009 : PseudoVFMADD_VV_M1_E32,
2010 : PseudoVFMADD_VV_M1_E32_MASK,
2011 : PseudoVFMADD_VV_M1_E64,
2012 : PseudoVFMADD_VV_M1_E64_MASK,
2013 : PseudoVFMADD_VV_M2_E16,
2014 : PseudoVFMADD_VV_M2_E16_MASK,
2015 : PseudoVFMADD_VV_M2_E32,
2016 : PseudoVFMADD_VV_M2_E32_MASK,
2017 : PseudoVFMADD_VV_M2_E64,
2018 : PseudoVFMADD_VV_M2_E64_MASK,
2019 : PseudoVFMADD_VV_M4_E16,
2020 : PseudoVFMADD_VV_M4_E16_MASK,
2021 : PseudoVFMADD_VV_M4_E32,
2022 : PseudoVFMADD_VV_M4_E32_MASK,
2023 : PseudoVFMADD_VV_M4_E64,
2024 : PseudoVFMADD_VV_M4_E64_MASK,
2025 : PseudoVFMADD_VV_M8_E16,
2026 : PseudoVFMADD_VV_M8_E16_MASK,
2027 : PseudoVFMADD_VV_M8_E32,
2028 : PseudoVFMADD_VV_M8_E32_MASK,
2029 : PseudoVFMADD_VV_M8_E64,
2030 : PseudoVFMADD_VV_M8_E64_MASK,
2031 : PseudoVFMADD_VV_MF2_E16,
2032 : PseudoVFMADD_VV_MF2_E16_MASK,
2033 : PseudoVFMADD_VV_MF2_E32,
2034 : PseudoVFMADD_VV_MF2_E32_MASK,
2035 : PseudoVFMADD_VV_MF4_E16,
2036 : PseudoVFMADD_VV_MF4_E16_MASK,
2037 : PseudoVFMAX_VFPR16_M1_E16,
2038 : PseudoVFMAX_VFPR16_M1_E16_MASK,
2039 : PseudoVFMAX_VFPR16_M2_E16,
2040 : PseudoVFMAX_VFPR16_M2_E16_MASK,
2041 : PseudoVFMAX_VFPR16_M4_E16,
2042 : PseudoVFMAX_VFPR16_M4_E16_MASK,
2043 : PseudoVFMAX_VFPR16_M8_E16,
2044 : PseudoVFMAX_VFPR16_M8_E16_MASK,
2045 : PseudoVFMAX_VFPR16_MF2_E16,
2046 : PseudoVFMAX_VFPR16_MF2_E16_MASK,
2047 : PseudoVFMAX_VFPR16_MF4_E16,
2048 : PseudoVFMAX_VFPR16_MF4_E16_MASK,
2049 : PseudoVFMAX_VFPR32_M1_E32,
2050 : PseudoVFMAX_VFPR32_M1_E32_MASK,
2051 : PseudoVFMAX_VFPR32_M2_E32,
2052 : PseudoVFMAX_VFPR32_M2_E32_MASK,
2053 : PseudoVFMAX_VFPR32_M4_E32,
2054 : PseudoVFMAX_VFPR32_M4_E32_MASK,
2055 : PseudoVFMAX_VFPR32_M8_E32,
2056 : PseudoVFMAX_VFPR32_M8_E32_MASK,
2057 : PseudoVFMAX_VFPR32_MF2_E32,
2058 : PseudoVFMAX_VFPR32_MF2_E32_MASK,
2059 : PseudoVFMAX_VFPR64_M1_E64,
2060 : PseudoVFMAX_VFPR64_M1_E64_MASK,
2061 : PseudoVFMAX_VFPR64_M2_E64,
2062 : PseudoVFMAX_VFPR64_M2_E64_MASK,
2063 : PseudoVFMAX_VFPR64_M4_E64,
2064 : PseudoVFMAX_VFPR64_M4_E64_MASK,
2065 : PseudoVFMAX_VFPR64_M8_E64,
2066 : PseudoVFMAX_VFPR64_M8_E64_MASK,
2067 : PseudoVFMAX_VV_M1_E16,
2068 : PseudoVFMAX_VV_M1_E16_MASK,
2069 : PseudoVFMAX_VV_M1_E32,
2070 : PseudoVFMAX_VV_M1_E32_MASK,
2071 : PseudoVFMAX_VV_M1_E64,
2072 : PseudoVFMAX_VV_M1_E64_MASK,
2073 : PseudoVFMAX_VV_M2_E16,
2074 : PseudoVFMAX_VV_M2_E16_MASK,
2075 : PseudoVFMAX_VV_M2_E32,
2076 : PseudoVFMAX_VV_M2_E32_MASK,
2077 : PseudoVFMAX_VV_M2_E64,
2078 : PseudoVFMAX_VV_M2_E64_MASK,
2079 : PseudoVFMAX_VV_M4_E16,
2080 : PseudoVFMAX_VV_M4_E16_MASK,
2081 : PseudoVFMAX_VV_M4_E32,
2082 : PseudoVFMAX_VV_M4_E32_MASK,
2083 : PseudoVFMAX_VV_M4_E64,
2084 : PseudoVFMAX_VV_M4_E64_MASK,
2085 : PseudoVFMAX_VV_M8_E16,
2086 : PseudoVFMAX_VV_M8_E16_MASK,
2087 : PseudoVFMAX_VV_M8_E32,
2088 : PseudoVFMAX_VV_M8_E32_MASK,
2089 : PseudoVFMAX_VV_M8_E64,
2090 : PseudoVFMAX_VV_M8_E64_MASK,
2091 : PseudoVFMAX_VV_MF2_E16,
2092 : PseudoVFMAX_VV_MF2_E16_MASK,
2093 : PseudoVFMAX_VV_MF2_E32,
2094 : PseudoVFMAX_VV_MF2_E32_MASK,
2095 : PseudoVFMAX_VV_MF4_E16,
2096 : PseudoVFMAX_VV_MF4_E16_MASK,
2097 : PseudoVFMERGE_VFPR16M_M1,
2098 : PseudoVFMERGE_VFPR16M_M2,
2099 : PseudoVFMERGE_VFPR16M_M4,
2100 : PseudoVFMERGE_VFPR16M_M8,
2101 : PseudoVFMERGE_VFPR16M_MF2,
2102 : PseudoVFMERGE_VFPR16M_MF4,
2103 : PseudoVFMERGE_VFPR32M_M1,
2104 : PseudoVFMERGE_VFPR32M_M2,
2105 : PseudoVFMERGE_VFPR32M_M4,
2106 : PseudoVFMERGE_VFPR32M_M8,
2107 : PseudoVFMERGE_VFPR32M_MF2,
2108 : PseudoVFMERGE_VFPR64M_M1,
2109 : PseudoVFMERGE_VFPR64M_M2,
2110 : PseudoVFMERGE_VFPR64M_M4,
2111 : PseudoVFMERGE_VFPR64M_M8,
2112 : PseudoVFMIN_VFPR16_M1_E16,
2113 : PseudoVFMIN_VFPR16_M1_E16_MASK,
2114 : PseudoVFMIN_VFPR16_M2_E16,
2115 : PseudoVFMIN_VFPR16_M2_E16_MASK,
2116 : PseudoVFMIN_VFPR16_M4_E16,
2117 : PseudoVFMIN_VFPR16_M4_E16_MASK,
2118 : PseudoVFMIN_VFPR16_M8_E16,
2119 : PseudoVFMIN_VFPR16_M8_E16_MASK,
2120 : PseudoVFMIN_VFPR16_MF2_E16,
2121 : PseudoVFMIN_VFPR16_MF2_E16_MASK,
2122 : PseudoVFMIN_VFPR16_MF4_E16,
2123 : PseudoVFMIN_VFPR16_MF4_E16_MASK,
2124 : PseudoVFMIN_VFPR32_M1_E32,
2125 : PseudoVFMIN_VFPR32_M1_E32_MASK,
2126 : PseudoVFMIN_VFPR32_M2_E32,
2127 : PseudoVFMIN_VFPR32_M2_E32_MASK,
2128 : PseudoVFMIN_VFPR32_M4_E32,
2129 : PseudoVFMIN_VFPR32_M4_E32_MASK,
2130 : PseudoVFMIN_VFPR32_M8_E32,
2131 : PseudoVFMIN_VFPR32_M8_E32_MASK,
2132 : PseudoVFMIN_VFPR32_MF2_E32,
2133 : PseudoVFMIN_VFPR32_MF2_E32_MASK,
2134 : PseudoVFMIN_VFPR64_M1_E64,
2135 : PseudoVFMIN_VFPR64_M1_E64_MASK,
2136 : PseudoVFMIN_VFPR64_M2_E64,
2137 : PseudoVFMIN_VFPR64_M2_E64_MASK,
2138 : PseudoVFMIN_VFPR64_M4_E64,
2139 : PseudoVFMIN_VFPR64_M4_E64_MASK,
2140 : PseudoVFMIN_VFPR64_M8_E64,
2141 : PseudoVFMIN_VFPR64_M8_E64_MASK,
2142 : PseudoVFMIN_VV_M1_E16,
2143 : PseudoVFMIN_VV_M1_E16_MASK,
2144 : PseudoVFMIN_VV_M1_E32,
2145 : PseudoVFMIN_VV_M1_E32_MASK,
2146 : PseudoVFMIN_VV_M1_E64,
2147 : PseudoVFMIN_VV_M1_E64_MASK,
2148 : PseudoVFMIN_VV_M2_E16,
2149 : PseudoVFMIN_VV_M2_E16_MASK,
2150 : PseudoVFMIN_VV_M2_E32,
2151 : PseudoVFMIN_VV_M2_E32_MASK,
2152 : PseudoVFMIN_VV_M2_E64,
2153 : PseudoVFMIN_VV_M2_E64_MASK,
2154 : PseudoVFMIN_VV_M4_E16,
2155 : PseudoVFMIN_VV_M4_E16_MASK,
2156 : PseudoVFMIN_VV_M4_E32,
2157 : PseudoVFMIN_VV_M4_E32_MASK,
2158 : PseudoVFMIN_VV_M4_E64,
2159 : PseudoVFMIN_VV_M4_E64_MASK,
2160 : PseudoVFMIN_VV_M8_E16,
2161 : PseudoVFMIN_VV_M8_E16_MASK,
2162 : PseudoVFMIN_VV_M8_E32,
2163 : PseudoVFMIN_VV_M8_E32_MASK,
2164 : PseudoVFMIN_VV_M8_E64,
2165 : PseudoVFMIN_VV_M8_E64_MASK,
2166 : PseudoVFMIN_VV_MF2_E16,
2167 : PseudoVFMIN_VV_MF2_E16_MASK,
2168 : PseudoVFMIN_VV_MF2_E32,
2169 : PseudoVFMIN_VV_MF2_E32_MASK,
2170 : PseudoVFMIN_VV_MF4_E16,
2171 : PseudoVFMIN_VV_MF4_E16_MASK,
2172 : PseudoVFMSAC_VFPR16_M1_E16,
2173 : PseudoVFMSAC_VFPR16_M1_E16_MASK,
2174 : PseudoVFMSAC_VFPR16_M2_E16,
2175 : PseudoVFMSAC_VFPR16_M2_E16_MASK,
2176 : PseudoVFMSAC_VFPR16_M4_E16,
2177 : PseudoVFMSAC_VFPR16_M4_E16_MASK,
2178 : PseudoVFMSAC_VFPR16_M8_E16,
2179 : PseudoVFMSAC_VFPR16_M8_E16_MASK,
2180 : PseudoVFMSAC_VFPR16_MF2_E16,
2181 : PseudoVFMSAC_VFPR16_MF2_E16_MASK,
2182 : PseudoVFMSAC_VFPR16_MF4_E16,
2183 : PseudoVFMSAC_VFPR16_MF4_E16_MASK,
2184 : PseudoVFMSAC_VFPR32_M1_E32,
2185 : PseudoVFMSAC_VFPR32_M1_E32_MASK,
2186 : PseudoVFMSAC_VFPR32_M2_E32,
2187 : PseudoVFMSAC_VFPR32_M2_E32_MASK,
2188 : PseudoVFMSAC_VFPR32_M4_E32,
2189 : PseudoVFMSAC_VFPR32_M4_E32_MASK,
2190 : PseudoVFMSAC_VFPR32_M8_E32,
2191 : PseudoVFMSAC_VFPR32_M8_E32_MASK,
2192 : PseudoVFMSAC_VFPR32_MF2_E32,
2193 : PseudoVFMSAC_VFPR32_MF2_E32_MASK,
2194 : PseudoVFMSAC_VFPR64_M1_E64,
2195 : PseudoVFMSAC_VFPR64_M1_E64_MASK,
2196 : PseudoVFMSAC_VFPR64_M2_E64,
2197 : PseudoVFMSAC_VFPR64_M2_E64_MASK,
2198 : PseudoVFMSAC_VFPR64_M4_E64,
2199 : PseudoVFMSAC_VFPR64_M4_E64_MASK,
2200 : PseudoVFMSAC_VFPR64_M8_E64,
2201 : PseudoVFMSAC_VFPR64_M8_E64_MASK,
2202 : PseudoVFMSAC_VV_M1_E16,
2203 : PseudoVFMSAC_VV_M1_E16_MASK,
2204 : PseudoVFMSAC_VV_M1_E32,
2205 : PseudoVFMSAC_VV_M1_E32_MASK,
2206 : PseudoVFMSAC_VV_M1_E64,
2207 : PseudoVFMSAC_VV_M1_E64_MASK,
2208 : PseudoVFMSAC_VV_M2_E16,
2209 : PseudoVFMSAC_VV_M2_E16_MASK,
2210 : PseudoVFMSAC_VV_M2_E32,
2211 : PseudoVFMSAC_VV_M2_E32_MASK,
2212 : PseudoVFMSAC_VV_M2_E64,
2213 : PseudoVFMSAC_VV_M2_E64_MASK,
2214 : PseudoVFMSAC_VV_M4_E16,
2215 : PseudoVFMSAC_VV_M4_E16_MASK,
2216 : PseudoVFMSAC_VV_M4_E32,
2217 : PseudoVFMSAC_VV_M4_E32_MASK,
2218 : PseudoVFMSAC_VV_M4_E64,
2219 : PseudoVFMSAC_VV_M4_E64_MASK,
2220 : PseudoVFMSAC_VV_M8_E16,
2221 : PseudoVFMSAC_VV_M8_E16_MASK,
2222 : PseudoVFMSAC_VV_M8_E32,
2223 : PseudoVFMSAC_VV_M8_E32_MASK,
2224 : PseudoVFMSAC_VV_M8_E64,
2225 : PseudoVFMSAC_VV_M8_E64_MASK,
2226 : PseudoVFMSAC_VV_MF2_E16,
2227 : PseudoVFMSAC_VV_MF2_E16_MASK,
2228 : PseudoVFMSAC_VV_MF2_E32,
2229 : PseudoVFMSAC_VV_MF2_E32_MASK,
2230 : PseudoVFMSAC_VV_MF4_E16,
2231 : PseudoVFMSAC_VV_MF4_E16_MASK,
2232 : PseudoVFMSUB_VFPR16_M1_E16,
2233 : PseudoVFMSUB_VFPR16_M1_E16_MASK,
2234 : PseudoVFMSUB_VFPR16_M2_E16,
2235 : PseudoVFMSUB_VFPR16_M2_E16_MASK,
2236 : PseudoVFMSUB_VFPR16_M4_E16,
2237 : PseudoVFMSUB_VFPR16_M4_E16_MASK,
2238 : PseudoVFMSUB_VFPR16_M8_E16,
2239 : PseudoVFMSUB_VFPR16_M8_E16_MASK,
2240 : PseudoVFMSUB_VFPR16_MF2_E16,
2241 : PseudoVFMSUB_VFPR16_MF2_E16_MASK,
2242 : PseudoVFMSUB_VFPR16_MF4_E16,
2243 : PseudoVFMSUB_VFPR16_MF4_E16_MASK,
2244 : PseudoVFMSUB_VFPR32_M1_E32,
2245 : PseudoVFMSUB_VFPR32_M1_E32_MASK,
2246 : PseudoVFMSUB_VFPR32_M2_E32,
2247 : PseudoVFMSUB_VFPR32_M2_E32_MASK,
2248 : PseudoVFMSUB_VFPR32_M4_E32,
2249 : PseudoVFMSUB_VFPR32_M4_E32_MASK,
2250 : PseudoVFMSUB_VFPR32_M8_E32,
2251 : PseudoVFMSUB_VFPR32_M8_E32_MASK,
2252 : PseudoVFMSUB_VFPR32_MF2_E32,
2253 : PseudoVFMSUB_VFPR32_MF2_E32_MASK,
2254 : PseudoVFMSUB_VFPR64_M1_E64,
2255 : PseudoVFMSUB_VFPR64_M1_E64_MASK,
2256 : PseudoVFMSUB_VFPR64_M2_E64,
2257 : PseudoVFMSUB_VFPR64_M2_E64_MASK,
2258 : PseudoVFMSUB_VFPR64_M4_E64,
2259 : PseudoVFMSUB_VFPR64_M4_E64_MASK,
2260 : PseudoVFMSUB_VFPR64_M8_E64,
2261 : PseudoVFMSUB_VFPR64_M8_E64_MASK,
2262 : PseudoVFMSUB_VV_M1_E16,
2263 : PseudoVFMSUB_VV_M1_E16_MASK,
2264 : PseudoVFMSUB_VV_M1_E32,
2265 : PseudoVFMSUB_VV_M1_E32_MASK,
2266 : PseudoVFMSUB_VV_M1_E64,
2267 : PseudoVFMSUB_VV_M1_E64_MASK,
2268 : PseudoVFMSUB_VV_M2_E16,
2269 : PseudoVFMSUB_VV_M2_E16_MASK,
2270 : PseudoVFMSUB_VV_M2_E32,
2271 : PseudoVFMSUB_VV_M2_E32_MASK,
2272 : PseudoVFMSUB_VV_M2_E64,
2273 : PseudoVFMSUB_VV_M2_E64_MASK,
2274 : PseudoVFMSUB_VV_M4_E16,
2275 : PseudoVFMSUB_VV_M4_E16_MASK,
2276 : PseudoVFMSUB_VV_M4_E32,
2277 : PseudoVFMSUB_VV_M4_E32_MASK,
2278 : PseudoVFMSUB_VV_M4_E64,
2279 : PseudoVFMSUB_VV_M4_E64_MASK,
2280 : PseudoVFMSUB_VV_M8_E16,
2281 : PseudoVFMSUB_VV_M8_E16_MASK,
2282 : PseudoVFMSUB_VV_M8_E32,
2283 : PseudoVFMSUB_VV_M8_E32_MASK,
2284 : PseudoVFMSUB_VV_M8_E64,
2285 : PseudoVFMSUB_VV_M8_E64_MASK,
2286 : PseudoVFMSUB_VV_MF2_E16,
2287 : PseudoVFMSUB_VV_MF2_E16_MASK,
2288 : PseudoVFMSUB_VV_MF2_E32,
2289 : PseudoVFMSUB_VV_MF2_E32_MASK,
2290 : PseudoVFMSUB_VV_MF4_E16,
2291 : PseudoVFMSUB_VV_MF4_E16_MASK,
2292 : PseudoVFMUL_VFPR16_M1_E16,
2293 : PseudoVFMUL_VFPR16_M1_E16_MASK,
2294 : PseudoVFMUL_VFPR16_M2_E16,
2295 : PseudoVFMUL_VFPR16_M2_E16_MASK,
2296 : PseudoVFMUL_VFPR16_M4_E16,
2297 : PseudoVFMUL_VFPR16_M4_E16_MASK,
2298 : PseudoVFMUL_VFPR16_M8_E16,
2299 : PseudoVFMUL_VFPR16_M8_E16_MASK,
2300 : PseudoVFMUL_VFPR16_MF2_E16,
2301 : PseudoVFMUL_VFPR16_MF2_E16_MASK,
2302 : PseudoVFMUL_VFPR16_MF4_E16,
2303 : PseudoVFMUL_VFPR16_MF4_E16_MASK,
2304 : PseudoVFMUL_VFPR32_M1_E32,
2305 : PseudoVFMUL_VFPR32_M1_E32_MASK,
2306 : PseudoVFMUL_VFPR32_M2_E32,
2307 : PseudoVFMUL_VFPR32_M2_E32_MASK,
2308 : PseudoVFMUL_VFPR32_M4_E32,
2309 : PseudoVFMUL_VFPR32_M4_E32_MASK,
2310 : PseudoVFMUL_VFPR32_M8_E32,
2311 : PseudoVFMUL_VFPR32_M8_E32_MASK,
2312 : PseudoVFMUL_VFPR32_MF2_E32,
2313 : PseudoVFMUL_VFPR32_MF2_E32_MASK,
2314 : PseudoVFMUL_VFPR64_M1_E64,
2315 : PseudoVFMUL_VFPR64_M1_E64_MASK,
2316 : PseudoVFMUL_VFPR64_M2_E64,
2317 : PseudoVFMUL_VFPR64_M2_E64_MASK,
2318 : PseudoVFMUL_VFPR64_M4_E64,
2319 : PseudoVFMUL_VFPR64_M4_E64_MASK,
2320 : PseudoVFMUL_VFPR64_M8_E64,
2321 : PseudoVFMUL_VFPR64_M8_E64_MASK,
2322 : PseudoVFMUL_VV_M1_E16,
2323 : PseudoVFMUL_VV_M1_E16_MASK,
2324 : PseudoVFMUL_VV_M1_E32,
2325 : PseudoVFMUL_VV_M1_E32_MASK,
2326 : PseudoVFMUL_VV_M1_E64,
2327 : PseudoVFMUL_VV_M1_E64_MASK,
2328 : PseudoVFMUL_VV_M2_E16,
2329 : PseudoVFMUL_VV_M2_E16_MASK,
2330 : PseudoVFMUL_VV_M2_E32,
2331 : PseudoVFMUL_VV_M2_E32_MASK,
2332 : PseudoVFMUL_VV_M2_E64,
2333 : PseudoVFMUL_VV_M2_E64_MASK,
2334 : PseudoVFMUL_VV_M4_E16,
2335 : PseudoVFMUL_VV_M4_E16_MASK,
2336 : PseudoVFMUL_VV_M4_E32,
2337 : PseudoVFMUL_VV_M4_E32_MASK,
2338 : PseudoVFMUL_VV_M4_E64,
2339 : PseudoVFMUL_VV_M4_E64_MASK,
2340 : PseudoVFMUL_VV_M8_E16,
2341 : PseudoVFMUL_VV_M8_E16_MASK,
2342 : PseudoVFMUL_VV_M8_E32,
2343 : PseudoVFMUL_VV_M8_E32_MASK,
2344 : PseudoVFMUL_VV_M8_E64,
2345 : PseudoVFMUL_VV_M8_E64_MASK,
2346 : PseudoVFMUL_VV_MF2_E16,
2347 : PseudoVFMUL_VV_MF2_E16_MASK,
2348 : PseudoVFMUL_VV_MF2_E32,
2349 : PseudoVFMUL_VV_MF2_E32_MASK,
2350 : PseudoVFMUL_VV_MF4_E16,
2351 : PseudoVFMUL_VV_MF4_E16_MASK,
2352 : PseudoVFMV_FPR16_S_M1,
2353 : PseudoVFMV_FPR16_S_M2,
2354 : PseudoVFMV_FPR16_S_M4,
2355 : PseudoVFMV_FPR16_S_M8,
2356 : PseudoVFMV_FPR16_S_MF2,
2357 : PseudoVFMV_FPR16_S_MF4,
2358 : PseudoVFMV_FPR32_S_M1,
2359 : PseudoVFMV_FPR32_S_M2,
2360 : PseudoVFMV_FPR32_S_M4,
2361 : PseudoVFMV_FPR32_S_M8,
2362 : PseudoVFMV_FPR32_S_MF2,
2363 : PseudoVFMV_FPR64_S_M1,
2364 : PseudoVFMV_FPR64_S_M2,
2365 : PseudoVFMV_FPR64_S_M4,
2366 : PseudoVFMV_FPR64_S_M8,
2367 : PseudoVFMV_S_FPR16_M1,
2368 : PseudoVFMV_S_FPR16_M2,
2369 : PseudoVFMV_S_FPR16_M4,
2370 : PseudoVFMV_S_FPR16_M8,
2371 : PseudoVFMV_S_FPR16_MF2,
2372 : PseudoVFMV_S_FPR16_MF4,
2373 : PseudoVFMV_S_FPR32_M1,
2374 : PseudoVFMV_S_FPR32_M2,
2375 : PseudoVFMV_S_FPR32_M4,
2376 : PseudoVFMV_S_FPR32_M8,
2377 : PseudoVFMV_S_FPR32_MF2,
2378 : PseudoVFMV_S_FPR64_M1,
2379 : PseudoVFMV_S_FPR64_M2,
2380 : PseudoVFMV_S_FPR64_M4,
2381 : PseudoVFMV_S_FPR64_M8,
2382 : PseudoVFMV_V_FPR16_M1,
2383 : PseudoVFMV_V_FPR16_M2,
2384 : PseudoVFMV_V_FPR16_M4,
2385 : PseudoVFMV_V_FPR16_M8,
2386 : PseudoVFMV_V_FPR16_MF2,
2387 : PseudoVFMV_V_FPR16_MF4,
2388 : PseudoVFMV_V_FPR32_M1,
2389 : PseudoVFMV_V_FPR32_M2,
2390 : PseudoVFMV_V_FPR32_M4,
2391 : PseudoVFMV_V_FPR32_M8,
2392 : PseudoVFMV_V_FPR32_MF2,
2393 : PseudoVFMV_V_FPR64_M1,
2394 : PseudoVFMV_V_FPR64_M2,
2395 : PseudoVFMV_V_FPR64_M4,
2396 : PseudoVFMV_V_FPR64_M8,
2397 : PseudoVFNCVTBF16_F_F_W_M1_E16,
2398 : PseudoVFNCVTBF16_F_F_W_M1_E16_MASK,
2399 : PseudoVFNCVTBF16_F_F_W_M1_E32,
2400 : PseudoVFNCVTBF16_F_F_W_M1_E32_MASK,
2401 : PseudoVFNCVTBF16_F_F_W_M2_E16,
2402 : PseudoVFNCVTBF16_F_F_W_M2_E16_MASK,
2403 : PseudoVFNCVTBF16_F_F_W_M2_E32,
2404 : PseudoVFNCVTBF16_F_F_W_M2_E32_MASK,
2405 : PseudoVFNCVTBF16_F_F_W_M4_E16,
2406 : PseudoVFNCVTBF16_F_F_W_M4_E16_MASK,
2407 : PseudoVFNCVTBF16_F_F_W_M4_E32,
2408 : PseudoVFNCVTBF16_F_F_W_M4_E32_MASK,
2409 : PseudoVFNCVTBF16_F_F_W_MF2_E16,
2410 : PseudoVFNCVTBF16_F_F_W_MF2_E16_MASK,
2411 : PseudoVFNCVTBF16_F_F_W_MF2_E32,
2412 : PseudoVFNCVTBF16_F_F_W_MF2_E32_MASK,
2413 : PseudoVFNCVTBF16_F_F_W_MF4_E16,
2414 : PseudoVFNCVTBF16_F_F_W_MF4_E16_MASK,
2415 : PseudoVFNCVT_F_F_W_M1_E16,
2416 : PseudoVFNCVT_F_F_W_M1_E16_MASK,
2417 : PseudoVFNCVT_F_F_W_M1_E32,
2418 : PseudoVFNCVT_F_F_W_M1_E32_MASK,
2419 : PseudoVFNCVT_F_F_W_M2_E16,
2420 : PseudoVFNCVT_F_F_W_M2_E16_MASK,
2421 : PseudoVFNCVT_F_F_W_M2_E32,
2422 : PseudoVFNCVT_F_F_W_M2_E32_MASK,
2423 : PseudoVFNCVT_F_F_W_M4_E16,
2424 : PseudoVFNCVT_F_F_W_M4_E16_MASK,
2425 : PseudoVFNCVT_F_F_W_M4_E32,
2426 : PseudoVFNCVT_F_F_W_M4_E32_MASK,
2427 : PseudoVFNCVT_F_F_W_MF2_E16,
2428 : PseudoVFNCVT_F_F_W_MF2_E16_MASK,
2429 : PseudoVFNCVT_F_F_W_MF2_E32,
2430 : PseudoVFNCVT_F_F_W_MF2_E32_MASK,
2431 : PseudoVFNCVT_F_F_W_MF4_E16,
2432 : PseudoVFNCVT_F_F_W_MF4_E16_MASK,
2433 : PseudoVFNCVT_F_XU_W_M1_E16,
2434 : PseudoVFNCVT_F_XU_W_M1_E16_MASK,
2435 : PseudoVFNCVT_F_XU_W_M1_E32,
2436 : PseudoVFNCVT_F_XU_W_M1_E32_MASK,
2437 : PseudoVFNCVT_F_XU_W_M2_E16,
2438 : PseudoVFNCVT_F_XU_W_M2_E16_MASK,
2439 : PseudoVFNCVT_F_XU_W_M2_E32,
2440 : PseudoVFNCVT_F_XU_W_M2_E32_MASK,
2441 : PseudoVFNCVT_F_XU_W_M4_E16,
2442 : PseudoVFNCVT_F_XU_W_M4_E16_MASK,
2443 : PseudoVFNCVT_F_XU_W_M4_E32,
2444 : PseudoVFNCVT_F_XU_W_M4_E32_MASK,
2445 : PseudoVFNCVT_F_XU_W_MF2_E16,
2446 : PseudoVFNCVT_F_XU_W_MF2_E16_MASK,
2447 : PseudoVFNCVT_F_XU_W_MF2_E32,
2448 : PseudoVFNCVT_F_XU_W_MF2_E32_MASK,
2449 : PseudoVFNCVT_F_XU_W_MF4_E16,
2450 : PseudoVFNCVT_F_XU_W_MF4_E16_MASK,
2451 : PseudoVFNCVT_F_X_W_M1_E16,
2452 : PseudoVFNCVT_F_X_W_M1_E16_MASK,
2453 : PseudoVFNCVT_F_X_W_M1_E32,
2454 : PseudoVFNCVT_F_X_W_M1_E32_MASK,
2455 : PseudoVFNCVT_F_X_W_M2_E16,
2456 : PseudoVFNCVT_F_X_W_M2_E16_MASK,
2457 : PseudoVFNCVT_F_X_W_M2_E32,
2458 : PseudoVFNCVT_F_X_W_M2_E32_MASK,
2459 : PseudoVFNCVT_F_X_W_M4_E16,
2460 : PseudoVFNCVT_F_X_W_M4_E16_MASK,
2461 : PseudoVFNCVT_F_X_W_M4_E32,
2462 : PseudoVFNCVT_F_X_W_M4_E32_MASK,
2463 : PseudoVFNCVT_F_X_W_MF2_E16,
2464 : PseudoVFNCVT_F_X_W_MF2_E16_MASK,
2465 : PseudoVFNCVT_F_X_W_MF2_E32,
2466 : PseudoVFNCVT_F_X_W_MF2_E32_MASK,
2467 : PseudoVFNCVT_F_X_W_MF4_E16,
2468 : PseudoVFNCVT_F_X_W_MF4_E16_MASK,
2469 : PseudoVFNCVT_RM_F_XU_W_M1_E16,
2470 : PseudoVFNCVT_RM_F_XU_W_M1_E16_MASK,
2471 : PseudoVFNCVT_RM_F_XU_W_M1_E32,
2472 : PseudoVFNCVT_RM_F_XU_W_M1_E32_MASK,
2473 : PseudoVFNCVT_RM_F_XU_W_M2_E16,
2474 : PseudoVFNCVT_RM_F_XU_W_M2_E16_MASK,
2475 : PseudoVFNCVT_RM_F_XU_W_M2_E32,
2476 : PseudoVFNCVT_RM_F_XU_W_M2_E32_MASK,
2477 : PseudoVFNCVT_RM_F_XU_W_M4_E16,
2478 : PseudoVFNCVT_RM_F_XU_W_M4_E16_MASK,
2479 : PseudoVFNCVT_RM_F_XU_W_M4_E32,
2480 : PseudoVFNCVT_RM_F_XU_W_M4_E32_MASK,
2481 : PseudoVFNCVT_RM_F_XU_W_MF2_E16,
2482 : PseudoVFNCVT_RM_F_XU_W_MF2_E16_MASK,
2483 : PseudoVFNCVT_RM_F_XU_W_MF2_E32,
2484 : PseudoVFNCVT_RM_F_XU_W_MF2_E32_MASK,
2485 : PseudoVFNCVT_RM_F_XU_W_MF4_E16,
2486 : PseudoVFNCVT_RM_F_XU_W_MF4_E16_MASK,
2487 : PseudoVFNCVT_RM_F_X_W_M1_E16,
2488 : PseudoVFNCVT_RM_F_X_W_M1_E16_MASK,
2489 : PseudoVFNCVT_RM_F_X_W_M1_E32,
2490 : PseudoVFNCVT_RM_F_X_W_M1_E32_MASK,
2491 : PseudoVFNCVT_RM_F_X_W_M2_E16,
2492 : PseudoVFNCVT_RM_F_X_W_M2_E16_MASK,
2493 : PseudoVFNCVT_RM_F_X_W_M2_E32,
2494 : PseudoVFNCVT_RM_F_X_W_M2_E32_MASK,
2495 : PseudoVFNCVT_RM_F_X_W_M4_E16,
2496 : PseudoVFNCVT_RM_F_X_W_M4_E16_MASK,
2497 : PseudoVFNCVT_RM_F_X_W_M4_E32,
2498 : PseudoVFNCVT_RM_F_X_W_M4_E32_MASK,
2499 : PseudoVFNCVT_RM_F_X_W_MF2_E16,
2500 : PseudoVFNCVT_RM_F_X_W_MF2_E16_MASK,
2501 : PseudoVFNCVT_RM_F_X_W_MF2_E32,
2502 : PseudoVFNCVT_RM_F_X_W_MF2_E32_MASK,
2503 : PseudoVFNCVT_RM_F_X_W_MF4_E16,
2504 : PseudoVFNCVT_RM_F_X_W_MF4_E16_MASK,
2505 : PseudoVFNCVT_RM_XU_F_W_M1,
2506 : PseudoVFNCVT_RM_XU_F_W_M1_MASK,
2507 : PseudoVFNCVT_RM_XU_F_W_M2,
2508 : PseudoVFNCVT_RM_XU_F_W_M2_MASK,
2509 : PseudoVFNCVT_RM_XU_F_W_M4,
2510 : PseudoVFNCVT_RM_XU_F_W_M4_MASK,
2511 : PseudoVFNCVT_RM_XU_F_W_MF2,
2512 : PseudoVFNCVT_RM_XU_F_W_MF2_MASK,
2513 : PseudoVFNCVT_RM_XU_F_W_MF4,
2514 : PseudoVFNCVT_RM_XU_F_W_MF4_MASK,
2515 : PseudoVFNCVT_RM_XU_F_W_MF8,
2516 : PseudoVFNCVT_RM_XU_F_W_MF8_MASK,
2517 : PseudoVFNCVT_RM_X_F_W_M1,
2518 : PseudoVFNCVT_RM_X_F_W_M1_MASK,
2519 : PseudoVFNCVT_RM_X_F_W_M2,
2520 : PseudoVFNCVT_RM_X_F_W_M2_MASK,
2521 : PseudoVFNCVT_RM_X_F_W_M4,
2522 : PseudoVFNCVT_RM_X_F_W_M4_MASK,
2523 : PseudoVFNCVT_RM_X_F_W_MF2,
2524 : PseudoVFNCVT_RM_X_F_W_MF2_MASK,
2525 : PseudoVFNCVT_RM_X_F_W_MF4,
2526 : PseudoVFNCVT_RM_X_F_W_MF4_MASK,
2527 : PseudoVFNCVT_RM_X_F_W_MF8,
2528 : PseudoVFNCVT_RM_X_F_W_MF8_MASK,
2529 : PseudoVFNCVT_ROD_F_F_W_M1_E16,
2530 : PseudoVFNCVT_ROD_F_F_W_M1_E16_MASK,
2531 : PseudoVFNCVT_ROD_F_F_W_M1_E32,
2532 : PseudoVFNCVT_ROD_F_F_W_M1_E32_MASK,
2533 : PseudoVFNCVT_ROD_F_F_W_M2_E16,
2534 : PseudoVFNCVT_ROD_F_F_W_M2_E16_MASK,
2535 : PseudoVFNCVT_ROD_F_F_W_M2_E32,
2536 : PseudoVFNCVT_ROD_F_F_W_M2_E32_MASK,
2537 : PseudoVFNCVT_ROD_F_F_W_M4_E16,
2538 : PseudoVFNCVT_ROD_F_F_W_M4_E16_MASK,
2539 : PseudoVFNCVT_ROD_F_F_W_M4_E32,
2540 : PseudoVFNCVT_ROD_F_F_W_M4_E32_MASK,
2541 : PseudoVFNCVT_ROD_F_F_W_MF2_E16,
2542 : PseudoVFNCVT_ROD_F_F_W_MF2_E16_MASK,
2543 : PseudoVFNCVT_ROD_F_F_W_MF2_E32,
2544 : PseudoVFNCVT_ROD_F_F_W_MF2_E32_MASK,
2545 : PseudoVFNCVT_ROD_F_F_W_MF4_E16,
2546 : PseudoVFNCVT_ROD_F_F_W_MF4_E16_MASK,
2547 : PseudoVFNCVT_RTZ_XU_F_W_M1,
2548 : PseudoVFNCVT_RTZ_XU_F_W_M1_MASK,
2549 : PseudoVFNCVT_RTZ_XU_F_W_M2,
2550 : PseudoVFNCVT_RTZ_XU_F_W_M2_MASK,
2551 : PseudoVFNCVT_RTZ_XU_F_W_M4,
2552 : PseudoVFNCVT_RTZ_XU_F_W_M4_MASK,
2553 : PseudoVFNCVT_RTZ_XU_F_W_MF2,
2554 : PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK,
2555 : PseudoVFNCVT_RTZ_XU_F_W_MF4,
2556 : PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK,
2557 : PseudoVFNCVT_RTZ_XU_F_W_MF8,
2558 : PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK,
2559 : PseudoVFNCVT_RTZ_X_F_W_M1,
2560 : PseudoVFNCVT_RTZ_X_F_W_M1_MASK,
2561 : PseudoVFNCVT_RTZ_X_F_W_M2,
2562 : PseudoVFNCVT_RTZ_X_F_W_M2_MASK,
2563 : PseudoVFNCVT_RTZ_X_F_W_M4,
2564 : PseudoVFNCVT_RTZ_X_F_W_M4_MASK,
2565 : PseudoVFNCVT_RTZ_X_F_W_MF2,
2566 : PseudoVFNCVT_RTZ_X_F_W_MF2_MASK,
2567 : PseudoVFNCVT_RTZ_X_F_W_MF4,
2568 : PseudoVFNCVT_RTZ_X_F_W_MF4_MASK,
2569 : PseudoVFNCVT_RTZ_X_F_W_MF8,
2570 : PseudoVFNCVT_RTZ_X_F_W_MF8_MASK,
2571 : PseudoVFNCVT_XU_F_W_M1,
2572 : PseudoVFNCVT_XU_F_W_M1_MASK,
2573 : PseudoVFNCVT_XU_F_W_M2,
2574 : PseudoVFNCVT_XU_F_W_M2_MASK,
2575 : PseudoVFNCVT_XU_F_W_M4,
2576 : PseudoVFNCVT_XU_F_W_M4_MASK,
2577 : PseudoVFNCVT_XU_F_W_MF2,
2578 : PseudoVFNCVT_XU_F_W_MF2_MASK,
2579 : PseudoVFNCVT_XU_F_W_MF4,
2580 : PseudoVFNCVT_XU_F_W_MF4_MASK,
2581 : PseudoVFNCVT_XU_F_W_MF8,
2582 : PseudoVFNCVT_XU_F_W_MF8_MASK,
2583 : PseudoVFNCVT_X_F_W_M1,
2584 : PseudoVFNCVT_X_F_W_M1_MASK,
2585 : PseudoVFNCVT_X_F_W_M2,
2586 : PseudoVFNCVT_X_F_W_M2_MASK,
2587 : PseudoVFNCVT_X_F_W_M4,
2588 : PseudoVFNCVT_X_F_W_M4_MASK,
2589 : PseudoVFNCVT_X_F_W_MF2,
2590 : PseudoVFNCVT_X_F_W_MF2_MASK,
2591 : PseudoVFNCVT_X_F_W_MF4,
2592 : PseudoVFNCVT_X_F_W_MF4_MASK,
2593 : PseudoVFNCVT_X_F_W_MF8,
2594 : PseudoVFNCVT_X_F_W_MF8_MASK,
2595 : PseudoVFNMACC_VFPR16_M1_E16,
2596 : PseudoVFNMACC_VFPR16_M1_E16_MASK,
2597 : PseudoVFNMACC_VFPR16_M2_E16,
2598 : PseudoVFNMACC_VFPR16_M2_E16_MASK,
2599 : PseudoVFNMACC_VFPR16_M4_E16,
2600 : PseudoVFNMACC_VFPR16_M4_E16_MASK,
2601 : PseudoVFNMACC_VFPR16_M8_E16,
2602 : PseudoVFNMACC_VFPR16_M8_E16_MASK,
2603 : PseudoVFNMACC_VFPR16_MF2_E16,
2604 : PseudoVFNMACC_VFPR16_MF2_E16_MASK,
2605 : PseudoVFNMACC_VFPR16_MF4_E16,
2606 : PseudoVFNMACC_VFPR16_MF4_E16_MASK,
2607 : PseudoVFNMACC_VFPR32_M1_E32,
2608 : PseudoVFNMACC_VFPR32_M1_E32_MASK,
2609 : PseudoVFNMACC_VFPR32_M2_E32,
2610 : PseudoVFNMACC_VFPR32_M2_E32_MASK,
2611 : PseudoVFNMACC_VFPR32_M4_E32,
2612 : PseudoVFNMACC_VFPR32_M4_E32_MASK,
2613 : PseudoVFNMACC_VFPR32_M8_E32,
2614 : PseudoVFNMACC_VFPR32_M8_E32_MASK,
2615 : PseudoVFNMACC_VFPR32_MF2_E32,
2616 : PseudoVFNMACC_VFPR32_MF2_E32_MASK,
2617 : PseudoVFNMACC_VFPR64_M1_E64,
2618 : PseudoVFNMACC_VFPR64_M1_E64_MASK,
2619 : PseudoVFNMACC_VFPR64_M2_E64,
2620 : PseudoVFNMACC_VFPR64_M2_E64_MASK,
2621 : PseudoVFNMACC_VFPR64_M4_E64,
2622 : PseudoVFNMACC_VFPR64_M4_E64_MASK,
2623 : PseudoVFNMACC_VFPR64_M8_E64,
2624 : PseudoVFNMACC_VFPR64_M8_E64_MASK,
2625 : PseudoVFNMACC_VV_M1_E16,
2626 : PseudoVFNMACC_VV_M1_E16_MASK,
2627 : PseudoVFNMACC_VV_M1_E32,
2628 : PseudoVFNMACC_VV_M1_E32_MASK,
2629 : PseudoVFNMACC_VV_M1_E64,
2630 : PseudoVFNMACC_VV_M1_E64_MASK,
2631 : PseudoVFNMACC_VV_M2_E16,
2632 : PseudoVFNMACC_VV_M2_E16_MASK,
2633 : PseudoVFNMACC_VV_M2_E32,
2634 : PseudoVFNMACC_VV_M2_E32_MASK,
2635 : PseudoVFNMACC_VV_M2_E64,
2636 : PseudoVFNMACC_VV_M2_E64_MASK,
2637 : PseudoVFNMACC_VV_M4_E16,
2638 : PseudoVFNMACC_VV_M4_E16_MASK,
2639 : PseudoVFNMACC_VV_M4_E32,
2640 : PseudoVFNMACC_VV_M4_E32_MASK,
2641 : PseudoVFNMACC_VV_M4_E64,
2642 : PseudoVFNMACC_VV_M4_E64_MASK,
2643 : PseudoVFNMACC_VV_M8_E16,
2644 : PseudoVFNMACC_VV_M8_E16_MASK,
2645 : PseudoVFNMACC_VV_M8_E32,
2646 : PseudoVFNMACC_VV_M8_E32_MASK,
2647 : PseudoVFNMACC_VV_M8_E64,
2648 : PseudoVFNMACC_VV_M8_E64_MASK,
2649 : PseudoVFNMACC_VV_MF2_E16,
2650 : PseudoVFNMACC_VV_MF2_E16_MASK,
2651 : PseudoVFNMACC_VV_MF2_E32,
2652 : PseudoVFNMACC_VV_MF2_E32_MASK,
2653 : PseudoVFNMACC_VV_MF4_E16,
2654 : PseudoVFNMACC_VV_MF4_E16_MASK,
2655 : PseudoVFNMADD_VFPR16_M1_E16,
2656 : PseudoVFNMADD_VFPR16_M1_E16_MASK,
2657 : PseudoVFNMADD_VFPR16_M2_E16,
2658 : PseudoVFNMADD_VFPR16_M2_E16_MASK,
2659 : PseudoVFNMADD_VFPR16_M4_E16,
2660 : PseudoVFNMADD_VFPR16_M4_E16_MASK,
2661 : PseudoVFNMADD_VFPR16_M8_E16,
2662 : PseudoVFNMADD_VFPR16_M8_E16_MASK,
2663 : PseudoVFNMADD_VFPR16_MF2_E16,
2664 : PseudoVFNMADD_VFPR16_MF2_E16_MASK,
2665 : PseudoVFNMADD_VFPR16_MF4_E16,
2666 : PseudoVFNMADD_VFPR16_MF4_E16_MASK,
2667 : PseudoVFNMADD_VFPR32_M1_E32,
2668 : PseudoVFNMADD_VFPR32_M1_E32_MASK,
2669 : PseudoVFNMADD_VFPR32_M2_E32,
2670 : PseudoVFNMADD_VFPR32_M2_E32_MASK,
2671 : PseudoVFNMADD_VFPR32_M4_E32,
2672 : PseudoVFNMADD_VFPR32_M4_E32_MASK,
2673 : PseudoVFNMADD_VFPR32_M8_E32,
2674 : PseudoVFNMADD_VFPR32_M8_E32_MASK,
2675 : PseudoVFNMADD_VFPR32_MF2_E32,
2676 : PseudoVFNMADD_VFPR32_MF2_E32_MASK,
2677 : PseudoVFNMADD_VFPR64_M1_E64,
2678 : PseudoVFNMADD_VFPR64_M1_E64_MASK,
2679 : PseudoVFNMADD_VFPR64_M2_E64,
2680 : PseudoVFNMADD_VFPR64_M2_E64_MASK,
2681 : PseudoVFNMADD_VFPR64_M4_E64,
2682 : PseudoVFNMADD_VFPR64_M4_E64_MASK,
2683 : PseudoVFNMADD_VFPR64_M8_E64,
2684 : PseudoVFNMADD_VFPR64_M8_E64_MASK,
2685 : PseudoVFNMADD_VV_M1_E16,
2686 : PseudoVFNMADD_VV_M1_E16_MASK,
2687 : PseudoVFNMADD_VV_M1_E32,
2688 : PseudoVFNMADD_VV_M1_E32_MASK,
2689 : PseudoVFNMADD_VV_M1_E64,
2690 : PseudoVFNMADD_VV_M1_E64_MASK,
2691 : PseudoVFNMADD_VV_M2_E16,
2692 : PseudoVFNMADD_VV_M2_E16_MASK,
2693 : PseudoVFNMADD_VV_M2_E32,
2694 : PseudoVFNMADD_VV_M2_E32_MASK,
2695 : PseudoVFNMADD_VV_M2_E64,
2696 : PseudoVFNMADD_VV_M2_E64_MASK,
2697 : PseudoVFNMADD_VV_M4_E16,
2698 : PseudoVFNMADD_VV_M4_E16_MASK,
2699 : PseudoVFNMADD_VV_M4_E32,
2700 : PseudoVFNMADD_VV_M4_E32_MASK,
2701 : PseudoVFNMADD_VV_M4_E64,
2702 : PseudoVFNMADD_VV_M4_E64_MASK,
2703 : PseudoVFNMADD_VV_M8_E16,
2704 : PseudoVFNMADD_VV_M8_E16_MASK,
2705 : PseudoVFNMADD_VV_M8_E32,
2706 : PseudoVFNMADD_VV_M8_E32_MASK,
2707 : PseudoVFNMADD_VV_M8_E64,
2708 : PseudoVFNMADD_VV_M8_E64_MASK,
2709 : PseudoVFNMADD_VV_MF2_E16,
2710 : PseudoVFNMADD_VV_MF2_E16_MASK,
2711 : PseudoVFNMADD_VV_MF2_E32,
2712 : PseudoVFNMADD_VV_MF2_E32_MASK,
2713 : PseudoVFNMADD_VV_MF4_E16,
2714 : PseudoVFNMADD_VV_MF4_E16_MASK,
2715 : PseudoVFNMSAC_VFPR16_M1_E16,
2716 : PseudoVFNMSAC_VFPR16_M1_E16_MASK,
2717 : PseudoVFNMSAC_VFPR16_M2_E16,
2718 : PseudoVFNMSAC_VFPR16_M2_E16_MASK,
2719 : PseudoVFNMSAC_VFPR16_M4_E16,
2720 : PseudoVFNMSAC_VFPR16_M4_E16_MASK,
2721 : PseudoVFNMSAC_VFPR16_M8_E16,
2722 : PseudoVFNMSAC_VFPR16_M8_E16_MASK,
2723 : PseudoVFNMSAC_VFPR16_MF2_E16,
2724 : PseudoVFNMSAC_VFPR16_MF2_E16_MASK,
2725 : PseudoVFNMSAC_VFPR16_MF4_E16,
2726 : PseudoVFNMSAC_VFPR16_MF4_E16_MASK,
2727 : PseudoVFNMSAC_VFPR32_M1_E32,
2728 : PseudoVFNMSAC_VFPR32_M1_E32_MASK,
2729 : PseudoVFNMSAC_VFPR32_M2_E32,
2730 : PseudoVFNMSAC_VFPR32_M2_E32_MASK,
2731 : PseudoVFNMSAC_VFPR32_M4_E32,
2732 : PseudoVFNMSAC_VFPR32_M4_E32_MASK,
2733 : PseudoVFNMSAC_VFPR32_M8_E32,
2734 : PseudoVFNMSAC_VFPR32_M8_E32_MASK,
2735 : PseudoVFNMSAC_VFPR32_MF2_E32,
2736 : PseudoVFNMSAC_VFPR32_MF2_E32_MASK,
2737 : PseudoVFNMSAC_VFPR64_M1_E64,
2738 : PseudoVFNMSAC_VFPR64_M1_E64_MASK,
2739 : PseudoVFNMSAC_VFPR64_M2_E64,
2740 : PseudoVFNMSAC_VFPR64_M2_E64_MASK,
2741 : PseudoVFNMSAC_VFPR64_M4_E64,
2742 : PseudoVFNMSAC_VFPR64_M4_E64_MASK,
2743 : PseudoVFNMSAC_VFPR64_M8_E64,
2744 : PseudoVFNMSAC_VFPR64_M8_E64_MASK,
2745 : PseudoVFNMSAC_VV_M1_E16,
2746 : PseudoVFNMSAC_VV_M1_E16_MASK,
2747 : PseudoVFNMSAC_VV_M1_E32,
2748 : PseudoVFNMSAC_VV_M1_E32_MASK,
2749 : PseudoVFNMSAC_VV_M1_E64,
2750 : PseudoVFNMSAC_VV_M1_E64_MASK,
2751 : PseudoVFNMSAC_VV_M2_E16,
2752 : PseudoVFNMSAC_VV_M2_E16_MASK,
2753 : PseudoVFNMSAC_VV_M2_E32,
2754 : PseudoVFNMSAC_VV_M2_E32_MASK,
2755 : PseudoVFNMSAC_VV_M2_E64,
2756 : PseudoVFNMSAC_VV_M2_E64_MASK,
2757 : PseudoVFNMSAC_VV_M4_E16,
2758 : PseudoVFNMSAC_VV_M4_E16_MASK,
2759 : PseudoVFNMSAC_VV_M4_E32,
2760 : PseudoVFNMSAC_VV_M4_E32_MASK,
2761 : PseudoVFNMSAC_VV_M4_E64,
2762 : PseudoVFNMSAC_VV_M4_E64_MASK,
2763 : PseudoVFNMSAC_VV_M8_E16,
2764 : PseudoVFNMSAC_VV_M8_E16_MASK,
2765 : PseudoVFNMSAC_VV_M8_E32,
2766 : PseudoVFNMSAC_VV_M8_E32_MASK,
2767 : PseudoVFNMSAC_VV_M8_E64,
2768 : PseudoVFNMSAC_VV_M8_E64_MASK,
2769 : PseudoVFNMSAC_VV_MF2_E16,
2770 : PseudoVFNMSAC_VV_MF2_E16_MASK,
2771 : PseudoVFNMSAC_VV_MF2_E32,
2772 : PseudoVFNMSAC_VV_MF2_E32_MASK,
2773 : PseudoVFNMSAC_VV_MF4_E16,
2774 : PseudoVFNMSAC_VV_MF4_E16_MASK,
2775 : PseudoVFNMSUB_VFPR16_M1_E16,
2776 : PseudoVFNMSUB_VFPR16_M1_E16_MASK,
2777 : PseudoVFNMSUB_VFPR16_M2_E16,
2778 : PseudoVFNMSUB_VFPR16_M2_E16_MASK,
2779 : PseudoVFNMSUB_VFPR16_M4_E16,
2780 : PseudoVFNMSUB_VFPR16_M4_E16_MASK,
2781 : PseudoVFNMSUB_VFPR16_M8_E16,
2782 : PseudoVFNMSUB_VFPR16_M8_E16_MASK,
2783 : PseudoVFNMSUB_VFPR16_MF2_E16,
2784 : PseudoVFNMSUB_VFPR16_MF2_E16_MASK,
2785 : PseudoVFNMSUB_VFPR16_MF4_E16,
2786 : PseudoVFNMSUB_VFPR16_MF4_E16_MASK,
2787 : PseudoVFNMSUB_VFPR32_M1_E32,
2788 : PseudoVFNMSUB_VFPR32_M1_E32_MASK,
2789 : PseudoVFNMSUB_VFPR32_M2_E32,
2790 : PseudoVFNMSUB_VFPR32_M2_E32_MASK,
2791 : PseudoVFNMSUB_VFPR32_M4_E32,
2792 : PseudoVFNMSUB_VFPR32_M4_E32_MASK,
2793 : PseudoVFNMSUB_VFPR32_M8_E32,
2794 : PseudoVFNMSUB_VFPR32_M8_E32_MASK,
2795 : PseudoVFNMSUB_VFPR32_MF2_E32,
2796 : PseudoVFNMSUB_VFPR32_MF2_E32_MASK,
2797 : PseudoVFNMSUB_VFPR64_M1_E64,
2798 : PseudoVFNMSUB_VFPR64_M1_E64_MASK,
2799 : PseudoVFNMSUB_VFPR64_M2_E64,
2800 : PseudoVFNMSUB_VFPR64_M2_E64_MASK,
2801 : PseudoVFNMSUB_VFPR64_M4_E64,
2802 : PseudoVFNMSUB_VFPR64_M4_E64_MASK,
2803 : PseudoVFNMSUB_VFPR64_M8_E64,
2804 : PseudoVFNMSUB_VFPR64_M8_E64_MASK,
2805 : PseudoVFNMSUB_VV_M1_E16,
2806 : PseudoVFNMSUB_VV_M1_E16_MASK,
2807 : PseudoVFNMSUB_VV_M1_E32,
2808 : PseudoVFNMSUB_VV_M1_E32_MASK,
2809 : PseudoVFNMSUB_VV_M1_E64,
2810 : PseudoVFNMSUB_VV_M1_E64_MASK,
2811 : PseudoVFNMSUB_VV_M2_E16,
2812 : PseudoVFNMSUB_VV_M2_E16_MASK,
2813 : PseudoVFNMSUB_VV_M2_E32,
2814 : PseudoVFNMSUB_VV_M2_E32_MASK,
2815 : PseudoVFNMSUB_VV_M2_E64,
2816 : PseudoVFNMSUB_VV_M2_E64_MASK,
2817 : PseudoVFNMSUB_VV_M4_E16,
2818 : PseudoVFNMSUB_VV_M4_E16_MASK,
2819 : PseudoVFNMSUB_VV_M4_E32,
2820 : PseudoVFNMSUB_VV_M4_E32_MASK,
2821 : PseudoVFNMSUB_VV_M4_E64,
2822 : PseudoVFNMSUB_VV_M4_E64_MASK,
2823 : PseudoVFNMSUB_VV_M8_E16,
2824 : PseudoVFNMSUB_VV_M8_E16_MASK,
2825 : PseudoVFNMSUB_VV_M8_E32,
2826 : PseudoVFNMSUB_VV_M8_E32_MASK,
2827 : PseudoVFNMSUB_VV_M8_E64,
2828 : PseudoVFNMSUB_VV_M8_E64_MASK,
2829 : PseudoVFNMSUB_VV_MF2_E16,
2830 : PseudoVFNMSUB_VV_MF2_E16_MASK,
2831 : PseudoVFNMSUB_VV_MF2_E32,
2832 : PseudoVFNMSUB_VV_MF2_E32_MASK,
2833 : PseudoVFNMSUB_VV_MF4_E16,
2834 : PseudoVFNMSUB_VV_MF4_E16_MASK,
2835 : PseudoVFNRCLIP_XU_F_QF_M1,
2836 : PseudoVFNRCLIP_XU_F_QF_M1_MASK,
2837 : PseudoVFNRCLIP_XU_F_QF_M2,
2838 : PseudoVFNRCLIP_XU_F_QF_M2_MASK,
2839 : PseudoVFNRCLIP_XU_F_QF_MF2,
2840 : PseudoVFNRCLIP_XU_F_QF_MF2_MASK,
2841 : PseudoVFNRCLIP_XU_F_QF_MF4,
2842 : PseudoVFNRCLIP_XU_F_QF_MF4_MASK,
2843 : PseudoVFNRCLIP_XU_F_QF_MF8,
2844 : PseudoVFNRCLIP_XU_F_QF_MF8_MASK,
2845 : PseudoVFNRCLIP_X_F_QF_M1,
2846 : PseudoVFNRCLIP_X_F_QF_M1_MASK,
2847 : PseudoVFNRCLIP_X_F_QF_M2,
2848 : PseudoVFNRCLIP_X_F_QF_M2_MASK,
2849 : PseudoVFNRCLIP_X_F_QF_MF2,
2850 : PseudoVFNRCLIP_X_F_QF_MF2_MASK,
2851 : PseudoVFNRCLIP_X_F_QF_MF4,
2852 : PseudoVFNRCLIP_X_F_QF_MF4_MASK,
2853 : PseudoVFNRCLIP_X_F_QF_MF8,
2854 : PseudoVFNRCLIP_X_F_QF_MF8_MASK,
2855 : PseudoVFRDIV_VFPR16_M1_E16,
2856 : PseudoVFRDIV_VFPR16_M1_E16_MASK,
2857 : PseudoVFRDIV_VFPR16_M2_E16,
2858 : PseudoVFRDIV_VFPR16_M2_E16_MASK,
2859 : PseudoVFRDIV_VFPR16_M4_E16,
2860 : PseudoVFRDIV_VFPR16_M4_E16_MASK,
2861 : PseudoVFRDIV_VFPR16_M8_E16,
2862 : PseudoVFRDIV_VFPR16_M8_E16_MASK,
2863 : PseudoVFRDIV_VFPR16_MF2_E16,
2864 : PseudoVFRDIV_VFPR16_MF2_E16_MASK,
2865 : PseudoVFRDIV_VFPR16_MF4_E16,
2866 : PseudoVFRDIV_VFPR16_MF4_E16_MASK,
2867 : PseudoVFRDIV_VFPR32_M1_E32,
2868 : PseudoVFRDIV_VFPR32_M1_E32_MASK,
2869 : PseudoVFRDIV_VFPR32_M2_E32,
2870 : PseudoVFRDIV_VFPR32_M2_E32_MASK,
2871 : PseudoVFRDIV_VFPR32_M4_E32,
2872 : PseudoVFRDIV_VFPR32_M4_E32_MASK,
2873 : PseudoVFRDIV_VFPR32_M8_E32,
2874 : PseudoVFRDIV_VFPR32_M8_E32_MASK,
2875 : PseudoVFRDIV_VFPR32_MF2_E32,
2876 : PseudoVFRDIV_VFPR32_MF2_E32_MASK,
2877 : PseudoVFRDIV_VFPR64_M1_E64,
2878 : PseudoVFRDIV_VFPR64_M1_E64_MASK,
2879 : PseudoVFRDIV_VFPR64_M2_E64,
2880 : PseudoVFRDIV_VFPR64_M2_E64_MASK,
2881 : PseudoVFRDIV_VFPR64_M4_E64,
2882 : PseudoVFRDIV_VFPR64_M4_E64_MASK,
2883 : PseudoVFRDIV_VFPR64_M8_E64,
2884 : PseudoVFRDIV_VFPR64_M8_E64_MASK,
2885 : PseudoVFREC7_V_M1_E16,
2886 : PseudoVFREC7_V_M1_E16_MASK,
2887 : PseudoVFREC7_V_M1_E32,
2888 : PseudoVFREC7_V_M1_E32_MASK,
2889 : PseudoVFREC7_V_M1_E64,
2890 : PseudoVFREC7_V_M1_E64_MASK,
2891 : PseudoVFREC7_V_M2_E16,
2892 : PseudoVFREC7_V_M2_E16_MASK,
2893 : PseudoVFREC7_V_M2_E32,
2894 : PseudoVFREC7_V_M2_E32_MASK,
2895 : PseudoVFREC7_V_M2_E64,
2896 : PseudoVFREC7_V_M2_E64_MASK,
2897 : PseudoVFREC7_V_M4_E16,
2898 : PseudoVFREC7_V_M4_E16_MASK,
2899 : PseudoVFREC7_V_M4_E32,
2900 : PseudoVFREC7_V_M4_E32_MASK,
2901 : PseudoVFREC7_V_M4_E64,
2902 : PseudoVFREC7_V_M4_E64_MASK,
2903 : PseudoVFREC7_V_M8_E16,
2904 : PseudoVFREC7_V_M8_E16_MASK,
2905 : PseudoVFREC7_V_M8_E32,
2906 : PseudoVFREC7_V_M8_E32_MASK,
2907 : PseudoVFREC7_V_M8_E64,
2908 : PseudoVFREC7_V_M8_E64_MASK,
2909 : PseudoVFREC7_V_MF2_E16,
2910 : PseudoVFREC7_V_MF2_E16_MASK,
2911 : PseudoVFREC7_V_MF2_E32,
2912 : PseudoVFREC7_V_MF2_E32_MASK,
2913 : PseudoVFREC7_V_MF4_E16,
2914 : PseudoVFREC7_V_MF4_E16_MASK,
2915 : PseudoVFREDMAX_VS_M1_E16,
2916 : PseudoVFREDMAX_VS_M1_E16_MASK,
2917 : PseudoVFREDMAX_VS_M1_E32,
2918 : PseudoVFREDMAX_VS_M1_E32_MASK,
2919 : PseudoVFREDMAX_VS_M1_E64,
2920 : PseudoVFREDMAX_VS_M1_E64_MASK,
2921 : PseudoVFREDMAX_VS_M2_E16,
2922 : PseudoVFREDMAX_VS_M2_E16_MASK,
2923 : PseudoVFREDMAX_VS_M2_E32,
2924 : PseudoVFREDMAX_VS_M2_E32_MASK,
2925 : PseudoVFREDMAX_VS_M2_E64,
2926 : PseudoVFREDMAX_VS_M2_E64_MASK,
2927 : PseudoVFREDMAX_VS_M4_E16,
2928 : PseudoVFREDMAX_VS_M4_E16_MASK,
2929 : PseudoVFREDMAX_VS_M4_E32,
2930 : PseudoVFREDMAX_VS_M4_E32_MASK,
2931 : PseudoVFREDMAX_VS_M4_E64,
2932 : PseudoVFREDMAX_VS_M4_E64_MASK,
2933 : PseudoVFREDMAX_VS_M8_E16,
2934 : PseudoVFREDMAX_VS_M8_E16_MASK,
2935 : PseudoVFREDMAX_VS_M8_E32,
2936 : PseudoVFREDMAX_VS_M8_E32_MASK,
2937 : PseudoVFREDMAX_VS_M8_E64,
2938 : PseudoVFREDMAX_VS_M8_E64_MASK,
2939 : PseudoVFREDMAX_VS_MF2_E16,
2940 : PseudoVFREDMAX_VS_MF2_E16_MASK,
2941 : PseudoVFREDMAX_VS_MF2_E32,
2942 : PseudoVFREDMAX_VS_MF2_E32_MASK,
2943 : PseudoVFREDMAX_VS_MF4_E16,
2944 : PseudoVFREDMAX_VS_MF4_E16_MASK,
2945 : PseudoVFREDMIN_VS_M1_E16,
2946 : PseudoVFREDMIN_VS_M1_E16_MASK,
2947 : PseudoVFREDMIN_VS_M1_E32,
2948 : PseudoVFREDMIN_VS_M1_E32_MASK,
2949 : PseudoVFREDMIN_VS_M1_E64,
2950 : PseudoVFREDMIN_VS_M1_E64_MASK,
2951 : PseudoVFREDMIN_VS_M2_E16,
2952 : PseudoVFREDMIN_VS_M2_E16_MASK,
2953 : PseudoVFREDMIN_VS_M2_E32,
2954 : PseudoVFREDMIN_VS_M2_E32_MASK,
2955 : PseudoVFREDMIN_VS_M2_E64,
2956 : PseudoVFREDMIN_VS_M2_E64_MASK,
2957 : PseudoVFREDMIN_VS_M4_E16,
2958 : PseudoVFREDMIN_VS_M4_E16_MASK,
2959 : PseudoVFREDMIN_VS_M4_E32,
2960 : PseudoVFREDMIN_VS_M4_E32_MASK,
2961 : PseudoVFREDMIN_VS_M4_E64,
2962 : PseudoVFREDMIN_VS_M4_E64_MASK,
2963 : PseudoVFREDMIN_VS_M8_E16,
2964 : PseudoVFREDMIN_VS_M8_E16_MASK,
2965 : PseudoVFREDMIN_VS_M8_E32,
2966 : PseudoVFREDMIN_VS_M8_E32_MASK,
2967 : PseudoVFREDMIN_VS_M8_E64,
2968 : PseudoVFREDMIN_VS_M8_E64_MASK,
2969 : PseudoVFREDMIN_VS_MF2_E16,
2970 : PseudoVFREDMIN_VS_MF2_E16_MASK,
2971 : PseudoVFREDMIN_VS_MF2_E32,
2972 : PseudoVFREDMIN_VS_MF2_E32_MASK,
2973 : PseudoVFREDMIN_VS_MF4_E16,
2974 : PseudoVFREDMIN_VS_MF4_E16_MASK,
2975 : PseudoVFREDOSUM_VS_M1_E16,
2976 : PseudoVFREDOSUM_VS_M1_E16_MASK,
2977 : PseudoVFREDOSUM_VS_M1_E32,
2978 : PseudoVFREDOSUM_VS_M1_E32_MASK,
2979 : PseudoVFREDOSUM_VS_M1_E64,
2980 : PseudoVFREDOSUM_VS_M1_E64_MASK,
2981 : PseudoVFREDOSUM_VS_M2_E16,
2982 : PseudoVFREDOSUM_VS_M2_E16_MASK,
2983 : PseudoVFREDOSUM_VS_M2_E32,
2984 : PseudoVFREDOSUM_VS_M2_E32_MASK,
2985 : PseudoVFREDOSUM_VS_M2_E64,
2986 : PseudoVFREDOSUM_VS_M2_E64_MASK,
2987 : PseudoVFREDOSUM_VS_M4_E16,
2988 : PseudoVFREDOSUM_VS_M4_E16_MASK,
2989 : PseudoVFREDOSUM_VS_M4_E32,
2990 : PseudoVFREDOSUM_VS_M4_E32_MASK,
2991 : PseudoVFREDOSUM_VS_M4_E64,
2992 : PseudoVFREDOSUM_VS_M4_E64_MASK,
2993 : PseudoVFREDOSUM_VS_M8_E16,
2994 : PseudoVFREDOSUM_VS_M8_E16_MASK,
2995 : PseudoVFREDOSUM_VS_M8_E32,
2996 : PseudoVFREDOSUM_VS_M8_E32_MASK,
2997 : PseudoVFREDOSUM_VS_M8_E64,
2998 : PseudoVFREDOSUM_VS_M8_E64_MASK,
2999 : PseudoVFREDOSUM_VS_MF2_E16,
3000 : PseudoVFREDOSUM_VS_MF2_E16_MASK,
3001 : PseudoVFREDOSUM_VS_MF2_E32,
3002 : PseudoVFREDOSUM_VS_MF2_E32_MASK,
3003 : PseudoVFREDOSUM_VS_MF4_E16,
3004 : PseudoVFREDOSUM_VS_MF4_E16_MASK,
3005 : PseudoVFREDUSUM_VS_M1_E16,
3006 : PseudoVFREDUSUM_VS_M1_E16_MASK,
3007 : PseudoVFREDUSUM_VS_M1_E32,
3008 : PseudoVFREDUSUM_VS_M1_E32_MASK,
3009 : PseudoVFREDUSUM_VS_M1_E64,
3010 : PseudoVFREDUSUM_VS_M1_E64_MASK,
3011 : PseudoVFREDUSUM_VS_M2_E16,
3012 : PseudoVFREDUSUM_VS_M2_E16_MASK,
3013 : PseudoVFREDUSUM_VS_M2_E32,
3014 : PseudoVFREDUSUM_VS_M2_E32_MASK,
3015 : PseudoVFREDUSUM_VS_M2_E64,
3016 : PseudoVFREDUSUM_VS_M2_E64_MASK,
3017 : PseudoVFREDUSUM_VS_M4_E16,
3018 : PseudoVFREDUSUM_VS_M4_E16_MASK,
3019 : PseudoVFREDUSUM_VS_M4_E32,
3020 : PseudoVFREDUSUM_VS_M4_E32_MASK,
3021 : PseudoVFREDUSUM_VS_M4_E64,
3022 : PseudoVFREDUSUM_VS_M4_E64_MASK,
3023 : PseudoVFREDUSUM_VS_M8_E16,
3024 : PseudoVFREDUSUM_VS_M8_E16_MASK,
3025 : PseudoVFREDUSUM_VS_M8_E32,
3026 : PseudoVFREDUSUM_VS_M8_E32_MASK,
3027 : PseudoVFREDUSUM_VS_M8_E64,
3028 : PseudoVFREDUSUM_VS_M8_E64_MASK,
3029 : PseudoVFREDUSUM_VS_MF2_E16,
3030 : PseudoVFREDUSUM_VS_MF2_E16_MASK,
3031 : PseudoVFREDUSUM_VS_MF2_E32,
3032 : PseudoVFREDUSUM_VS_MF2_E32_MASK,
3033 : PseudoVFREDUSUM_VS_MF4_E16,
3034 : PseudoVFREDUSUM_VS_MF4_E16_MASK,
3035 : PseudoVFROUND_NOEXCEPT_V_M1_MASK,
3036 : PseudoVFROUND_NOEXCEPT_V_M2_MASK,
3037 : PseudoVFROUND_NOEXCEPT_V_M4_MASK,
3038 : PseudoVFROUND_NOEXCEPT_V_M8_MASK,
3039 : PseudoVFROUND_NOEXCEPT_V_MF2_MASK,
3040 : PseudoVFROUND_NOEXCEPT_V_MF4_MASK,
3041 : PseudoVFRSQRT7_V_M1_E16,
3042 : PseudoVFRSQRT7_V_M1_E16_MASK,
3043 : PseudoVFRSQRT7_V_M1_E32,
3044 : PseudoVFRSQRT7_V_M1_E32_MASK,
3045 : PseudoVFRSQRT7_V_M1_E64,
3046 : PseudoVFRSQRT7_V_M1_E64_MASK,
3047 : PseudoVFRSQRT7_V_M2_E16,
3048 : PseudoVFRSQRT7_V_M2_E16_MASK,
3049 : PseudoVFRSQRT7_V_M2_E32,
3050 : PseudoVFRSQRT7_V_M2_E32_MASK,
3051 : PseudoVFRSQRT7_V_M2_E64,
3052 : PseudoVFRSQRT7_V_M2_E64_MASK,
3053 : PseudoVFRSQRT7_V_M4_E16,
3054 : PseudoVFRSQRT7_V_M4_E16_MASK,
3055 : PseudoVFRSQRT7_V_M4_E32,
3056 : PseudoVFRSQRT7_V_M4_E32_MASK,
3057 : PseudoVFRSQRT7_V_M4_E64,
3058 : PseudoVFRSQRT7_V_M4_E64_MASK,
3059 : PseudoVFRSQRT7_V_M8_E16,
3060 : PseudoVFRSQRT7_V_M8_E16_MASK,
3061 : PseudoVFRSQRT7_V_M8_E32,
3062 : PseudoVFRSQRT7_V_M8_E32_MASK,
3063 : PseudoVFRSQRT7_V_M8_E64,
3064 : PseudoVFRSQRT7_V_M8_E64_MASK,
3065 : PseudoVFRSQRT7_V_MF2_E16,
3066 : PseudoVFRSQRT7_V_MF2_E16_MASK,
3067 : PseudoVFRSQRT7_V_MF2_E32,
3068 : PseudoVFRSQRT7_V_MF2_E32_MASK,
3069 : PseudoVFRSQRT7_V_MF4_E16,
3070 : PseudoVFRSQRT7_V_MF4_E16_MASK,
3071 : PseudoVFRSUB_VFPR16_M1_E16,
3072 : PseudoVFRSUB_VFPR16_M1_E16_MASK,
3073 : PseudoVFRSUB_VFPR16_M2_E16,
3074 : PseudoVFRSUB_VFPR16_M2_E16_MASK,
3075 : PseudoVFRSUB_VFPR16_M4_E16,
3076 : PseudoVFRSUB_VFPR16_M4_E16_MASK,
3077 : PseudoVFRSUB_VFPR16_M8_E16,
3078 : PseudoVFRSUB_VFPR16_M8_E16_MASK,
3079 : PseudoVFRSUB_VFPR16_MF2_E16,
3080 : PseudoVFRSUB_VFPR16_MF2_E16_MASK,
3081 : PseudoVFRSUB_VFPR16_MF4_E16,
3082 : PseudoVFRSUB_VFPR16_MF4_E16_MASK,
3083 : PseudoVFRSUB_VFPR32_M1_E32,
3084 : PseudoVFRSUB_VFPR32_M1_E32_MASK,
3085 : PseudoVFRSUB_VFPR32_M2_E32,
3086 : PseudoVFRSUB_VFPR32_M2_E32_MASK,
3087 : PseudoVFRSUB_VFPR32_M4_E32,
3088 : PseudoVFRSUB_VFPR32_M4_E32_MASK,
3089 : PseudoVFRSUB_VFPR32_M8_E32,
3090 : PseudoVFRSUB_VFPR32_M8_E32_MASK,
3091 : PseudoVFRSUB_VFPR32_MF2_E32,
3092 : PseudoVFRSUB_VFPR32_MF2_E32_MASK,
3093 : PseudoVFRSUB_VFPR64_M1_E64,
3094 : PseudoVFRSUB_VFPR64_M1_E64_MASK,
3095 : PseudoVFRSUB_VFPR64_M2_E64,
3096 : PseudoVFRSUB_VFPR64_M2_E64_MASK,
3097 : PseudoVFRSUB_VFPR64_M4_E64,
3098 : PseudoVFRSUB_VFPR64_M4_E64_MASK,
3099 : PseudoVFRSUB_VFPR64_M8_E64,
3100 : PseudoVFRSUB_VFPR64_M8_E64_MASK,
3101 : PseudoVFSGNJN_VFPR16_M1_E16,
3102 : PseudoVFSGNJN_VFPR16_M1_E16_MASK,
3103 : PseudoVFSGNJN_VFPR16_M2_E16,
3104 : PseudoVFSGNJN_VFPR16_M2_E16_MASK,
3105 : PseudoVFSGNJN_VFPR16_M4_E16,
3106 : PseudoVFSGNJN_VFPR16_M4_E16_MASK,
3107 : PseudoVFSGNJN_VFPR16_M8_E16,
3108 : PseudoVFSGNJN_VFPR16_M8_E16_MASK,
3109 : PseudoVFSGNJN_VFPR16_MF2_E16,
3110 : PseudoVFSGNJN_VFPR16_MF2_E16_MASK,
3111 : PseudoVFSGNJN_VFPR16_MF4_E16,
3112 : PseudoVFSGNJN_VFPR16_MF4_E16_MASK,
3113 : PseudoVFSGNJN_VFPR32_M1_E32,
3114 : PseudoVFSGNJN_VFPR32_M1_E32_MASK,
3115 : PseudoVFSGNJN_VFPR32_M2_E32,
3116 : PseudoVFSGNJN_VFPR32_M2_E32_MASK,
3117 : PseudoVFSGNJN_VFPR32_M4_E32,
3118 : PseudoVFSGNJN_VFPR32_M4_E32_MASK,
3119 : PseudoVFSGNJN_VFPR32_M8_E32,
3120 : PseudoVFSGNJN_VFPR32_M8_E32_MASK,
3121 : PseudoVFSGNJN_VFPR32_MF2_E32,
3122 : PseudoVFSGNJN_VFPR32_MF2_E32_MASK,
3123 : PseudoVFSGNJN_VFPR64_M1_E64,
3124 : PseudoVFSGNJN_VFPR64_M1_E64_MASK,
3125 : PseudoVFSGNJN_VFPR64_M2_E64,
3126 : PseudoVFSGNJN_VFPR64_M2_E64_MASK,
3127 : PseudoVFSGNJN_VFPR64_M4_E64,
3128 : PseudoVFSGNJN_VFPR64_M4_E64_MASK,
3129 : PseudoVFSGNJN_VFPR64_M8_E64,
3130 : PseudoVFSGNJN_VFPR64_M8_E64_MASK,
3131 : PseudoVFSGNJN_VV_M1_E16,
3132 : PseudoVFSGNJN_VV_M1_E16_MASK,
3133 : PseudoVFSGNJN_VV_M1_E32,
3134 : PseudoVFSGNJN_VV_M1_E32_MASK,
3135 : PseudoVFSGNJN_VV_M1_E64,
3136 : PseudoVFSGNJN_VV_M1_E64_MASK,
3137 : PseudoVFSGNJN_VV_M2_E16,
3138 : PseudoVFSGNJN_VV_M2_E16_MASK,
3139 : PseudoVFSGNJN_VV_M2_E32,
3140 : PseudoVFSGNJN_VV_M2_E32_MASK,
3141 : PseudoVFSGNJN_VV_M2_E64,
3142 : PseudoVFSGNJN_VV_M2_E64_MASK,
3143 : PseudoVFSGNJN_VV_M4_E16,
3144 : PseudoVFSGNJN_VV_M4_E16_MASK,
3145 : PseudoVFSGNJN_VV_M4_E32,
3146 : PseudoVFSGNJN_VV_M4_E32_MASK,
3147 : PseudoVFSGNJN_VV_M4_E64,
3148 : PseudoVFSGNJN_VV_M4_E64_MASK,
3149 : PseudoVFSGNJN_VV_M8_E16,
3150 : PseudoVFSGNJN_VV_M8_E16_MASK,
3151 : PseudoVFSGNJN_VV_M8_E32,
3152 : PseudoVFSGNJN_VV_M8_E32_MASK,
3153 : PseudoVFSGNJN_VV_M8_E64,
3154 : PseudoVFSGNJN_VV_M8_E64_MASK,
3155 : PseudoVFSGNJN_VV_MF2_E16,
3156 : PseudoVFSGNJN_VV_MF2_E16_MASK,
3157 : PseudoVFSGNJN_VV_MF2_E32,
3158 : PseudoVFSGNJN_VV_MF2_E32_MASK,
3159 : PseudoVFSGNJN_VV_MF4_E16,
3160 : PseudoVFSGNJN_VV_MF4_E16_MASK,
3161 : PseudoVFSGNJX_VFPR16_M1_E16,
3162 : PseudoVFSGNJX_VFPR16_M1_E16_MASK,
3163 : PseudoVFSGNJX_VFPR16_M2_E16,
3164 : PseudoVFSGNJX_VFPR16_M2_E16_MASK,
3165 : PseudoVFSGNJX_VFPR16_M4_E16,
3166 : PseudoVFSGNJX_VFPR16_M4_E16_MASK,
3167 : PseudoVFSGNJX_VFPR16_M8_E16,
3168 : PseudoVFSGNJX_VFPR16_M8_E16_MASK,
3169 : PseudoVFSGNJX_VFPR16_MF2_E16,
3170 : PseudoVFSGNJX_VFPR16_MF2_E16_MASK,
3171 : PseudoVFSGNJX_VFPR16_MF4_E16,
3172 : PseudoVFSGNJX_VFPR16_MF4_E16_MASK,
3173 : PseudoVFSGNJX_VFPR32_M1_E32,
3174 : PseudoVFSGNJX_VFPR32_M1_E32_MASK,
3175 : PseudoVFSGNJX_VFPR32_M2_E32,
3176 : PseudoVFSGNJX_VFPR32_M2_E32_MASK,
3177 : PseudoVFSGNJX_VFPR32_M4_E32,
3178 : PseudoVFSGNJX_VFPR32_M4_E32_MASK,
3179 : PseudoVFSGNJX_VFPR32_M8_E32,
3180 : PseudoVFSGNJX_VFPR32_M8_E32_MASK,
3181 : PseudoVFSGNJX_VFPR32_MF2_E32,
3182 : PseudoVFSGNJX_VFPR32_MF2_E32_MASK,
3183 : PseudoVFSGNJX_VFPR64_M1_E64,
3184 : PseudoVFSGNJX_VFPR64_M1_E64_MASK,
3185 : PseudoVFSGNJX_VFPR64_M2_E64,
3186 : PseudoVFSGNJX_VFPR64_M2_E64_MASK,
3187 : PseudoVFSGNJX_VFPR64_M4_E64,
3188 : PseudoVFSGNJX_VFPR64_M4_E64_MASK,
3189 : PseudoVFSGNJX_VFPR64_M8_E64,
3190 : PseudoVFSGNJX_VFPR64_M8_E64_MASK,
3191 : PseudoVFSGNJX_VV_M1_E16,
3192 : PseudoVFSGNJX_VV_M1_E16_MASK,
3193 : PseudoVFSGNJX_VV_M1_E32,
3194 : PseudoVFSGNJX_VV_M1_E32_MASK,
3195 : PseudoVFSGNJX_VV_M1_E64,
3196 : PseudoVFSGNJX_VV_M1_E64_MASK,
3197 : PseudoVFSGNJX_VV_M2_E16,
3198 : PseudoVFSGNJX_VV_M2_E16_MASK,
3199 : PseudoVFSGNJX_VV_M2_E32,
3200 : PseudoVFSGNJX_VV_M2_E32_MASK,
3201 : PseudoVFSGNJX_VV_M2_E64,
3202 : PseudoVFSGNJX_VV_M2_E64_MASK,
3203 : PseudoVFSGNJX_VV_M4_E16,
3204 : PseudoVFSGNJX_VV_M4_E16_MASK,
3205 : PseudoVFSGNJX_VV_M4_E32,
3206 : PseudoVFSGNJX_VV_M4_E32_MASK,
3207 : PseudoVFSGNJX_VV_M4_E64,
3208 : PseudoVFSGNJX_VV_M4_E64_MASK,
3209 : PseudoVFSGNJX_VV_M8_E16,
3210 : PseudoVFSGNJX_VV_M8_E16_MASK,
3211 : PseudoVFSGNJX_VV_M8_E32,
3212 : PseudoVFSGNJX_VV_M8_E32_MASK,
3213 : PseudoVFSGNJX_VV_M8_E64,
3214 : PseudoVFSGNJX_VV_M8_E64_MASK,
3215 : PseudoVFSGNJX_VV_MF2_E16,
3216 : PseudoVFSGNJX_VV_MF2_E16_MASK,
3217 : PseudoVFSGNJX_VV_MF2_E32,
3218 : PseudoVFSGNJX_VV_MF2_E32_MASK,
3219 : PseudoVFSGNJX_VV_MF4_E16,
3220 : PseudoVFSGNJX_VV_MF4_E16_MASK,
3221 : PseudoVFSGNJ_VFPR16_M1_E16,
3222 : PseudoVFSGNJ_VFPR16_M1_E16_MASK,
3223 : PseudoVFSGNJ_VFPR16_M2_E16,
3224 : PseudoVFSGNJ_VFPR16_M2_E16_MASK,
3225 : PseudoVFSGNJ_VFPR16_M4_E16,
3226 : PseudoVFSGNJ_VFPR16_M4_E16_MASK,
3227 : PseudoVFSGNJ_VFPR16_M8_E16,
3228 : PseudoVFSGNJ_VFPR16_M8_E16_MASK,
3229 : PseudoVFSGNJ_VFPR16_MF2_E16,
3230 : PseudoVFSGNJ_VFPR16_MF2_E16_MASK,
3231 : PseudoVFSGNJ_VFPR16_MF4_E16,
3232 : PseudoVFSGNJ_VFPR16_MF4_E16_MASK,
3233 : PseudoVFSGNJ_VFPR32_M1_E32,
3234 : PseudoVFSGNJ_VFPR32_M1_E32_MASK,
3235 : PseudoVFSGNJ_VFPR32_M2_E32,
3236 : PseudoVFSGNJ_VFPR32_M2_E32_MASK,
3237 : PseudoVFSGNJ_VFPR32_M4_E32,
3238 : PseudoVFSGNJ_VFPR32_M4_E32_MASK,
3239 : PseudoVFSGNJ_VFPR32_M8_E32,
3240 : PseudoVFSGNJ_VFPR32_M8_E32_MASK,
3241 : PseudoVFSGNJ_VFPR32_MF2_E32,
3242 : PseudoVFSGNJ_VFPR32_MF2_E32_MASK,
3243 : PseudoVFSGNJ_VFPR64_M1_E64,
3244 : PseudoVFSGNJ_VFPR64_M1_E64_MASK,
3245 : PseudoVFSGNJ_VFPR64_M2_E64,
3246 : PseudoVFSGNJ_VFPR64_M2_E64_MASK,
3247 : PseudoVFSGNJ_VFPR64_M4_E64,
3248 : PseudoVFSGNJ_VFPR64_M4_E64_MASK,
3249 : PseudoVFSGNJ_VFPR64_M8_E64,
3250 : PseudoVFSGNJ_VFPR64_M8_E64_MASK,
3251 : PseudoVFSGNJ_VV_M1_E16,
3252 : PseudoVFSGNJ_VV_M1_E16_MASK,
3253 : PseudoVFSGNJ_VV_M1_E32,
3254 : PseudoVFSGNJ_VV_M1_E32_MASK,
3255 : PseudoVFSGNJ_VV_M1_E64,
3256 : PseudoVFSGNJ_VV_M1_E64_MASK,
3257 : PseudoVFSGNJ_VV_M2_E16,
3258 : PseudoVFSGNJ_VV_M2_E16_MASK,
3259 : PseudoVFSGNJ_VV_M2_E32,
3260 : PseudoVFSGNJ_VV_M2_E32_MASK,
3261 : PseudoVFSGNJ_VV_M2_E64,
3262 : PseudoVFSGNJ_VV_M2_E64_MASK,
3263 : PseudoVFSGNJ_VV_M4_E16,
3264 : PseudoVFSGNJ_VV_M4_E16_MASK,
3265 : PseudoVFSGNJ_VV_M4_E32,
3266 : PseudoVFSGNJ_VV_M4_E32_MASK,
3267 : PseudoVFSGNJ_VV_M4_E64,
3268 : PseudoVFSGNJ_VV_M4_E64_MASK,
3269 : PseudoVFSGNJ_VV_M8_E16,
3270 : PseudoVFSGNJ_VV_M8_E16_MASK,
3271 : PseudoVFSGNJ_VV_M8_E32,
3272 : PseudoVFSGNJ_VV_M8_E32_MASK,
3273 : PseudoVFSGNJ_VV_M8_E64,
3274 : PseudoVFSGNJ_VV_M8_E64_MASK,
3275 : PseudoVFSGNJ_VV_MF2_E16,
3276 : PseudoVFSGNJ_VV_MF2_E16_MASK,
3277 : PseudoVFSGNJ_VV_MF2_E32,
3278 : PseudoVFSGNJ_VV_MF2_E32_MASK,
3279 : PseudoVFSGNJ_VV_MF4_E16,
3280 : PseudoVFSGNJ_VV_MF4_E16_MASK,
3281 : PseudoVFSLIDE1DOWN_VFPR16_M1,
3282 : PseudoVFSLIDE1DOWN_VFPR16_M1_MASK,
3283 : PseudoVFSLIDE1DOWN_VFPR16_M2,
3284 : PseudoVFSLIDE1DOWN_VFPR16_M2_MASK,
3285 : PseudoVFSLIDE1DOWN_VFPR16_M4,
3286 : PseudoVFSLIDE1DOWN_VFPR16_M4_MASK,
3287 : PseudoVFSLIDE1DOWN_VFPR16_M8,
3288 : PseudoVFSLIDE1DOWN_VFPR16_M8_MASK,
3289 : PseudoVFSLIDE1DOWN_VFPR16_MF2,
3290 : PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK,
3291 : PseudoVFSLIDE1DOWN_VFPR16_MF4,
3292 : PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK,
3293 : PseudoVFSLIDE1DOWN_VFPR32_M1,
3294 : PseudoVFSLIDE1DOWN_VFPR32_M1_MASK,
3295 : PseudoVFSLIDE1DOWN_VFPR32_M2,
3296 : PseudoVFSLIDE1DOWN_VFPR32_M2_MASK,
3297 : PseudoVFSLIDE1DOWN_VFPR32_M4,
3298 : PseudoVFSLIDE1DOWN_VFPR32_M4_MASK,
3299 : PseudoVFSLIDE1DOWN_VFPR32_M8,
3300 : PseudoVFSLIDE1DOWN_VFPR32_M8_MASK,
3301 : PseudoVFSLIDE1DOWN_VFPR32_MF2,
3302 : PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK,
3303 : PseudoVFSLIDE1DOWN_VFPR64_M1,
3304 : PseudoVFSLIDE1DOWN_VFPR64_M1_MASK,
3305 : PseudoVFSLIDE1DOWN_VFPR64_M2,
3306 : PseudoVFSLIDE1DOWN_VFPR64_M2_MASK,
3307 : PseudoVFSLIDE1DOWN_VFPR64_M4,
3308 : PseudoVFSLIDE1DOWN_VFPR64_M4_MASK,
3309 : PseudoVFSLIDE1DOWN_VFPR64_M8,
3310 : PseudoVFSLIDE1DOWN_VFPR64_M8_MASK,
3311 : PseudoVFSLIDE1UP_VFPR16_M1,
3312 : PseudoVFSLIDE1UP_VFPR16_M1_MASK,
3313 : PseudoVFSLIDE1UP_VFPR16_M2,
3314 : PseudoVFSLIDE1UP_VFPR16_M2_MASK,
3315 : PseudoVFSLIDE1UP_VFPR16_M4,
3316 : PseudoVFSLIDE1UP_VFPR16_M4_MASK,
3317 : PseudoVFSLIDE1UP_VFPR16_M8,
3318 : PseudoVFSLIDE1UP_VFPR16_M8_MASK,
3319 : PseudoVFSLIDE1UP_VFPR16_MF2,
3320 : PseudoVFSLIDE1UP_VFPR16_MF2_MASK,
3321 : PseudoVFSLIDE1UP_VFPR16_MF4,
3322 : PseudoVFSLIDE1UP_VFPR16_MF4_MASK,
3323 : PseudoVFSLIDE1UP_VFPR32_M1,
3324 : PseudoVFSLIDE1UP_VFPR32_M1_MASK,
3325 : PseudoVFSLIDE1UP_VFPR32_M2,
3326 : PseudoVFSLIDE1UP_VFPR32_M2_MASK,
3327 : PseudoVFSLIDE1UP_VFPR32_M4,
3328 : PseudoVFSLIDE1UP_VFPR32_M4_MASK,
3329 : PseudoVFSLIDE1UP_VFPR32_M8,
3330 : PseudoVFSLIDE1UP_VFPR32_M8_MASK,
3331 : PseudoVFSLIDE1UP_VFPR32_MF2,
3332 : PseudoVFSLIDE1UP_VFPR32_MF2_MASK,
3333 : PseudoVFSLIDE1UP_VFPR64_M1,
3334 : PseudoVFSLIDE1UP_VFPR64_M1_MASK,
3335 : PseudoVFSLIDE1UP_VFPR64_M2,
3336 : PseudoVFSLIDE1UP_VFPR64_M2_MASK,
3337 : PseudoVFSLIDE1UP_VFPR64_M4,
3338 : PseudoVFSLIDE1UP_VFPR64_M4_MASK,
3339 : PseudoVFSLIDE1UP_VFPR64_M8,
3340 : PseudoVFSLIDE1UP_VFPR64_M8_MASK,
3341 : PseudoVFSQRT_V_M1_E16,
3342 : PseudoVFSQRT_V_M1_E16_MASK,
3343 : PseudoVFSQRT_V_M1_E32,
3344 : PseudoVFSQRT_V_M1_E32_MASK,
3345 : PseudoVFSQRT_V_M1_E64,
3346 : PseudoVFSQRT_V_M1_E64_MASK,
3347 : PseudoVFSQRT_V_M2_E16,
3348 : PseudoVFSQRT_V_M2_E16_MASK,
3349 : PseudoVFSQRT_V_M2_E32,
3350 : PseudoVFSQRT_V_M2_E32_MASK,
3351 : PseudoVFSQRT_V_M2_E64,
3352 : PseudoVFSQRT_V_M2_E64_MASK,
3353 : PseudoVFSQRT_V_M4_E16,
3354 : PseudoVFSQRT_V_M4_E16_MASK,
3355 : PseudoVFSQRT_V_M4_E32,
3356 : PseudoVFSQRT_V_M4_E32_MASK,
3357 : PseudoVFSQRT_V_M4_E64,
3358 : PseudoVFSQRT_V_M4_E64_MASK,
3359 : PseudoVFSQRT_V_M8_E16,
3360 : PseudoVFSQRT_V_M8_E16_MASK,
3361 : PseudoVFSQRT_V_M8_E32,
3362 : PseudoVFSQRT_V_M8_E32_MASK,
3363 : PseudoVFSQRT_V_M8_E64,
3364 : PseudoVFSQRT_V_M8_E64_MASK,
3365 : PseudoVFSQRT_V_MF2_E16,
3366 : PseudoVFSQRT_V_MF2_E16_MASK,
3367 : PseudoVFSQRT_V_MF2_E32,
3368 : PseudoVFSQRT_V_MF2_E32_MASK,
3369 : PseudoVFSQRT_V_MF4_E16,
3370 : PseudoVFSQRT_V_MF4_E16_MASK,
3371 : PseudoVFSUB_VFPR16_M1_E16,
3372 : PseudoVFSUB_VFPR16_M1_E16_MASK,
3373 : PseudoVFSUB_VFPR16_M2_E16,
3374 : PseudoVFSUB_VFPR16_M2_E16_MASK,
3375 : PseudoVFSUB_VFPR16_M4_E16,
3376 : PseudoVFSUB_VFPR16_M4_E16_MASK,
3377 : PseudoVFSUB_VFPR16_M8_E16,
3378 : PseudoVFSUB_VFPR16_M8_E16_MASK,
3379 : PseudoVFSUB_VFPR16_MF2_E16,
3380 : PseudoVFSUB_VFPR16_MF2_E16_MASK,
3381 : PseudoVFSUB_VFPR16_MF4_E16,
3382 : PseudoVFSUB_VFPR16_MF4_E16_MASK,
3383 : PseudoVFSUB_VFPR32_M1_E32,
3384 : PseudoVFSUB_VFPR32_M1_E32_MASK,
3385 : PseudoVFSUB_VFPR32_M2_E32,
3386 : PseudoVFSUB_VFPR32_M2_E32_MASK,
3387 : PseudoVFSUB_VFPR32_M4_E32,
3388 : PseudoVFSUB_VFPR32_M4_E32_MASK,
3389 : PseudoVFSUB_VFPR32_M8_E32,
3390 : PseudoVFSUB_VFPR32_M8_E32_MASK,
3391 : PseudoVFSUB_VFPR32_MF2_E32,
3392 : PseudoVFSUB_VFPR32_MF2_E32_MASK,
3393 : PseudoVFSUB_VFPR64_M1_E64,
3394 : PseudoVFSUB_VFPR64_M1_E64_MASK,
3395 : PseudoVFSUB_VFPR64_M2_E64,
3396 : PseudoVFSUB_VFPR64_M2_E64_MASK,
3397 : PseudoVFSUB_VFPR64_M4_E64,
3398 : PseudoVFSUB_VFPR64_M4_E64_MASK,
3399 : PseudoVFSUB_VFPR64_M8_E64,
3400 : PseudoVFSUB_VFPR64_M8_E64_MASK,
3401 : PseudoVFSUB_VV_M1_E16,
3402 : PseudoVFSUB_VV_M1_E16_MASK,
3403 : PseudoVFSUB_VV_M1_E32,
3404 : PseudoVFSUB_VV_M1_E32_MASK,
3405 : PseudoVFSUB_VV_M1_E64,
3406 : PseudoVFSUB_VV_M1_E64_MASK,
3407 : PseudoVFSUB_VV_M2_E16,
3408 : PseudoVFSUB_VV_M2_E16_MASK,
3409 : PseudoVFSUB_VV_M2_E32,
3410 : PseudoVFSUB_VV_M2_E32_MASK,
3411 : PseudoVFSUB_VV_M2_E64,
3412 : PseudoVFSUB_VV_M2_E64_MASK,
3413 : PseudoVFSUB_VV_M4_E16,
3414 : PseudoVFSUB_VV_M4_E16_MASK,
3415 : PseudoVFSUB_VV_M4_E32,
3416 : PseudoVFSUB_VV_M4_E32_MASK,
3417 : PseudoVFSUB_VV_M4_E64,
3418 : PseudoVFSUB_VV_M4_E64_MASK,
3419 : PseudoVFSUB_VV_M8_E16,
3420 : PseudoVFSUB_VV_M8_E16_MASK,
3421 : PseudoVFSUB_VV_M8_E32,
3422 : PseudoVFSUB_VV_M8_E32_MASK,
3423 : PseudoVFSUB_VV_M8_E64,
3424 : PseudoVFSUB_VV_M8_E64_MASK,
3425 : PseudoVFSUB_VV_MF2_E16,
3426 : PseudoVFSUB_VV_MF2_E16_MASK,
3427 : PseudoVFSUB_VV_MF2_E32,
3428 : PseudoVFSUB_VV_MF2_E32_MASK,
3429 : PseudoVFSUB_VV_MF4_E16,
3430 : PseudoVFSUB_VV_MF4_E16_MASK,
3431 : PseudoVFWADD_VFPR16_M1_E16,
3432 : PseudoVFWADD_VFPR16_M1_E16_MASK,
3433 : PseudoVFWADD_VFPR16_M2_E16,
3434 : PseudoVFWADD_VFPR16_M2_E16_MASK,
3435 : PseudoVFWADD_VFPR16_M4_E16,
3436 : PseudoVFWADD_VFPR16_M4_E16_MASK,
3437 : PseudoVFWADD_VFPR16_MF2_E16,
3438 : PseudoVFWADD_VFPR16_MF2_E16_MASK,
3439 : PseudoVFWADD_VFPR16_MF4_E16,
3440 : PseudoVFWADD_VFPR16_MF4_E16_MASK,
3441 : PseudoVFWADD_VFPR32_M1_E32,
3442 : PseudoVFWADD_VFPR32_M1_E32_MASK,
3443 : PseudoVFWADD_VFPR32_M2_E32,
3444 : PseudoVFWADD_VFPR32_M2_E32_MASK,
3445 : PseudoVFWADD_VFPR32_M4_E32,
3446 : PseudoVFWADD_VFPR32_M4_E32_MASK,
3447 : PseudoVFWADD_VFPR32_MF2_E32,
3448 : PseudoVFWADD_VFPR32_MF2_E32_MASK,
3449 : PseudoVFWADD_VV_M1_E16,
3450 : PseudoVFWADD_VV_M1_E16_MASK,
3451 : PseudoVFWADD_VV_M1_E32,
3452 : PseudoVFWADD_VV_M1_E32_MASK,
3453 : PseudoVFWADD_VV_M2_E16,
3454 : PseudoVFWADD_VV_M2_E16_MASK,
3455 : PseudoVFWADD_VV_M2_E32,
3456 : PseudoVFWADD_VV_M2_E32_MASK,
3457 : PseudoVFWADD_VV_M4_E16,
3458 : PseudoVFWADD_VV_M4_E16_MASK,
3459 : PseudoVFWADD_VV_M4_E32,
3460 : PseudoVFWADD_VV_M4_E32_MASK,
3461 : PseudoVFWADD_VV_MF2_E16,
3462 : PseudoVFWADD_VV_MF2_E16_MASK,
3463 : PseudoVFWADD_VV_MF2_E32,
3464 : PseudoVFWADD_VV_MF2_E32_MASK,
3465 : PseudoVFWADD_VV_MF4_E16,
3466 : PseudoVFWADD_VV_MF4_E16_MASK,
3467 : PseudoVFWADD_WFPR16_M1_E16,
3468 : PseudoVFWADD_WFPR16_M1_E16_MASK,
3469 : PseudoVFWADD_WFPR16_M2_E16,
3470 : PseudoVFWADD_WFPR16_M2_E16_MASK,
3471 : PseudoVFWADD_WFPR16_M4_E16,
3472 : PseudoVFWADD_WFPR16_M4_E16_MASK,
3473 : PseudoVFWADD_WFPR16_MF2_E16,
3474 : PseudoVFWADD_WFPR16_MF2_E16_MASK,
3475 : PseudoVFWADD_WFPR16_MF4_E16,
3476 : PseudoVFWADD_WFPR16_MF4_E16_MASK,
3477 : PseudoVFWADD_WFPR32_M1_E32,
3478 : PseudoVFWADD_WFPR32_M1_E32_MASK,
3479 : PseudoVFWADD_WFPR32_M2_E32,
3480 : PseudoVFWADD_WFPR32_M2_E32_MASK,
3481 : PseudoVFWADD_WFPR32_M4_E32,
3482 : PseudoVFWADD_WFPR32_M4_E32_MASK,
3483 : PseudoVFWADD_WFPR32_MF2_E32,
3484 : PseudoVFWADD_WFPR32_MF2_E32_MASK,
3485 : PseudoVFWADD_WV_M1_E16,
3486 : PseudoVFWADD_WV_M1_E16_MASK,
3487 : PseudoVFWADD_WV_M1_E16_MASK_TIED,
3488 : PseudoVFWADD_WV_M1_E16_TIED,
3489 : PseudoVFWADD_WV_M1_E32,
3490 : PseudoVFWADD_WV_M1_E32_MASK,
3491 : PseudoVFWADD_WV_M1_E32_MASK_TIED,
3492 : PseudoVFWADD_WV_M1_E32_TIED,
3493 : PseudoVFWADD_WV_M2_E16,
3494 : PseudoVFWADD_WV_M2_E16_MASK,
3495 : PseudoVFWADD_WV_M2_E16_MASK_TIED,
3496 : PseudoVFWADD_WV_M2_E16_TIED,
3497 : PseudoVFWADD_WV_M2_E32,
3498 : PseudoVFWADD_WV_M2_E32_MASK,
3499 : PseudoVFWADD_WV_M2_E32_MASK_TIED,
3500 : PseudoVFWADD_WV_M2_E32_TIED,
3501 : PseudoVFWADD_WV_M4_E16,
3502 : PseudoVFWADD_WV_M4_E16_MASK,
3503 : PseudoVFWADD_WV_M4_E16_MASK_TIED,
3504 : PseudoVFWADD_WV_M4_E16_TIED,
3505 : PseudoVFWADD_WV_M4_E32,
3506 : PseudoVFWADD_WV_M4_E32_MASK,
3507 : PseudoVFWADD_WV_M4_E32_MASK_TIED,
3508 : PseudoVFWADD_WV_M4_E32_TIED,
3509 : PseudoVFWADD_WV_MF2_E16,
3510 : PseudoVFWADD_WV_MF2_E16_MASK,
3511 : PseudoVFWADD_WV_MF2_E16_MASK_TIED,
3512 : PseudoVFWADD_WV_MF2_E16_TIED,
3513 : PseudoVFWADD_WV_MF2_E32,
3514 : PseudoVFWADD_WV_MF2_E32_MASK,
3515 : PseudoVFWADD_WV_MF2_E32_MASK_TIED,
3516 : PseudoVFWADD_WV_MF2_E32_TIED,
3517 : PseudoVFWADD_WV_MF4_E16,
3518 : PseudoVFWADD_WV_MF4_E16_MASK,
3519 : PseudoVFWADD_WV_MF4_E16_MASK_TIED,
3520 : PseudoVFWADD_WV_MF4_E16_TIED,
3521 : PseudoVFWCVTBF16_F_F_V_M1_E16,
3522 : PseudoVFWCVTBF16_F_F_V_M1_E16_MASK,
3523 : PseudoVFWCVTBF16_F_F_V_M1_E32,
3524 : PseudoVFWCVTBF16_F_F_V_M1_E32_MASK,
3525 : PseudoVFWCVTBF16_F_F_V_M2_E16,
3526 : PseudoVFWCVTBF16_F_F_V_M2_E16_MASK,
3527 : PseudoVFWCVTBF16_F_F_V_M2_E32,
3528 : PseudoVFWCVTBF16_F_F_V_M2_E32_MASK,
3529 : PseudoVFWCVTBF16_F_F_V_M4_E16,
3530 : PseudoVFWCVTBF16_F_F_V_M4_E16_MASK,
3531 : PseudoVFWCVTBF16_F_F_V_M4_E32,
3532 : PseudoVFWCVTBF16_F_F_V_M4_E32_MASK,
3533 : PseudoVFWCVTBF16_F_F_V_MF2_E16,
3534 : PseudoVFWCVTBF16_F_F_V_MF2_E16_MASK,
3535 : PseudoVFWCVTBF16_F_F_V_MF2_E32,
3536 : PseudoVFWCVTBF16_F_F_V_MF2_E32_MASK,
3537 : PseudoVFWCVTBF16_F_F_V_MF4_E16,
3538 : PseudoVFWCVTBF16_F_F_V_MF4_E16_MASK,
3539 : PseudoVFWCVT_F_F_V_M1_E16,
3540 : PseudoVFWCVT_F_F_V_M1_E16_MASK,
3541 : PseudoVFWCVT_F_F_V_M1_E32,
3542 : PseudoVFWCVT_F_F_V_M1_E32_MASK,
3543 : PseudoVFWCVT_F_F_V_M2_E16,
3544 : PseudoVFWCVT_F_F_V_M2_E16_MASK,
3545 : PseudoVFWCVT_F_F_V_M2_E32,
3546 : PseudoVFWCVT_F_F_V_M2_E32_MASK,
3547 : PseudoVFWCVT_F_F_V_M4_E16,
3548 : PseudoVFWCVT_F_F_V_M4_E16_MASK,
3549 : PseudoVFWCVT_F_F_V_M4_E32,
3550 : PseudoVFWCVT_F_F_V_M4_E32_MASK,
3551 : PseudoVFWCVT_F_F_V_MF2_E16,
3552 : PseudoVFWCVT_F_F_V_MF2_E16_MASK,
3553 : PseudoVFWCVT_F_F_V_MF2_E32,
3554 : PseudoVFWCVT_F_F_V_MF2_E32_MASK,
3555 : PseudoVFWCVT_F_F_V_MF4_E16,
3556 : PseudoVFWCVT_F_F_V_MF4_E16_MASK,
3557 : PseudoVFWCVT_F_XU_V_M1_E16,
3558 : PseudoVFWCVT_F_XU_V_M1_E16_MASK,
3559 : PseudoVFWCVT_F_XU_V_M1_E32,
3560 : PseudoVFWCVT_F_XU_V_M1_E32_MASK,
3561 : PseudoVFWCVT_F_XU_V_M1_E8,
3562 : PseudoVFWCVT_F_XU_V_M1_E8_MASK,
3563 : PseudoVFWCVT_F_XU_V_M2_E16,
3564 : PseudoVFWCVT_F_XU_V_M2_E16_MASK,
3565 : PseudoVFWCVT_F_XU_V_M2_E32,
3566 : PseudoVFWCVT_F_XU_V_M2_E32_MASK,
3567 : PseudoVFWCVT_F_XU_V_M2_E8,
3568 : PseudoVFWCVT_F_XU_V_M2_E8_MASK,
3569 : PseudoVFWCVT_F_XU_V_M4_E16,
3570 : PseudoVFWCVT_F_XU_V_M4_E16_MASK,
3571 : PseudoVFWCVT_F_XU_V_M4_E32,
3572 : PseudoVFWCVT_F_XU_V_M4_E32_MASK,
3573 : PseudoVFWCVT_F_XU_V_M4_E8,
3574 : PseudoVFWCVT_F_XU_V_M4_E8_MASK,
3575 : PseudoVFWCVT_F_XU_V_MF2_E16,
3576 : PseudoVFWCVT_F_XU_V_MF2_E16_MASK,
3577 : PseudoVFWCVT_F_XU_V_MF2_E32,
3578 : PseudoVFWCVT_F_XU_V_MF2_E32_MASK,
3579 : PseudoVFWCVT_F_XU_V_MF2_E8,
3580 : PseudoVFWCVT_F_XU_V_MF2_E8_MASK,
3581 : PseudoVFWCVT_F_XU_V_MF4_E16,
3582 : PseudoVFWCVT_F_XU_V_MF4_E16_MASK,
3583 : PseudoVFWCVT_F_XU_V_MF4_E8,
3584 : PseudoVFWCVT_F_XU_V_MF4_E8_MASK,
3585 : PseudoVFWCVT_F_XU_V_MF8_E8,
3586 : PseudoVFWCVT_F_XU_V_MF8_E8_MASK,
3587 : PseudoVFWCVT_F_X_V_M1_E16,
3588 : PseudoVFWCVT_F_X_V_M1_E16_MASK,
3589 : PseudoVFWCVT_F_X_V_M1_E32,
3590 : PseudoVFWCVT_F_X_V_M1_E32_MASK,
3591 : PseudoVFWCVT_F_X_V_M1_E8,
3592 : PseudoVFWCVT_F_X_V_M1_E8_MASK,
3593 : PseudoVFWCVT_F_X_V_M2_E16,
3594 : PseudoVFWCVT_F_X_V_M2_E16_MASK,
3595 : PseudoVFWCVT_F_X_V_M2_E32,
3596 : PseudoVFWCVT_F_X_V_M2_E32_MASK,
3597 : PseudoVFWCVT_F_X_V_M2_E8,
3598 : PseudoVFWCVT_F_X_V_M2_E8_MASK,
3599 : PseudoVFWCVT_F_X_V_M4_E16,
3600 : PseudoVFWCVT_F_X_V_M4_E16_MASK,
3601 : PseudoVFWCVT_F_X_V_M4_E32,
3602 : PseudoVFWCVT_F_X_V_M4_E32_MASK,
3603 : PseudoVFWCVT_F_X_V_M4_E8,
3604 : PseudoVFWCVT_F_X_V_M4_E8_MASK,
3605 : PseudoVFWCVT_F_X_V_MF2_E16,
3606 : PseudoVFWCVT_F_X_V_MF2_E16_MASK,
3607 : PseudoVFWCVT_F_X_V_MF2_E32,
3608 : PseudoVFWCVT_F_X_V_MF2_E32_MASK,
3609 : PseudoVFWCVT_F_X_V_MF2_E8,
3610 : PseudoVFWCVT_F_X_V_MF2_E8_MASK,
3611 : PseudoVFWCVT_F_X_V_MF4_E16,
3612 : PseudoVFWCVT_F_X_V_MF4_E16_MASK,
3613 : PseudoVFWCVT_F_X_V_MF4_E8,
3614 : PseudoVFWCVT_F_X_V_MF4_E8_MASK,
3615 : PseudoVFWCVT_F_X_V_MF8_E8,
3616 : PseudoVFWCVT_F_X_V_MF8_E8_MASK,
3617 : PseudoVFWCVT_RM_XU_F_V_M1,
3618 : PseudoVFWCVT_RM_XU_F_V_M1_MASK,
3619 : PseudoVFWCVT_RM_XU_F_V_M2,
3620 : PseudoVFWCVT_RM_XU_F_V_M2_MASK,
3621 : PseudoVFWCVT_RM_XU_F_V_M4,
3622 : PseudoVFWCVT_RM_XU_F_V_M4_MASK,
3623 : PseudoVFWCVT_RM_XU_F_V_MF2,
3624 : PseudoVFWCVT_RM_XU_F_V_MF2_MASK,
3625 : PseudoVFWCVT_RM_XU_F_V_MF4,
3626 : PseudoVFWCVT_RM_XU_F_V_MF4_MASK,
3627 : PseudoVFWCVT_RM_X_F_V_M1,
3628 : PseudoVFWCVT_RM_X_F_V_M1_MASK,
3629 : PseudoVFWCVT_RM_X_F_V_M2,
3630 : PseudoVFWCVT_RM_X_F_V_M2_MASK,
3631 : PseudoVFWCVT_RM_X_F_V_M4,
3632 : PseudoVFWCVT_RM_X_F_V_M4_MASK,
3633 : PseudoVFWCVT_RM_X_F_V_MF2,
3634 : PseudoVFWCVT_RM_X_F_V_MF2_MASK,
3635 : PseudoVFWCVT_RM_X_F_V_MF4,
3636 : PseudoVFWCVT_RM_X_F_V_MF4_MASK,
3637 : PseudoVFWCVT_RTZ_XU_F_V_M1,
3638 : PseudoVFWCVT_RTZ_XU_F_V_M1_MASK,
3639 : PseudoVFWCVT_RTZ_XU_F_V_M2,
3640 : PseudoVFWCVT_RTZ_XU_F_V_M2_MASK,
3641 : PseudoVFWCVT_RTZ_XU_F_V_M4,
3642 : PseudoVFWCVT_RTZ_XU_F_V_M4_MASK,
3643 : PseudoVFWCVT_RTZ_XU_F_V_MF2,
3644 : PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK,
3645 : PseudoVFWCVT_RTZ_XU_F_V_MF4,
3646 : PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK,
3647 : PseudoVFWCVT_RTZ_X_F_V_M1,
3648 : PseudoVFWCVT_RTZ_X_F_V_M1_MASK,
3649 : PseudoVFWCVT_RTZ_X_F_V_M2,
3650 : PseudoVFWCVT_RTZ_X_F_V_M2_MASK,
3651 : PseudoVFWCVT_RTZ_X_F_V_M4,
3652 : PseudoVFWCVT_RTZ_X_F_V_M4_MASK,
3653 : PseudoVFWCVT_RTZ_X_F_V_MF2,
3654 : PseudoVFWCVT_RTZ_X_F_V_MF2_MASK,
3655 : PseudoVFWCVT_RTZ_X_F_V_MF4,
3656 : PseudoVFWCVT_RTZ_X_F_V_MF4_MASK,
3657 : PseudoVFWCVT_XU_F_V_M1,
3658 : PseudoVFWCVT_XU_F_V_M1_MASK,
3659 : PseudoVFWCVT_XU_F_V_M2,
3660 : PseudoVFWCVT_XU_F_V_M2_MASK,
3661 : PseudoVFWCVT_XU_F_V_M4,
3662 : PseudoVFWCVT_XU_F_V_M4_MASK,
3663 : PseudoVFWCVT_XU_F_V_MF2,
3664 : PseudoVFWCVT_XU_F_V_MF2_MASK,
3665 : PseudoVFWCVT_XU_F_V_MF4,
3666 : PseudoVFWCVT_XU_F_V_MF4_MASK,
3667 : PseudoVFWCVT_X_F_V_M1,
3668 : PseudoVFWCVT_X_F_V_M1_MASK,
3669 : PseudoVFWCVT_X_F_V_M2,
3670 : PseudoVFWCVT_X_F_V_M2_MASK,
3671 : PseudoVFWCVT_X_F_V_M4,
3672 : PseudoVFWCVT_X_F_V_M4_MASK,
3673 : PseudoVFWCVT_X_F_V_MF2,
3674 : PseudoVFWCVT_X_F_V_MF2_MASK,
3675 : PseudoVFWCVT_X_F_V_MF4,
3676 : PseudoVFWCVT_X_F_V_MF4_MASK,
3677 : PseudoVFWMACCBF16_VFPR16_M1_E16,
3678 : PseudoVFWMACCBF16_VFPR16_M1_E16_MASK,
3679 : PseudoVFWMACCBF16_VFPR16_M2_E16,
3680 : PseudoVFWMACCBF16_VFPR16_M2_E16_MASK,
3681 : PseudoVFWMACCBF16_VFPR16_M4_E16,
3682 : PseudoVFWMACCBF16_VFPR16_M4_E16_MASK,
3683 : PseudoVFWMACCBF16_VFPR16_MF2_E16,
3684 : PseudoVFWMACCBF16_VFPR16_MF2_E16_MASK,
3685 : PseudoVFWMACCBF16_VFPR16_MF4_E16,
3686 : PseudoVFWMACCBF16_VFPR16_MF4_E16_MASK,
3687 : PseudoVFWMACCBF16_VV_M1_E16,
3688 : PseudoVFWMACCBF16_VV_M1_E16_MASK,
3689 : PseudoVFWMACCBF16_VV_M1_E32,
3690 : PseudoVFWMACCBF16_VV_M1_E32_MASK,
3691 : PseudoVFWMACCBF16_VV_M2_E16,
3692 : PseudoVFWMACCBF16_VV_M2_E16_MASK,
3693 : PseudoVFWMACCBF16_VV_M2_E32,
3694 : PseudoVFWMACCBF16_VV_M2_E32_MASK,
3695 : PseudoVFWMACCBF16_VV_M4_E16,
3696 : PseudoVFWMACCBF16_VV_M4_E16_MASK,
3697 : PseudoVFWMACCBF16_VV_M4_E32,
3698 : PseudoVFWMACCBF16_VV_M4_E32_MASK,
3699 : PseudoVFWMACCBF16_VV_MF2_E16,
3700 : PseudoVFWMACCBF16_VV_MF2_E16_MASK,
3701 : PseudoVFWMACCBF16_VV_MF2_E32,
3702 : PseudoVFWMACCBF16_VV_MF2_E32_MASK,
3703 : PseudoVFWMACCBF16_VV_MF4_E16,
3704 : PseudoVFWMACCBF16_VV_MF4_E16_MASK,
3705 : PseudoVFWMACC_4x4x4_M1,
3706 : PseudoVFWMACC_4x4x4_M2,
3707 : PseudoVFWMACC_4x4x4_M4,
3708 : PseudoVFWMACC_4x4x4_M8,
3709 : PseudoVFWMACC_4x4x4_MF2,
3710 : PseudoVFWMACC_4x4x4_MF4,
3711 : PseudoVFWMACC_VFPR16_M1_E16,
3712 : PseudoVFWMACC_VFPR16_M1_E16_MASK,
3713 : PseudoVFWMACC_VFPR16_M2_E16,
3714 : PseudoVFWMACC_VFPR16_M2_E16_MASK,
3715 : PseudoVFWMACC_VFPR16_M4_E16,
3716 : PseudoVFWMACC_VFPR16_M4_E16_MASK,
3717 : PseudoVFWMACC_VFPR16_MF2_E16,
3718 : PseudoVFWMACC_VFPR16_MF2_E16_MASK,
3719 : PseudoVFWMACC_VFPR16_MF4_E16,
3720 : PseudoVFWMACC_VFPR16_MF4_E16_MASK,
3721 : PseudoVFWMACC_VFPR32_M1_E32,
3722 : PseudoVFWMACC_VFPR32_M1_E32_MASK,
3723 : PseudoVFWMACC_VFPR32_M2_E32,
3724 : PseudoVFWMACC_VFPR32_M2_E32_MASK,
3725 : PseudoVFWMACC_VFPR32_M4_E32,
3726 : PseudoVFWMACC_VFPR32_M4_E32_MASK,
3727 : PseudoVFWMACC_VFPR32_MF2_E32,
3728 : PseudoVFWMACC_VFPR32_MF2_E32_MASK,
3729 : PseudoVFWMACC_VV_M1_E16,
3730 : PseudoVFWMACC_VV_M1_E16_MASK,
3731 : PseudoVFWMACC_VV_M1_E32,
3732 : PseudoVFWMACC_VV_M1_E32_MASK,
3733 : PseudoVFWMACC_VV_M2_E16,
3734 : PseudoVFWMACC_VV_M2_E16_MASK,
3735 : PseudoVFWMACC_VV_M2_E32,
3736 : PseudoVFWMACC_VV_M2_E32_MASK,
3737 : PseudoVFWMACC_VV_M4_E16,
3738 : PseudoVFWMACC_VV_M4_E16_MASK,
3739 : PseudoVFWMACC_VV_M4_E32,
3740 : PseudoVFWMACC_VV_M4_E32_MASK,
3741 : PseudoVFWMACC_VV_MF2_E16,
3742 : PseudoVFWMACC_VV_MF2_E16_MASK,
3743 : PseudoVFWMACC_VV_MF2_E32,
3744 : PseudoVFWMACC_VV_MF2_E32_MASK,
3745 : PseudoVFWMACC_VV_MF4_E16,
3746 : PseudoVFWMACC_VV_MF4_E16_MASK,
3747 : PseudoVFWMSAC_VFPR16_M1_E16,
3748 : PseudoVFWMSAC_VFPR16_M1_E16_MASK,
3749 : PseudoVFWMSAC_VFPR16_M2_E16,
3750 : PseudoVFWMSAC_VFPR16_M2_E16_MASK,
3751 : PseudoVFWMSAC_VFPR16_M4_E16,
3752 : PseudoVFWMSAC_VFPR16_M4_E16_MASK,
3753 : PseudoVFWMSAC_VFPR16_MF2_E16,
3754 : PseudoVFWMSAC_VFPR16_MF2_E16_MASK,
3755 : PseudoVFWMSAC_VFPR16_MF4_E16,
3756 : PseudoVFWMSAC_VFPR16_MF4_E16_MASK,
3757 : PseudoVFWMSAC_VFPR32_M1_E32,
3758 : PseudoVFWMSAC_VFPR32_M1_E32_MASK,
3759 : PseudoVFWMSAC_VFPR32_M2_E32,
3760 : PseudoVFWMSAC_VFPR32_M2_E32_MASK,
3761 : PseudoVFWMSAC_VFPR32_M4_E32,
3762 : PseudoVFWMSAC_VFPR32_M4_E32_MASK,
3763 : PseudoVFWMSAC_VFPR32_MF2_E32,
3764 : PseudoVFWMSAC_VFPR32_MF2_E32_MASK,
3765 : PseudoVFWMSAC_VV_M1_E16,
3766 : PseudoVFWMSAC_VV_M1_E16_MASK,
3767 : PseudoVFWMSAC_VV_M1_E32,
3768 : PseudoVFWMSAC_VV_M1_E32_MASK,
3769 : PseudoVFWMSAC_VV_M2_E16,
3770 : PseudoVFWMSAC_VV_M2_E16_MASK,
3771 : PseudoVFWMSAC_VV_M2_E32,
3772 : PseudoVFWMSAC_VV_M2_E32_MASK,
3773 : PseudoVFWMSAC_VV_M4_E16,
3774 : PseudoVFWMSAC_VV_M4_E16_MASK,
3775 : PseudoVFWMSAC_VV_M4_E32,
3776 : PseudoVFWMSAC_VV_M4_E32_MASK,
3777 : PseudoVFWMSAC_VV_MF2_E16,
3778 : PseudoVFWMSAC_VV_MF2_E16_MASK,
3779 : PseudoVFWMSAC_VV_MF2_E32,
3780 : PseudoVFWMSAC_VV_MF2_E32_MASK,
3781 : PseudoVFWMSAC_VV_MF4_E16,
3782 : PseudoVFWMSAC_VV_MF4_E16_MASK,
3783 : PseudoVFWMUL_VFPR16_M1_E16,
3784 : PseudoVFWMUL_VFPR16_M1_E16_MASK,
3785 : PseudoVFWMUL_VFPR16_M2_E16,
3786 : PseudoVFWMUL_VFPR16_M2_E16_MASK,
3787 : PseudoVFWMUL_VFPR16_M4_E16,
3788 : PseudoVFWMUL_VFPR16_M4_E16_MASK,
3789 : PseudoVFWMUL_VFPR16_MF2_E16,
3790 : PseudoVFWMUL_VFPR16_MF2_E16_MASK,
3791 : PseudoVFWMUL_VFPR16_MF4_E16,
3792 : PseudoVFWMUL_VFPR16_MF4_E16_MASK,
3793 : PseudoVFWMUL_VFPR32_M1_E32,
3794 : PseudoVFWMUL_VFPR32_M1_E32_MASK,
3795 : PseudoVFWMUL_VFPR32_M2_E32,
3796 : PseudoVFWMUL_VFPR32_M2_E32_MASK,
3797 : PseudoVFWMUL_VFPR32_M4_E32,
3798 : PseudoVFWMUL_VFPR32_M4_E32_MASK,
3799 : PseudoVFWMUL_VFPR32_MF2_E32,
3800 : PseudoVFWMUL_VFPR32_MF2_E32_MASK,
3801 : PseudoVFWMUL_VV_M1_E16,
3802 : PseudoVFWMUL_VV_M1_E16_MASK,
3803 : PseudoVFWMUL_VV_M1_E32,
3804 : PseudoVFWMUL_VV_M1_E32_MASK,
3805 : PseudoVFWMUL_VV_M2_E16,
3806 : PseudoVFWMUL_VV_M2_E16_MASK,
3807 : PseudoVFWMUL_VV_M2_E32,
3808 : PseudoVFWMUL_VV_M2_E32_MASK,
3809 : PseudoVFWMUL_VV_M4_E16,
3810 : PseudoVFWMUL_VV_M4_E16_MASK,
3811 : PseudoVFWMUL_VV_M4_E32,
3812 : PseudoVFWMUL_VV_M4_E32_MASK,
3813 : PseudoVFWMUL_VV_MF2_E16,
3814 : PseudoVFWMUL_VV_MF2_E16_MASK,
3815 : PseudoVFWMUL_VV_MF2_E32,
3816 : PseudoVFWMUL_VV_MF2_E32_MASK,
3817 : PseudoVFWMUL_VV_MF4_E16,
3818 : PseudoVFWMUL_VV_MF4_E16_MASK,
3819 : PseudoVFWNMACC_VFPR16_M1_E16,
3820 : PseudoVFWNMACC_VFPR16_M1_E16_MASK,
3821 : PseudoVFWNMACC_VFPR16_M2_E16,
3822 : PseudoVFWNMACC_VFPR16_M2_E16_MASK,
3823 : PseudoVFWNMACC_VFPR16_M4_E16,
3824 : PseudoVFWNMACC_VFPR16_M4_E16_MASK,
3825 : PseudoVFWNMACC_VFPR16_MF2_E16,
3826 : PseudoVFWNMACC_VFPR16_MF2_E16_MASK,
3827 : PseudoVFWNMACC_VFPR16_MF4_E16,
3828 : PseudoVFWNMACC_VFPR16_MF4_E16_MASK,
3829 : PseudoVFWNMACC_VFPR32_M1_E32,
3830 : PseudoVFWNMACC_VFPR32_M1_E32_MASK,
3831 : PseudoVFWNMACC_VFPR32_M2_E32,
3832 : PseudoVFWNMACC_VFPR32_M2_E32_MASK,
3833 : PseudoVFWNMACC_VFPR32_M4_E32,
3834 : PseudoVFWNMACC_VFPR32_M4_E32_MASK,
3835 : PseudoVFWNMACC_VFPR32_MF2_E32,
3836 : PseudoVFWNMACC_VFPR32_MF2_E32_MASK,
3837 : PseudoVFWNMACC_VV_M1_E16,
3838 : PseudoVFWNMACC_VV_M1_E16_MASK,
3839 : PseudoVFWNMACC_VV_M1_E32,
3840 : PseudoVFWNMACC_VV_M1_E32_MASK,
3841 : PseudoVFWNMACC_VV_M2_E16,
3842 : PseudoVFWNMACC_VV_M2_E16_MASK,
3843 : PseudoVFWNMACC_VV_M2_E32,
3844 : PseudoVFWNMACC_VV_M2_E32_MASK,
3845 : PseudoVFWNMACC_VV_M4_E16,
3846 : PseudoVFWNMACC_VV_M4_E16_MASK,
3847 : PseudoVFWNMACC_VV_M4_E32,
3848 : PseudoVFWNMACC_VV_M4_E32_MASK,
3849 : PseudoVFWNMACC_VV_MF2_E16,
3850 : PseudoVFWNMACC_VV_MF2_E16_MASK,
3851 : PseudoVFWNMACC_VV_MF2_E32,
3852 : PseudoVFWNMACC_VV_MF2_E32_MASK,
3853 : PseudoVFWNMACC_VV_MF4_E16,
3854 : PseudoVFWNMACC_VV_MF4_E16_MASK,
3855 : PseudoVFWNMSAC_VFPR16_M1_E16,
3856 : PseudoVFWNMSAC_VFPR16_M1_E16_MASK,
3857 : PseudoVFWNMSAC_VFPR16_M2_E16,
3858 : PseudoVFWNMSAC_VFPR16_M2_E16_MASK,
3859 : PseudoVFWNMSAC_VFPR16_M4_E16,
3860 : PseudoVFWNMSAC_VFPR16_M4_E16_MASK,
3861 : PseudoVFWNMSAC_VFPR16_MF2_E16,
3862 : PseudoVFWNMSAC_VFPR16_MF2_E16_MASK,
3863 : PseudoVFWNMSAC_VFPR16_MF4_E16,
3864 : PseudoVFWNMSAC_VFPR16_MF4_E16_MASK,
3865 : PseudoVFWNMSAC_VFPR32_M1_E32,
3866 : PseudoVFWNMSAC_VFPR32_M1_E32_MASK,
3867 : PseudoVFWNMSAC_VFPR32_M2_E32,
3868 : PseudoVFWNMSAC_VFPR32_M2_E32_MASK,
3869 : PseudoVFWNMSAC_VFPR32_M4_E32,
3870 : PseudoVFWNMSAC_VFPR32_M4_E32_MASK,
3871 : PseudoVFWNMSAC_VFPR32_MF2_E32,
3872 : PseudoVFWNMSAC_VFPR32_MF2_E32_MASK,
3873 : PseudoVFWNMSAC_VV_M1_E16,
3874 : PseudoVFWNMSAC_VV_M1_E16_MASK,
3875 : PseudoVFWNMSAC_VV_M1_E32,
3876 : PseudoVFWNMSAC_VV_M1_E32_MASK,
3877 : PseudoVFWNMSAC_VV_M2_E16,
3878 : PseudoVFWNMSAC_VV_M2_E16_MASK,
3879 : PseudoVFWNMSAC_VV_M2_E32,
3880 : PseudoVFWNMSAC_VV_M2_E32_MASK,
3881 : PseudoVFWNMSAC_VV_M4_E16,
3882 : PseudoVFWNMSAC_VV_M4_E16_MASK,
3883 : PseudoVFWNMSAC_VV_M4_E32,
3884 : PseudoVFWNMSAC_VV_M4_E32_MASK,
3885 : PseudoVFWNMSAC_VV_MF2_E16,
3886 : PseudoVFWNMSAC_VV_MF2_E16_MASK,
3887 : PseudoVFWNMSAC_VV_MF2_E32,
3888 : PseudoVFWNMSAC_VV_MF2_E32_MASK,
3889 : PseudoVFWNMSAC_VV_MF4_E16,
3890 : PseudoVFWNMSAC_VV_MF4_E16_MASK,
3891 : PseudoVFWREDOSUM_VS_M1_E16,
3892 : PseudoVFWREDOSUM_VS_M1_E16_MASK,
3893 : PseudoVFWREDOSUM_VS_M1_E32,
3894 : PseudoVFWREDOSUM_VS_M1_E32_MASK,
3895 : PseudoVFWREDOSUM_VS_M2_E16,
3896 : PseudoVFWREDOSUM_VS_M2_E16_MASK,
3897 : PseudoVFWREDOSUM_VS_M2_E32,
3898 : PseudoVFWREDOSUM_VS_M2_E32_MASK,
3899 : PseudoVFWREDOSUM_VS_M4_E16,
3900 : PseudoVFWREDOSUM_VS_M4_E16_MASK,
3901 : PseudoVFWREDOSUM_VS_M4_E32,
3902 : PseudoVFWREDOSUM_VS_M4_E32_MASK,
3903 : PseudoVFWREDOSUM_VS_M8_E16,
3904 : PseudoVFWREDOSUM_VS_M8_E16_MASK,
3905 : PseudoVFWREDOSUM_VS_M8_E32,
3906 : PseudoVFWREDOSUM_VS_M8_E32_MASK,
3907 : PseudoVFWREDOSUM_VS_MF2_E16,
3908 : PseudoVFWREDOSUM_VS_MF2_E16_MASK,
3909 : PseudoVFWREDOSUM_VS_MF2_E32,
3910 : PseudoVFWREDOSUM_VS_MF2_E32_MASK,
3911 : PseudoVFWREDOSUM_VS_MF4_E16,
3912 : PseudoVFWREDOSUM_VS_MF4_E16_MASK,
3913 : PseudoVFWREDUSUM_VS_M1_E16,
3914 : PseudoVFWREDUSUM_VS_M1_E16_MASK,
3915 : PseudoVFWREDUSUM_VS_M1_E32,
3916 : PseudoVFWREDUSUM_VS_M1_E32_MASK,
3917 : PseudoVFWREDUSUM_VS_M2_E16,
3918 : PseudoVFWREDUSUM_VS_M2_E16_MASK,
3919 : PseudoVFWREDUSUM_VS_M2_E32,
3920 : PseudoVFWREDUSUM_VS_M2_E32_MASK,
3921 : PseudoVFWREDUSUM_VS_M4_E16,
3922 : PseudoVFWREDUSUM_VS_M4_E16_MASK,
3923 : PseudoVFWREDUSUM_VS_M4_E32,
3924 : PseudoVFWREDUSUM_VS_M4_E32_MASK,
3925 : PseudoVFWREDUSUM_VS_M8_E16,
3926 : PseudoVFWREDUSUM_VS_M8_E16_MASK,
3927 : PseudoVFWREDUSUM_VS_M8_E32,
3928 : PseudoVFWREDUSUM_VS_M8_E32_MASK,
3929 : PseudoVFWREDUSUM_VS_MF2_E16,
3930 : PseudoVFWREDUSUM_VS_MF2_E16_MASK,
3931 : PseudoVFWREDUSUM_VS_MF2_E32,
3932 : PseudoVFWREDUSUM_VS_MF2_E32_MASK,
3933 : PseudoVFWREDUSUM_VS_MF4_E16,
3934 : PseudoVFWREDUSUM_VS_MF4_E16_MASK,
3935 : PseudoVFWSUB_VFPR16_M1_E16,
3936 : PseudoVFWSUB_VFPR16_M1_E16_MASK,
3937 : PseudoVFWSUB_VFPR16_M2_E16,
3938 : PseudoVFWSUB_VFPR16_M2_E16_MASK,
3939 : PseudoVFWSUB_VFPR16_M4_E16,
3940 : PseudoVFWSUB_VFPR16_M4_E16_MASK,
3941 : PseudoVFWSUB_VFPR16_MF2_E16,
3942 : PseudoVFWSUB_VFPR16_MF2_E16_MASK,
3943 : PseudoVFWSUB_VFPR16_MF4_E16,
3944 : PseudoVFWSUB_VFPR16_MF4_E16_MASK,
3945 : PseudoVFWSUB_VFPR32_M1_E32,
3946 : PseudoVFWSUB_VFPR32_M1_E32_MASK,
3947 : PseudoVFWSUB_VFPR32_M2_E32,
3948 : PseudoVFWSUB_VFPR32_M2_E32_MASK,
3949 : PseudoVFWSUB_VFPR32_M4_E32,
3950 : PseudoVFWSUB_VFPR32_M4_E32_MASK,
3951 : PseudoVFWSUB_VFPR32_MF2_E32,
3952 : PseudoVFWSUB_VFPR32_MF2_E32_MASK,
3953 : PseudoVFWSUB_VV_M1_E16,
3954 : PseudoVFWSUB_VV_M1_E16_MASK,
3955 : PseudoVFWSUB_VV_M1_E32,
3956 : PseudoVFWSUB_VV_M1_E32_MASK,
3957 : PseudoVFWSUB_VV_M2_E16,
3958 : PseudoVFWSUB_VV_M2_E16_MASK,
3959 : PseudoVFWSUB_VV_M2_E32,
3960 : PseudoVFWSUB_VV_M2_E32_MASK,
3961 : PseudoVFWSUB_VV_M4_E16,
3962 : PseudoVFWSUB_VV_M4_E16_MASK,
3963 : PseudoVFWSUB_VV_M4_E32,
3964 : PseudoVFWSUB_VV_M4_E32_MASK,
3965 : PseudoVFWSUB_VV_MF2_E16,
3966 : PseudoVFWSUB_VV_MF2_E16_MASK,
3967 : PseudoVFWSUB_VV_MF2_E32,
3968 : PseudoVFWSUB_VV_MF2_E32_MASK,
3969 : PseudoVFWSUB_VV_MF4_E16,
3970 : PseudoVFWSUB_VV_MF4_E16_MASK,
3971 : PseudoVFWSUB_WFPR16_M1_E16,
3972 : PseudoVFWSUB_WFPR16_M1_E16_MASK,
3973 : PseudoVFWSUB_WFPR16_M2_E16,
3974 : PseudoVFWSUB_WFPR16_M2_E16_MASK,
3975 : PseudoVFWSUB_WFPR16_M4_E16,
3976 : PseudoVFWSUB_WFPR16_M4_E16_MASK,
3977 : PseudoVFWSUB_WFPR16_MF2_E16,
3978 : PseudoVFWSUB_WFPR16_MF2_E16_MASK,
3979 : PseudoVFWSUB_WFPR16_MF4_E16,
3980 : PseudoVFWSUB_WFPR16_MF4_E16_MASK,
3981 : PseudoVFWSUB_WFPR32_M1_E32,
3982 : PseudoVFWSUB_WFPR32_M1_E32_MASK,
3983 : PseudoVFWSUB_WFPR32_M2_E32,
3984 : PseudoVFWSUB_WFPR32_M2_E32_MASK,
3985 : PseudoVFWSUB_WFPR32_M4_E32,
3986 : PseudoVFWSUB_WFPR32_M4_E32_MASK,
3987 : PseudoVFWSUB_WFPR32_MF2_E32,
3988 : PseudoVFWSUB_WFPR32_MF2_E32_MASK,
3989 : PseudoVFWSUB_WV_M1_E16,
3990 : PseudoVFWSUB_WV_M1_E16_MASK,
3991 : PseudoVFWSUB_WV_M1_E16_MASK_TIED,
3992 : PseudoVFWSUB_WV_M1_E16_TIED,
3993 : PseudoVFWSUB_WV_M1_E32,
3994 : PseudoVFWSUB_WV_M1_E32_MASK,
3995 : PseudoVFWSUB_WV_M1_E32_MASK_TIED,
3996 : PseudoVFWSUB_WV_M1_E32_TIED,
3997 : PseudoVFWSUB_WV_M2_E16,
3998 : PseudoVFWSUB_WV_M2_E16_MASK,
3999 : PseudoVFWSUB_WV_M2_E16_MASK_TIED,
4000 : PseudoVFWSUB_WV_M2_E16_TIED,
4001 : PseudoVFWSUB_WV_M2_E32,
4002 : PseudoVFWSUB_WV_M2_E32_MASK,
4003 : PseudoVFWSUB_WV_M2_E32_MASK_TIED,
4004 : PseudoVFWSUB_WV_M2_E32_TIED,
4005 : PseudoVFWSUB_WV_M4_E16,
4006 : PseudoVFWSUB_WV_M4_E16_MASK,
4007 : PseudoVFWSUB_WV_M4_E16_MASK_TIED,
4008 : PseudoVFWSUB_WV_M4_E16_TIED,
4009 : PseudoVFWSUB_WV_M4_E32,
4010 : PseudoVFWSUB_WV_M4_E32_MASK,
4011 : PseudoVFWSUB_WV_M4_E32_MASK_TIED,
4012 : PseudoVFWSUB_WV_M4_E32_TIED,
4013 : PseudoVFWSUB_WV_MF2_E16,
4014 : PseudoVFWSUB_WV_MF2_E16_MASK,
4015 : PseudoVFWSUB_WV_MF2_E16_MASK_TIED,
4016 : PseudoVFWSUB_WV_MF2_E16_TIED,
4017 : PseudoVFWSUB_WV_MF2_E32,
4018 : PseudoVFWSUB_WV_MF2_E32_MASK,
4019 : PseudoVFWSUB_WV_MF2_E32_MASK_TIED,
4020 : PseudoVFWSUB_WV_MF2_E32_TIED,
4021 : PseudoVFWSUB_WV_MF4_E16,
4022 : PseudoVFWSUB_WV_MF4_E16_MASK,
4023 : PseudoVFWSUB_WV_MF4_E16_MASK_TIED,
4024 : PseudoVFWSUB_WV_MF4_E16_TIED,
4025 : PseudoVGHSH_VV_M1,
4026 : PseudoVGHSH_VV_M2,
4027 : PseudoVGHSH_VV_M4,
4028 : PseudoVGHSH_VV_M8,
4029 : PseudoVGHSH_VV_MF2,
4030 : PseudoVGMUL_VV_M1,
4031 : PseudoVGMUL_VV_M2,
4032 : PseudoVGMUL_VV_M4,
4033 : PseudoVGMUL_VV_M8,
4034 : PseudoVGMUL_VV_MF2,
4035 : PseudoVID_V_M1,
4036 : PseudoVID_V_M1_MASK,
4037 : PseudoVID_V_M2,
4038 : PseudoVID_V_M2_MASK,
4039 : PseudoVID_V_M4,
4040 : PseudoVID_V_M4_MASK,
4041 : PseudoVID_V_M8,
4042 : PseudoVID_V_M8_MASK,
4043 : PseudoVID_V_MF2,
4044 : PseudoVID_V_MF2_MASK,
4045 : PseudoVID_V_MF4,
4046 : PseudoVID_V_MF4_MASK,
4047 : PseudoVID_V_MF8,
4048 : PseudoVID_V_MF8_MASK,
4049 : PseudoVIOTA_M_M1,
4050 : PseudoVIOTA_M_M1_MASK,
4051 : PseudoVIOTA_M_M2,
4052 : PseudoVIOTA_M_M2_MASK,
4053 : PseudoVIOTA_M_M4,
4054 : PseudoVIOTA_M_M4_MASK,
4055 : PseudoVIOTA_M_M8,
4056 : PseudoVIOTA_M_M8_MASK,
4057 : PseudoVIOTA_M_MF2,
4058 : PseudoVIOTA_M_MF2_MASK,
4059 : PseudoVIOTA_M_MF4,
4060 : PseudoVIOTA_M_MF4_MASK,
4061 : PseudoVIOTA_M_MF8,
4062 : PseudoVIOTA_M_MF8_MASK,
4063 : PseudoVLE16FF_V_M1,
4064 : PseudoVLE16FF_V_M1_MASK,
4065 : PseudoVLE16FF_V_M2,
4066 : PseudoVLE16FF_V_M2_MASK,
4067 : PseudoVLE16FF_V_M4,
4068 : PseudoVLE16FF_V_M4_MASK,
4069 : PseudoVLE16FF_V_M8,
4070 : PseudoVLE16FF_V_M8_MASK,
4071 : PseudoVLE16FF_V_MF2,
4072 : PseudoVLE16FF_V_MF2_MASK,
4073 : PseudoVLE16FF_V_MF4,
4074 : PseudoVLE16FF_V_MF4_MASK,
4075 : PseudoVLE16_V_M1,
4076 : PseudoVLE16_V_M1_MASK,
4077 : PseudoVLE16_V_M2,
4078 : PseudoVLE16_V_M2_MASK,
4079 : PseudoVLE16_V_M4,
4080 : PseudoVLE16_V_M4_MASK,
4081 : PseudoVLE16_V_M8,
4082 : PseudoVLE16_V_M8_MASK,
4083 : PseudoVLE16_V_MF2,
4084 : PseudoVLE16_V_MF2_MASK,
4085 : PseudoVLE16_V_MF4,
4086 : PseudoVLE16_V_MF4_MASK,
4087 : PseudoVLE32FF_V_M1,
4088 : PseudoVLE32FF_V_M1_MASK,
4089 : PseudoVLE32FF_V_M2,
4090 : PseudoVLE32FF_V_M2_MASK,
4091 : PseudoVLE32FF_V_M4,
4092 : PseudoVLE32FF_V_M4_MASK,
4093 : PseudoVLE32FF_V_M8,
4094 : PseudoVLE32FF_V_M8_MASK,
4095 : PseudoVLE32FF_V_MF2,
4096 : PseudoVLE32FF_V_MF2_MASK,
4097 : PseudoVLE32_V_M1,
4098 : PseudoVLE32_V_M1_MASK,
4099 : PseudoVLE32_V_M2,
4100 : PseudoVLE32_V_M2_MASK,
4101 : PseudoVLE32_V_M4,
4102 : PseudoVLE32_V_M4_MASK,
4103 : PseudoVLE32_V_M8,
4104 : PseudoVLE32_V_M8_MASK,
4105 : PseudoVLE32_V_MF2,
4106 : PseudoVLE32_V_MF2_MASK,
4107 : PseudoVLE64FF_V_M1,
4108 : PseudoVLE64FF_V_M1_MASK,
4109 : PseudoVLE64FF_V_M2,
4110 : PseudoVLE64FF_V_M2_MASK,
4111 : PseudoVLE64FF_V_M4,
4112 : PseudoVLE64FF_V_M4_MASK,
4113 : PseudoVLE64FF_V_M8,
4114 : PseudoVLE64FF_V_M8_MASK,
4115 : PseudoVLE64_V_M1,
4116 : PseudoVLE64_V_M1_MASK,
4117 : PseudoVLE64_V_M2,
4118 : PseudoVLE64_V_M2_MASK,
4119 : PseudoVLE64_V_M4,
4120 : PseudoVLE64_V_M4_MASK,
4121 : PseudoVLE64_V_M8,
4122 : PseudoVLE64_V_M8_MASK,
4123 : PseudoVLE8FF_V_M1,
4124 : PseudoVLE8FF_V_M1_MASK,
4125 : PseudoVLE8FF_V_M2,
4126 : PseudoVLE8FF_V_M2_MASK,
4127 : PseudoVLE8FF_V_M4,
4128 : PseudoVLE8FF_V_M4_MASK,
4129 : PseudoVLE8FF_V_M8,
4130 : PseudoVLE8FF_V_M8_MASK,
4131 : PseudoVLE8FF_V_MF2,
4132 : PseudoVLE8FF_V_MF2_MASK,
4133 : PseudoVLE8FF_V_MF4,
4134 : PseudoVLE8FF_V_MF4_MASK,
4135 : PseudoVLE8FF_V_MF8,
4136 : PseudoVLE8FF_V_MF8_MASK,
4137 : PseudoVLE8_V_M1,
4138 : PseudoVLE8_V_M1_MASK,
4139 : PseudoVLE8_V_M2,
4140 : PseudoVLE8_V_M2_MASK,
4141 : PseudoVLE8_V_M4,
4142 : PseudoVLE8_V_M4_MASK,
4143 : PseudoVLE8_V_M8,
4144 : PseudoVLE8_V_M8_MASK,
4145 : PseudoVLE8_V_MF2,
4146 : PseudoVLE8_V_MF2_MASK,
4147 : PseudoVLE8_V_MF4,
4148 : PseudoVLE8_V_MF4_MASK,
4149 : PseudoVLE8_V_MF8,
4150 : PseudoVLE8_V_MF8_MASK,
4151 : PseudoVLM_V_B1,
4152 : PseudoVLM_V_B16,
4153 : PseudoVLM_V_B2,
4154 : PseudoVLM_V_B32,
4155 : PseudoVLM_V_B4,
4156 : PseudoVLM_V_B64,
4157 : PseudoVLM_V_B8,
4158 : PseudoVLOXEI16_V_M1_M1,
4159 : PseudoVLOXEI16_V_M1_M1_MASK,
4160 : PseudoVLOXEI16_V_M1_M2,
4161 : PseudoVLOXEI16_V_M1_M2_MASK,
4162 : PseudoVLOXEI16_V_M1_M4,
4163 : PseudoVLOXEI16_V_M1_M4_MASK,
4164 : PseudoVLOXEI16_V_M1_MF2,
4165 : PseudoVLOXEI16_V_M1_MF2_MASK,
4166 : PseudoVLOXEI16_V_M2_M1,
4167 : PseudoVLOXEI16_V_M2_M1_MASK,
4168 : PseudoVLOXEI16_V_M2_M2,
4169 : PseudoVLOXEI16_V_M2_M2_MASK,
4170 : PseudoVLOXEI16_V_M2_M4,
4171 : PseudoVLOXEI16_V_M2_M4_MASK,
4172 : PseudoVLOXEI16_V_M2_M8,
4173 : PseudoVLOXEI16_V_M2_M8_MASK,
4174 : PseudoVLOXEI16_V_M4_M2,
4175 : PseudoVLOXEI16_V_M4_M2_MASK,
4176 : PseudoVLOXEI16_V_M4_M4,
4177 : PseudoVLOXEI16_V_M4_M4_MASK,
4178 : PseudoVLOXEI16_V_M4_M8,
4179 : PseudoVLOXEI16_V_M4_M8_MASK,
4180 : PseudoVLOXEI16_V_M8_M4,
4181 : PseudoVLOXEI16_V_M8_M4_MASK,
4182 : PseudoVLOXEI16_V_M8_M8,
4183 : PseudoVLOXEI16_V_M8_M8_MASK,
4184 : PseudoVLOXEI16_V_MF2_M1,
4185 : PseudoVLOXEI16_V_MF2_M1_MASK,
4186 : PseudoVLOXEI16_V_MF2_M2,
4187 : PseudoVLOXEI16_V_MF2_M2_MASK,
4188 : PseudoVLOXEI16_V_MF2_MF2,
4189 : PseudoVLOXEI16_V_MF2_MF2_MASK,
4190 : PseudoVLOXEI16_V_MF2_MF4,
4191 : PseudoVLOXEI16_V_MF2_MF4_MASK,
4192 : PseudoVLOXEI16_V_MF4_M1,
4193 : PseudoVLOXEI16_V_MF4_M1_MASK,
4194 : PseudoVLOXEI16_V_MF4_MF2,
4195 : PseudoVLOXEI16_V_MF4_MF2_MASK,
4196 : PseudoVLOXEI16_V_MF4_MF4,
4197 : PseudoVLOXEI16_V_MF4_MF4_MASK,
4198 : PseudoVLOXEI16_V_MF4_MF8,
4199 : PseudoVLOXEI16_V_MF4_MF8_MASK,
4200 : PseudoVLOXEI32_V_M1_M1,
4201 : PseudoVLOXEI32_V_M1_M1_MASK,
4202 : PseudoVLOXEI32_V_M1_M2,
4203 : PseudoVLOXEI32_V_M1_M2_MASK,
4204 : PseudoVLOXEI32_V_M1_MF2,
4205 : PseudoVLOXEI32_V_M1_MF2_MASK,
4206 : PseudoVLOXEI32_V_M1_MF4,
4207 : PseudoVLOXEI32_V_M1_MF4_MASK,
4208 : PseudoVLOXEI32_V_M2_M1,
4209 : PseudoVLOXEI32_V_M2_M1_MASK,
4210 : PseudoVLOXEI32_V_M2_M2,
4211 : PseudoVLOXEI32_V_M2_M2_MASK,
4212 : PseudoVLOXEI32_V_M2_M4,
4213 : PseudoVLOXEI32_V_M2_M4_MASK,
4214 : PseudoVLOXEI32_V_M2_MF2,
4215 : PseudoVLOXEI32_V_M2_MF2_MASK,
4216 : PseudoVLOXEI32_V_M4_M1,
4217 : PseudoVLOXEI32_V_M4_M1_MASK,
4218 : PseudoVLOXEI32_V_M4_M2,
4219 : PseudoVLOXEI32_V_M4_M2_MASK,
4220 : PseudoVLOXEI32_V_M4_M4,
4221 : PseudoVLOXEI32_V_M4_M4_MASK,
4222 : PseudoVLOXEI32_V_M4_M8,
4223 : PseudoVLOXEI32_V_M4_M8_MASK,
4224 : PseudoVLOXEI32_V_M8_M2,
4225 : PseudoVLOXEI32_V_M8_M2_MASK,
4226 : PseudoVLOXEI32_V_M8_M4,
4227 : PseudoVLOXEI32_V_M8_M4_MASK,
4228 : PseudoVLOXEI32_V_M8_M8,
4229 : PseudoVLOXEI32_V_M8_M8_MASK,
4230 : PseudoVLOXEI32_V_MF2_M1,
4231 : PseudoVLOXEI32_V_MF2_M1_MASK,
4232 : PseudoVLOXEI32_V_MF2_MF2,
4233 : PseudoVLOXEI32_V_MF2_MF2_MASK,
4234 : PseudoVLOXEI32_V_MF2_MF4,
4235 : PseudoVLOXEI32_V_MF2_MF4_MASK,
4236 : PseudoVLOXEI32_V_MF2_MF8,
4237 : PseudoVLOXEI32_V_MF2_MF8_MASK,
4238 : PseudoVLOXEI64_V_M1_M1,
4239 : PseudoVLOXEI64_V_M1_M1_MASK,
4240 : PseudoVLOXEI64_V_M1_MF2,
4241 : PseudoVLOXEI64_V_M1_MF2_MASK,
4242 : PseudoVLOXEI64_V_M1_MF4,
4243 : PseudoVLOXEI64_V_M1_MF4_MASK,
4244 : PseudoVLOXEI64_V_M1_MF8,
4245 : PseudoVLOXEI64_V_M1_MF8_MASK,
4246 : PseudoVLOXEI64_V_M2_M1,
4247 : PseudoVLOXEI64_V_M2_M1_MASK,
4248 : PseudoVLOXEI64_V_M2_M2,
4249 : PseudoVLOXEI64_V_M2_M2_MASK,
4250 : PseudoVLOXEI64_V_M2_MF2,
4251 : PseudoVLOXEI64_V_M2_MF2_MASK,
4252 : PseudoVLOXEI64_V_M2_MF4,
4253 : PseudoVLOXEI64_V_M2_MF4_MASK,
4254 : PseudoVLOXEI64_V_M4_M1,
4255 : PseudoVLOXEI64_V_M4_M1_MASK,
4256 : PseudoVLOXEI64_V_M4_M2,
4257 : PseudoVLOXEI64_V_M4_M2_MASK,
4258 : PseudoVLOXEI64_V_M4_M4,
4259 : PseudoVLOXEI64_V_M4_M4_MASK,
4260 : PseudoVLOXEI64_V_M4_MF2,
4261 : PseudoVLOXEI64_V_M4_MF2_MASK,
4262 : PseudoVLOXEI64_V_M8_M1,
4263 : PseudoVLOXEI64_V_M8_M1_MASK,
4264 : PseudoVLOXEI64_V_M8_M2,
4265 : PseudoVLOXEI64_V_M8_M2_MASK,
4266 : PseudoVLOXEI64_V_M8_M4,
4267 : PseudoVLOXEI64_V_M8_M4_MASK,
4268 : PseudoVLOXEI64_V_M8_M8,
4269 : PseudoVLOXEI64_V_M8_M8_MASK,
4270 : PseudoVLOXEI8_V_M1_M1,
4271 : PseudoVLOXEI8_V_M1_M1_MASK,
4272 : PseudoVLOXEI8_V_M1_M2,
4273 : PseudoVLOXEI8_V_M1_M2_MASK,
4274 : PseudoVLOXEI8_V_M1_M4,
4275 : PseudoVLOXEI8_V_M1_M4_MASK,
4276 : PseudoVLOXEI8_V_M1_M8,
4277 : PseudoVLOXEI8_V_M1_M8_MASK,
4278 : PseudoVLOXEI8_V_M2_M2,
4279 : PseudoVLOXEI8_V_M2_M2_MASK,
4280 : PseudoVLOXEI8_V_M2_M4,
4281 : PseudoVLOXEI8_V_M2_M4_MASK,
4282 : PseudoVLOXEI8_V_M2_M8,
4283 : PseudoVLOXEI8_V_M2_M8_MASK,
4284 : PseudoVLOXEI8_V_M4_M4,
4285 : PseudoVLOXEI8_V_M4_M4_MASK,
4286 : PseudoVLOXEI8_V_M4_M8,
4287 : PseudoVLOXEI8_V_M4_M8_MASK,
4288 : PseudoVLOXEI8_V_M8_M8,
4289 : PseudoVLOXEI8_V_M8_M8_MASK,
4290 : PseudoVLOXEI8_V_MF2_M1,
4291 : PseudoVLOXEI8_V_MF2_M1_MASK,
4292 : PseudoVLOXEI8_V_MF2_M2,
4293 : PseudoVLOXEI8_V_MF2_M2_MASK,
4294 : PseudoVLOXEI8_V_MF2_M4,
4295 : PseudoVLOXEI8_V_MF2_M4_MASK,
4296 : PseudoVLOXEI8_V_MF2_MF2,
4297 : PseudoVLOXEI8_V_MF2_MF2_MASK,
4298 : PseudoVLOXEI8_V_MF4_M1,
4299 : PseudoVLOXEI8_V_MF4_M1_MASK,
4300 : PseudoVLOXEI8_V_MF4_M2,
4301 : PseudoVLOXEI8_V_MF4_M2_MASK,
4302 : PseudoVLOXEI8_V_MF4_MF2,
4303 : PseudoVLOXEI8_V_MF4_MF2_MASK,
4304 : PseudoVLOXEI8_V_MF4_MF4,
4305 : PseudoVLOXEI8_V_MF4_MF4_MASK,
4306 : PseudoVLOXEI8_V_MF8_M1,
4307 : PseudoVLOXEI8_V_MF8_M1_MASK,
4308 : PseudoVLOXEI8_V_MF8_MF2,
4309 : PseudoVLOXEI8_V_MF8_MF2_MASK,
4310 : PseudoVLOXEI8_V_MF8_MF4,
4311 : PseudoVLOXEI8_V_MF8_MF4_MASK,
4312 : PseudoVLOXEI8_V_MF8_MF8,
4313 : PseudoVLOXEI8_V_MF8_MF8_MASK,
4314 : PseudoVLOXSEG2EI16_V_M1_M1,
4315 : PseudoVLOXSEG2EI16_V_M1_M1_MASK,
4316 : PseudoVLOXSEG2EI16_V_M1_M2,
4317 : PseudoVLOXSEG2EI16_V_M1_M2_MASK,
4318 : PseudoVLOXSEG2EI16_V_M1_M4,
4319 : PseudoVLOXSEG2EI16_V_M1_M4_MASK,
4320 : PseudoVLOXSEG2EI16_V_M1_MF2,
4321 : PseudoVLOXSEG2EI16_V_M1_MF2_MASK,
4322 : PseudoVLOXSEG2EI16_V_M2_M1,
4323 : PseudoVLOXSEG2EI16_V_M2_M1_MASK,
4324 : PseudoVLOXSEG2EI16_V_M2_M2,
4325 : PseudoVLOXSEG2EI16_V_M2_M2_MASK,
4326 : PseudoVLOXSEG2EI16_V_M2_M4,
4327 : PseudoVLOXSEG2EI16_V_M2_M4_MASK,
4328 : PseudoVLOXSEG2EI16_V_M4_M2,
4329 : PseudoVLOXSEG2EI16_V_M4_M2_MASK,
4330 : PseudoVLOXSEG2EI16_V_M4_M4,
4331 : PseudoVLOXSEG2EI16_V_M4_M4_MASK,
4332 : PseudoVLOXSEG2EI16_V_M8_M4,
4333 : PseudoVLOXSEG2EI16_V_M8_M4_MASK,
4334 : PseudoVLOXSEG2EI16_V_MF2_M1,
4335 : PseudoVLOXSEG2EI16_V_MF2_M1_MASK,
4336 : PseudoVLOXSEG2EI16_V_MF2_M2,
4337 : PseudoVLOXSEG2EI16_V_MF2_M2_MASK,
4338 : PseudoVLOXSEG2EI16_V_MF2_MF2,
4339 : PseudoVLOXSEG2EI16_V_MF2_MF2_MASK,
4340 : PseudoVLOXSEG2EI16_V_MF2_MF4,
4341 : PseudoVLOXSEG2EI16_V_MF2_MF4_MASK,
4342 : PseudoVLOXSEG2EI16_V_MF4_M1,
4343 : PseudoVLOXSEG2EI16_V_MF4_M1_MASK,
4344 : PseudoVLOXSEG2EI16_V_MF4_MF2,
4345 : PseudoVLOXSEG2EI16_V_MF4_MF2_MASK,
4346 : PseudoVLOXSEG2EI16_V_MF4_MF4,
4347 : PseudoVLOXSEG2EI16_V_MF4_MF4_MASK,
4348 : PseudoVLOXSEG2EI16_V_MF4_MF8,
4349 : PseudoVLOXSEG2EI16_V_MF4_MF8_MASK,
4350 : PseudoVLOXSEG2EI32_V_M1_M1,
4351 : PseudoVLOXSEG2EI32_V_M1_M1_MASK,
4352 : PseudoVLOXSEG2EI32_V_M1_M2,
4353 : PseudoVLOXSEG2EI32_V_M1_M2_MASK,
4354 : PseudoVLOXSEG2EI32_V_M1_MF2,
4355 : PseudoVLOXSEG2EI32_V_M1_MF2_MASK,
4356 : PseudoVLOXSEG2EI32_V_M1_MF4,
4357 : PseudoVLOXSEG2EI32_V_M1_MF4_MASK,
4358 : PseudoVLOXSEG2EI32_V_M2_M1,
4359 : PseudoVLOXSEG2EI32_V_M2_M1_MASK,
4360 : PseudoVLOXSEG2EI32_V_M2_M2,
4361 : PseudoVLOXSEG2EI32_V_M2_M2_MASK,
4362 : PseudoVLOXSEG2EI32_V_M2_M4,
4363 : PseudoVLOXSEG2EI32_V_M2_M4_MASK,
4364 : PseudoVLOXSEG2EI32_V_M2_MF2,
4365 : PseudoVLOXSEG2EI32_V_M2_MF2_MASK,
4366 : PseudoVLOXSEG2EI32_V_M4_M1,
4367 : PseudoVLOXSEG2EI32_V_M4_M1_MASK,
4368 : PseudoVLOXSEG2EI32_V_M4_M2,
4369 : PseudoVLOXSEG2EI32_V_M4_M2_MASK,
4370 : PseudoVLOXSEG2EI32_V_M4_M4,
4371 : PseudoVLOXSEG2EI32_V_M4_M4_MASK,
4372 : PseudoVLOXSEG2EI32_V_M8_M2,
4373 : PseudoVLOXSEG2EI32_V_M8_M2_MASK,
4374 : PseudoVLOXSEG2EI32_V_M8_M4,
4375 : PseudoVLOXSEG2EI32_V_M8_M4_MASK,
4376 : PseudoVLOXSEG2EI32_V_MF2_M1,
4377 : PseudoVLOXSEG2EI32_V_MF2_M1_MASK,
4378 : PseudoVLOXSEG2EI32_V_MF2_MF2,
4379 : PseudoVLOXSEG2EI32_V_MF2_MF2_MASK,
4380 : PseudoVLOXSEG2EI32_V_MF2_MF4,
4381 : PseudoVLOXSEG2EI32_V_MF2_MF4_MASK,
4382 : PseudoVLOXSEG2EI32_V_MF2_MF8,
4383 : PseudoVLOXSEG2EI32_V_MF2_MF8_MASK,
4384 : PseudoVLOXSEG2EI64_V_M1_M1,
4385 : PseudoVLOXSEG2EI64_V_M1_M1_MASK,
4386 : PseudoVLOXSEG2EI64_V_M1_MF2,
4387 : PseudoVLOXSEG2EI64_V_M1_MF2_MASK,
4388 : PseudoVLOXSEG2EI64_V_M1_MF4,
4389 : PseudoVLOXSEG2EI64_V_M1_MF4_MASK,
4390 : PseudoVLOXSEG2EI64_V_M1_MF8,
4391 : PseudoVLOXSEG2EI64_V_M1_MF8_MASK,
4392 : PseudoVLOXSEG2EI64_V_M2_M1,
4393 : PseudoVLOXSEG2EI64_V_M2_M1_MASK,
4394 : PseudoVLOXSEG2EI64_V_M2_M2,
4395 : PseudoVLOXSEG2EI64_V_M2_M2_MASK,
4396 : PseudoVLOXSEG2EI64_V_M2_MF2,
4397 : PseudoVLOXSEG2EI64_V_M2_MF2_MASK,
4398 : PseudoVLOXSEG2EI64_V_M2_MF4,
4399 : PseudoVLOXSEG2EI64_V_M2_MF4_MASK,
4400 : PseudoVLOXSEG2EI64_V_M4_M1,
4401 : PseudoVLOXSEG2EI64_V_M4_M1_MASK,
4402 : PseudoVLOXSEG2EI64_V_M4_M2,
4403 : PseudoVLOXSEG2EI64_V_M4_M2_MASK,
4404 : PseudoVLOXSEG2EI64_V_M4_M4,
4405 : PseudoVLOXSEG2EI64_V_M4_M4_MASK,
4406 : PseudoVLOXSEG2EI64_V_M4_MF2,
4407 : PseudoVLOXSEG2EI64_V_M4_MF2_MASK,
4408 : PseudoVLOXSEG2EI64_V_M8_M1,
4409 : PseudoVLOXSEG2EI64_V_M8_M1_MASK,
4410 : PseudoVLOXSEG2EI64_V_M8_M2,
4411 : PseudoVLOXSEG2EI64_V_M8_M2_MASK,
4412 : PseudoVLOXSEG2EI64_V_M8_M4,
4413 : PseudoVLOXSEG2EI64_V_M8_M4_MASK,
4414 : PseudoVLOXSEG2EI8_V_M1_M1,
4415 : PseudoVLOXSEG2EI8_V_M1_M1_MASK,
4416 : PseudoVLOXSEG2EI8_V_M1_M2,
4417 : PseudoVLOXSEG2EI8_V_M1_M2_MASK,
4418 : PseudoVLOXSEG2EI8_V_M1_M4,
4419 : PseudoVLOXSEG2EI8_V_M1_M4_MASK,
4420 : PseudoVLOXSEG2EI8_V_M2_M2,
4421 : PseudoVLOXSEG2EI8_V_M2_M2_MASK,
4422 : PseudoVLOXSEG2EI8_V_M2_M4,
4423 : PseudoVLOXSEG2EI8_V_M2_M4_MASK,
4424 : PseudoVLOXSEG2EI8_V_M4_M4,
4425 : PseudoVLOXSEG2EI8_V_M4_M4_MASK,
4426 : PseudoVLOXSEG2EI8_V_MF2_M1,
4427 : PseudoVLOXSEG2EI8_V_MF2_M1_MASK,
4428 : PseudoVLOXSEG2EI8_V_MF2_M2,
4429 : PseudoVLOXSEG2EI8_V_MF2_M2_MASK,
4430 : PseudoVLOXSEG2EI8_V_MF2_M4,
4431 : PseudoVLOXSEG2EI8_V_MF2_M4_MASK,
4432 : PseudoVLOXSEG2EI8_V_MF2_MF2,
4433 : PseudoVLOXSEG2EI8_V_MF2_MF2_MASK,
4434 : PseudoVLOXSEG2EI8_V_MF4_M1,
4435 : PseudoVLOXSEG2EI8_V_MF4_M1_MASK,
4436 : PseudoVLOXSEG2EI8_V_MF4_M2,
4437 : PseudoVLOXSEG2EI8_V_MF4_M2_MASK,
4438 : PseudoVLOXSEG2EI8_V_MF4_MF2,
4439 : PseudoVLOXSEG2EI8_V_MF4_MF2_MASK,
4440 : PseudoVLOXSEG2EI8_V_MF4_MF4,
4441 : PseudoVLOXSEG2EI8_V_MF4_MF4_MASK,
4442 : PseudoVLOXSEG2EI8_V_MF8_M1,
4443 : PseudoVLOXSEG2EI8_V_MF8_M1_MASK,
4444 : PseudoVLOXSEG2EI8_V_MF8_MF2,
4445 : PseudoVLOXSEG2EI8_V_MF8_MF2_MASK,
4446 : PseudoVLOXSEG2EI8_V_MF8_MF4,
4447 : PseudoVLOXSEG2EI8_V_MF8_MF4_MASK,
4448 : PseudoVLOXSEG2EI8_V_MF8_MF8,
4449 : PseudoVLOXSEG2EI8_V_MF8_MF8_MASK,
4450 : PseudoVLOXSEG3EI16_V_M1_M1,
4451 : PseudoVLOXSEG3EI16_V_M1_M1_MASK,
4452 : PseudoVLOXSEG3EI16_V_M1_M2,
4453 : PseudoVLOXSEG3EI16_V_M1_M2_MASK,
4454 : PseudoVLOXSEG3EI16_V_M1_MF2,
4455 : PseudoVLOXSEG3EI16_V_M1_MF2_MASK,
4456 : PseudoVLOXSEG3EI16_V_M2_M1,
4457 : PseudoVLOXSEG3EI16_V_M2_M1_MASK,
4458 : PseudoVLOXSEG3EI16_V_M2_M2,
4459 : PseudoVLOXSEG3EI16_V_M2_M2_MASK,
4460 : PseudoVLOXSEG3EI16_V_M4_M2,
4461 : PseudoVLOXSEG3EI16_V_M4_M2_MASK,
4462 : PseudoVLOXSEG3EI16_V_MF2_M1,
4463 : PseudoVLOXSEG3EI16_V_MF2_M1_MASK,
4464 : PseudoVLOXSEG3EI16_V_MF2_M2,
4465 : PseudoVLOXSEG3EI16_V_MF2_M2_MASK,
4466 : PseudoVLOXSEG3EI16_V_MF2_MF2,
4467 : PseudoVLOXSEG3EI16_V_MF2_MF2_MASK,
4468 : PseudoVLOXSEG3EI16_V_MF2_MF4,
4469 : PseudoVLOXSEG3EI16_V_MF2_MF4_MASK,
4470 : PseudoVLOXSEG3EI16_V_MF4_M1,
4471 : PseudoVLOXSEG3EI16_V_MF4_M1_MASK,
4472 : PseudoVLOXSEG3EI16_V_MF4_MF2,
4473 : PseudoVLOXSEG3EI16_V_MF4_MF2_MASK,
4474 : PseudoVLOXSEG3EI16_V_MF4_MF4,
4475 : PseudoVLOXSEG3EI16_V_MF4_MF4_MASK,
4476 : PseudoVLOXSEG3EI16_V_MF4_MF8,
4477 : PseudoVLOXSEG3EI16_V_MF4_MF8_MASK,
4478 : PseudoVLOXSEG3EI32_V_M1_M1,
4479 : PseudoVLOXSEG3EI32_V_M1_M1_MASK,
4480 : PseudoVLOXSEG3EI32_V_M1_M2,
4481 : PseudoVLOXSEG3EI32_V_M1_M2_MASK,
4482 : PseudoVLOXSEG3EI32_V_M1_MF2,
4483 : PseudoVLOXSEG3EI32_V_M1_MF2_MASK,
4484 : PseudoVLOXSEG3EI32_V_M1_MF4,
4485 : PseudoVLOXSEG3EI32_V_M1_MF4_MASK,
4486 : PseudoVLOXSEG3EI32_V_M2_M1,
4487 : PseudoVLOXSEG3EI32_V_M2_M1_MASK,
4488 : PseudoVLOXSEG3EI32_V_M2_M2,
4489 : PseudoVLOXSEG3EI32_V_M2_M2_MASK,
4490 : PseudoVLOXSEG3EI32_V_M2_MF2,
4491 : PseudoVLOXSEG3EI32_V_M2_MF2_MASK,
4492 : PseudoVLOXSEG3EI32_V_M4_M1,
4493 : PseudoVLOXSEG3EI32_V_M4_M1_MASK,
4494 : PseudoVLOXSEG3EI32_V_M4_M2,
4495 : PseudoVLOXSEG3EI32_V_M4_M2_MASK,
4496 : PseudoVLOXSEG3EI32_V_M8_M2,
4497 : PseudoVLOXSEG3EI32_V_M8_M2_MASK,
4498 : PseudoVLOXSEG3EI32_V_MF2_M1,
4499 : PseudoVLOXSEG3EI32_V_MF2_M1_MASK,
4500 : PseudoVLOXSEG3EI32_V_MF2_MF2,
4501 : PseudoVLOXSEG3EI32_V_MF2_MF2_MASK,
4502 : PseudoVLOXSEG3EI32_V_MF2_MF4,
4503 : PseudoVLOXSEG3EI32_V_MF2_MF4_MASK,
4504 : PseudoVLOXSEG3EI32_V_MF2_MF8,
4505 : PseudoVLOXSEG3EI32_V_MF2_MF8_MASK,
4506 : PseudoVLOXSEG3EI64_V_M1_M1,
4507 : PseudoVLOXSEG3EI64_V_M1_M1_MASK,
4508 : PseudoVLOXSEG3EI64_V_M1_MF2,
4509 : PseudoVLOXSEG3EI64_V_M1_MF2_MASK,
4510 : PseudoVLOXSEG3EI64_V_M1_MF4,
4511 : PseudoVLOXSEG3EI64_V_M1_MF4_MASK,
4512 : PseudoVLOXSEG3EI64_V_M1_MF8,
4513 : PseudoVLOXSEG3EI64_V_M1_MF8_MASK,
4514 : PseudoVLOXSEG3EI64_V_M2_M1,
4515 : PseudoVLOXSEG3EI64_V_M2_M1_MASK,
4516 : PseudoVLOXSEG3EI64_V_M2_M2,
4517 : PseudoVLOXSEG3EI64_V_M2_M2_MASK,
4518 : PseudoVLOXSEG3EI64_V_M2_MF2,
4519 : PseudoVLOXSEG3EI64_V_M2_MF2_MASK,
4520 : PseudoVLOXSEG3EI64_V_M2_MF4,
4521 : PseudoVLOXSEG3EI64_V_M2_MF4_MASK,
4522 : PseudoVLOXSEG3EI64_V_M4_M1,
4523 : PseudoVLOXSEG3EI64_V_M4_M1_MASK,
4524 : PseudoVLOXSEG3EI64_V_M4_M2,
4525 : PseudoVLOXSEG3EI64_V_M4_M2_MASK,
4526 : PseudoVLOXSEG3EI64_V_M4_MF2,
4527 : PseudoVLOXSEG3EI64_V_M4_MF2_MASK,
4528 : PseudoVLOXSEG3EI64_V_M8_M1,
4529 : PseudoVLOXSEG3EI64_V_M8_M1_MASK,
4530 : PseudoVLOXSEG3EI64_V_M8_M2,
4531 : PseudoVLOXSEG3EI64_V_M8_M2_MASK,
4532 : PseudoVLOXSEG3EI8_V_M1_M1,
4533 : PseudoVLOXSEG3EI8_V_M1_M1_MASK,
4534 : PseudoVLOXSEG3EI8_V_M1_M2,
4535 : PseudoVLOXSEG3EI8_V_M1_M2_MASK,
4536 : PseudoVLOXSEG3EI8_V_M2_M2,
4537 : PseudoVLOXSEG3EI8_V_M2_M2_MASK,
4538 : PseudoVLOXSEG3EI8_V_MF2_M1,
4539 : PseudoVLOXSEG3EI8_V_MF2_M1_MASK,
4540 : PseudoVLOXSEG3EI8_V_MF2_M2,
4541 : PseudoVLOXSEG3EI8_V_MF2_M2_MASK,
4542 : PseudoVLOXSEG3EI8_V_MF2_MF2,
4543 : PseudoVLOXSEG3EI8_V_MF2_MF2_MASK,
4544 : PseudoVLOXSEG3EI8_V_MF4_M1,
4545 : PseudoVLOXSEG3EI8_V_MF4_M1_MASK,
4546 : PseudoVLOXSEG3EI8_V_MF4_M2,
4547 : PseudoVLOXSEG3EI8_V_MF4_M2_MASK,
4548 : PseudoVLOXSEG3EI8_V_MF4_MF2,
4549 : PseudoVLOXSEG3EI8_V_MF4_MF2_MASK,
4550 : PseudoVLOXSEG3EI8_V_MF4_MF4,
4551 : PseudoVLOXSEG3EI8_V_MF4_MF4_MASK,
4552 : PseudoVLOXSEG3EI8_V_MF8_M1,
4553 : PseudoVLOXSEG3EI8_V_MF8_M1_MASK,
4554 : PseudoVLOXSEG3EI8_V_MF8_MF2,
4555 : PseudoVLOXSEG3EI8_V_MF8_MF2_MASK,
4556 : PseudoVLOXSEG3EI8_V_MF8_MF4,
4557 : PseudoVLOXSEG3EI8_V_MF8_MF4_MASK,
4558 : PseudoVLOXSEG3EI8_V_MF8_MF8,
4559 : PseudoVLOXSEG3EI8_V_MF8_MF8_MASK,
4560 : PseudoVLOXSEG4EI16_V_M1_M1,
4561 : PseudoVLOXSEG4EI16_V_M1_M1_MASK,
4562 : PseudoVLOXSEG4EI16_V_M1_M2,
4563 : PseudoVLOXSEG4EI16_V_M1_M2_MASK,
4564 : PseudoVLOXSEG4EI16_V_M1_MF2,
4565 : PseudoVLOXSEG4EI16_V_M1_MF2_MASK,
4566 : PseudoVLOXSEG4EI16_V_M2_M1,
4567 : PseudoVLOXSEG4EI16_V_M2_M1_MASK,
4568 : PseudoVLOXSEG4EI16_V_M2_M2,
4569 : PseudoVLOXSEG4EI16_V_M2_M2_MASK,
4570 : PseudoVLOXSEG4EI16_V_M4_M2,
4571 : PseudoVLOXSEG4EI16_V_M4_M2_MASK,
4572 : PseudoVLOXSEG4EI16_V_MF2_M1,
4573 : PseudoVLOXSEG4EI16_V_MF2_M1_MASK,
4574 : PseudoVLOXSEG4EI16_V_MF2_M2,
4575 : PseudoVLOXSEG4EI16_V_MF2_M2_MASK,
4576 : PseudoVLOXSEG4EI16_V_MF2_MF2,
4577 : PseudoVLOXSEG4EI16_V_MF2_MF2_MASK,
4578 : PseudoVLOXSEG4EI16_V_MF2_MF4,
4579 : PseudoVLOXSEG4EI16_V_MF2_MF4_MASK,
4580 : PseudoVLOXSEG4EI16_V_MF4_M1,
4581 : PseudoVLOXSEG4EI16_V_MF4_M1_MASK,
4582 : PseudoVLOXSEG4EI16_V_MF4_MF2,
4583 : PseudoVLOXSEG4EI16_V_MF4_MF2_MASK,
4584 : PseudoVLOXSEG4EI16_V_MF4_MF4,
4585 : PseudoVLOXSEG4EI16_V_MF4_MF4_MASK,
4586 : PseudoVLOXSEG4EI16_V_MF4_MF8,
4587 : PseudoVLOXSEG4EI16_V_MF4_MF8_MASK,
4588 : PseudoVLOXSEG4EI32_V_M1_M1,
4589 : PseudoVLOXSEG4EI32_V_M1_M1_MASK,
4590 : PseudoVLOXSEG4EI32_V_M1_M2,
4591 : PseudoVLOXSEG4EI32_V_M1_M2_MASK,
4592 : PseudoVLOXSEG4EI32_V_M1_MF2,
4593 : PseudoVLOXSEG4EI32_V_M1_MF2_MASK,
4594 : PseudoVLOXSEG4EI32_V_M1_MF4,
4595 : PseudoVLOXSEG4EI32_V_M1_MF4_MASK,
4596 : PseudoVLOXSEG4EI32_V_M2_M1,
4597 : PseudoVLOXSEG4EI32_V_M2_M1_MASK,
4598 : PseudoVLOXSEG4EI32_V_M2_M2,
4599 : PseudoVLOXSEG4EI32_V_M2_M2_MASK,
4600 : PseudoVLOXSEG4EI32_V_M2_MF2,
4601 : PseudoVLOXSEG4EI32_V_M2_MF2_MASK,
4602 : PseudoVLOXSEG4EI32_V_M4_M1,
4603 : PseudoVLOXSEG4EI32_V_M4_M1_MASK,
4604 : PseudoVLOXSEG4EI32_V_M4_M2,
4605 : PseudoVLOXSEG4EI32_V_M4_M2_MASK,
4606 : PseudoVLOXSEG4EI32_V_M8_M2,
4607 : PseudoVLOXSEG4EI32_V_M8_M2_MASK,
4608 : PseudoVLOXSEG4EI32_V_MF2_M1,
4609 : PseudoVLOXSEG4EI32_V_MF2_M1_MASK,
4610 : PseudoVLOXSEG4EI32_V_MF2_MF2,
4611 : PseudoVLOXSEG4EI32_V_MF2_MF2_MASK,
4612 : PseudoVLOXSEG4EI32_V_MF2_MF4,
4613 : PseudoVLOXSEG4EI32_V_MF2_MF4_MASK,
4614 : PseudoVLOXSEG4EI32_V_MF2_MF8,
4615 : PseudoVLOXSEG4EI32_V_MF2_MF8_MASK,
4616 : PseudoVLOXSEG4EI64_V_M1_M1,
4617 : PseudoVLOXSEG4EI64_V_M1_M1_MASK,
4618 : PseudoVLOXSEG4EI64_V_M1_MF2,
4619 : PseudoVLOXSEG4EI64_V_M1_MF2_MASK,
4620 : PseudoVLOXSEG4EI64_V_M1_MF4,
4621 : PseudoVLOXSEG4EI64_V_M1_MF4_MASK,
4622 : PseudoVLOXSEG4EI64_V_M1_MF8,
4623 : PseudoVLOXSEG4EI64_V_M1_MF8_MASK,
4624 : PseudoVLOXSEG4EI64_V_M2_M1,
4625 : PseudoVLOXSEG4EI64_V_M2_M1_MASK,
4626 : PseudoVLOXSEG4EI64_V_M2_M2,
4627 : PseudoVLOXSEG4EI64_V_M2_M2_MASK,
4628 : PseudoVLOXSEG4EI64_V_M2_MF2,
4629 : PseudoVLOXSEG4EI64_V_M2_MF2_MASK,
4630 : PseudoVLOXSEG4EI64_V_M2_MF4,
4631 : PseudoVLOXSEG4EI64_V_M2_MF4_MASK,
4632 : PseudoVLOXSEG4EI64_V_M4_M1,
4633 : PseudoVLOXSEG4EI64_V_M4_M1_MASK,
4634 : PseudoVLOXSEG4EI64_V_M4_M2,
4635 : PseudoVLOXSEG4EI64_V_M4_M2_MASK,
4636 : PseudoVLOXSEG4EI64_V_M4_MF2,
4637 : PseudoVLOXSEG4EI64_V_M4_MF2_MASK,
4638 : PseudoVLOXSEG4EI64_V_M8_M1,
4639 : PseudoVLOXSEG4EI64_V_M8_M1_MASK,
4640 : PseudoVLOXSEG4EI64_V_M8_M2,
4641 : PseudoVLOXSEG4EI64_V_M8_M2_MASK,
4642 : PseudoVLOXSEG4EI8_V_M1_M1,
4643 : PseudoVLOXSEG4EI8_V_M1_M1_MASK,
4644 : PseudoVLOXSEG4EI8_V_M1_M2,
4645 : PseudoVLOXSEG4EI8_V_M1_M2_MASK,
4646 : PseudoVLOXSEG4EI8_V_M2_M2,
4647 : PseudoVLOXSEG4EI8_V_M2_M2_MASK,
4648 : PseudoVLOXSEG4EI8_V_MF2_M1,
4649 : PseudoVLOXSEG4EI8_V_MF2_M1_MASK,
4650 : PseudoVLOXSEG4EI8_V_MF2_M2,
4651 : PseudoVLOXSEG4EI8_V_MF2_M2_MASK,
4652 : PseudoVLOXSEG4EI8_V_MF2_MF2,
4653 : PseudoVLOXSEG4EI8_V_MF2_MF2_MASK,
4654 : PseudoVLOXSEG4EI8_V_MF4_M1,
4655 : PseudoVLOXSEG4EI8_V_MF4_M1_MASK,
4656 : PseudoVLOXSEG4EI8_V_MF4_M2,
4657 : PseudoVLOXSEG4EI8_V_MF4_M2_MASK,
4658 : PseudoVLOXSEG4EI8_V_MF4_MF2,
4659 : PseudoVLOXSEG4EI8_V_MF4_MF2_MASK,
4660 : PseudoVLOXSEG4EI8_V_MF4_MF4,
4661 : PseudoVLOXSEG4EI8_V_MF4_MF4_MASK,
4662 : PseudoVLOXSEG4EI8_V_MF8_M1,
4663 : PseudoVLOXSEG4EI8_V_MF8_M1_MASK,
4664 : PseudoVLOXSEG4EI8_V_MF8_MF2,
4665 : PseudoVLOXSEG4EI8_V_MF8_MF2_MASK,
4666 : PseudoVLOXSEG4EI8_V_MF8_MF4,
4667 : PseudoVLOXSEG4EI8_V_MF8_MF4_MASK,
4668 : PseudoVLOXSEG4EI8_V_MF8_MF8,
4669 : PseudoVLOXSEG4EI8_V_MF8_MF8_MASK,
4670 : PseudoVLOXSEG5EI16_V_M1_M1,
4671 : PseudoVLOXSEG5EI16_V_M1_M1_MASK,
4672 : PseudoVLOXSEG5EI16_V_M1_MF2,
4673 : PseudoVLOXSEG5EI16_V_M1_MF2_MASK,
4674 : PseudoVLOXSEG5EI16_V_M2_M1,
4675 : PseudoVLOXSEG5EI16_V_M2_M1_MASK,
4676 : PseudoVLOXSEG5EI16_V_MF2_M1,
4677 : PseudoVLOXSEG5EI16_V_MF2_M1_MASK,
4678 : PseudoVLOXSEG5EI16_V_MF2_MF2,
4679 : PseudoVLOXSEG5EI16_V_MF2_MF2_MASK,
4680 : PseudoVLOXSEG5EI16_V_MF2_MF4,
4681 : PseudoVLOXSEG5EI16_V_MF2_MF4_MASK,
4682 : PseudoVLOXSEG5EI16_V_MF4_M1,
4683 : PseudoVLOXSEG5EI16_V_MF4_M1_MASK,
4684 : PseudoVLOXSEG5EI16_V_MF4_MF2,
4685 : PseudoVLOXSEG5EI16_V_MF4_MF2_MASK,
4686 : PseudoVLOXSEG5EI16_V_MF4_MF4,
4687 : PseudoVLOXSEG5EI16_V_MF4_MF4_MASK,
4688 : PseudoVLOXSEG5EI16_V_MF4_MF8,
4689 : PseudoVLOXSEG5EI16_V_MF4_MF8_MASK,
4690 : PseudoVLOXSEG5EI32_V_M1_M1,
4691 : PseudoVLOXSEG5EI32_V_M1_M1_MASK,
4692 : PseudoVLOXSEG5EI32_V_M1_MF2,
4693 : PseudoVLOXSEG5EI32_V_M1_MF2_MASK,
4694 : PseudoVLOXSEG5EI32_V_M1_MF4,
4695 : PseudoVLOXSEG5EI32_V_M1_MF4_MASK,
4696 : PseudoVLOXSEG5EI32_V_M2_M1,
4697 : PseudoVLOXSEG5EI32_V_M2_M1_MASK,
4698 : PseudoVLOXSEG5EI32_V_M2_MF2,
4699 : PseudoVLOXSEG5EI32_V_M2_MF2_MASK,
4700 : PseudoVLOXSEG5EI32_V_M4_M1,
4701 : PseudoVLOXSEG5EI32_V_M4_M1_MASK,
4702 : PseudoVLOXSEG5EI32_V_MF2_M1,
4703 : PseudoVLOXSEG5EI32_V_MF2_M1_MASK,
4704 : PseudoVLOXSEG5EI32_V_MF2_MF2,
4705 : PseudoVLOXSEG5EI32_V_MF2_MF2_MASK,
4706 : PseudoVLOXSEG5EI32_V_MF2_MF4,
4707 : PseudoVLOXSEG5EI32_V_MF2_MF4_MASK,
4708 : PseudoVLOXSEG5EI32_V_MF2_MF8,
4709 : PseudoVLOXSEG5EI32_V_MF2_MF8_MASK,
4710 : PseudoVLOXSEG5EI64_V_M1_M1,
4711 : PseudoVLOXSEG5EI64_V_M1_M1_MASK,
4712 : PseudoVLOXSEG5EI64_V_M1_MF2,
4713 : PseudoVLOXSEG5EI64_V_M1_MF2_MASK,
4714 : PseudoVLOXSEG5EI64_V_M1_MF4,
4715 : PseudoVLOXSEG5EI64_V_M1_MF4_MASK,
4716 : PseudoVLOXSEG5EI64_V_M1_MF8,
4717 : PseudoVLOXSEG5EI64_V_M1_MF8_MASK,
4718 : PseudoVLOXSEG5EI64_V_M2_M1,
4719 : PseudoVLOXSEG5EI64_V_M2_M1_MASK,
4720 : PseudoVLOXSEG5EI64_V_M2_MF2,
4721 : PseudoVLOXSEG5EI64_V_M2_MF2_MASK,
4722 : PseudoVLOXSEG5EI64_V_M2_MF4,
4723 : PseudoVLOXSEG5EI64_V_M2_MF4_MASK,
4724 : PseudoVLOXSEG5EI64_V_M4_M1,
4725 : PseudoVLOXSEG5EI64_V_M4_M1_MASK,
4726 : PseudoVLOXSEG5EI64_V_M4_MF2,
4727 : PseudoVLOXSEG5EI64_V_M4_MF2_MASK,
4728 : PseudoVLOXSEG5EI64_V_M8_M1,
4729 : PseudoVLOXSEG5EI64_V_M8_M1_MASK,
4730 : PseudoVLOXSEG5EI8_V_M1_M1,
4731 : PseudoVLOXSEG5EI8_V_M1_M1_MASK,
4732 : PseudoVLOXSEG5EI8_V_MF2_M1,
4733 : PseudoVLOXSEG5EI8_V_MF2_M1_MASK,
4734 : PseudoVLOXSEG5EI8_V_MF2_MF2,
4735 : PseudoVLOXSEG5EI8_V_MF2_MF2_MASK,
4736 : PseudoVLOXSEG5EI8_V_MF4_M1,
4737 : PseudoVLOXSEG5EI8_V_MF4_M1_MASK,
4738 : PseudoVLOXSEG5EI8_V_MF4_MF2,
4739 : PseudoVLOXSEG5EI8_V_MF4_MF2_MASK,
4740 : PseudoVLOXSEG5EI8_V_MF4_MF4,
4741 : PseudoVLOXSEG5EI8_V_MF4_MF4_MASK,
4742 : PseudoVLOXSEG5EI8_V_MF8_M1,
4743 : PseudoVLOXSEG5EI8_V_MF8_M1_MASK,
4744 : PseudoVLOXSEG5EI8_V_MF8_MF2,
4745 : PseudoVLOXSEG5EI8_V_MF8_MF2_MASK,
4746 : PseudoVLOXSEG5EI8_V_MF8_MF4,
4747 : PseudoVLOXSEG5EI8_V_MF8_MF4_MASK,
4748 : PseudoVLOXSEG5EI8_V_MF8_MF8,
4749 : PseudoVLOXSEG5EI8_V_MF8_MF8_MASK,
4750 : PseudoVLOXSEG6EI16_V_M1_M1,
4751 : PseudoVLOXSEG6EI16_V_M1_M1_MASK,
4752 : PseudoVLOXSEG6EI16_V_M1_MF2,
4753 : PseudoVLOXSEG6EI16_V_M1_MF2_MASK,
4754 : PseudoVLOXSEG6EI16_V_M2_M1,
4755 : PseudoVLOXSEG6EI16_V_M2_M1_MASK,
4756 : PseudoVLOXSEG6EI16_V_MF2_M1,
4757 : PseudoVLOXSEG6EI16_V_MF2_M1_MASK,
4758 : PseudoVLOXSEG6EI16_V_MF2_MF2,
4759 : PseudoVLOXSEG6EI16_V_MF2_MF2_MASK,
4760 : PseudoVLOXSEG6EI16_V_MF2_MF4,
4761 : PseudoVLOXSEG6EI16_V_MF2_MF4_MASK,
4762 : PseudoVLOXSEG6EI16_V_MF4_M1,
4763 : PseudoVLOXSEG6EI16_V_MF4_M1_MASK,
4764 : PseudoVLOXSEG6EI16_V_MF4_MF2,
4765 : PseudoVLOXSEG6EI16_V_MF4_MF2_MASK,
4766 : PseudoVLOXSEG6EI16_V_MF4_MF4,
4767 : PseudoVLOXSEG6EI16_V_MF4_MF4_MASK,
4768 : PseudoVLOXSEG6EI16_V_MF4_MF8,
4769 : PseudoVLOXSEG6EI16_V_MF4_MF8_MASK,
4770 : PseudoVLOXSEG6EI32_V_M1_M1,
4771 : PseudoVLOXSEG6EI32_V_M1_M1_MASK,
4772 : PseudoVLOXSEG6EI32_V_M1_MF2,
4773 : PseudoVLOXSEG6EI32_V_M1_MF2_MASK,
4774 : PseudoVLOXSEG6EI32_V_M1_MF4,
4775 : PseudoVLOXSEG6EI32_V_M1_MF4_MASK,
4776 : PseudoVLOXSEG6EI32_V_M2_M1,
4777 : PseudoVLOXSEG6EI32_V_M2_M1_MASK,
4778 : PseudoVLOXSEG6EI32_V_M2_MF2,
4779 : PseudoVLOXSEG6EI32_V_M2_MF2_MASK,
4780 : PseudoVLOXSEG6EI32_V_M4_M1,
4781 : PseudoVLOXSEG6EI32_V_M4_M1_MASK,
4782 : PseudoVLOXSEG6EI32_V_MF2_M1,
4783 : PseudoVLOXSEG6EI32_V_MF2_M1_MASK,
4784 : PseudoVLOXSEG6EI32_V_MF2_MF2,
4785 : PseudoVLOXSEG6EI32_V_MF2_MF2_MASK,
4786 : PseudoVLOXSEG6EI32_V_MF2_MF4,
4787 : PseudoVLOXSEG6EI32_V_MF2_MF4_MASK,
4788 : PseudoVLOXSEG6EI32_V_MF2_MF8,
4789 : PseudoVLOXSEG6EI32_V_MF2_MF8_MASK,
4790 : PseudoVLOXSEG6EI64_V_M1_M1,
4791 : PseudoVLOXSEG6EI64_V_M1_M1_MASK,
4792 : PseudoVLOXSEG6EI64_V_M1_MF2,
4793 : PseudoVLOXSEG6EI64_V_M1_MF2_MASK,
4794 : PseudoVLOXSEG6EI64_V_M1_MF4,
4795 : PseudoVLOXSEG6EI64_V_M1_MF4_MASK,
4796 : PseudoVLOXSEG6EI64_V_M1_MF8,
4797 : PseudoVLOXSEG6EI64_V_M1_MF8_MASK,
4798 : PseudoVLOXSEG6EI64_V_M2_M1,
4799 : PseudoVLOXSEG6EI64_V_M2_M1_MASK,
4800 : PseudoVLOXSEG6EI64_V_M2_MF2,
4801 : PseudoVLOXSEG6EI64_V_M2_MF2_MASK,
4802 : PseudoVLOXSEG6EI64_V_M2_MF4,
4803 : PseudoVLOXSEG6EI64_V_M2_MF4_MASK,
4804 : PseudoVLOXSEG6EI64_V_M4_M1,
4805 : PseudoVLOXSEG6EI64_V_M4_M1_MASK,
4806 : PseudoVLOXSEG6EI64_V_M4_MF2,
4807 : PseudoVLOXSEG6EI64_V_M4_MF2_MASK,
4808 : PseudoVLOXSEG6EI64_V_M8_M1,
4809 : PseudoVLOXSEG6EI64_V_M8_M1_MASK,
4810 : PseudoVLOXSEG6EI8_V_M1_M1,
4811 : PseudoVLOXSEG6EI8_V_M1_M1_MASK,
4812 : PseudoVLOXSEG6EI8_V_MF2_M1,
4813 : PseudoVLOXSEG6EI8_V_MF2_M1_MASK,
4814 : PseudoVLOXSEG6EI8_V_MF2_MF2,
4815 : PseudoVLOXSEG6EI8_V_MF2_MF2_MASK,
4816 : PseudoVLOXSEG6EI8_V_MF4_M1,
4817 : PseudoVLOXSEG6EI8_V_MF4_M1_MASK,
4818 : PseudoVLOXSEG6EI8_V_MF4_MF2,
4819 : PseudoVLOXSEG6EI8_V_MF4_MF2_MASK,
4820 : PseudoVLOXSEG6EI8_V_MF4_MF4,
4821 : PseudoVLOXSEG6EI8_V_MF4_MF4_MASK,
4822 : PseudoVLOXSEG6EI8_V_MF8_M1,
4823 : PseudoVLOXSEG6EI8_V_MF8_M1_MASK,
4824 : PseudoVLOXSEG6EI8_V_MF8_MF2,
4825 : PseudoVLOXSEG6EI8_V_MF8_MF2_MASK,
4826 : PseudoVLOXSEG6EI8_V_MF8_MF4,
4827 : PseudoVLOXSEG6EI8_V_MF8_MF4_MASK,
4828 : PseudoVLOXSEG6EI8_V_MF8_MF8,
4829 : PseudoVLOXSEG6EI8_V_MF8_MF8_MASK,
4830 : PseudoVLOXSEG7EI16_V_M1_M1,
4831 : PseudoVLOXSEG7EI16_V_M1_M1_MASK,
4832 : PseudoVLOXSEG7EI16_V_M1_MF2,
4833 : PseudoVLOXSEG7EI16_V_M1_MF2_MASK,
4834 : PseudoVLOXSEG7EI16_V_M2_M1,
4835 : PseudoVLOXSEG7EI16_V_M2_M1_MASK,
4836 : PseudoVLOXSEG7EI16_V_MF2_M1,
4837 : PseudoVLOXSEG7EI16_V_MF2_M1_MASK,
4838 : PseudoVLOXSEG7EI16_V_MF2_MF2,
4839 : PseudoVLOXSEG7EI16_V_MF2_MF2_MASK,
4840 : PseudoVLOXSEG7EI16_V_MF2_MF4,
4841 : PseudoVLOXSEG7EI16_V_MF2_MF4_MASK,
4842 : PseudoVLOXSEG7EI16_V_MF4_M1,
4843 : PseudoVLOXSEG7EI16_V_MF4_M1_MASK,
4844 : PseudoVLOXSEG7EI16_V_MF4_MF2,
4845 : PseudoVLOXSEG7EI16_V_MF4_MF2_MASK,
4846 : PseudoVLOXSEG7EI16_V_MF4_MF4,
4847 : PseudoVLOXSEG7EI16_V_MF4_MF4_MASK,
4848 : PseudoVLOXSEG7EI16_V_MF4_MF8,
4849 : PseudoVLOXSEG7EI16_V_MF4_MF8_MASK,
4850 : PseudoVLOXSEG7EI32_V_M1_M1,
4851 : PseudoVLOXSEG7EI32_V_M1_M1_MASK,
4852 : PseudoVLOXSEG7EI32_V_M1_MF2,
4853 : PseudoVLOXSEG7EI32_V_M1_MF2_MASK,
4854 : PseudoVLOXSEG7EI32_V_M1_MF4,
4855 : PseudoVLOXSEG7EI32_V_M1_MF4_MASK,
4856 : PseudoVLOXSEG7EI32_V_M2_M1,
4857 : PseudoVLOXSEG7EI32_V_M2_M1_MASK,
4858 : PseudoVLOXSEG7EI32_V_M2_MF2,
4859 : PseudoVLOXSEG7EI32_V_M2_MF2_MASK,
4860 : PseudoVLOXSEG7EI32_V_M4_M1,
4861 : PseudoVLOXSEG7EI32_V_M4_M1_MASK,
4862 : PseudoVLOXSEG7EI32_V_MF2_M1,
4863 : PseudoVLOXSEG7EI32_V_MF2_M1_MASK,
4864 : PseudoVLOXSEG7EI32_V_MF2_MF2,
4865 : PseudoVLOXSEG7EI32_V_MF2_MF2_MASK,
4866 : PseudoVLOXSEG7EI32_V_MF2_MF4,
4867 : PseudoVLOXSEG7EI32_V_MF2_MF4_MASK,
4868 : PseudoVLOXSEG7EI32_V_MF2_MF8,
4869 : PseudoVLOXSEG7EI32_V_MF2_MF8_MASK,
4870 : PseudoVLOXSEG7EI64_V_M1_M1,
4871 : PseudoVLOXSEG7EI64_V_M1_M1_MASK,
4872 : PseudoVLOXSEG7EI64_V_M1_MF2,
4873 : PseudoVLOXSEG7EI64_V_M1_MF2_MASK,
4874 : PseudoVLOXSEG7EI64_V_M1_MF4,
4875 : PseudoVLOXSEG7EI64_V_M1_MF4_MASK,
4876 : PseudoVLOXSEG7EI64_V_M1_MF8,
4877 : PseudoVLOXSEG7EI64_V_M1_MF8_MASK,
4878 : PseudoVLOXSEG7EI64_V_M2_M1,
4879 : PseudoVLOXSEG7EI64_V_M2_M1_MASK,
4880 : PseudoVLOXSEG7EI64_V_M2_MF2,
4881 : PseudoVLOXSEG7EI64_V_M2_MF2_MASK,
4882 : PseudoVLOXSEG7EI64_V_M2_MF4,
4883 : PseudoVLOXSEG7EI64_V_M2_MF4_MASK,
4884 : PseudoVLOXSEG7EI64_V_M4_M1,
4885 : PseudoVLOXSEG7EI64_V_M4_M1_MASK,
4886 : PseudoVLOXSEG7EI64_V_M4_MF2,
4887 : PseudoVLOXSEG7EI64_V_M4_MF2_MASK,
4888 : PseudoVLOXSEG7EI64_V_M8_M1,
4889 : PseudoVLOXSEG7EI64_V_M8_M1_MASK,
4890 : PseudoVLOXSEG7EI8_V_M1_M1,
4891 : PseudoVLOXSEG7EI8_V_M1_M1_MASK,
4892 : PseudoVLOXSEG7EI8_V_MF2_M1,
4893 : PseudoVLOXSEG7EI8_V_MF2_M1_MASK,
4894 : PseudoVLOXSEG7EI8_V_MF2_MF2,
4895 : PseudoVLOXSEG7EI8_V_MF2_MF2_MASK,
4896 : PseudoVLOXSEG7EI8_V_MF4_M1,
4897 : PseudoVLOXSEG7EI8_V_MF4_M1_MASK,
4898 : PseudoVLOXSEG7EI8_V_MF4_MF2,
4899 : PseudoVLOXSEG7EI8_V_MF4_MF2_MASK,
4900 : PseudoVLOXSEG7EI8_V_MF4_MF4,
4901 : PseudoVLOXSEG7EI8_V_MF4_MF4_MASK,
4902 : PseudoVLOXSEG7EI8_V_MF8_M1,
4903 : PseudoVLOXSEG7EI8_V_MF8_M1_MASK,
4904 : PseudoVLOXSEG7EI8_V_MF8_MF2,
4905 : PseudoVLOXSEG7EI8_V_MF8_MF2_MASK,
4906 : PseudoVLOXSEG7EI8_V_MF8_MF4,
4907 : PseudoVLOXSEG7EI8_V_MF8_MF4_MASK,
4908 : PseudoVLOXSEG7EI8_V_MF8_MF8,
4909 : PseudoVLOXSEG7EI8_V_MF8_MF8_MASK,
4910 : PseudoVLOXSEG8EI16_V_M1_M1,
4911 : PseudoVLOXSEG8EI16_V_M1_M1_MASK,
4912 : PseudoVLOXSEG8EI16_V_M1_MF2,
4913 : PseudoVLOXSEG8EI16_V_M1_MF2_MASK,
4914 : PseudoVLOXSEG8EI16_V_M2_M1,
4915 : PseudoVLOXSEG8EI16_V_M2_M1_MASK,
4916 : PseudoVLOXSEG8EI16_V_MF2_M1,
4917 : PseudoVLOXSEG8EI16_V_MF2_M1_MASK,
4918 : PseudoVLOXSEG8EI16_V_MF2_MF2,
4919 : PseudoVLOXSEG8EI16_V_MF2_MF2_MASK,
4920 : PseudoVLOXSEG8EI16_V_MF2_MF4,
4921 : PseudoVLOXSEG8EI16_V_MF2_MF4_MASK,
4922 : PseudoVLOXSEG8EI16_V_MF4_M1,
4923 : PseudoVLOXSEG8EI16_V_MF4_M1_MASK,
4924 : PseudoVLOXSEG8EI16_V_MF4_MF2,
4925 : PseudoVLOXSEG8EI16_V_MF4_MF2_MASK,
4926 : PseudoVLOXSEG8EI16_V_MF4_MF4,
4927 : PseudoVLOXSEG8EI16_V_MF4_MF4_MASK,
4928 : PseudoVLOXSEG8EI16_V_MF4_MF8,
4929 : PseudoVLOXSEG8EI16_V_MF4_MF8_MASK,
4930 : PseudoVLOXSEG8EI32_V_M1_M1,
4931 : PseudoVLOXSEG8EI32_V_M1_M1_MASK,
4932 : PseudoVLOXSEG8EI32_V_M1_MF2,
4933 : PseudoVLOXSEG8EI32_V_M1_MF2_MASK,
4934 : PseudoVLOXSEG8EI32_V_M1_MF4,
4935 : PseudoVLOXSEG8EI32_V_M1_MF4_MASK,
4936 : PseudoVLOXSEG8EI32_V_M2_M1,
4937 : PseudoVLOXSEG8EI32_V_M2_M1_MASK,
4938 : PseudoVLOXSEG8EI32_V_M2_MF2,
4939 : PseudoVLOXSEG8EI32_V_M2_MF2_MASK,
4940 : PseudoVLOXSEG8EI32_V_M4_M1,
4941 : PseudoVLOXSEG8EI32_V_M4_M1_MASK,
4942 : PseudoVLOXSEG8EI32_V_MF2_M1,
4943 : PseudoVLOXSEG8EI32_V_MF2_M1_MASK,
4944 : PseudoVLOXSEG8EI32_V_MF2_MF2,
4945 : PseudoVLOXSEG8EI32_V_MF2_MF2_MASK,
4946 : PseudoVLOXSEG8EI32_V_MF2_MF4,
4947 : PseudoVLOXSEG8EI32_V_MF2_MF4_MASK,
4948 : PseudoVLOXSEG8EI32_V_MF2_MF8,
4949 : PseudoVLOXSEG8EI32_V_MF2_MF8_MASK,
4950 : PseudoVLOXSEG8EI64_V_M1_M1,
4951 : PseudoVLOXSEG8EI64_V_M1_M1_MASK,
4952 : PseudoVLOXSEG8EI64_V_M1_MF2,
4953 : PseudoVLOXSEG8EI64_V_M1_MF2_MASK,
4954 : PseudoVLOXSEG8EI64_V_M1_MF4,
4955 : PseudoVLOXSEG8EI64_V_M1_MF4_MASK,
4956 : PseudoVLOXSEG8EI64_V_M1_MF8,
4957 : PseudoVLOXSEG8EI64_V_M1_MF8_MASK,
4958 : PseudoVLOXSEG8EI64_V_M2_M1,
4959 : PseudoVLOXSEG8EI64_V_M2_M1_MASK,
4960 : PseudoVLOXSEG8EI64_V_M2_MF2,
4961 : PseudoVLOXSEG8EI64_V_M2_MF2_MASK,
4962 : PseudoVLOXSEG8EI64_V_M2_MF4,
4963 : PseudoVLOXSEG8EI64_V_M2_MF4_MASK,
4964 : PseudoVLOXSEG8EI64_V_M4_M1,
4965 : PseudoVLOXSEG8EI64_V_M4_M1_MASK,
4966 : PseudoVLOXSEG8EI64_V_M4_MF2,
4967 : PseudoVLOXSEG8EI64_V_M4_MF2_MASK,
4968 : PseudoVLOXSEG8EI64_V_M8_M1,
4969 : PseudoVLOXSEG8EI64_V_M8_M1_MASK,
4970 : PseudoVLOXSEG8EI8_V_M1_M1,
4971 : PseudoVLOXSEG8EI8_V_M1_M1_MASK,
4972 : PseudoVLOXSEG8EI8_V_MF2_M1,
4973 : PseudoVLOXSEG8EI8_V_MF2_M1_MASK,
4974 : PseudoVLOXSEG8EI8_V_MF2_MF2,
4975 : PseudoVLOXSEG8EI8_V_MF2_MF2_MASK,
4976 : PseudoVLOXSEG8EI8_V_MF4_M1,
4977 : PseudoVLOXSEG8EI8_V_MF4_M1_MASK,
4978 : PseudoVLOXSEG8EI8_V_MF4_MF2,
4979 : PseudoVLOXSEG8EI8_V_MF4_MF2_MASK,
4980 : PseudoVLOXSEG8EI8_V_MF4_MF4,
4981 : PseudoVLOXSEG8EI8_V_MF4_MF4_MASK,
4982 : PseudoVLOXSEG8EI8_V_MF8_M1,
4983 : PseudoVLOXSEG8EI8_V_MF8_M1_MASK,
4984 : PseudoVLOXSEG8EI8_V_MF8_MF2,
4985 : PseudoVLOXSEG8EI8_V_MF8_MF2_MASK,
4986 : PseudoVLOXSEG8EI8_V_MF8_MF4,
4987 : PseudoVLOXSEG8EI8_V_MF8_MF4_MASK,
4988 : PseudoVLOXSEG8EI8_V_MF8_MF8,
4989 : PseudoVLOXSEG8EI8_V_MF8_MF8_MASK,
4990 : PseudoVLSE16_V_M1,
4991 : PseudoVLSE16_V_M1_MASK,
4992 : PseudoVLSE16_V_M2,
4993 : PseudoVLSE16_V_M2_MASK,
4994 : PseudoVLSE16_V_M4,
4995 : PseudoVLSE16_V_M4_MASK,
4996 : PseudoVLSE16_V_M8,
4997 : PseudoVLSE16_V_M8_MASK,
4998 : PseudoVLSE16_V_MF2,
4999 : PseudoVLSE16_V_MF2_MASK,
5000 : PseudoVLSE16_V_MF4,
5001 : PseudoVLSE16_V_MF4_MASK,
5002 : PseudoVLSE32_V_M1,
5003 : PseudoVLSE32_V_M1_MASK,
5004 : PseudoVLSE32_V_M2,
5005 : PseudoVLSE32_V_M2_MASK,
5006 : PseudoVLSE32_V_M4,
5007 : PseudoVLSE32_V_M4_MASK,
5008 : PseudoVLSE32_V_M8,
5009 : PseudoVLSE32_V_M8_MASK,
5010 : PseudoVLSE32_V_MF2,
5011 : PseudoVLSE32_V_MF2_MASK,
5012 : PseudoVLSE64_V_M1,
5013 : PseudoVLSE64_V_M1_MASK,
5014 : PseudoVLSE64_V_M2,
5015 : PseudoVLSE64_V_M2_MASK,
5016 : PseudoVLSE64_V_M4,
5017 : PseudoVLSE64_V_M4_MASK,
5018 : PseudoVLSE64_V_M8,
5019 : PseudoVLSE64_V_M8_MASK,
5020 : PseudoVLSE8_V_M1,
5021 : PseudoVLSE8_V_M1_MASK,
5022 : PseudoVLSE8_V_M2,
5023 : PseudoVLSE8_V_M2_MASK,
5024 : PseudoVLSE8_V_M4,
5025 : PseudoVLSE8_V_M4_MASK,
5026 : PseudoVLSE8_V_M8,
5027 : PseudoVLSE8_V_M8_MASK,
5028 : PseudoVLSE8_V_MF2,
5029 : PseudoVLSE8_V_MF2_MASK,
5030 : PseudoVLSE8_V_MF4,
5031 : PseudoVLSE8_V_MF4_MASK,
5032 : PseudoVLSE8_V_MF8,
5033 : PseudoVLSE8_V_MF8_MASK,
5034 : PseudoVLSEG2E16FF_V_M1,
5035 : PseudoVLSEG2E16FF_V_M1_MASK,
5036 : PseudoVLSEG2E16FF_V_M2,
5037 : PseudoVLSEG2E16FF_V_M2_MASK,
5038 : PseudoVLSEG2E16FF_V_M4,
5039 : PseudoVLSEG2E16FF_V_M4_MASK,
5040 : PseudoVLSEG2E16FF_V_MF2,
5041 : PseudoVLSEG2E16FF_V_MF2_MASK,
5042 : PseudoVLSEG2E16FF_V_MF4,
5043 : PseudoVLSEG2E16FF_V_MF4_MASK,
5044 : PseudoVLSEG2E16_V_M1,
5045 : PseudoVLSEG2E16_V_M1_MASK,
5046 : PseudoVLSEG2E16_V_M2,
5047 : PseudoVLSEG2E16_V_M2_MASK,
5048 : PseudoVLSEG2E16_V_M4,
5049 : PseudoVLSEG2E16_V_M4_MASK,
5050 : PseudoVLSEG2E16_V_MF2,
5051 : PseudoVLSEG2E16_V_MF2_MASK,
5052 : PseudoVLSEG2E16_V_MF4,
5053 : PseudoVLSEG2E16_V_MF4_MASK,
5054 : PseudoVLSEG2E32FF_V_M1,
5055 : PseudoVLSEG2E32FF_V_M1_MASK,
5056 : PseudoVLSEG2E32FF_V_M2,
5057 : PseudoVLSEG2E32FF_V_M2_MASK,
5058 : PseudoVLSEG2E32FF_V_M4,
5059 : PseudoVLSEG2E32FF_V_M4_MASK,
5060 : PseudoVLSEG2E32FF_V_MF2,
5061 : PseudoVLSEG2E32FF_V_MF2_MASK,
5062 : PseudoVLSEG2E32_V_M1,
5063 : PseudoVLSEG2E32_V_M1_MASK,
5064 : PseudoVLSEG2E32_V_M2,
5065 : PseudoVLSEG2E32_V_M2_MASK,
5066 : PseudoVLSEG2E32_V_M4,
5067 : PseudoVLSEG2E32_V_M4_MASK,
5068 : PseudoVLSEG2E32_V_MF2,
5069 : PseudoVLSEG2E32_V_MF2_MASK,
5070 : PseudoVLSEG2E64FF_V_M1,
5071 : PseudoVLSEG2E64FF_V_M1_MASK,
5072 : PseudoVLSEG2E64FF_V_M2,
5073 : PseudoVLSEG2E64FF_V_M2_MASK,
5074 : PseudoVLSEG2E64FF_V_M4,
5075 : PseudoVLSEG2E64FF_V_M4_MASK,
5076 : PseudoVLSEG2E64_V_M1,
5077 : PseudoVLSEG2E64_V_M1_MASK,
5078 : PseudoVLSEG2E64_V_M2,
5079 : PseudoVLSEG2E64_V_M2_MASK,
5080 : PseudoVLSEG2E64_V_M4,
5081 : PseudoVLSEG2E64_V_M4_MASK,
5082 : PseudoVLSEG2E8FF_V_M1,
5083 : PseudoVLSEG2E8FF_V_M1_MASK,
5084 : PseudoVLSEG2E8FF_V_M2,
5085 : PseudoVLSEG2E8FF_V_M2_MASK,
5086 : PseudoVLSEG2E8FF_V_M4,
5087 : PseudoVLSEG2E8FF_V_M4_MASK,
5088 : PseudoVLSEG2E8FF_V_MF2,
5089 : PseudoVLSEG2E8FF_V_MF2_MASK,
5090 : PseudoVLSEG2E8FF_V_MF4,
5091 : PseudoVLSEG2E8FF_V_MF4_MASK,
5092 : PseudoVLSEG2E8FF_V_MF8,
5093 : PseudoVLSEG2E8FF_V_MF8_MASK,
5094 : PseudoVLSEG2E8_V_M1,
5095 : PseudoVLSEG2E8_V_M1_MASK,
5096 : PseudoVLSEG2E8_V_M2,
5097 : PseudoVLSEG2E8_V_M2_MASK,
5098 : PseudoVLSEG2E8_V_M4,
5099 : PseudoVLSEG2E8_V_M4_MASK,
5100 : PseudoVLSEG2E8_V_MF2,
5101 : PseudoVLSEG2E8_V_MF2_MASK,
5102 : PseudoVLSEG2E8_V_MF4,
5103 : PseudoVLSEG2E8_V_MF4_MASK,
5104 : PseudoVLSEG2E8_V_MF8,
5105 : PseudoVLSEG2E8_V_MF8_MASK,
5106 : PseudoVLSEG3E16FF_V_M1,
5107 : PseudoVLSEG3E16FF_V_M1_MASK,
5108 : PseudoVLSEG3E16FF_V_M2,
5109 : PseudoVLSEG3E16FF_V_M2_MASK,
5110 : PseudoVLSEG3E16FF_V_MF2,
5111 : PseudoVLSEG3E16FF_V_MF2_MASK,
5112 : PseudoVLSEG3E16FF_V_MF4,
5113 : PseudoVLSEG3E16FF_V_MF4_MASK,
5114 : PseudoVLSEG3E16_V_M1,
5115 : PseudoVLSEG3E16_V_M1_MASK,
5116 : PseudoVLSEG3E16_V_M2,
5117 : PseudoVLSEG3E16_V_M2_MASK,
5118 : PseudoVLSEG3E16_V_MF2,
5119 : PseudoVLSEG3E16_V_MF2_MASK,
5120 : PseudoVLSEG3E16_V_MF4,
5121 : PseudoVLSEG3E16_V_MF4_MASK,
5122 : PseudoVLSEG3E32FF_V_M1,
5123 : PseudoVLSEG3E32FF_V_M1_MASK,
5124 : PseudoVLSEG3E32FF_V_M2,
5125 : PseudoVLSEG3E32FF_V_M2_MASK,
5126 : PseudoVLSEG3E32FF_V_MF2,
5127 : PseudoVLSEG3E32FF_V_MF2_MASK,
5128 : PseudoVLSEG3E32_V_M1,
5129 : PseudoVLSEG3E32_V_M1_MASK,
5130 : PseudoVLSEG3E32_V_M2,
5131 : PseudoVLSEG3E32_V_M2_MASK,
5132 : PseudoVLSEG3E32_V_MF2,
5133 : PseudoVLSEG3E32_V_MF2_MASK,
5134 : PseudoVLSEG3E64FF_V_M1,
5135 : PseudoVLSEG3E64FF_V_M1_MASK,
5136 : PseudoVLSEG3E64FF_V_M2,
5137 : PseudoVLSEG3E64FF_V_M2_MASK,
5138 : PseudoVLSEG3E64_V_M1,
5139 : PseudoVLSEG3E64_V_M1_MASK,
5140 : PseudoVLSEG3E64_V_M2,
5141 : PseudoVLSEG3E64_V_M2_MASK,
5142 : PseudoVLSEG3E8FF_V_M1,
5143 : PseudoVLSEG3E8FF_V_M1_MASK,
5144 : PseudoVLSEG3E8FF_V_M2,
5145 : PseudoVLSEG3E8FF_V_M2_MASK,
5146 : PseudoVLSEG3E8FF_V_MF2,
5147 : PseudoVLSEG3E8FF_V_MF2_MASK,
5148 : PseudoVLSEG3E8FF_V_MF4,
5149 : PseudoVLSEG3E8FF_V_MF4_MASK,
5150 : PseudoVLSEG3E8FF_V_MF8,
5151 : PseudoVLSEG3E8FF_V_MF8_MASK,
5152 : PseudoVLSEG3E8_V_M1,
5153 : PseudoVLSEG3E8_V_M1_MASK,
5154 : PseudoVLSEG3E8_V_M2,
5155 : PseudoVLSEG3E8_V_M2_MASK,
5156 : PseudoVLSEG3E8_V_MF2,
5157 : PseudoVLSEG3E8_V_MF2_MASK,
5158 : PseudoVLSEG3E8_V_MF4,
5159 : PseudoVLSEG3E8_V_MF4_MASK,
5160 : PseudoVLSEG3E8_V_MF8,
5161 : PseudoVLSEG3E8_V_MF8_MASK,
5162 : PseudoVLSEG4E16FF_V_M1,
5163 : PseudoVLSEG4E16FF_V_M1_MASK,
5164 : PseudoVLSEG4E16FF_V_M2,
5165 : PseudoVLSEG4E16FF_V_M2_MASK,
5166 : PseudoVLSEG4E16FF_V_MF2,
5167 : PseudoVLSEG4E16FF_V_MF2_MASK,
5168 : PseudoVLSEG4E16FF_V_MF4,
5169 : PseudoVLSEG4E16FF_V_MF4_MASK,
5170 : PseudoVLSEG4E16_V_M1,
5171 : PseudoVLSEG4E16_V_M1_MASK,
5172 : PseudoVLSEG4E16_V_M2,
5173 : PseudoVLSEG4E16_V_M2_MASK,
5174 : PseudoVLSEG4E16_V_MF2,
5175 : PseudoVLSEG4E16_V_MF2_MASK,
5176 : PseudoVLSEG4E16_V_MF4,
5177 : PseudoVLSEG4E16_V_MF4_MASK,
5178 : PseudoVLSEG4E32FF_V_M1,
5179 : PseudoVLSEG4E32FF_V_M1_MASK,
5180 : PseudoVLSEG4E32FF_V_M2,
5181 : PseudoVLSEG4E32FF_V_M2_MASK,
5182 : PseudoVLSEG4E32FF_V_MF2,
5183 : PseudoVLSEG4E32FF_V_MF2_MASK,
5184 : PseudoVLSEG4E32_V_M1,
5185 : PseudoVLSEG4E32_V_M1_MASK,
5186 : PseudoVLSEG4E32_V_M2,
5187 : PseudoVLSEG4E32_V_M2_MASK,
5188 : PseudoVLSEG4E32_V_MF2,
5189 : PseudoVLSEG4E32_V_MF2_MASK,
5190 : PseudoVLSEG4E64FF_V_M1,
5191 : PseudoVLSEG4E64FF_V_M1_MASK,
5192 : PseudoVLSEG4E64FF_V_M2,
5193 : PseudoVLSEG4E64FF_V_M2_MASK,
5194 : PseudoVLSEG4E64_V_M1,
5195 : PseudoVLSEG4E64_V_M1_MASK,
5196 : PseudoVLSEG4E64_V_M2,
5197 : PseudoVLSEG4E64_V_M2_MASK,
5198 : PseudoVLSEG4E8FF_V_M1,
5199 : PseudoVLSEG4E8FF_V_M1_MASK,
5200 : PseudoVLSEG4E8FF_V_M2,
5201 : PseudoVLSEG4E8FF_V_M2_MASK,
5202 : PseudoVLSEG4E8FF_V_MF2,
5203 : PseudoVLSEG4E8FF_V_MF2_MASK,
5204 : PseudoVLSEG4E8FF_V_MF4,
5205 : PseudoVLSEG4E8FF_V_MF4_MASK,
5206 : PseudoVLSEG4E8FF_V_MF8,
5207 : PseudoVLSEG4E8FF_V_MF8_MASK,
5208 : PseudoVLSEG4E8_V_M1,
5209 : PseudoVLSEG4E8_V_M1_MASK,
5210 : PseudoVLSEG4E8_V_M2,
5211 : PseudoVLSEG4E8_V_M2_MASK,
5212 : PseudoVLSEG4E8_V_MF2,
5213 : PseudoVLSEG4E8_V_MF2_MASK,
5214 : PseudoVLSEG4E8_V_MF4,
5215 : PseudoVLSEG4E8_V_MF4_MASK,
5216 : PseudoVLSEG4E8_V_MF8,
5217 : PseudoVLSEG4E8_V_MF8_MASK,
5218 : PseudoVLSEG5E16FF_V_M1,
5219 : PseudoVLSEG5E16FF_V_M1_MASK,
5220 : PseudoVLSEG5E16FF_V_MF2,
5221 : PseudoVLSEG5E16FF_V_MF2_MASK,
5222 : PseudoVLSEG5E16FF_V_MF4,
5223 : PseudoVLSEG5E16FF_V_MF4_MASK,
5224 : PseudoVLSEG5E16_V_M1,
5225 : PseudoVLSEG5E16_V_M1_MASK,
5226 : PseudoVLSEG5E16_V_MF2,
5227 : PseudoVLSEG5E16_V_MF2_MASK,
5228 : PseudoVLSEG5E16_V_MF4,
5229 : PseudoVLSEG5E16_V_MF4_MASK,
5230 : PseudoVLSEG5E32FF_V_M1,
5231 : PseudoVLSEG5E32FF_V_M1_MASK,
5232 : PseudoVLSEG5E32FF_V_MF2,
5233 : PseudoVLSEG5E32FF_V_MF2_MASK,
5234 : PseudoVLSEG5E32_V_M1,
5235 : PseudoVLSEG5E32_V_M1_MASK,
5236 : PseudoVLSEG5E32_V_MF2,
5237 : PseudoVLSEG5E32_V_MF2_MASK,
5238 : PseudoVLSEG5E64FF_V_M1,
5239 : PseudoVLSEG5E64FF_V_M1_MASK,
5240 : PseudoVLSEG5E64_V_M1,
5241 : PseudoVLSEG5E64_V_M1_MASK,
5242 : PseudoVLSEG5E8FF_V_M1,
5243 : PseudoVLSEG5E8FF_V_M1_MASK,
5244 : PseudoVLSEG5E8FF_V_MF2,
5245 : PseudoVLSEG5E8FF_V_MF2_MASK,
5246 : PseudoVLSEG5E8FF_V_MF4,
5247 : PseudoVLSEG5E8FF_V_MF4_MASK,
5248 : PseudoVLSEG5E8FF_V_MF8,
5249 : PseudoVLSEG5E8FF_V_MF8_MASK,
5250 : PseudoVLSEG5E8_V_M1,
5251 : PseudoVLSEG5E8_V_M1_MASK,
5252 : PseudoVLSEG5E8_V_MF2,
5253 : PseudoVLSEG5E8_V_MF2_MASK,
5254 : PseudoVLSEG5E8_V_MF4,
5255 : PseudoVLSEG5E8_V_MF4_MASK,
5256 : PseudoVLSEG5E8_V_MF8,
5257 : PseudoVLSEG5E8_V_MF8_MASK,
5258 : PseudoVLSEG6E16FF_V_M1,
5259 : PseudoVLSEG6E16FF_V_M1_MASK,
5260 : PseudoVLSEG6E16FF_V_MF2,
5261 : PseudoVLSEG6E16FF_V_MF2_MASK,
5262 : PseudoVLSEG6E16FF_V_MF4,
5263 : PseudoVLSEG6E16FF_V_MF4_MASK,
5264 : PseudoVLSEG6E16_V_M1,
5265 : PseudoVLSEG6E16_V_M1_MASK,
5266 : PseudoVLSEG6E16_V_MF2,
5267 : PseudoVLSEG6E16_V_MF2_MASK,
5268 : PseudoVLSEG6E16_V_MF4,
5269 : PseudoVLSEG6E16_V_MF4_MASK,
5270 : PseudoVLSEG6E32FF_V_M1,
5271 : PseudoVLSEG6E32FF_V_M1_MASK,
5272 : PseudoVLSEG6E32FF_V_MF2,
5273 : PseudoVLSEG6E32FF_V_MF2_MASK,
5274 : PseudoVLSEG6E32_V_M1,
5275 : PseudoVLSEG6E32_V_M1_MASK,
5276 : PseudoVLSEG6E32_V_MF2,
5277 : PseudoVLSEG6E32_V_MF2_MASK,
5278 : PseudoVLSEG6E64FF_V_M1,
5279 : PseudoVLSEG6E64FF_V_M1_MASK,
5280 : PseudoVLSEG6E64_V_M1,
5281 : PseudoVLSEG6E64_V_M1_MASK,
5282 : PseudoVLSEG6E8FF_V_M1,
5283 : PseudoVLSEG6E8FF_V_M1_MASK,
5284 : PseudoVLSEG6E8FF_V_MF2,
5285 : PseudoVLSEG6E8FF_V_MF2_MASK,
5286 : PseudoVLSEG6E8FF_V_MF4,
5287 : PseudoVLSEG6E8FF_V_MF4_MASK,
5288 : PseudoVLSEG6E8FF_V_MF8,
5289 : PseudoVLSEG6E8FF_V_MF8_MASK,
5290 : PseudoVLSEG6E8_V_M1,
5291 : PseudoVLSEG6E8_V_M1_MASK,
5292 : PseudoVLSEG6E8_V_MF2,
5293 : PseudoVLSEG6E8_V_MF2_MASK,
5294 : PseudoVLSEG6E8_V_MF4,
5295 : PseudoVLSEG6E8_V_MF4_MASK,
5296 : PseudoVLSEG6E8_V_MF8,
5297 : PseudoVLSEG6E8_V_MF8_MASK,
5298 : PseudoVLSEG7E16FF_V_M1,
5299 : PseudoVLSEG7E16FF_V_M1_MASK,
5300 : PseudoVLSEG7E16FF_V_MF2,
5301 : PseudoVLSEG7E16FF_V_MF2_MASK,
5302 : PseudoVLSEG7E16FF_V_MF4,
5303 : PseudoVLSEG7E16FF_V_MF4_MASK,
5304 : PseudoVLSEG7E16_V_M1,
5305 : PseudoVLSEG7E16_V_M1_MASK,
5306 : PseudoVLSEG7E16_V_MF2,
5307 : PseudoVLSEG7E16_V_MF2_MASK,
5308 : PseudoVLSEG7E16_V_MF4,
5309 : PseudoVLSEG7E16_V_MF4_MASK,
5310 : PseudoVLSEG7E32FF_V_M1,
5311 : PseudoVLSEG7E32FF_V_M1_MASK,
5312 : PseudoVLSEG7E32FF_V_MF2,
5313 : PseudoVLSEG7E32FF_V_MF2_MASK,
5314 : PseudoVLSEG7E32_V_M1,
5315 : PseudoVLSEG7E32_V_M1_MASK,
5316 : PseudoVLSEG7E32_V_MF2,
5317 : PseudoVLSEG7E32_V_MF2_MASK,
5318 : PseudoVLSEG7E64FF_V_M1,
5319 : PseudoVLSEG7E64FF_V_M1_MASK,
5320 : PseudoVLSEG7E64_V_M1,
5321 : PseudoVLSEG7E64_V_M1_MASK,
5322 : PseudoVLSEG7E8FF_V_M1,
5323 : PseudoVLSEG7E8FF_V_M1_MASK,
5324 : PseudoVLSEG7E8FF_V_MF2,
5325 : PseudoVLSEG7E8FF_V_MF2_MASK,
5326 : PseudoVLSEG7E8FF_V_MF4,
5327 : PseudoVLSEG7E8FF_V_MF4_MASK,
5328 : PseudoVLSEG7E8FF_V_MF8,
5329 : PseudoVLSEG7E8FF_V_MF8_MASK,
5330 : PseudoVLSEG7E8_V_M1,
5331 : PseudoVLSEG7E8_V_M1_MASK,
5332 : PseudoVLSEG7E8_V_MF2,
5333 : PseudoVLSEG7E8_V_MF2_MASK,
5334 : PseudoVLSEG7E8_V_MF4,
5335 : PseudoVLSEG7E8_V_MF4_MASK,
5336 : PseudoVLSEG7E8_V_MF8,
5337 : PseudoVLSEG7E8_V_MF8_MASK,
5338 : PseudoVLSEG8E16FF_V_M1,
5339 : PseudoVLSEG8E16FF_V_M1_MASK,
5340 : PseudoVLSEG8E16FF_V_MF2,
5341 : PseudoVLSEG8E16FF_V_MF2_MASK,
5342 : PseudoVLSEG8E16FF_V_MF4,
5343 : PseudoVLSEG8E16FF_V_MF4_MASK,
5344 : PseudoVLSEG8E16_V_M1,
5345 : PseudoVLSEG8E16_V_M1_MASK,
5346 : PseudoVLSEG8E16_V_MF2,
5347 : PseudoVLSEG8E16_V_MF2_MASK,
5348 : PseudoVLSEG8E16_V_MF4,
5349 : PseudoVLSEG8E16_V_MF4_MASK,
5350 : PseudoVLSEG8E32FF_V_M1,
5351 : PseudoVLSEG8E32FF_V_M1_MASK,
5352 : PseudoVLSEG8E32FF_V_MF2,
5353 : PseudoVLSEG8E32FF_V_MF2_MASK,
5354 : PseudoVLSEG8E32_V_M1,
5355 : PseudoVLSEG8E32_V_M1_MASK,
5356 : PseudoVLSEG8E32_V_MF2,
5357 : PseudoVLSEG8E32_V_MF2_MASK,
5358 : PseudoVLSEG8E64FF_V_M1,
5359 : PseudoVLSEG8E64FF_V_M1_MASK,
5360 : PseudoVLSEG8E64_V_M1,
5361 : PseudoVLSEG8E64_V_M1_MASK,
5362 : PseudoVLSEG8E8FF_V_M1,
5363 : PseudoVLSEG8E8FF_V_M1_MASK,
5364 : PseudoVLSEG8E8FF_V_MF2,
5365 : PseudoVLSEG8E8FF_V_MF2_MASK,
5366 : PseudoVLSEG8E8FF_V_MF4,
5367 : PseudoVLSEG8E8FF_V_MF4_MASK,
5368 : PseudoVLSEG8E8FF_V_MF8,
5369 : PseudoVLSEG8E8FF_V_MF8_MASK,
5370 : PseudoVLSEG8E8_V_M1,
5371 : PseudoVLSEG8E8_V_M1_MASK,
5372 : PseudoVLSEG8E8_V_MF2,
5373 : PseudoVLSEG8E8_V_MF2_MASK,
5374 : PseudoVLSEG8E8_V_MF4,
5375 : PseudoVLSEG8E8_V_MF4_MASK,
5376 : PseudoVLSEG8E8_V_MF8,
5377 : PseudoVLSEG8E8_V_MF8_MASK,
5378 : PseudoVLSSEG2E16_V_M1,
5379 : PseudoVLSSEG2E16_V_M1_MASK,
5380 : PseudoVLSSEG2E16_V_M2,
5381 : PseudoVLSSEG2E16_V_M2_MASK,
5382 : PseudoVLSSEG2E16_V_M4,
5383 : PseudoVLSSEG2E16_V_M4_MASK,
5384 : PseudoVLSSEG2E16_V_MF2,
5385 : PseudoVLSSEG2E16_V_MF2_MASK,
5386 : PseudoVLSSEG2E16_V_MF4,
5387 : PseudoVLSSEG2E16_V_MF4_MASK,
5388 : PseudoVLSSEG2E32_V_M1,
5389 : PseudoVLSSEG2E32_V_M1_MASK,
5390 : PseudoVLSSEG2E32_V_M2,
5391 : PseudoVLSSEG2E32_V_M2_MASK,
5392 : PseudoVLSSEG2E32_V_M4,
5393 : PseudoVLSSEG2E32_V_M4_MASK,
5394 : PseudoVLSSEG2E32_V_MF2,
5395 : PseudoVLSSEG2E32_V_MF2_MASK,
5396 : PseudoVLSSEG2E64_V_M1,
5397 : PseudoVLSSEG2E64_V_M1_MASK,
5398 : PseudoVLSSEG2E64_V_M2,
5399 : PseudoVLSSEG2E64_V_M2_MASK,
5400 : PseudoVLSSEG2E64_V_M4,
5401 : PseudoVLSSEG2E64_V_M4_MASK,
5402 : PseudoVLSSEG2E8_V_M1,
5403 : PseudoVLSSEG2E8_V_M1_MASK,
5404 : PseudoVLSSEG2E8_V_M2,
5405 : PseudoVLSSEG2E8_V_M2_MASK,
5406 : PseudoVLSSEG2E8_V_M4,
5407 : PseudoVLSSEG2E8_V_M4_MASK,
5408 : PseudoVLSSEG2E8_V_MF2,
5409 : PseudoVLSSEG2E8_V_MF2_MASK,
5410 : PseudoVLSSEG2E8_V_MF4,
5411 : PseudoVLSSEG2E8_V_MF4_MASK,
5412 : PseudoVLSSEG2E8_V_MF8,
5413 : PseudoVLSSEG2E8_V_MF8_MASK,
5414 : PseudoVLSSEG3E16_V_M1,
5415 : PseudoVLSSEG3E16_V_M1_MASK,
5416 : PseudoVLSSEG3E16_V_M2,
5417 : PseudoVLSSEG3E16_V_M2_MASK,
5418 : PseudoVLSSEG3E16_V_MF2,
5419 : PseudoVLSSEG3E16_V_MF2_MASK,
5420 : PseudoVLSSEG3E16_V_MF4,
5421 : PseudoVLSSEG3E16_V_MF4_MASK,
5422 : PseudoVLSSEG3E32_V_M1,
5423 : PseudoVLSSEG3E32_V_M1_MASK,
5424 : PseudoVLSSEG3E32_V_M2,
5425 : PseudoVLSSEG3E32_V_M2_MASK,
5426 : PseudoVLSSEG3E32_V_MF2,
5427 : PseudoVLSSEG3E32_V_MF2_MASK,
5428 : PseudoVLSSEG3E64_V_M1,
5429 : PseudoVLSSEG3E64_V_M1_MASK,
5430 : PseudoVLSSEG3E64_V_M2,
5431 : PseudoVLSSEG3E64_V_M2_MASK,
5432 : PseudoVLSSEG3E8_V_M1,
5433 : PseudoVLSSEG3E8_V_M1_MASK,
5434 : PseudoVLSSEG3E8_V_M2,
5435 : PseudoVLSSEG3E8_V_M2_MASK,
5436 : PseudoVLSSEG3E8_V_MF2,
5437 : PseudoVLSSEG3E8_V_MF2_MASK,
5438 : PseudoVLSSEG3E8_V_MF4,
5439 : PseudoVLSSEG3E8_V_MF4_MASK,
5440 : PseudoVLSSEG3E8_V_MF8,
5441 : PseudoVLSSEG3E8_V_MF8_MASK,
5442 : PseudoVLSSEG4E16_V_M1,
5443 : PseudoVLSSEG4E16_V_M1_MASK,
5444 : PseudoVLSSEG4E16_V_M2,
5445 : PseudoVLSSEG4E16_V_M2_MASK,
5446 : PseudoVLSSEG4E16_V_MF2,
5447 : PseudoVLSSEG4E16_V_MF2_MASK,
5448 : PseudoVLSSEG4E16_V_MF4,
5449 : PseudoVLSSEG4E16_V_MF4_MASK,
5450 : PseudoVLSSEG4E32_V_M1,
5451 : PseudoVLSSEG4E32_V_M1_MASK,
5452 : PseudoVLSSEG4E32_V_M2,
5453 : PseudoVLSSEG4E32_V_M2_MASK,
5454 : PseudoVLSSEG4E32_V_MF2,
5455 : PseudoVLSSEG4E32_V_MF2_MASK,
5456 : PseudoVLSSEG4E64_V_M1,
5457 : PseudoVLSSEG4E64_V_M1_MASK,
5458 : PseudoVLSSEG4E64_V_M2,
5459 : PseudoVLSSEG4E64_V_M2_MASK,
5460 : PseudoVLSSEG4E8_V_M1,
5461 : PseudoVLSSEG4E8_V_M1_MASK,
5462 : PseudoVLSSEG4E8_V_M2,
5463 : PseudoVLSSEG4E8_V_M2_MASK,
5464 : PseudoVLSSEG4E8_V_MF2,
5465 : PseudoVLSSEG4E8_V_MF2_MASK,
5466 : PseudoVLSSEG4E8_V_MF4,
5467 : PseudoVLSSEG4E8_V_MF4_MASK,
5468 : PseudoVLSSEG4E8_V_MF8,
5469 : PseudoVLSSEG4E8_V_MF8_MASK,
5470 : PseudoVLSSEG5E16_V_M1,
5471 : PseudoVLSSEG5E16_V_M1_MASK,
5472 : PseudoVLSSEG5E16_V_MF2,
5473 : PseudoVLSSEG5E16_V_MF2_MASK,
5474 : PseudoVLSSEG5E16_V_MF4,
5475 : PseudoVLSSEG5E16_V_MF4_MASK,
5476 : PseudoVLSSEG5E32_V_M1,
5477 : PseudoVLSSEG5E32_V_M1_MASK,
5478 : PseudoVLSSEG5E32_V_MF2,
5479 : PseudoVLSSEG5E32_V_MF2_MASK,
5480 : PseudoVLSSEG5E64_V_M1,
5481 : PseudoVLSSEG5E64_V_M1_MASK,
5482 : PseudoVLSSEG5E8_V_M1,
5483 : PseudoVLSSEG5E8_V_M1_MASK,
5484 : PseudoVLSSEG5E8_V_MF2,
5485 : PseudoVLSSEG5E8_V_MF2_MASK,
5486 : PseudoVLSSEG5E8_V_MF4,
5487 : PseudoVLSSEG5E8_V_MF4_MASK,
5488 : PseudoVLSSEG5E8_V_MF8,
5489 : PseudoVLSSEG5E8_V_MF8_MASK,
5490 : PseudoVLSSEG6E16_V_M1,
5491 : PseudoVLSSEG6E16_V_M1_MASK,
5492 : PseudoVLSSEG6E16_V_MF2,
5493 : PseudoVLSSEG6E16_V_MF2_MASK,
5494 : PseudoVLSSEG6E16_V_MF4,
5495 : PseudoVLSSEG6E16_V_MF4_MASK,
5496 : PseudoVLSSEG6E32_V_M1,
5497 : PseudoVLSSEG6E32_V_M1_MASK,
5498 : PseudoVLSSEG6E32_V_MF2,
5499 : PseudoVLSSEG6E32_V_MF2_MASK,
5500 : PseudoVLSSEG6E64_V_M1,
5501 : PseudoVLSSEG6E64_V_M1_MASK,
5502 : PseudoVLSSEG6E8_V_M1,
5503 : PseudoVLSSEG6E8_V_M1_MASK,
5504 : PseudoVLSSEG6E8_V_MF2,
5505 : PseudoVLSSEG6E8_V_MF2_MASK,
5506 : PseudoVLSSEG6E8_V_MF4,
5507 : PseudoVLSSEG6E8_V_MF4_MASK,
5508 : PseudoVLSSEG6E8_V_MF8,
5509 : PseudoVLSSEG6E8_V_MF8_MASK,
5510 : PseudoVLSSEG7E16_V_M1,
5511 : PseudoVLSSEG7E16_V_M1_MASK,
5512 : PseudoVLSSEG7E16_V_MF2,
5513 : PseudoVLSSEG7E16_V_MF2_MASK,
5514 : PseudoVLSSEG7E16_V_MF4,
5515 : PseudoVLSSEG7E16_V_MF4_MASK,
5516 : PseudoVLSSEG7E32_V_M1,
5517 : PseudoVLSSEG7E32_V_M1_MASK,
5518 : PseudoVLSSEG7E32_V_MF2,
5519 : PseudoVLSSEG7E32_V_MF2_MASK,
5520 : PseudoVLSSEG7E64_V_M1,
5521 : PseudoVLSSEG7E64_V_M1_MASK,
5522 : PseudoVLSSEG7E8_V_M1,
5523 : PseudoVLSSEG7E8_V_M1_MASK,
5524 : PseudoVLSSEG7E8_V_MF2,
5525 : PseudoVLSSEG7E8_V_MF2_MASK,
5526 : PseudoVLSSEG7E8_V_MF4,
5527 : PseudoVLSSEG7E8_V_MF4_MASK,
5528 : PseudoVLSSEG7E8_V_MF8,
5529 : PseudoVLSSEG7E8_V_MF8_MASK,
5530 : PseudoVLSSEG8E16_V_M1,
5531 : PseudoVLSSEG8E16_V_M1_MASK,
5532 : PseudoVLSSEG8E16_V_MF2,
5533 : PseudoVLSSEG8E16_V_MF2_MASK,
5534 : PseudoVLSSEG8E16_V_MF4,
5535 : PseudoVLSSEG8E16_V_MF4_MASK,
5536 : PseudoVLSSEG8E32_V_M1,
5537 : PseudoVLSSEG8E32_V_M1_MASK,
5538 : PseudoVLSSEG8E32_V_MF2,
5539 : PseudoVLSSEG8E32_V_MF2_MASK,
5540 : PseudoVLSSEG8E64_V_M1,
5541 : PseudoVLSSEG8E64_V_M1_MASK,
5542 : PseudoVLSSEG8E8_V_M1,
5543 : PseudoVLSSEG8E8_V_M1_MASK,
5544 : PseudoVLSSEG8E8_V_MF2,
5545 : PseudoVLSSEG8E8_V_MF2_MASK,
5546 : PseudoVLSSEG8E8_V_MF4,
5547 : PseudoVLSSEG8E8_V_MF4_MASK,
5548 : PseudoVLSSEG8E8_V_MF8,
5549 : PseudoVLSSEG8E8_V_MF8_MASK,
5550 : PseudoVLUXEI16_V_M1_M1,
5551 : PseudoVLUXEI16_V_M1_M1_MASK,
5552 : PseudoVLUXEI16_V_M1_M2,
5553 : PseudoVLUXEI16_V_M1_M2_MASK,
5554 : PseudoVLUXEI16_V_M1_M4,
5555 : PseudoVLUXEI16_V_M1_M4_MASK,
5556 : PseudoVLUXEI16_V_M1_MF2,
5557 : PseudoVLUXEI16_V_M1_MF2_MASK,
5558 : PseudoVLUXEI16_V_M2_M1,
5559 : PseudoVLUXEI16_V_M2_M1_MASK,
5560 : PseudoVLUXEI16_V_M2_M2,
5561 : PseudoVLUXEI16_V_M2_M2_MASK,
5562 : PseudoVLUXEI16_V_M2_M4,
5563 : PseudoVLUXEI16_V_M2_M4_MASK,
5564 : PseudoVLUXEI16_V_M2_M8,
5565 : PseudoVLUXEI16_V_M2_M8_MASK,
5566 : PseudoVLUXEI16_V_M4_M2,
5567 : PseudoVLUXEI16_V_M4_M2_MASK,
5568 : PseudoVLUXEI16_V_M4_M4,
5569 : PseudoVLUXEI16_V_M4_M4_MASK,
5570 : PseudoVLUXEI16_V_M4_M8,
5571 : PseudoVLUXEI16_V_M4_M8_MASK,
5572 : PseudoVLUXEI16_V_M8_M4,
5573 : PseudoVLUXEI16_V_M8_M4_MASK,
5574 : PseudoVLUXEI16_V_M8_M8,
5575 : PseudoVLUXEI16_V_M8_M8_MASK,
5576 : PseudoVLUXEI16_V_MF2_M1,
5577 : PseudoVLUXEI16_V_MF2_M1_MASK,
5578 : PseudoVLUXEI16_V_MF2_M2,
5579 : PseudoVLUXEI16_V_MF2_M2_MASK,
5580 : PseudoVLUXEI16_V_MF2_MF2,
5581 : PseudoVLUXEI16_V_MF2_MF2_MASK,
5582 : PseudoVLUXEI16_V_MF2_MF4,
5583 : PseudoVLUXEI16_V_MF2_MF4_MASK,
5584 : PseudoVLUXEI16_V_MF4_M1,
5585 : PseudoVLUXEI16_V_MF4_M1_MASK,
5586 : PseudoVLUXEI16_V_MF4_MF2,
5587 : PseudoVLUXEI16_V_MF4_MF2_MASK,
5588 : PseudoVLUXEI16_V_MF4_MF4,
5589 : PseudoVLUXEI16_V_MF4_MF4_MASK,
5590 : PseudoVLUXEI16_V_MF4_MF8,
5591 : PseudoVLUXEI16_V_MF4_MF8_MASK,
5592 : PseudoVLUXEI32_V_M1_M1,
5593 : PseudoVLUXEI32_V_M1_M1_MASK,
5594 : PseudoVLUXEI32_V_M1_M2,
5595 : PseudoVLUXEI32_V_M1_M2_MASK,
5596 : PseudoVLUXEI32_V_M1_MF2,
5597 : PseudoVLUXEI32_V_M1_MF2_MASK,
5598 : PseudoVLUXEI32_V_M1_MF4,
5599 : PseudoVLUXEI32_V_M1_MF4_MASK,
5600 : PseudoVLUXEI32_V_M2_M1,
5601 : PseudoVLUXEI32_V_M2_M1_MASK,
5602 : PseudoVLUXEI32_V_M2_M2,
5603 : PseudoVLUXEI32_V_M2_M2_MASK,
5604 : PseudoVLUXEI32_V_M2_M4,
5605 : PseudoVLUXEI32_V_M2_M4_MASK,
5606 : PseudoVLUXEI32_V_M2_MF2,
5607 : PseudoVLUXEI32_V_M2_MF2_MASK,
5608 : PseudoVLUXEI32_V_M4_M1,
5609 : PseudoVLUXEI32_V_M4_M1_MASK,
5610 : PseudoVLUXEI32_V_M4_M2,
5611 : PseudoVLUXEI32_V_M4_M2_MASK,
5612 : PseudoVLUXEI32_V_M4_M4,
5613 : PseudoVLUXEI32_V_M4_M4_MASK,
5614 : PseudoVLUXEI32_V_M4_M8,
5615 : PseudoVLUXEI32_V_M4_M8_MASK,
5616 : PseudoVLUXEI32_V_M8_M2,
5617 : PseudoVLUXEI32_V_M8_M2_MASK,
5618 : PseudoVLUXEI32_V_M8_M4,
5619 : PseudoVLUXEI32_V_M8_M4_MASK,
5620 : PseudoVLUXEI32_V_M8_M8,
5621 : PseudoVLUXEI32_V_M8_M8_MASK,
5622 : PseudoVLUXEI32_V_MF2_M1,
5623 : PseudoVLUXEI32_V_MF2_M1_MASK,
5624 : PseudoVLUXEI32_V_MF2_MF2,
5625 : PseudoVLUXEI32_V_MF2_MF2_MASK,
5626 : PseudoVLUXEI32_V_MF2_MF4,
5627 : PseudoVLUXEI32_V_MF2_MF4_MASK,
5628 : PseudoVLUXEI32_V_MF2_MF8,
5629 : PseudoVLUXEI32_V_MF2_MF8_MASK,
5630 : PseudoVLUXEI64_V_M1_M1,
5631 : PseudoVLUXEI64_V_M1_M1_MASK,
5632 : PseudoVLUXEI64_V_M1_MF2,
5633 : PseudoVLUXEI64_V_M1_MF2_MASK,
5634 : PseudoVLUXEI64_V_M1_MF4,
5635 : PseudoVLUXEI64_V_M1_MF4_MASK,
5636 : PseudoVLUXEI64_V_M1_MF8,
5637 : PseudoVLUXEI64_V_M1_MF8_MASK,
5638 : PseudoVLUXEI64_V_M2_M1,
5639 : PseudoVLUXEI64_V_M2_M1_MASK,
5640 : PseudoVLUXEI64_V_M2_M2,
5641 : PseudoVLUXEI64_V_M2_M2_MASK,
5642 : PseudoVLUXEI64_V_M2_MF2,
5643 : PseudoVLUXEI64_V_M2_MF2_MASK,
5644 : PseudoVLUXEI64_V_M2_MF4,
5645 : PseudoVLUXEI64_V_M2_MF4_MASK,
5646 : PseudoVLUXEI64_V_M4_M1,
5647 : PseudoVLUXEI64_V_M4_M1_MASK,
5648 : PseudoVLUXEI64_V_M4_M2,
5649 : PseudoVLUXEI64_V_M4_M2_MASK,
5650 : PseudoVLUXEI64_V_M4_M4,
5651 : PseudoVLUXEI64_V_M4_M4_MASK,
5652 : PseudoVLUXEI64_V_M4_MF2,
5653 : PseudoVLUXEI64_V_M4_MF2_MASK,
5654 : PseudoVLUXEI64_V_M8_M1,
5655 : PseudoVLUXEI64_V_M8_M1_MASK,
5656 : PseudoVLUXEI64_V_M8_M2,
5657 : PseudoVLUXEI64_V_M8_M2_MASK,
5658 : PseudoVLUXEI64_V_M8_M4,
5659 : PseudoVLUXEI64_V_M8_M4_MASK,
5660 : PseudoVLUXEI64_V_M8_M8,
5661 : PseudoVLUXEI64_V_M8_M8_MASK,
5662 : PseudoVLUXEI8_V_M1_M1,
5663 : PseudoVLUXEI8_V_M1_M1_MASK,
5664 : PseudoVLUXEI8_V_M1_M2,
5665 : PseudoVLUXEI8_V_M1_M2_MASK,
5666 : PseudoVLUXEI8_V_M1_M4,
5667 : PseudoVLUXEI8_V_M1_M4_MASK,
5668 : PseudoVLUXEI8_V_M1_M8,
5669 : PseudoVLUXEI8_V_M1_M8_MASK,
5670 : PseudoVLUXEI8_V_M2_M2,
5671 : PseudoVLUXEI8_V_M2_M2_MASK,
5672 : PseudoVLUXEI8_V_M2_M4,
5673 : PseudoVLUXEI8_V_M2_M4_MASK,
5674 : PseudoVLUXEI8_V_M2_M8,
5675 : PseudoVLUXEI8_V_M2_M8_MASK,
5676 : PseudoVLUXEI8_V_M4_M4,
5677 : PseudoVLUXEI8_V_M4_M4_MASK,
5678 : PseudoVLUXEI8_V_M4_M8,
5679 : PseudoVLUXEI8_V_M4_M8_MASK,
5680 : PseudoVLUXEI8_V_M8_M8,
5681 : PseudoVLUXEI8_V_M8_M8_MASK,
5682 : PseudoVLUXEI8_V_MF2_M1,
5683 : PseudoVLUXEI8_V_MF2_M1_MASK,
5684 : PseudoVLUXEI8_V_MF2_M2,
5685 : PseudoVLUXEI8_V_MF2_M2_MASK,
5686 : PseudoVLUXEI8_V_MF2_M4,
5687 : PseudoVLUXEI8_V_MF2_M4_MASK,
5688 : PseudoVLUXEI8_V_MF2_MF2,
5689 : PseudoVLUXEI8_V_MF2_MF2_MASK,
5690 : PseudoVLUXEI8_V_MF4_M1,
5691 : PseudoVLUXEI8_V_MF4_M1_MASK,
5692 : PseudoVLUXEI8_V_MF4_M2,
5693 : PseudoVLUXEI8_V_MF4_M2_MASK,
5694 : PseudoVLUXEI8_V_MF4_MF2,
5695 : PseudoVLUXEI8_V_MF4_MF2_MASK,
5696 : PseudoVLUXEI8_V_MF4_MF4,
5697 : PseudoVLUXEI8_V_MF4_MF4_MASK,
5698 : PseudoVLUXEI8_V_MF8_M1,
5699 : PseudoVLUXEI8_V_MF8_M1_MASK,
5700 : PseudoVLUXEI8_V_MF8_MF2,
5701 : PseudoVLUXEI8_V_MF8_MF2_MASK,
5702 : PseudoVLUXEI8_V_MF8_MF4,
5703 : PseudoVLUXEI8_V_MF8_MF4_MASK,
5704 : PseudoVLUXEI8_V_MF8_MF8,
5705 : PseudoVLUXEI8_V_MF8_MF8_MASK,
5706 : PseudoVLUXSEG2EI16_V_M1_M1,
5707 : PseudoVLUXSEG2EI16_V_M1_M1_MASK,
5708 : PseudoVLUXSEG2EI16_V_M1_M2,
5709 : PseudoVLUXSEG2EI16_V_M1_M2_MASK,
5710 : PseudoVLUXSEG2EI16_V_M1_M4,
5711 : PseudoVLUXSEG2EI16_V_M1_M4_MASK,
5712 : PseudoVLUXSEG2EI16_V_M1_MF2,
5713 : PseudoVLUXSEG2EI16_V_M1_MF2_MASK,
5714 : PseudoVLUXSEG2EI16_V_M2_M1,
5715 : PseudoVLUXSEG2EI16_V_M2_M1_MASK,
5716 : PseudoVLUXSEG2EI16_V_M2_M2,
5717 : PseudoVLUXSEG2EI16_V_M2_M2_MASK,
5718 : PseudoVLUXSEG2EI16_V_M2_M4,
5719 : PseudoVLUXSEG2EI16_V_M2_M4_MASK,
5720 : PseudoVLUXSEG2EI16_V_M4_M2,
5721 : PseudoVLUXSEG2EI16_V_M4_M2_MASK,
5722 : PseudoVLUXSEG2EI16_V_M4_M4,
5723 : PseudoVLUXSEG2EI16_V_M4_M4_MASK,
5724 : PseudoVLUXSEG2EI16_V_M8_M4,
5725 : PseudoVLUXSEG2EI16_V_M8_M4_MASK,
5726 : PseudoVLUXSEG2EI16_V_MF2_M1,
5727 : PseudoVLUXSEG2EI16_V_MF2_M1_MASK,
5728 : PseudoVLUXSEG2EI16_V_MF2_M2,
5729 : PseudoVLUXSEG2EI16_V_MF2_M2_MASK,
5730 : PseudoVLUXSEG2EI16_V_MF2_MF2,
5731 : PseudoVLUXSEG2EI16_V_MF2_MF2_MASK,
5732 : PseudoVLUXSEG2EI16_V_MF2_MF4,
5733 : PseudoVLUXSEG2EI16_V_MF2_MF4_MASK,
5734 : PseudoVLUXSEG2EI16_V_MF4_M1,
5735 : PseudoVLUXSEG2EI16_V_MF4_M1_MASK,
5736 : PseudoVLUXSEG2EI16_V_MF4_MF2,
5737 : PseudoVLUXSEG2EI16_V_MF4_MF2_MASK,
5738 : PseudoVLUXSEG2EI16_V_MF4_MF4,
5739 : PseudoVLUXSEG2EI16_V_MF4_MF4_MASK,
5740 : PseudoVLUXSEG2EI16_V_MF4_MF8,
5741 : PseudoVLUXSEG2EI16_V_MF4_MF8_MASK,
5742 : PseudoVLUXSEG2EI32_V_M1_M1,
5743 : PseudoVLUXSEG2EI32_V_M1_M1_MASK,
5744 : PseudoVLUXSEG2EI32_V_M1_M2,
5745 : PseudoVLUXSEG2EI32_V_M1_M2_MASK,
5746 : PseudoVLUXSEG2EI32_V_M1_MF2,
5747 : PseudoVLUXSEG2EI32_V_M1_MF2_MASK,
5748 : PseudoVLUXSEG2EI32_V_M1_MF4,
5749 : PseudoVLUXSEG2EI32_V_M1_MF4_MASK,
5750 : PseudoVLUXSEG2EI32_V_M2_M1,
5751 : PseudoVLUXSEG2EI32_V_M2_M1_MASK,
5752 : PseudoVLUXSEG2EI32_V_M2_M2,
5753 : PseudoVLUXSEG2EI32_V_M2_M2_MASK,
5754 : PseudoVLUXSEG2EI32_V_M2_M4,
5755 : PseudoVLUXSEG2EI32_V_M2_M4_MASK,
5756 : PseudoVLUXSEG2EI32_V_M2_MF2,
5757 : PseudoVLUXSEG2EI32_V_M2_MF2_MASK,
5758 : PseudoVLUXSEG2EI32_V_M4_M1,
5759 : PseudoVLUXSEG2EI32_V_M4_M1_MASK,
5760 : PseudoVLUXSEG2EI32_V_M4_M2,
5761 : PseudoVLUXSEG2EI32_V_M4_M2_MASK,
5762 : PseudoVLUXSEG2EI32_V_M4_M4,
5763 : PseudoVLUXSEG2EI32_V_M4_M4_MASK,
5764 : PseudoVLUXSEG2EI32_V_M8_M2,
5765 : PseudoVLUXSEG2EI32_V_M8_M2_MASK,
5766 : PseudoVLUXSEG2EI32_V_M8_M4,
5767 : PseudoVLUXSEG2EI32_V_M8_M4_MASK,
5768 : PseudoVLUXSEG2EI32_V_MF2_M1,
5769 : PseudoVLUXSEG2EI32_V_MF2_M1_MASK,
5770 : PseudoVLUXSEG2EI32_V_MF2_MF2,
5771 : PseudoVLUXSEG2EI32_V_MF2_MF2_MASK,
5772 : PseudoVLUXSEG2EI32_V_MF2_MF4,
5773 : PseudoVLUXSEG2EI32_V_MF2_MF4_MASK,
5774 : PseudoVLUXSEG2EI32_V_MF2_MF8,
5775 : PseudoVLUXSEG2EI32_V_MF2_MF8_MASK,
5776 : PseudoVLUXSEG2EI64_V_M1_M1,
5777 : PseudoVLUXSEG2EI64_V_M1_M1_MASK,
5778 : PseudoVLUXSEG2EI64_V_M1_MF2,
5779 : PseudoVLUXSEG2EI64_V_M1_MF2_MASK,
5780 : PseudoVLUXSEG2EI64_V_M1_MF4,
5781 : PseudoVLUXSEG2EI64_V_M1_MF4_MASK,
5782 : PseudoVLUXSEG2EI64_V_M1_MF8,
5783 : PseudoVLUXSEG2EI64_V_M1_MF8_MASK,
5784 : PseudoVLUXSEG2EI64_V_M2_M1,
5785 : PseudoVLUXSEG2EI64_V_M2_M1_MASK,
5786 : PseudoVLUXSEG2EI64_V_M2_M2,
5787 : PseudoVLUXSEG2EI64_V_M2_M2_MASK,
5788 : PseudoVLUXSEG2EI64_V_M2_MF2,
5789 : PseudoVLUXSEG2EI64_V_M2_MF2_MASK,
5790 : PseudoVLUXSEG2EI64_V_M2_MF4,
5791 : PseudoVLUXSEG2EI64_V_M2_MF4_MASK,
5792 : PseudoVLUXSEG2EI64_V_M4_M1,
5793 : PseudoVLUXSEG2EI64_V_M4_M1_MASK,
5794 : PseudoVLUXSEG2EI64_V_M4_M2,
5795 : PseudoVLUXSEG2EI64_V_M4_M2_MASK,
5796 : PseudoVLUXSEG2EI64_V_M4_M4,
5797 : PseudoVLUXSEG2EI64_V_M4_M4_MASK,
5798 : PseudoVLUXSEG2EI64_V_M4_MF2,
5799 : PseudoVLUXSEG2EI64_V_M4_MF2_MASK,
5800 : PseudoVLUXSEG2EI64_V_M8_M1,
5801 : PseudoVLUXSEG2EI64_V_M8_M1_MASK,
5802 : PseudoVLUXSEG2EI64_V_M8_M2,
5803 : PseudoVLUXSEG2EI64_V_M8_M2_MASK,
5804 : PseudoVLUXSEG2EI64_V_M8_M4,
5805 : PseudoVLUXSEG2EI64_V_M8_M4_MASK,
5806 : PseudoVLUXSEG2EI8_V_M1_M1,
5807 : PseudoVLUXSEG2EI8_V_M1_M1_MASK,
5808 : PseudoVLUXSEG2EI8_V_M1_M2,
5809 : PseudoVLUXSEG2EI8_V_M1_M2_MASK,
5810 : PseudoVLUXSEG2EI8_V_M1_M4,
5811 : PseudoVLUXSEG2EI8_V_M1_M4_MASK,
5812 : PseudoVLUXSEG2EI8_V_M2_M2,
5813 : PseudoVLUXSEG2EI8_V_M2_M2_MASK,
5814 : PseudoVLUXSEG2EI8_V_M2_M4,
5815 : PseudoVLUXSEG2EI8_V_M2_M4_MASK,
5816 : PseudoVLUXSEG2EI8_V_M4_M4,
5817 : PseudoVLUXSEG2EI8_V_M4_M4_MASK,
5818 : PseudoVLUXSEG2EI8_V_MF2_M1,
5819 : PseudoVLUXSEG2EI8_V_MF2_M1_MASK,
5820 : PseudoVLUXSEG2EI8_V_MF2_M2,
5821 : PseudoVLUXSEG2EI8_V_MF2_M2_MASK,
5822 : PseudoVLUXSEG2EI8_V_MF2_M4,
5823 : PseudoVLUXSEG2EI8_V_MF2_M4_MASK,
5824 : PseudoVLUXSEG2EI8_V_MF2_MF2,
5825 : PseudoVLUXSEG2EI8_V_MF2_MF2_MASK,
5826 : PseudoVLUXSEG2EI8_V_MF4_M1,
5827 : PseudoVLUXSEG2EI8_V_MF4_M1_MASK,
5828 : PseudoVLUXSEG2EI8_V_MF4_M2,
5829 : PseudoVLUXSEG2EI8_V_MF4_M2_MASK,
5830 : PseudoVLUXSEG2EI8_V_MF4_MF2,
5831 : PseudoVLUXSEG2EI8_V_MF4_MF2_MASK,
5832 : PseudoVLUXSEG2EI8_V_MF4_MF4,
5833 : PseudoVLUXSEG2EI8_V_MF4_MF4_MASK,
5834 : PseudoVLUXSEG2EI8_V_MF8_M1,
5835 : PseudoVLUXSEG2EI8_V_MF8_M1_MASK,
5836 : PseudoVLUXSEG2EI8_V_MF8_MF2,
5837 : PseudoVLUXSEG2EI8_V_MF8_MF2_MASK,
5838 : PseudoVLUXSEG2EI8_V_MF8_MF4,
5839 : PseudoVLUXSEG2EI8_V_MF8_MF4_MASK,
5840 : PseudoVLUXSEG2EI8_V_MF8_MF8,
5841 : PseudoVLUXSEG2EI8_V_MF8_MF8_MASK,
5842 : PseudoVLUXSEG3EI16_V_M1_M1,
5843 : PseudoVLUXSEG3EI16_V_M1_M1_MASK,
5844 : PseudoVLUXSEG3EI16_V_M1_M2,
5845 : PseudoVLUXSEG3EI16_V_M1_M2_MASK,
5846 : PseudoVLUXSEG3EI16_V_M1_MF2,
5847 : PseudoVLUXSEG3EI16_V_M1_MF2_MASK,
5848 : PseudoVLUXSEG3EI16_V_M2_M1,
5849 : PseudoVLUXSEG3EI16_V_M2_M1_MASK,
5850 : PseudoVLUXSEG3EI16_V_M2_M2,
5851 : PseudoVLUXSEG3EI16_V_M2_M2_MASK,
5852 : PseudoVLUXSEG3EI16_V_M4_M2,
5853 : PseudoVLUXSEG3EI16_V_M4_M2_MASK,
5854 : PseudoVLUXSEG3EI16_V_MF2_M1,
5855 : PseudoVLUXSEG3EI16_V_MF2_M1_MASK,
5856 : PseudoVLUXSEG3EI16_V_MF2_M2,
5857 : PseudoVLUXSEG3EI16_V_MF2_M2_MASK,
5858 : PseudoVLUXSEG3EI16_V_MF2_MF2,
5859 : PseudoVLUXSEG3EI16_V_MF2_MF2_MASK,
5860 : PseudoVLUXSEG3EI16_V_MF2_MF4,
5861 : PseudoVLUXSEG3EI16_V_MF2_MF4_MASK,
5862 : PseudoVLUXSEG3EI16_V_MF4_M1,
5863 : PseudoVLUXSEG3EI16_V_MF4_M1_MASK,
5864 : PseudoVLUXSEG3EI16_V_MF4_MF2,
5865 : PseudoVLUXSEG3EI16_V_MF4_MF2_MASK,
5866 : PseudoVLUXSEG3EI16_V_MF4_MF4,
5867 : PseudoVLUXSEG3EI16_V_MF4_MF4_MASK,
5868 : PseudoVLUXSEG3EI16_V_MF4_MF8,
5869 : PseudoVLUXSEG3EI16_V_MF4_MF8_MASK,
5870 : PseudoVLUXSEG3EI32_V_M1_M1,
5871 : PseudoVLUXSEG3EI32_V_M1_M1_MASK,
5872 : PseudoVLUXSEG3EI32_V_M1_M2,
5873 : PseudoVLUXSEG3EI32_V_M1_M2_MASK,
5874 : PseudoVLUXSEG3EI32_V_M1_MF2,
5875 : PseudoVLUXSEG3EI32_V_M1_MF2_MASK,
5876 : PseudoVLUXSEG3EI32_V_M1_MF4,
5877 : PseudoVLUXSEG3EI32_V_M1_MF4_MASK,
5878 : PseudoVLUXSEG3EI32_V_M2_M1,
5879 : PseudoVLUXSEG3EI32_V_M2_M1_MASK,
5880 : PseudoVLUXSEG3EI32_V_M2_M2,
5881 : PseudoVLUXSEG3EI32_V_M2_M2_MASK,
5882 : PseudoVLUXSEG3EI32_V_M2_MF2,
5883 : PseudoVLUXSEG3EI32_V_M2_MF2_MASK,
5884 : PseudoVLUXSEG3EI32_V_M4_M1,
5885 : PseudoVLUXSEG3EI32_V_M4_M1_MASK,
5886 : PseudoVLUXSEG3EI32_V_M4_M2,
5887 : PseudoVLUXSEG3EI32_V_M4_M2_MASK,
5888 : PseudoVLUXSEG3EI32_V_M8_M2,
5889 : PseudoVLUXSEG3EI32_V_M8_M2_MASK,
5890 : PseudoVLUXSEG3EI32_V_MF2_M1,
5891 : PseudoVLUXSEG3EI32_V_MF2_M1_MASK,
5892 : PseudoVLUXSEG3EI32_V_MF2_MF2,
5893 : PseudoVLUXSEG3EI32_V_MF2_MF2_MASK,
5894 : PseudoVLUXSEG3EI32_V_MF2_MF4,
5895 : PseudoVLUXSEG3EI32_V_MF2_MF4_MASK,
5896 : PseudoVLUXSEG3EI32_V_MF2_MF8,
5897 : PseudoVLUXSEG3EI32_V_MF2_MF8_MASK,
5898 : PseudoVLUXSEG3EI64_V_M1_M1,
5899 : PseudoVLUXSEG3EI64_V_M1_M1_MASK,
5900 : PseudoVLUXSEG3EI64_V_M1_MF2,
5901 : PseudoVLUXSEG3EI64_V_M1_MF2_MASK,
5902 : PseudoVLUXSEG3EI64_V_M1_MF4,
5903 : PseudoVLUXSEG3EI64_V_M1_MF4_MASK,
5904 : PseudoVLUXSEG3EI64_V_M1_MF8,
5905 : PseudoVLUXSEG3EI64_V_M1_MF8_MASK,
5906 : PseudoVLUXSEG3EI64_V_M2_M1,
5907 : PseudoVLUXSEG3EI64_V_M2_M1_MASK,
5908 : PseudoVLUXSEG3EI64_V_M2_M2,
5909 : PseudoVLUXSEG3EI64_V_M2_M2_MASK,
5910 : PseudoVLUXSEG3EI64_V_M2_MF2,
5911 : PseudoVLUXSEG3EI64_V_M2_MF2_MASK,
5912 : PseudoVLUXSEG3EI64_V_M2_MF4,
5913 : PseudoVLUXSEG3EI64_V_M2_MF4_MASK,
5914 : PseudoVLUXSEG3EI64_V_M4_M1,
5915 : PseudoVLUXSEG3EI64_V_M4_M1_MASK,
5916 : PseudoVLUXSEG3EI64_V_M4_M2,
5917 : PseudoVLUXSEG3EI64_V_M4_M2_MASK,
5918 : PseudoVLUXSEG3EI64_V_M4_MF2,
5919 : PseudoVLUXSEG3EI64_V_M4_MF2_MASK,
5920 : PseudoVLUXSEG3EI64_V_M8_M1,
5921 : PseudoVLUXSEG3EI64_V_M8_M1_MASK,
5922 : PseudoVLUXSEG3EI64_V_M8_M2,
5923 : PseudoVLUXSEG3EI64_V_M8_M2_MASK,
5924 : PseudoVLUXSEG3EI8_V_M1_M1,
5925 : PseudoVLUXSEG3EI8_V_M1_M1_MASK,
5926 : PseudoVLUXSEG3EI8_V_M1_M2,
5927 : PseudoVLUXSEG3EI8_V_M1_M2_MASK,
5928 : PseudoVLUXSEG3EI8_V_M2_M2,
5929 : PseudoVLUXSEG3EI8_V_M2_M2_MASK,
5930 : PseudoVLUXSEG3EI8_V_MF2_M1,
5931 : PseudoVLUXSEG3EI8_V_MF2_M1_MASK,
5932 : PseudoVLUXSEG3EI8_V_MF2_M2,
5933 : PseudoVLUXSEG3EI8_V_MF2_M2_MASK,
5934 : PseudoVLUXSEG3EI8_V_MF2_MF2,
5935 : PseudoVLUXSEG3EI8_V_MF2_MF2_MASK,
5936 : PseudoVLUXSEG3EI8_V_MF4_M1,
5937 : PseudoVLUXSEG3EI8_V_MF4_M1_MASK,
5938 : PseudoVLUXSEG3EI8_V_MF4_M2,
5939 : PseudoVLUXSEG3EI8_V_MF4_M2_MASK,
5940 : PseudoVLUXSEG3EI8_V_MF4_MF2,
5941 : PseudoVLUXSEG3EI8_V_MF4_MF2_MASK,
5942 : PseudoVLUXSEG3EI8_V_MF4_MF4,
5943 : PseudoVLUXSEG3EI8_V_MF4_MF4_MASK,
5944 : PseudoVLUXSEG3EI8_V_MF8_M1,
5945 : PseudoVLUXSEG3EI8_V_MF8_M1_MASK,
5946 : PseudoVLUXSEG3EI8_V_MF8_MF2,
5947 : PseudoVLUXSEG3EI8_V_MF8_MF2_MASK,
5948 : PseudoVLUXSEG3EI8_V_MF8_MF4,
5949 : PseudoVLUXSEG3EI8_V_MF8_MF4_MASK,
5950 : PseudoVLUXSEG3EI8_V_MF8_MF8,
5951 : PseudoVLUXSEG3EI8_V_MF8_MF8_MASK,
5952 : PseudoVLUXSEG4EI16_V_M1_M1,
5953 : PseudoVLUXSEG4EI16_V_M1_M1_MASK,
5954 : PseudoVLUXSEG4EI16_V_M1_M2,
5955 : PseudoVLUXSEG4EI16_V_M1_M2_MASK,
5956 : PseudoVLUXSEG4EI16_V_M1_MF2,
5957 : PseudoVLUXSEG4EI16_V_M1_MF2_MASK,
5958 : PseudoVLUXSEG4EI16_V_M2_M1,
5959 : PseudoVLUXSEG4EI16_V_M2_M1_MASK,
5960 : PseudoVLUXSEG4EI16_V_M2_M2,
5961 : PseudoVLUXSEG4EI16_V_M2_M2_MASK,
5962 : PseudoVLUXSEG4EI16_V_M4_M2,
5963 : PseudoVLUXSEG4EI16_V_M4_M2_MASK,
5964 : PseudoVLUXSEG4EI16_V_MF2_M1,
5965 : PseudoVLUXSEG4EI16_V_MF2_M1_MASK,
5966 : PseudoVLUXSEG4EI16_V_MF2_M2,
5967 : PseudoVLUXSEG4EI16_V_MF2_M2_MASK,
5968 : PseudoVLUXSEG4EI16_V_MF2_MF2,
5969 : PseudoVLUXSEG4EI16_V_MF2_MF2_MASK,
5970 : PseudoVLUXSEG4EI16_V_MF2_MF4,
5971 : PseudoVLUXSEG4EI16_V_MF2_MF4_MASK,
5972 : PseudoVLUXSEG4EI16_V_MF4_M1,
5973 : PseudoVLUXSEG4EI16_V_MF4_M1_MASK,
5974 : PseudoVLUXSEG4EI16_V_MF4_MF2,
5975 : PseudoVLUXSEG4EI16_V_MF4_MF2_MASK,
5976 : PseudoVLUXSEG4EI16_V_MF4_MF4,
5977 : PseudoVLUXSEG4EI16_V_MF4_MF4_MASK,
5978 : PseudoVLUXSEG4EI16_V_MF4_MF8,
5979 : PseudoVLUXSEG4EI16_V_MF4_MF8_MASK,
5980 : PseudoVLUXSEG4EI32_V_M1_M1,
5981 : PseudoVLUXSEG4EI32_V_M1_M1_MASK,
5982 : PseudoVLUXSEG4EI32_V_M1_M2,
5983 : PseudoVLUXSEG4EI32_V_M1_M2_MASK,
5984 : PseudoVLUXSEG4EI32_V_M1_MF2,
5985 : PseudoVLUXSEG4EI32_V_M1_MF2_MASK,
5986 : PseudoVLUXSEG4EI32_V_M1_MF4,
5987 : PseudoVLUXSEG4EI32_V_M1_MF4_MASK,
5988 : PseudoVLUXSEG4EI32_V_M2_M1,
5989 : PseudoVLUXSEG4EI32_V_M2_M1_MASK,
5990 : PseudoVLUXSEG4EI32_V_M2_M2,
5991 : PseudoVLUXSEG4EI32_V_M2_M2_MASK,
5992 : PseudoVLUXSEG4EI32_V_M2_MF2,
5993 : PseudoVLUXSEG4EI32_V_M2_MF2_MASK,
5994 : PseudoVLUXSEG4EI32_V_M4_M1,
5995 : PseudoVLUXSEG4EI32_V_M4_M1_MASK,
5996 : PseudoVLUXSEG4EI32_V_M4_M2,
5997 : PseudoVLUXSEG4EI32_V_M4_M2_MASK,
5998 : PseudoVLUXSEG4EI32_V_M8_M2,
5999 : PseudoVLUXSEG4EI32_V_M8_M2_MASK,
6000 : PseudoVLUXSEG4EI32_V_MF2_M1,
6001 : PseudoVLUXSEG4EI32_V_MF2_M1_MASK,
6002 : PseudoVLUXSEG4EI32_V_MF2_MF2,
6003 : PseudoVLUXSEG4EI32_V_MF2_MF2_MASK,
6004 : PseudoVLUXSEG4EI32_V_MF2_MF4,
6005 : PseudoVLUXSEG4EI32_V_MF2_MF4_MASK,
6006 : PseudoVLUXSEG4EI32_V_MF2_MF8,
6007 : PseudoVLUXSEG4EI32_V_MF2_MF8_MASK,
6008 : PseudoVLUXSEG4EI64_V_M1_M1,
6009 : PseudoVLUXSEG4EI64_V_M1_M1_MASK,
6010 : PseudoVLUXSEG4EI64_V_M1_MF2,
6011 : PseudoVLUXSEG4EI64_V_M1_MF2_MASK,
6012 : PseudoVLUXSEG4EI64_V_M1_MF4,
6013 : PseudoVLUXSEG4EI64_V_M1_MF4_MASK,
6014 : PseudoVLUXSEG4EI64_V_M1_MF8,
6015 : PseudoVLUXSEG4EI64_V_M1_MF8_MASK,
6016 : PseudoVLUXSEG4EI64_V_M2_M1,
6017 : PseudoVLUXSEG4EI64_V_M2_M1_MASK,
6018 : PseudoVLUXSEG4EI64_V_M2_M2,
6019 : PseudoVLUXSEG4EI64_V_M2_M2_MASK,
6020 : PseudoVLUXSEG4EI64_V_M2_MF2,
6021 : PseudoVLUXSEG4EI64_V_M2_MF2_MASK,
6022 : PseudoVLUXSEG4EI64_V_M2_MF4,
6023 : PseudoVLUXSEG4EI64_V_M2_MF4_MASK,
6024 : PseudoVLUXSEG4EI64_V_M4_M1,
6025 : PseudoVLUXSEG4EI64_V_M4_M1_MASK,
6026 : PseudoVLUXSEG4EI64_V_M4_M2,
6027 : PseudoVLUXSEG4EI64_V_M4_M2_MASK,
6028 : PseudoVLUXSEG4EI64_V_M4_MF2,
6029 : PseudoVLUXSEG4EI64_V_M4_MF2_MASK,
6030 : PseudoVLUXSEG4EI64_V_M8_M1,
6031 : PseudoVLUXSEG4EI64_V_M8_M1_MASK,
6032 : PseudoVLUXSEG4EI64_V_M8_M2,
6033 : PseudoVLUXSEG4EI64_V_M8_M2_MASK,
6034 : PseudoVLUXSEG4EI8_V_M1_M1,
6035 : PseudoVLUXSEG4EI8_V_M1_M1_MASK,
6036 : PseudoVLUXSEG4EI8_V_M1_M2,
6037 : PseudoVLUXSEG4EI8_V_M1_M2_MASK,
6038 : PseudoVLUXSEG4EI8_V_M2_M2,
6039 : PseudoVLUXSEG4EI8_V_M2_M2_MASK,
6040 : PseudoVLUXSEG4EI8_V_MF2_M1,
6041 : PseudoVLUXSEG4EI8_V_MF2_M1_MASK,
6042 : PseudoVLUXSEG4EI8_V_MF2_M2,
6043 : PseudoVLUXSEG4EI8_V_MF2_M2_MASK,
6044 : PseudoVLUXSEG4EI8_V_MF2_MF2,
6045 : PseudoVLUXSEG4EI8_V_MF2_MF2_MASK,
6046 : PseudoVLUXSEG4EI8_V_MF4_M1,
6047 : PseudoVLUXSEG4EI8_V_MF4_M1_MASK,
6048 : PseudoVLUXSEG4EI8_V_MF4_M2,
6049 : PseudoVLUXSEG4EI8_V_MF4_M2_MASK,
6050 : PseudoVLUXSEG4EI8_V_MF4_MF2,
6051 : PseudoVLUXSEG4EI8_V_MF4_MF2_MASK,
6052 : PseudoVLUXSEG4EI8_V_MF4_MF4,
6053 : PseudoVLUXSEG4EI8_V_MF4_MF4_MASK,
6054 : PseudoVLUXSEG4EI8_V_MF8_M1,
6055 : PseudoVLUXSEG4EI8_V_MF8_M1_MASK,
6056 : PseudoVLUXSEG4EI8_V_MF8_MF2,
6057 : PseudoVLUXSEG4EI8_V_MF8_MF2_MASK,
6058 : PseudoVLUXSEG4EI8_V_MF8_MF4,
6059 : PseudoVLUXSEG4EI8_V_MF8_MF4_MASK,
6060 : PseudoVLUXSEG4EI8_V_MF8_MF8,
6061 : PseudoVLUXSEG4EI8_V_MF8_MF8_MASK,
6062 : PseudoVLUXSEG5EI16_V_M1_M1,
6063 : PseudoVLUXSEG5EI16_V_M1_M1_MASK,
6064 : PseudoVLUXSEG5EI16_V_M1_MF2,
6065 : PseudoVLUXSEG5EI16_V_M1_MF2_MASK,
6066 : PseudoVLUXSEG5EI16_V_M2_M1,
6067 : PseudoVLUXSEG5EI16_V_M2_M1_MASK,
6068 : PseudoVLUXSEG5EI16_V_MF2_M1,
6069 : PseudoVLUXSEG5EI16_V_MF2_M1_MASK,
6070 : PseudoVLUXSEG5EI16_V_MF2_MF2,
6071 : PseudoVLUXSEG5EI16_V_MF2_MF2_MASK,
6072 : PseudoVLUXSEG5EI16_V_MF2_MF4,
6073 : PseudoVLUXSEG5EI16_V_MF2_MF4_MASK,
6074 : PseudoVLUXSEG5EI16_V_MF4_M1,
6075 : PseudoVLUXSEG5EI16_V_MF4_M1_MASK,
6076 : PseudoVLUXSEG5EI16_V_MF4_MF2,
6077 : PseudoVLUXSEG5EI16_V_MF4_MF2_MASK,
6078 : PseudoVLUXSEG5EI16_V_MF4_MF4,
6079 : PseudoVLUXSEG5EI16_V_MF4_MF4_MASK,
6080 : PseudoVLUXSEG5EI16_V_MF4_MF8,
6081 : PseudoVLUXSEG5EI16_V_MF4_MF8_MASK,
6082 : PseudoVLUXSEG5EI32_V_M1_M1,
6083 : PseudoVLUXSEG5EI32_V_M1_M1_MASK,
6084 : PseudoVLUXSEG5EI32_V_M1_MF2,
6085 : PseudoVLUXSEG5EI32_V_M1_MF2_MASK,
6086 : PseudoVLUXSEG5EI32_V_M1_MF4,
6087 : PseudoVLUXSEG5EI32_V_M1_MF4_MASK,
6088 : PseudoVLUXSEG5EI32_V_M2_M1,
6089 : PseudoVLUXSEG5EI32_V_M2_M1_MASK,
6090 : PseudoVLUXSEG5EI32_V_M2_MF2,
6091 : PseudoVLUXSEG5EI32_V_M2_MF2_MASK,
6092 : PseudoVLUXSEG5EI32_V_M4_M1,
6093 : PseudoVLUXSEG5EI32_V_M4_M1_MASK,
6094 : PseudoVLUXSEG5EI32_V_MF2_M1,
6095 : PseudoVLUXSEG5EI32_V_MF2_M1_MASK,
6096 : PseudoVLUXSEG5EI32_V_MF2_MF2,
6097 : PseudoVLUXSEG5EI32_V_MF2_MF2_MASK,
6098 : PseudoVLUXSEG5EI32_V_MF2_MF4,
6099 : PseudoVLUXSEG5EI32_V_MF2_MF4_MASK,
6100 : PseudoVLUXSEG5EI32_V_MF2_MF8,
6101 : PseudoVLUXSEG5EI32_V_MF2_MF8_MASK,
6102 : PseudoVLUXSEG5EI64_V_M1_M1,
6103 : PseudoVLUXSEG5EI64_V_M1_M1_MASK,
6104 : PseudoVLUXSEG5EI64_V_M1_MF2,
6105 : PseudoVLUXSEG5EI64_V_M1_MF2_MASK,
6106 : PseudoVLUXSEG5EI64_V_M1_MF4,
6107 : PseudoVLUXSEG5EI64_V_M1_MF4_MASK,
6108 : PseudoVLUXSEG5EI64_V_M1_MF8,
6109 : PseudoVLUXSEG5EI64_V_M1_MF8_MASK,
6110 : PseudoVLUXSEG5EI64_V_M2_M1,
6111 : PseudoVLUXSEG5EI64_V_M2_M1_MASK,
6112 : PseudoVLUXSEG5EI64_V_M2_MF2,
6113 : PseudoVLUXSEG5EI64_V_M2_MF2_MASK,
6114 : PseudoVLUXSEG5EI64_V_M2_MF4,
6115 : PseudoVLUXSEG5EI64_V_M2_MF4_MASK,
6116 : PseudoVLUXSEG5EI64_V_M4_M1,
6117 : PseudoVLUXSEG5EI64_V_M4_M1_MASK,
6118 : PseudoVLUXSEG5EI64_V_M4_MF2,
6119 : PseudoVLUXSEG5EI64_V_M4_MF2_MASK,
6120 : PseudoVLUXSEG5EI64_V_M8_M1,
6121 : PseudoVLUXSEG5EI64_V_M8_M1_MASK,
6122 : PseudoVLUXSEG5EI8_V_M1_M1,
6123 : PseudoVLUXSEG5EI8_V_M1_M1_MASK,
6124 : PseudoVLUXSEG5EI8_V_MF2_M1,
6125 : PseudoVLUXSEG5EI8_V_MF2_M1_MASK,
6126 : PseudoVLUXSEG5EI8_V_MF2_MF2,
6127 : PseudoVLUXSEG5EI8_V_MF2_MF2_MASK,
6128 : PseudoVLUXSEG5EI8_V_MF4_M1,
6129 : PseudoVLUXSEG5EI8_V_MF4_M1_MASK,
6130 : PseudoVLUXSEG5EI8_V_MF4_MF2,
6131 : PseudoVLUXSEG5EI8_V_MF4_MF2_MASK,
6132 : PseudoVLUXSEG5EI8_V_MF4_MF4,
6133 : PseudoVLUXSEG5EI8_V_MF4_MF4_MASK,
6134 : PseudoVLUXSEG5EI8_V_MF8_M1,
6135 : PseudoVLUXSEG5EI8_V_MF8_M1_MASK,
6136 : PseudoVLUXSEG5EI8_V_MF8_MF2,
6137 : PseudoVLUXSEG5EI8_V_MF8_MF2_MASK,
6138 : PseudoVLUXSEG5EI8_V_MF8_MF4,
6139 : PseudoVLUXSEG5EI8_V_MF8_MF4_MASK,
6140 : PseudoVLUXSEG5EI8_V_MF8_MF8,
6141 : PseudoVLUXSEG5EI8_V_MF8_MF8_MASK,
6142 : PseudoVLUXSEG6EI16_V_M1_M1,
6143 : PseudoVLUXSEG6EI16_V_M1_M1_MASK,
6144 : PseudoVLUXSEG6EI16_V_M1_MF2,
6145 : PseudoVLUXSEG6EI16_V_M1_MF2_MASK,
6146 : PseudoVLUXSEG6EI16_V_M2_M1,
6147 : PseudoVLUXSEG6EI16_V_M2_M1_MASK,
6148 : PseudoVLUXSEG6EI16_V_MF2_M1,
6149 : PseudoVLUXSEG6EI16_V_MF2_M1_MASK,
6150 : PseudoVLUXSEG6EI16_V_MF2_MF2,
6151 : PseudoVLUXSEG6EI16_V_MF2_MF2_MASK,
6152 : PseudoVLUXSEG6EI16_V_MF2_MF4,
6153 : PseudoVLUXSEG6EI16_V_MF2_MF4_MASK,
6154 : PseudoVLUXSEG6EI16_V_MF4_M1,
6155 : PseudoVLUXSEG6EI16_V_MF4_M1_MASK,
6156 : PseudoVLUXSEG6EI16_V_MF4_MF2,
6157 : PseudoVLUXSEG6EI16_V_MF4_MF2_MASK,
6158 : PseudoVLUXSEG6EI16_V_MF4_MF4,
6159 : PseudoVLUXSEG6EI16_V_MF4_MF4_MASK,
6160 : PseudoVLUXSEG6EI16_V_MF4_MF8,
6161 : PseudoVLUXSEG6EI16_V_MF4_MF8_MASK,
6162 : PseudoVLUXSEG6EI32_V_M1_M1,
6163 : PseudoVLUXSEG6EI32_V_M1_M1_MASK,
6164 : PseudoVLUXSEG6EI32_V_M1_MF2,
6165 : PseudoVLUXSEG6EI32_V_M1_MF2_MASK,
6166 : PseudoVLUXSEG6EI32_V_M1_MF4,
6167 : PseudoVLUXSEG6EI32_V_M1_MF4_MASK,
6168 : PseudoVLUXSEG6EI32_V_M2_M1,
6169 : PseudoVLUXSEG6EI32_V_M2_M1_MASK,
6170 : PseudoVLUXSEG6EI32_V_M2_MF2,
6171 : PseudoVLUXSEG6EI32_V_M2_MF2_MASK,
6172 : PseudoVLUXSEG6EI32_V_M4_M1,
6173 : PseudoVLUXSEG6EI32_V_M4_M1_MASK,
6174 : PseudoVLUXSEG6EI32_V_MF2_M1,
6175 : PseudoVLUXSEG6EI32_V_MF2_M1_MASK,
6176 : PseudoVLUXSEG6EI32_V_MF2_MF2,
6177 : PseudoVLUXSEG6EI32_V_MF2_MF2_MASK,
6178 : PseudoVLUXSEG6EI32_V_MF2_MF4,
6179 : PseudoVLUXSEG6EI32_V_MF2_MF4_MASK,
6180 : PseudoVLUXSEG6EI32_V_MF2_MF8,
6181 : PseudoVLUXSEG6EI32_V_MF2_MF8_MASK,
6182 : PseudoVLUXSEG6EI64_V_M1_M1,
6183 : PseudoVLUXSEG6EI64_V_M1_M1_MASK,
6184 : PseudoVLUXSEG6EI64_V_M1_MF2,
6185 : PseudoVLUXSEG6EI64_V_M1_MF2_MASK,
6186 : PseudoVLUXSEG6EI64_V_M1_MF4,
6187 : PseudoVLUXSEG6EI64_V_M1_MF4_MASK,
6188 : PseudoVLUXSEG6EI64_V_M1_MF8,
6189 : PseudoVLUXSEG6EI64_V_M1_MF8_MASK,
6190 : PseudoVLUXSEG6EI64_V_M2_M1,
6191 : PseudoVLUXSEG6EI64_V_M2_M1_MASK,
6192 : PseudoVLUXSEG6EI64_V_M2_MF2,
6193 : PseudoVLUXSEG6EI64_V_M2_MF2_MASK,
6194 : PseudoVLUXSEG6EI64_V_M2_MF4,
6195 : PseudoVLUXSEG6EI64_V_M2_MF4_MASK,
6196 : PseudoVLUXSEG6EI64_V_M4_M1,
6197 : PseudoVLUXSEG6EI64_V_M4_M1_MASK,
6198 : PseudoVLUXSEG6EI64_V_M4_MF2,
6199 : PseudoVLUXSEG6EI64_V_M4_MF2_MASK,
6200 : PseudoVLUXSEG6EI64_V_M8_M1,
6201 : PseudoVLUXSEG6EI64_V_M8_M1_MASK,
6202 : PseudoVLUXSEG6EI8_V_M1_M1,
6203 : PseudoVLUXSEG6EI8_V_M1_M1_MASK,
6204 : PseudoVLUXSEG6EI8_V_MF2_M1,
6205 : PseudoVLUXSEG6EI8_V_MF2_M1_MASK,
6206 : PseudoVLUXSEG6EI8_V_MF2_MF2,
6207 : PseudoVLUXSEG6EI8_V_MF2_MF2_MASK,
6208 : PseudoVLUXSEG6EI8_V_MF4_M1,
6209 : PseudoVLUXSEG6EI8_V_MF4_M1_MASK,
6210 : PseudoVLUXSEG6EI8_V_MF4_MF2,
6211 : PseudoVLUXSEG6EI8_V_MF4_MF2_MASK,
6212 : PseudoVLUXSEG6EI8_V_MF4_MF4,
6213 : PseudoVLUXSEG6EI8_V_MF4_MF4_MASK,
6214 : PseudoVLUXSEG6EI8_V_MF8_M1,
6215 : PseudoVLUXSEG6EI8_V_MF8_M1_MASK,
6216 : PseudoVLUXSEG6EI8_V_MF8_MF2,
6217 : PseudoVLUXSEG6EI8_V_MF8_MF2_MASK,
6218 : PseudoVLUXSEG6EI8_V_MF8_MF4,
6219 : PseudoVLUXSEG6EI8_V_MF8_MF4_MASK,
6220 : PseudoVLUXSEG6EI8_V_MF8_MF8,
6221 : PseudoVLUXSEG6EI8_V_MF8_MF8_MASK,
6222 : PseudoVLUXSEG7EI16_V_M1_M1,
6223 : PseudoVLUXSEG7EI16_V_M1_M1_MASK,
6224 : PseudoVLUXSEG7EI16_V_M1_MF2,
6225 : PseudoVLUXSEG7EI16_V_M1_MF2_MASK,
6226 : PseudoVLUXSEG7EI16_V_M2_M1,
6227 : PseudoVLUXSEG7EI16_V_M2_M1_MASK,
6228 : PseudoVLUXSEG7EI16_V_MF2_M1,
6229 : PseudoVLUXSEG7EI16_V_MF2_M1_MASK,
6230 : PseudoVLUXSEG7EI16_V_MF2_MF2,
6231 : PseudoVLUXSEG7EI16_V_MF2_MF2_MASK,
6232 : PseudoVLUXSEG7EI16_V_MF2_MF4,
6233 : PseudoVLUXSEG7EI16_V_MF2_MF4_MASK,
6234 : PseudoVLUXSEG7EI16_V_MF4_M1,
6235 : PseudoVLUXSEG7EI16_V_MF4_M1_MASK,
6236 : PseudoVLUXSEG7EI16_V_MF4_MF2,
6237 : PseudoVLUXSEG7EI16_V_MF4_MF2_MASK,
6238 : PseudoVLUXSEG7EI16_V_MF4_MF4,
6239 : PseudoVLUXSEG7EI16_V_MF4_MF4_MASK,
6240 : PseudoVLUXSEG7EI16_V_MF4_MF8,
6241 : PseudoVLUXSEG7EI16_V_MF4_MF8_MASK,
6242 : PseudoVLUXSEG7EI32_V_M1_M1,
6243 : PseudoVLUXSEG7EI32_V_M1_M1_MASK,
6244 : PseudoVLUXSEG7EI32_V_M1_MF2,
6245 : PseudoVLUXSEG7EI32_V_M1_MF2_MASK,
6246 : PseudoVLUXSEG7EI32_V_M1_MF4,
6247 : PseudoVLUXSEG7EI32_V_M1_MF4_MASK,
6248 : PseudoVLUXSEG7EI32_V_M2_M1,
6249 : PseudoVLUXSEG7EI32_V_M2_M1_MASK,
6250 : PseudoVLUXSEG7EI32_V_M2_MF2,
6251 : PseudoVLUXSEG7EI32_V_M2_MF2_MASK,
6252 : PseudoVLUXSEG7EI32_V_M4_M1,
6253 : PseudoVLUXSEG7EI32_V_M4_M1_MASK,
6254 : PseudoVLUXSEG7EI32_V_MF2_M1,
6255 : PseudoVLUXSEG7EI32_V_MF2_M1_MASK,
6256 : PseudoVLUXSEG7EI32_V_MF2_MF2,
6257 : PseudoVLUXSEG7EI32_V_MF2_MF2_MASK,
6258 : PseudoVLUXSEG7EI32_V_MF2_MF4,
6259 : PseudoVLUXSEG7EI32_V_MF2_MF4_MASK,
6260 : PseudoVLUXSEG7EI32_V_MF2_MF8,
6261 : PseudoVLUXSEG7EI32_V_MF2_MF8_MASK,
6262 : PseudoVLUXSEG7EI64_V_M1_M1,
6263 : PseudoVLUXSEG7EI64_V_M1_M1_MASK,
6264 : PseudoVLUXSEG7EI64_V_M1_MF2,
6265 : PseudoVLUXSEG7EI64_V_M1_MF2_MASK,
6266 : PseudoVLUXSEG7EI64_V_M1_MF4,
6267 : PseudoVLUXSEG7EI64_V_M1_MF4_MASK,
6268 : PseudoVLUXSEG7EI64_V_M1_MF8,
6269 : PseudoVLUXSEG7EI64_V_M1_MF8_MASK,
6270 : PseudoVLUXSEG7EI64_V_M2_M1,
6271 : PseudoVLUXSEG7EI64_V_M2_M1_MASK,
6272 : PseudoVLUXSEG7EI64_V_M2_MF2,
6273 : PseudoVLUXSEG7EI64_V_M2_MF2_MASK,
6274 : PseudoVLUXSEG7EI64_V_M2_MF4,
6275 : PseudoVLUXSEG7EI64_V_M2_MF4_MASK,
6276 : PseudoVLUXSEG7EI64_V_M4_M1,
6277 : PseudoVLUXSEG7EI64_V_M4_M1_MASK,
6278 : PseudoVLUXSEG7EI64_V_M4_MF2,
6279 : PseudoVLUXSEG7EI64_V_M4_MF2_MASK,
6280 : PseudoVLUXSEG7EI64_V_M8_M1,
6281 : PseudoVLUXSEG7EI64_V_M8_M1_MASK,
6282 : PseudoVLUXSEG7EI8_V_M1_M1,
6283 : PseudoVLUXSEG7EI8_V_M1_M1_MASK,
6284 : PseudoVLUXSEG7EI8_V_MF2_M1,
6285 : PseudoVLUXSEG7EI8_V_MF2_M1_MASK,
6286 : PseudoVLUXSEG7EI8_V_MF2_MF2,
6287 : PseudoVLUXSEG7EI8_V_MF2_MF2_MASK,
6288 : PseudoVLUXSEG7EI8_V_MF4_M1,
6289 : PseudoVLUXSEG7EI8_V_MF4_M1_MASK,
6290 : PseudoVLUXSEG7EI8_V_MF4_MF2,
6291 : PseudoVLUXSEG7EI8_V_MF4_MF2_MASK,
6292 : PseudoVLUXSEG7EI8_V_MF4_MF4,
6293 : PseudoVLUXSEG7EI8_V_MF4_MF4_MASK,
6294 : PseudoVLUXSEG7EI8_V_MF8_M1,
6295 : PseudoVLUXSEG7EI8_V_MF8_M1_MASK,
6296 : PseudoVLUXSEG7EI8_V_MF8_MF2,
6297 : PseudoVLUXSEG7EI8_V_MF8_MF2_MASK,
6298 : PseudoVLUXSEG7EI8_V_MF8_MF4,
6299 : PseudoVLUXSEG7EI8_V_MF8_MF4_MASK,
6300 : PseudoVLUXSEG7EI8_V_MF8_MF8,
6301 : PseudoVLUXSEG7EI8_V_MF8_MF8_MASK,
6302 : PseudoVLUXSEG8EI16_V_M1_M1,
6303 : PseudoVLUXSEG8EI16_V_M1_M1_MASK,
6304 : PseudoVLUXSEG8EI16_V_M1_MF2,
6305 : PseudoVLUXSEG8EI16_V_M1_MF2_MASK,
6306 : PseudoVLUXSEG8EI16_V_M2_M1,
6307 : PseudoVLUXSEG8EI16_V_M2_M1_MASK,
6308 : PseudoVLUXSEG8EI16_V_MF2_M1,
6309 : PseudoVLUXSEG8EI16_V_MF2_M1_MASK,
6310 : PseudoVLUXSEG8EI16_V_MF2_MF2,
6311 : PseudoVLUXSEG8EI16_V_MF2_MF2_MASK,
6312 : PseudoVLUXSEG8EI16_V_MF2_MF4,
6313 : PseudoVLUXSEG8EI16_V_MF2_MF4_MASK,
6314 : PseudoVLUXSEG8EI16_V_MF4_M1,
6315 : PseudoVLUXSEG8EI16_V_MF4_M1_MASK,
6316 : PseudoVLUXSEG8EI16_V_MF4_MF2,
6317 : PseudoVLUXSEG8EI16_V_MF4_MF2_MASK,
6318 : PseudoVLUXSEG8EI16_V_MF4_MF4,
6319 : PseudoVLUXSEG8EI16_V_MF4_MF4_MASK,
6320 : PseudoVLUXSEG8EI16_V_MF4_MF8,
6321 : PseudoVLUXSEG8EI16_V_MF4_MF8_MASK,
6322 : PseudoVLUXSEG8EI32_V_M1_M1,
6323 : PseudoVLUXSEG8EI32_V_M1_M1_MASK,
6324 : PseudoVLUXSEG8EI32_V_M1_MF2,
6325 : PseudoVLUXSEG8EI32_V_M1_MF2_MASK,
6326 : PseudoVLUXSEG8EI32_V_M1_MF4,
6327 : PseudoVLUXSEG8EI32_V_M1_MF4_MASK,
6328 : PseudoVLUXSEG8EI32_V_M2_M1,
6329 : PseudoVLUXSEG8EI32_V_M2_M1_MASK,
6330 : PseudoVLUXSEG8EI32_V_M2_MF2,
6331 : PseudoVLUXSEG8EI32_V_M2_MF2_MASK,
6332 : PseudoVLUXSEG8EI32_V_M4_M1,
6333 : PseudoVLUXSEG8EI32_V_M4_M1_MASK,
6334 : PseudoVLUXSEG8EI32_V_MF2_M1,
6335 : PseudoVLUXSEG8EI32_V_MF2_M1_MASK,
6336 : PseudoVLUXSEG8EI32_V_MF2_MF2,
6337 : PseudoVLUXSEG8EI32_V_MF2_MF2_MASK,
6338 : PseudoVLUXSEG8EI32_V_MF2_MF4,
6339 : PseudoVLUXSEG8EI32_V_MF2_MF4_MASK,
6340 : PseudoVLUXSEG8EI32_V_MF2_MF8,
6341 : PseudoVLUXSEG8EI32_V_MF2_MF8_MASK,
6342 : PseudoVLUXSEG8EI64_V_M1_M1,
6343 : PseudoVLUXSEG8EI64_V_M1_M1_MASK,
6344 : PseudoVLUXSEG8EI64_V_M1_MF2,
6345 : PseudoVLUXSEG8EI64_V_M1_MF2_MASK,
6346 : PseudoVLUXSEG8EI64_V_M1_MF4,
6347 : PseudoVLUXSEG8EI64_V_M1_MF4_MASK,
6348 : PseudoVLUXSEG8EI64_V_M1_MF8,
6349 : PseudoVLUXSEG8EI64_V_M1_MF8_MASK,
6350 : PseudoVLUXSEG8EI64_V_M2_M1,
6351 : PseudoVLUXSEG8EI64_V_M2_M1_MASK,
6352 : PseudoVLUXSEG8EI64_V_M2_MF2,
6353 : PseudoVLUXSEG8EI64_V_M2_MF2_MASK,
6354 : PseudoVLUXSEG8EI64_V_M2_MF4,
6355 : PseudoVLUXSEG8EI64_V_M2_MF4_MASK,
6356 : PseudoVLUXSEG8EI64_V_M4_M1,
6357 : PseudoVLUXSEG8EI64_V_M4_M1_MASK,
6358 : PseudoVLUXSEG8EI64_V_M4_MF2,
6359 : PseudoVLUXSEG8EI64_V_M4_MF2_MASK,
6360 : PseudoVLUXSEG8EI64_V_M8_M1,
6361 : PseudoVLUXSEG8EI64_V_M8_M1_MASK,
6362 : PseudoVLUXSEG8EI8_V_M1_M1,
6363 : PseudoVLUXSEG8EI8_V_M1_M1_MASK,
6364 : PseudoVLUXSEG8EI8_V_MF2_M1,
6365 : PseudoVLUXSEG8EI8_V_MF2_M1_MASK,
6366 : PseudoVLUXSEG8EI8_V_MF2_MF2,
6367 : PseudoVLUXSEG8EI8_V_MF2_MF2_MASK,
6368 : PseudoVLUXSEG8EI8_V_MF4_M1,
6369 : PseudoVLUXSEG8EI8_V_MF4_M1_MASK,
6370 : PseudoVLUXSEG8EI8_V_MF4_MF2,
6371 : PseudoVLUXSEG8EI8_V_MF4_MF2_MASK,
6372 : PseudoVLUXSEG8EI8_V_MF4_MF4,
6373 : PseudoVLUXSEG8EI8_V_MF4_MF4_MASK,
6374 : PseudoVLUXSEG8EI8_V_MF8_M1,
6375 : PseudoVLUXSEG8EI8_V_MF8_M1_MASK,
6376 : PseudoVLUXSEG8EI8_V_MF8_MF2,
6377 : PseudoVLUXSEG8EI8_V_MF8_MF2_MASK,
6378 : PseudoVLUXSEG8EI8_V_MF8_MF4,
6379 : PseudoVLUXSEG8EI8_V_MF8_MF4_MASK,
6380 : PseudoVLUXSEG8EI8_V_MF8_MF8,
6381 : PseudoVLUXSEG8EI8_V_MF8_MF8_MASK,
6382 : PseudoVMACC_VV_M1,
6383 : PseudoVMACC_VV_M1_MASK,
6384 : PseudoVMACC_VV_M2,
6385 : PseudoVMACC_VV_M2_MASK,
6386 : PseudoVMACC_VV_M4,
6387 : PseudoVMACC_VV_M4_MASK,
6388 : PseudoVMACC_VV_M8,
6389 : PseudoVMACC_VV_M8_MASK,
6390 : PseudoVMACC_VV_MF2,
6391 : PseudoVMACC_VV_MF2_MASK,
6392 : PseudoVMACC_VV_MF4,
6393 : PseudoVMACC_VV_MF4_MASK,
6394 : PseudoVMACC_VV_MF8,
6395 : PseudoVMACC_VV_MF8_MASK,
6396 : PseudoVMACC_VX_M1,
6397 : PseudoVMACC_VX_M1_MASK,
6398 : PseudoVMACC_VX_M2,
6399 : PseudoVMACC_VX_M2_MASK,
6400 : PseudoVMACC_VX_M4,
6401 : PseudoVMACC_VX_M4_MASK,
6402 : PseudoVMACC_VX_M8,
6403 : PseudoVMACC_VX_M8_MASK,
6404 : PseudoVMACC_VX_MF2,
6405 : PseudoVMACC_VX_MF2_MASK,
6406 : PseudoVMACC_VX_MF4,
6407 : PseudoVMACC_VX_MF4_MASK,
6408 : PseudoVMACC_VX_MF8,
6409 : PseudoVMACC_VX_MF8_MASK,
6410 : PseudoVMADC_VIM_M1,
6411 : PseudoVMADC_VIM_M2,
6412 : PseudoVMADC_VIM_M4,
6413 : PseudoVMADC_VIM_M8,
6414 : PseudoVMADC_VIM_MF2,
6415 : PseudoVMADC_VIM_MF4,
6416 : PseudoVMADC_VIM_MF8,
6417 : PseudoVMADC_VI_M1,
6418 : PseudoVMADC_VI_M2,
6419 : PseudoVMADC_VI_M4,
6420 : PseudoVMADC_VI_M8,
6421 : PseudoVMADC_VI_MF2,
6422 : PseudoVMADC_VI_MF4,
6423 : PseudoVMADC_VI_MF8,
6424 : PseudoVMADC_VVM_M1,
6425 : PseudoVMADC_VVM_M2,
6426 : PseudoVMADC_VVM_M4,
6427 : PseudoVMADC_VVM_M8,
6428 : PseudoVMADC_VVM_MF2,
6429 : PseudoVMADC_VVM_MF4,
6430 : PseudoVMADC_VVM_MF8,
6431 : PseudoVMADC_VV_M1,
6432 : PseudoVMADC_VV_M2,
6433 : PseudoVMADC_VV_M4,
6434 : PseudoVMADC_VV_M8,
6435 : PseudoVMADC_VV_MF2,
6436 : PseudoVMADC_VV_MF4,
6437 : PseudoVMADC_VV_MF8,
6438 : PseudoVMADC_VXM_M1,
6439 : PseudoVMADC_VXM_M2,
6440 : PseudoVMADC_VXM_M4,
6441 : PseudoVMADC_VXM_M8,
6442 : PseudoVMADC_VXM_MF2,
6443 : PseudoVMADC_VXM_MF4,
6444 : PseudoVMADC_VXM_MF8,
6445 : PseudoVMADC_VX_M1,
6446 : PseudoVMADC_VX_M2,
6447 : PseudoVMADC_VX_M4,
6448 : PseudoVMADC_VX_M8,
6449 : PseudoVMADC_VX_MF2,
6450 : PseudoVMADC_VX_MF4,
6451 : PseudoVMADC_VX_MF8,
6452 : PseudoVMADD_VV_M1,
6453 : PseudoVMADD_VV_M1_MASK,
6454 : PseudoVMADD_VV_M2,
6455 : PseudoVMADD_VV_M2_MASK,
6456 : PseudoVMADD_VV_M4,
6457 : PseudoVMADD_VV_M4_MASK,
6458 : PseudoVMADD_VV_M8,
6459 : PseudoVMADD_VV_M8_MASK,
6460 : PseudoVMADD_VV_MF2,
6461 : PseudoVMADD_VV_MF2_MASK,
6462 : PseudoVMADD_VV_MF4,
6463 : PseudoVMADD_VV_MF4_MASK,
6464 : PseudoVMADD_VV_MF8,
6465 : PseudoVMADD_VV_MF8_MASK,
6466 : PseudoVMADD_VX_M1,
6467 : PseudoVMADD_VX_M1_MASK,
6468 : PseudoVMADD_VX_M2,
6469 : PseudoVMADD_VX_M2_MASK,
6470 : PseudoVMADD_VX_M4,
6471 : PseudoVMADD_VX_M4_MASK,
6472 : PseudoVMADD_VX_M8,
6473 : PseudoVMADD_VX_M8_MASK,
6474 : PseudoVMADD_VX_MF2,
6475 : PseudoVMADD_VX_MF2_MASK,
6476 : PseudoVMADD_VX_MF4,
6477 : PseudoVMADD_VX_MF4_MASK,
6478 : PseudoVMADD_VX_MF8,
6479 : PseudoVMADD_VX_MF8_MASK,
6480 : PseudoVMANDN_MM_M1,
6481 : PseudoVMANDN_MM_M2,
6482 : PseudoVMANDN_MM_M4,
6483 : PseudoVMANDN_MM_M8,
6484 : PseudoVMANDN_MM_MF2,
6485 : PseudoVMANDN_MM_MF4,
6486 : PseudoVMANDN_MM_MF8,
6487 : PseudoVMAND_MM_M1,
6488 : PseudoVMAND_MM_M2,
6489 : PseudoVMAND_MM_M4,
6490 : PseudoVMAND_MM_M8,
6491 : PseudoVMAND_MM_MF2,
6492 : PseudoVMAND_MM_MF4,
6493 : PseudoVMAND_MM_MF8,
6494 : PseudoVMAXU_VV_M1,
6495 : PseudoVMAXU_VV_M1_MASK,
6496 : PseudoVMAXU_VV_M2,
6497 : PseudoVMAXU_VV_M2_MASK,
6498 : PseudoVMAXU_VV_M4,
6499 : PseudoVMAXU_VV_M4_MASK,
6500 : PseudoVMAXU_VV_M8,
6501 : PseudoVMAXU_VV_M8_MASK,
6502 : PseudoVMAXU_VV_MF2,
6503 : PseudoVMAXU_VV_MF2_MASK,
6504 : PseudoVMAXU_VV_MF4,
6505 : PseudoVMAXU_VV_MF4_MASK,
6506 : PseudoVMAXU_VV_MF8,
6507 : PseudoVMAXU_VV_MF8_MASK,
6508 : PseudoVMAXU_VX_M1,
6509 : PseudoVMAXU_VX_M1_MASK,
6510 : PseudoVMAXU_VX_M2,
6511 : PseudoVMAXU_VX_M2_MASK,
6512 : PseudoVMAXU_VX_M4,
6513 : PseudoVMAXU_VX_M4_MASK,
6514 : PseudoVMAXU_VX_M8,
6515 : PseudoVMAXU_VX_M8_MASK,
6516 : PseudoVMAXU_VX_MF2,
6517 : PseudoVMAXU_VX_MF2_MASK,
6518 : PseudoVMAXU_VX_MF4,
6519 : PseudoVMAXU_VX_MF4_MASK,
6520 : PseudoVMAXU_VX_MF8,
6521 : PseudoVMAXU_VX_MF8_MASK,
6522 : PseudoVMAX_VV_M1,
6523 : PseudoVMAX_VV_M1_MASK,
6524 : PseudoVMAX_VV_M2,
6525 : PseudoVMAX_VV_M2_MASK,
6526 : PseudoVMAX_VV_M4,
6527 : PseudoVMAX_VV_M4_MASK,
6528 : PseudoVMAX_VV_M8,
6529 : PseudoVMAX_VV_M8_MASK,
6530 : PseudoVMAX_VV_MF2,
6531 : PseudoVMAX_VV_MF2_MASK,
6532 : PseudoVMAX_VV_MF4,
6533 : PseudoVMAX_VV_MF4_MASK,
6534 : PseudoVMAX_VV_MF8,
6535 : PseudoVMAX_VV_MF8_MASK,
6536 : PseudoVMAX_VX_M1,
6537 : PseudoVMAX_VX_M1_MASK,
6538 : PseudoVMAX_VX_M2,
6539 : PseudoVMAX_VX_M2_MASK,
6540 : PseudoVMAX_VX_M4,
6541 : PseudoVMAX_VX_M4_MASK,
6542 : PseudoVMAX_VX_M8,
6543 : PseudoVMAX_VX_M8_MASK,
6544 : PseudoVMAX_VX_MF2,
6545 : PseudoVMAX_VX_MF2_MASK,
6546 : PseudoVMAX_VX_MF4,
6547 : PseudoVMAX_VX_MF4_MASK,
6548 : PseudoVMAX_VX_MF8,
6549 : PseudoVMAX_VX_MF8_MASK,
6550 : PseudoVMCLR_M_B1,
6551 : PseudoVMCLR_M_B16,
6552 : PseudoVMCLR_M_B2,
6553 : PseudoVMCLR_M_B32,
6554 : PseudoVMCLR_M_B4,
6555 : PseudoVMCLR_M_B64,
6556 : PseudoVMCLR_M_B8,
6557 : PseudoVMERGE_VIM_M1,
6558 : PseudoVMERGE_VIM_M2,
6559 : PseudoVMERGE_VIM_M4,
6560 : PseudoVMERGE_VIM_M8,
6561 : PseudoVMERGE_VIM_MF2,
6562 : PseudoVMERGE_VIM_MF4,
6563 : PseudoVMERGE_VIM_MF8,
6564 : PseudoVMERGE_VVM_M1,
6565 : PseudoVMERGE_VVM_M2,
6566 : PseudoVMERGE_VVM_M4,
6567 : PseudoVMERGE_VVM_M8,
6568 : PseudoVMERGE_VVM_MF2,
6569 : PseudoVMERGE_VVM_MF4,
6570 : PseudoVMERGE_VVM_MF8,
6571 : PseudoVMERGE_VXM_M1,
6572 : PseudoVMERGE_VXM_M2,
6573 : PseudoVMERGE_VXM_M4,
6574 : PseudoVMERGE_VXM_M8,
6575 : PseudoVMERGE_VXM_MF2,
6576 : PseudoVMERGE_VXM_MF4,
6577 : PseudoVMERGE_VXM_MF8,
6578 : PseudoVMFEQ_VFPR16_M1,
6579 : PseudoVMFEQ_VFPR16_M1_MASK,
6580 : PseudoVMFEQ_VFPR16_M2,
6581 : PseudoVMFEQ_VFPR16_M2_MASK,
6582 : PseudoVMFEQ_VFPR16_M4,
6583 : PseudoVMFEQ_VFPR16_M4_MASK,
6584 : PseudoVMFEQ_VFPR16_M8,
6585 : PseudoVMFEQ_VFPR16_M8_MASK,
6586 : PseudoVMFEQ_VFPR16_MF2,
6587 : PseudoVMFEQ_VFPR16_MF2_MASK,
6588 : PseudoVMFEQ_VFPR16_MF4,
6589 : PseudoVMFEQ_VFPR16_MF4_MASK,
6590 : PseudoVMFEQ_VFPR32_M1,
6591 : PseudoVMFEQ_VFPR32_M1_MASK,
6592 : PseudoVMFEQ_VFPR32_M2,
6593 : PseudoVMFEQ_VFPR32_M2_MASK,
6594 : PseudoVMFEQ_VFPR32_M4,
6595 : PseudoVMFEQ_VFPR32_M4_MASK,
6596 : PseudoVMFEQ_VFPR32_M8,
6597 : PseudoVMFEQ_VFPR32_M8_MASK,
6598 : PseudoVMFEQ_VFPR32_MF2,
6599 : PseudoVMFEQ_VFPR32_MF2_MASK,
6600 : PseudoVMFEQ_VFPR64_M1,
6601 : PseudoVMFEQ_VFPR64_M1_MASK,
6602 : PseudoVMFEQ_VFPR64_M2,
6603 : PseudoVMFEQ_VFPR64_M2_MASK,
6604 : PseudoVMFEQ_VFPR64_M4,
6605 : PseudoVMFEQ_VFPR64_M4_MASK,
6606 : PseudoVMFEQ_VFPR64_M8,
6607 : PseudoVMFEQ_VFPR64_M8_MASK,
6608 : PseudoVMFEQ_VV_M1,
6609 : PseudoVMFEQ_VV_M1_MASK,
6610 : PseudoVMFEQ_VV_M2,
6611 : PseudoVMFEQ_VV_M2_MASK,
6612 : PseudoVMFEQ_VV_M4,
6613 : PseudoVMFEQ_VV_M4_MASK,
6614 : PseudoVMFEQ_VV_M8,
6615 : PseudoVMFEQ_VV_M8_MASK,
6616 : PseudoVMFEQ_VV_MF2,
6617 : PseudoVMFEQ_VV_MF2_MASK,
6618 : PseudoVMFEQ_VV_MF4,
6619 : PseudoVMFEQ_VV_MF4_MASK,
6620 : PseudoVMFGE_VFPR16_M1,
6621 : PseudoVMFGE_VFPR16_M1_MASK,
6622 : PseudoVMFGE_VFPR16_M2,
6623 : PseudoVMFGE_VFPR16_M2_MASK,
6624 : PseudoVMFGE_VFPR16_M4,
6625 : PseudoVMFGE_VFPR16_M4_MASK,
6626 : PseudoVMFGE_VFPR16_M8,
6627 : PseudoVMFGE_VFPR16_M8_MASK,
6628 : PseudoVMFGE_VFPR16_MF2,
6629 : PseudoVMFGE_VFPR16_MF2_MASK,
6630 : PseudoVMFGE_VFPR16_MF4,
6631 : PseudoVMFGE_VFPR16_MF4_MASK,
6632 : PseudoVMFGE_VFPR32_M1,
6633 : PseudoVMFGE_VFPR32_M1_MASK,
6634 : PseudoVMFGE_VFPR32_M2,
6635 : PseudoVMFGE_VFPR32_M2_MASK,
6636 : PseudoVMFGE_VFPR32_M4,
6637 : PseudoVMFGE_VFPR32_M4_MASK,
6638 : PseudoVMFGE_VFPR32_M8,
6639 : PseudoVMFGE_VFPR32_M8_MASK,
6640 : PseudoVMFGE_VFPR32_MF2,
6641 : PseudoVMFGE_VFPR32_MF2_MASK,
6642 : PseudoVMFGE_VFPR64_M1,
6643 : PseudoVMFGE_VFPR64_M1_MASK,
6644 : PseudoVMFGE_VFPR64_M2,
6645 : PseudoVMFGE_VFPR64_M2_MASK,
6646 : PseudoVMFGE_VFPR64_M4,
6647 : PseudoVMFGE_VFPR64_M4_MASK,
6648 : PseudoVMFGE_VFPR64_M8,
6649 : PseudoVMFGE_VFPR64_M8_MASK,
6650 : PseudoVMFGT_VFPR16_M1,
6651 : PseudoVMFGT_VFPR16_M1_MASK,
6652 : PseudoVMFGT_VFPR16_M2,
6653 : PseudoVMFGT_VFPR16_M2_MASK,
6654 : PseudoVMFGT_VFPR16_M4,
6655 : PseudoVMFGT_VFPR16_M4_MASK,
6656 : PseudoVMFGT_VFPR16_M8,
6657 : PseudoVMFGT_VFPR16_M8_MASK,
6658 : PseudoVMFGT_VFPR16_MF2,
6659 : PseudoVMFGT_VFPR16_MF2_MASK,
6660 : PseudoVMFGT_VFPR16_MF4,
6661 : PseudoVMFGT_VFPR16_MF4_MASK,
6662 : PseudoVMFGT_VFPR32_M1,
6663 : PseudoVMFGT_VFPR32_M1_MASK,
6664 : PseudoVMFGT_VFPR32_M2,
6665 : PseudoVMFGT_VFPR32_M2_MASK,
6666 : PseudoVMFGT_VFPR32_M4,
6667 : PseudoVMFGT_VFPR32_M4_MASK,
6668 : PseudoVMFGT_VFPR32_M8,
6669 : PseudoVMFGT_VFPR32_M8_MASK,
6670 : PseudoVMFGT_VFPR32_MF2,
6671 : PseudoVMFGT_VFPR32_MF2_MASK,
6672 : PseudoVMFGT_VFPR64_M1,
6673 : PseudoVMFGT_VFPR64_M1_MASK,
6674 : PseudoVMFGT_VFPR64_M2,
6675 : PseudoVMFGT_VFPR64_M2_MASK,
6676 : PseudoVMFGT_VFPR64_M4,
6677 : PseudoVMFGT_VFPR64_M4_MASK,
6678 : PseudoVMFGT_VFPR64_M8,
6679 : PseudoVMFGT_VFPR64_M8_MASK,
6680 : PseudoVMFLE_VFPR16_M1,
6681 : PseudoVMFLE_VFPR16_M1_MASK,
6682 : PseudoVMFLE_VFPR16_M2,
6683 : PseudoVMFLE_VFPR16_M2_MASK,
6684 : PseudoVMFLE_VFPR16_M4,
6685 : PseudoVMFLE_VFPR16_M4_MASK,
6686 : PseudoVMFLE_VFPR16_M8,
6687 : PseudoVMFLE_VFPR16_M8_MASK,
6688 : PseudoVMFLE_VFPR16_MF2,
6689 : PseudoVMFLE_VFPR16_MF2_MASK,
6690 : PseudoVMFLE_VFPR16_MF4,
6691 : PseudoVMFLE_VFPR16_MF4_MASK,
6692 : PseudoVMFLE_VFPR32_M1,
6693 : PseudoVMFLE_VFPR32_M1_MASK,
6694 : PseudoVMFLE_VFPR32_M2,
6695 : PseudoVMFLE_VFPR32_M2_MASK,
6696 : PseudoVMFLE_VFPR32_M4,
6697 : PseudoVMFLE_VFPR32_M4_MASK,
6698 : PseudoVMFLE_VFPR32_M8,
6699 : PseudoVMFLE_VFPR32_M8_MASK,
6700 : PseudoVMFLE_VFPR32_MF2,
6701 : PseudoVMFLE_VFPR32_MF2_MASK,
6702 : PseudoVMFLE_VFPR64_M1,
6703 : PseudoVMFLE_VFPR64_M1_MASK,
6704 : PseudoVMFLE_VFPR64_M2,
6705 : PseudoVMFLE_VFPR64_M2_MASK,
6706 : PseudoVMFLE_VFPR64_M4,
6707 : PseudoVMFLE_VFPR64_M4_MASK,
6708 : PseudoVMFLE_VFPR64_M8,
6709 : PseudoVMFLE_VFPR64_M8_MASK,
6710 : PseudoVMFLE_VV_M1,
6711 : PseudoVMFLE_VV_M1_MASK,
6712 : PseudoVMFLE_VV_M2,
6713 : PseudoVMFLE_VV_M2_MASK,
6714 : PseudoVMFLE_VV_M4,
6715 : PseudoVMFLE_VV_M4_MASK,
6716 : PseudoVMFLE_VV_M8,
6717 : PseudoVMFLE_VV_M8_MASK,
6718 : PseudoVMFLE_VV_MF2,
6719 : PseudoVMFLE_VV_MF2_MASK,
6720 : PseudoVMFLE_VV_MF4,
6721 : PseudoVMFLE_VV_MF4_MASK,
6722 : PseudoVMFLT_VFPR16_M1,
6723 : PseudoVMFLT_VFPR16_M1_MASK,
6724 : PseudoVMFLT_VFPR16_M2,
6725 : PseudoVMFLT_VFPR16_M2_MASK,
6726 : PseudoVMFLT_VFPR16_M4,
6727 : PseudoVMFLT_VFPR16_M4_MASK,
6728 : PseudoVMFLT_VFPR16_M8,
6729 : PseudoVMFLT_VFPR16_M8_MASK,
6730 : PseudoVMFLT_VFPR16_MF2,
6731 : PseudoVMFLT_VFPR16_MF2_MASK,
6732 : PseudoVMFLT_VFPR16_MF4,
6733 : PseudoVMFLT_VFPR16_MF4_MASK,
6734 : PseudoVMFLT_VFPR32_M1,
6735 : PseudoVMFLT_VFPR32_M1_MASK,
6736 : PseudoVMFLT_VFPR32_M2,
6737 : PseudoVMFLT_VFPR32_M2_MASK,
6738 : PseudoVMFLT_VFPR32_M4,
6739 : PseudoVMFLT_VFPR32_M4_MASK,
6740 : PseudoVMFLT_VFPR32_M8,
6741 : PseudoVMFLT_VFPR32_M8_MASK,
6742 : PseudoVMFLT_VFPR32_MF2,
6743 : PseudoVMFLT_VFPR32_MF2_MASK,
6744 : PseudoVMFLT_VFPR64_M1,
6745 : PseudoVMFLT_VFPR64_M1_MASK,
6746 : PseudoVMFLT_VFPR64_M2,
6747 : PseudoVMFLT_VFPR64_M2_MASK,
6748 : PseudoVMFLT_VFPR64_M4,
6749 : PseudoVMFLT_VFPR64_M4_MASK,
6750 : PseudoVMFLT_VFPR64_M8,
6751 : PseudoVMFLT_VFPR64_M8_MASK,
6752 : PseudoVMFLT_VV_M1,
6753 : PseudoVMFLT_VV_M1_MASK,
6754 : PseudoVMFLT_VV_M2,
6755 : PseudoVMFLT_VV_M2_MASK,
6756 : PseudoVMFLT_VV_M4,
6757 : PseudoVMFLT_VV_M4_MASK,
6758 : PseudoVMFLT_VV_M8,
6759 : PseudoVMFLT_VV_M8_MASK,
6760 : PseudoVMFLT_VV_MF2,
6761 : PseudoVMFLT_VV_MF2_MASK,
6762 : PseudoVMFLT_VV_MF4,
6763 : PseudoVMFLT_VV_MF4_MASK,
6764 : PseudoVMFNE_VFPR16_M1,
6765 : PseudoVMFNE_VFPR16_M1_MASK,
6766 : PseudoVMFNE_VFPR16_M2,
6767 : PseudoVMFNE_VFPR16_M2_MASK,
6768 : PseudoVMFNE_VFPR16_M4,
6769 : PseudoVMFNE_VFPR16_M4_MASK,
6770 : PseudoVMFNE_VFPR16_M8,
6771 : PseudoVMFNE_VFPR16_M8_MASK,
6772 : PseudoVMFNE_VFPR16_MF2,
6773 : PseudoVMFNE_VFPR16_MF2_MASK,
6774 : PseudoVMFNE_VFPR16_MF4,
6775 : PseudoVMFNE_VFPR16_MF4_MASK,
6776 : PseudoVMFNE_VFPR32_M1,
6777 : PseudoVMFNE_VFPR32_M1_MASK,
6778 : PseudoVMFNE_VFPR32_M2,
6779 : PseudoVMFNE_VFPR32_M2_MASK,
6780 : PseudoVMFNE_VFPR32_M4,
6781 : PseudoVMFNE_VFPR32_M4_MASK,
6782 : PseudoVMFNE_VFPR32_M8,
6783 : PseudoVMFNE_VFPR32_M8_MASK,
6784 : PseudoVMFNE_VFPR32_MF2,
6785 : PseudoVMFNE_VFPR32_MF2_MASK,
6786 : PseudoVMFNE_VFPR64_M1,
6787 : PseudoVMFNE_VFPR64_M1_MASK,
6788 : PseudoVMFNE_VFPR64_M2,
6789 : PseudoVMFNE_VFPR64_M2_MASK,
6790 : PseudoVMFNE_VFPR64_M4,
6791 : PseudoVMFNE_VFPR64_M4_MASK,
6792 : PseudoVMFNE_VFPR64_M8,
6793 : PseudoVMFNE_VFPR64_M8_MASK,
6794 : PseudoVMFNE_VV_M1,
6795 : PseudoVMFNE_VV_M1_MASK,
6796 : PseudoVMFNE_VV_M2,
6797 : PseudoVMFNE_VV_M2_MASK,
6798 : PseudoVMFNE_VV_M4,
6799 : PseudoVMFNE_VV_M4_MASK,
6800 : PseudoVMFNE_VV_M8,
6801 : PseudoVMFNE_VV_M8_MASK,
6802 : PseudoVMFNE_VV_MF2,
6803 : PseudoVMFNE_VV_MF2_MASK,
6804 : PseudoVMFNE_VV_MF4,
6805 : PseudoVMFNE_VV_MF4_MASK,
6806 : PseudoVMINU_VV_M1,
6807 : PseudoVMINU_VV_M1_MASK,
6808 : PseudoVMINU_VV_M2,
6809 : PseudoVMINU_VV_M2_MASK,
6810 : PseudoVMINU_VV_M4,
6811 : PseudoVMINU_VV_M4_MASK,
6812 : PseudoVMINU_VV_M8,
6813 : PseudoVMINU_VV_M8_MASK,
6814 : PseudoVMINU_VV_MF2,
6815 : PseudoVMINU_VV_MF2_MASK,
6816 : PseudoVMINU_VV_MF4,
6817 : PseudoVMINU_VV_MF4_MASK,
6818 : PseudoVMINU_VV_MF8,
6819 : PseudoVMINU_VV_MF8_MASK,
6820 : PseudoVMINU_VX_M1,
6821 : PseudoVMINU_VX_M1_MASK,
6822 : PseudoVMINU_VX_M2,
6823 : PseudoVMINU_VX_M2_MASK,
6824 : PseudoVMINU_VX_M4,
6825 : PseudoVMINU_VX_M4_MASK,
6826 : PseudoVMINU_VX_M8,
6827 : PseudoVMINU_VX_M8_MASK,
6828 : PseudoVMINU_VX_MF2,
6829 : PseudoVMINU_VX_MF2_MASK,
6830 : PseudoVMINU_VX_MF4,
6831 : PseudoVMINU_VX_MF4_MASK,
6832 : PseudoVMINU_VX_MF8,
6833 : PseudoVMINU_VX_MF8_MASK,
6834 : PseudoVMIN_VV_M1,
6835 : PseudoVMIN_VV_M1_MASK,
6836 : PseudoVMIN_VV_M2,
6837 : PseudoVMIN_VV_M2_MASK,
6838 : PseudoVMIN_VV_M4,
6839 : PseudoVMIN_VV_M4_MASK,
6840 : PseudoVMIN_VV_M8,
6841 : PseudoVMIN_VV_M8_MASK,
6842 : PseudoVMIN_VV_MF2,
6843 : PseudoVMIN_VV_MF2_MASK,
6844 : PseudoVMIN_VV_MF4,
6845 : PseudoVMIN_VV_MF4_MASK,
6846 : PseudoVMIN_VV_MF8,
6847 : PseudoVMIN_VV_MF8_MASK,
6848 : PseudoVMIN_VX_M1,
6849 : PseudoVMIN_VX_M1_MASK,
6850 : PseudoVMIN_VX_M2,
6851 : PseudoVMIN_VX_M2_MASK,
6852 : PseudoVMIN_VX_M4,
6853 : PseudoVMIN_VX_M4_MASK,
6854 : PseudoVMIN_VX_M8,
6855 : PseudoVMIN_VX_M8_MASK,
6856 : PseudoVMIN_VX_MF2,
6857 : PseudoVMIN_VX_MF2_MASK,
6858 : PseudoVMIN_VX_MF4,
6859 : PseudoVMIN_VX_MF4_MASK,
6860 : PseudoVMIN_VX_MF8,
6861 : PseudoVMIN_VX_MF8_MASK,
6862 : PseudoVMNAND_MM_M1,
6863 : PseudoVMNAND_MM_M2,
6864 : PseudoVMNAND_MM_M4,
6865 : PseudoVMNAND_MM_M8,
6866 : PseudoVMNAND_MM_MF2,
6867 : PseudoVMNAND_MM_MF4,
6868 : PseudoVMNAND_MM_MF8,
6869 : PseudoVMNOR_MM_M1,
6870 : PseudoVMNOR_MM_M2,
6871 : PseudoVMNOR_MM_M4,
6872 : PseudoVMNOR_MM_M8,
6873 : PseudoVMNOR_MM_MF2,
6874 : PseudoVMNOR_MM_MF4,
6875 : PseudoVMNOR_MM_MF8,
6876 : PseudoVMORN_MM_M1,
6877 : PseudoVMORN_MM_M2,
6878 : PseudoVMORN_MM_M4,
6879 : PseudoVMORN_MM_M8,
6880 : PseudoVMORN_MM_MF2,
6881 : PseudoVMORN_MM_MF4,
6882 : PseudoVMORN_MM_MF8,
6883 : PseudoVMOR_MM_M1,
6884 : PseudoVMOR_MM_M2,
6885 : PseudoVMOR_MM_M4,
6886 : PseudoVMOR_MM_M8,
6887 : PseudoVMOR_MM_MF2,
6888 : PseudoVMOR_MM_MF4,
6889 : PseudoVMOR_MM_MF8,
6890 : PseudoVMSBC_VVM_M1,
6891 : PseudoVMSBC_VVM_M2,
6892 : PseudoVMSBC_VVM_M4,
6893 : PseudoVMSBC_VVM_M8,
6894 : PseudoVMSBC_VVM_MF2,
6895 : PseudoVMSBC_VVM_MF4,
6896 : PseudoVMSBC_VVM_MF8,
6897 : PseudoVMSBC_VV_M1,
6898 : PseudoVMSBC_VV_M2,
6899 : PseudoVMSBC_VV_M4,
6900 : PseudoVMSBC_VV_M8,
6901 : PseudoVMSBC_VV_MF2,
6902 : PseudoVMSBC_VV_MF4,
6903 : PseudoVMSBC_VV_MF8,
6904 : PseudoVMSBC_VXM_M1,
6905 : PseudoVMSBC_VXM_M2,
6906 : PseudoVMSBC_VXM_M4,
6907 : PseudoVMSBC_VXM_M8,
6908 : PseudoVMSBC_VXM_MF2,
6909 : PseudoVMSBC_VXM_MF4,
6910 : PseudoVMSBC_VXM_MF8,
6911 : PseudoVMSBC_VX_M1,
6912 : PseudoVMSBC_VX_M2,
6913 : PseudoVMSBC_VX_M4,
6914 : PseudoVMSBC_VX_M8,
6915 : PseudoVMSBC_VX_MF2,
6916 : PseudoVMSBC_VX_MF4,
6917 : PseudoVMSBC_VX_MF8,
6918 : PseudoVMSBF_M_B1,
6919 : PseudoVMSBF_M_B16,
6920 : PseudoVMSBF_M_B16_MASK,
6921 : PseudoVMSBF_M_B1_MASK,
6922 : PseudoVMSBF_M_B2,
6923 : PseudoVMSBF_M_B2_MASK,
6924 : PseudoVMSBF_M_B32,
6925 : PseudoVMSBF_M_B32_MASK,
6926 : PseudoVMSBF_M_B4,
6927 : PseudoVMSBF_M_B4_MASK,
6928 : PseudoVMSBF_M_B64,
6929 : PseudoVMSBF_M_B64_MASK,
6930 : PseudoVMSBF_M_B8,
6931 : PseudoVMSBF_M_B8_MASK,
6932 : PseudoVMSEQ_VI_M1,
6933 : PseudoVMSEQ_VI_M1_MASK,
6934 : PseudoVMSEQ_VI_M2,
6935 : PseudoVMSEQ_VI_M2_MASK,
6936 : PseudoVMSEQ_VI_M4,
6937 : PseudoVMSEQ_VI_M4_MASK,
6938 : PseudoVMSEQ_VI_M8,
6939 : PseudoVMSEQ_VI_M8_MASK,
6940 : PseudoVMSEQ_VI_MF2,
6941 : PseudoVMSEQ_VI_MF2_MASK,
6942 : PseudoVMSEQ_VI_MF4,
6943 : PseudoVMSEQ_VI_MF4_MASK,
6944 : PseudoVMSEQ_VI_MF8,
6945 : PseudoVMSEQ_VI_MF8_MASK,
6946 : PseudoVMSEQ_VV_M1,
6947 : PseudoVMSEQ_VV_M1_MASK,
6948 : PseudoVMSEQ_VV_M2,
6949 : PseudoVMSEQ_VV_M2_MASK,
6950 : PseudoVMSEQ_VV_M4,
6951 : PseudoVMSEQ_VV_M4_MASK,
6952 : PseudoVMSEQ_VV_M8,
6953 : PseudoVMSEQ_VV_M8_MASK,
6954 : PseudoVMSEQ_VV_MF2,
6955 : PseudoVMSEQ_VV_MF2_MASK,
6956 : PseudoVMSEQ_VV_MF4,
6957 : PseudoVMSEQ_VV_MF4_MASK,
6958 : PseudoVMSEQ_VV_MF8,
6959 : PseudoVMSEQ_VV_MF8_MASK,
6960 : PseudoVMSEQ_VX_M1,
6961 : PseudoVMSEQ_VX_M1_MASK,
6962 : PseudoVMSEQ_VX_M2,
6963 : PseudoVMSEQ_VX_M2_MASK,
6964 : PseudoVMSEQ_VX_M4,
6965 : PseudoVMSEQ_VX_M4_MASK,
6966 : PseudoVMSEQ_VX_M8,
6967 : PseudoVMSEQ_VX_M8_MASK,
6968 : PseudoVMSEQ_VX_MF2,
6969 : PseudoVMSEQ_VX_MF2_MASK,
6970 : PseudoVMSEQ_VX_MF4,
6971 : PseudoVMSEQ_VX_MF4_MASK,
6972 : PseudoVMSEQ_VX_MF8,
6973 : PseudoVMSEQ_VX_MF8_MASK,
6974 : PseudoVMSET_M_B1,
6975 : PseudoVMSET_M_B16,
6976 : PseudoVMSET_M_B2,
6977 : PseudoVMSET_M_B32,
6978 : PseudoVMSET_M_B4,
6979 : PseudoVMSET_M_B64,
6980 : PseudoVMSET_M_B8,
6981 : PseudoVMSGEU_VI,
6982 : PseudoVMSGEU_VX,
6983 : PseudoVMSGEU_VX_M,
6984 : PseudoVMSGEU_VX_M_T,
6985 : PseudoVMSGE_VI,
6986 : PseudoVMSGE_VX,
6987 : PseudoVMSGE_VX_M,
6988 : PseudoVMSGE_VX_M_T,
6989 : PseudoVMSGTU_VI_M1,
6990 : PseudoVMSGTU_VI_M1_MASK,
6991 : PseudoVMSGTU_VI_M2,
6992 : PseudoVMSGTU_VI_M2_MASK,
6993 : PseudoVMSGTU_VI_M4,
6994 : PseudoVMSGTU_VI_M4_MASK,
6995 : PseudoVMSGTU_VI_M8,
6996 : PseudoVMSGTU_VI_M8_MASK,
6997 : PseudoVMSGTU_VI_MF2,
6998 : PseudoVMSGTU_VI_MF2_MASK,
6999 : PseudoVMSGTU_VI_MF4,
7000 : PseudoVMSGTU_VI_MF4_MASK,
7001 : PseudoVMSGTU_VI_MF8,
7002 : PseudoVMSGTU_VI_MF8_MASK,
7003 : PseudoVMSGTU_VX_M1,
7004 : PseudoVMSGTU_VX_M1_MASK,
7005 : PseudoVMSGTU_VX_M2,
7006 : PseudoVMSGTU_VX_M2_MASK,
7007 : PseudoVMSGTU_VX_M4,
7008 : PseudoVMSGTU_VX_M4_MASK,
7009 : PseudoVMSGTU_VX_M8,
7010 : PseudoVMSGTU_VX_M8_MASK,
7011 : PseudoVMSGTU_VX_MF2,
7012 : PseudoVMSGTU_VX_MF2_MASK,
7013 : PseudoVMSGTU_VX_MF4,
7014 : PseudoVMSGTU_VX_MF4_MASK,
7015 : PseudoVMSGTU_VX_MF8,
7016 : PseudoVMSGTU_VX_MF8_MASK,
7017 : PseudoVMSGT_VI_M1,
7018 : PseudoVMSGT_VI_M1_MASK,
7019 : PseudoVMSGT_VI_M2,
7020 : PseudoVMSGT_VI_M2_MASK,
7021 : PseudoVMSGT_VI_M4,
7022 : PseudoVMSGT_VI_M4_MASK,
7023 : PseudoVMSGT_VI_M8,
7024 : PseudoVMSGT_VI_M8_MASK,
7025 : PseudoVMSGT_VI_MF2,
7026 : PseudoVMSGT_VI_MF2_MASK,
7027 : PseudoVMSGT_VI_MF4,
7028 : PseudoVMSGT_VI_MF4_MASK,
7029 : PseudoVMSGT_VI_MF8,
7030 : PseudoVMSGT_VI_MF8_MASK,
7031 : PseudoVMSGT_VX_M1,
7032 : PseudoVMSGT_VX_M1_MASK,
7033 : PseudoVMSGT_VX_M2,
7034 : PseudoVMSGT_VX_M2_MASK,
7035 : PseudoVMSGT_VX_M4,
7036 : PseudoVMSGT_VX_M4_MASK,
7037 : PseudoVMSGT_VX_M8,
7038 : PseudoVMSGT_VX_M8_MASK,
7039 : PseudoVMSGT_VX_MF2,
7040 : PseudoVMSGT_VX_MF2_MASK,
7041 : PseudoVMSGT_VX_MF4,
7042 : PseudoVMSGT_VX_MF4_MASK,
7043 : PseudoVMSGT_VX_MF8,
7044 : PseudoVMSGT_VX_MF8_MASK,
7045 : PseudoVMSIF_M_B1,
7046 : PseudoVMSIF_M_B16,
7047 : PseudoVMSIF_M_B16_MASK,
7048 : PseudoVMSIF_M_B1_MASK,
7049 : PseudoVMSIF_M_B2,
7050 : PseudoVMSIF_M_B2_MASK,
7051 : PseudoVMSIF_M_B32,
7052 : PseudoVMSIF_M_B32_MASK,
7053 : PseudoVMSIF_M_B4,
7054 : PseudoVMSIF_M_B4_MASK,
7055 : PseudoVMSIF_M_B64,
7056 : PseudoVMSIF_M_B64_MASK,
7057 : PseudoVMSIF_M_B8,
7058 : PseudoVMSIF_M_B8_MASK,
7059 : PseudoVMSLEU_VI_M1,
7060 : PseudoVMSLEU_VI_M1_MASK,
7061 : PseudoVMSLEU_VI_M2,
7062 : PseudoVMSLEU_VI_M2_MASK,
7063 : PseudoVMSLEU_VI_M4,
7064 : PseudoVMSLEU_VI_M4_MASK,
7065 : PseudoVMSLEU_VI_M8,
7066 : PseudoVMSLEU_VI_M8_MASK,
7067 : PseudoVMSLEU_VI_MF2,
7068 : PseudoVMSLEU_VI_MF2_MASK,
7069 : PseudoVMSLEU_VI_MF4,
7070 : PseudoVMSLEU_VI_MF4_MASK,
7071 : PseudoVMSLEU_VI_MF8,
7072 : PseudoVMSLEU_VI_MF8_MASK,
7073 : PseudoVMSLEU_VV_M1,
7074 : PseudoVMSLEU_VV_M1_MASK,
7075 : PseudoVMSLEU_VV_M2,
7076 : PseudoVMSLEU_VV_M2_MASK,
7077 : PseudoVMSLEU_VV_M4,
7078 : PseudoVMSLEU_VV_M4_MASK,
7079 : PseudoVMSLEU_VV_M8,
7080 : PseudoVMSLEU_VV_M8_MASK,
7081 : PseudoVMSLEU_VV_MF2,
7082 : PseudoVMSLEU_VV_MF2_MASK,
7083 : PseudoVMSLEU_VV_MF4,
7084 : PseudoVMSLEU_VV_MF4_MASK,
7085 : PseudoVMSLEU_VV_MF8,
7086 : PseudoVMSLEU_VV_MF8_MASK,
7087 : PseudoVMSLEU_VX_M1,
7088 : PseudoVMSLEU_VX_M1_MASK,
7089 : PseudoVMSLEU_VX_M2,
7090 : PseudoVMSLEU_VX_M2_MASK,
7091 : PseudoVMSLEU_VX_M4,
7092 : PseudoVMSLEU_VX_M4_MASK,
7093 : PseudoVMSLEU_VX_M8,
7094 : PseudoVMSLEU_VX_M8_MASK,
7095 : PseudoVMSLEU_VX_MF2,
7096 : PseudoVMSLEU_VX_MF2_MASK,
7097 : PseudoVMSLEU_VX_MF4,
7098 : PseudoVMSLEU_VX_MF4_MASK,
7099 : PseudoVMSLEU_VX_MF8,
7100 : PseudoVMSLEU_VX_MF8_MASK,
7101 : PseudoVMSLE_VI_M1,
7102 : PseudoVMSLE_VI_M1_MASK,
7103 : PseudoVMSLE_VI_M2,
7104 : PseudoVMSLE_VI_M2_MASK,
7105 : PseudoVMSLE_VI_M4,
7106 : PseudoVMSLE_VI_M4_MASK,
7107 : PseudoVMSLE_VI_M8,
7108 : PseudoVMSLE_VI_M8_MASK,
7109 : PseudoVMSLE_VI_MF2,
7110 : PseudoVMSLE_VI_MF2_MASK,
7111 : PseudoVMSLE_VI_MF4,
7112 : PseudoVMSLE_VI_MF4_MASK,
7113 : PseudoVMSLE_VI_MF8,
7114 : PseudoVMSLE_VI_MF8_MASK,
7115 : PseudoVMSLE_VV_M1,
7116 : PseudoVMSLE_VV_M1_MASK,
7117 : PseudoVMSLE_VV_M2,
7118 : PseudoVMSLE_VV_M2_MASK,
7119 : PseudoVMSLE_VV_M4,
7120 : PseudoVMSLE_VV_M4_MASK,
7121 : PseudoVMSLE_VV_M8,
7122 : PseudoVMSLE_VV_M8_MASK,
7123 : PseudoVMSLE_VV_MF2,
7124 : PseudoVMSLE_VV_MF2_MASK,
7125 : PseudoVMSLE_VV_MF4,
7126 : PseudoVMSLE_VV_MF4_MASK,
7127 : PseudoVMSLE_VV_MF8,
7128 : PseudoVMSLE_VV_MF8_MASK,
7129 : PseudoVMSLE_VX_M1,
7130 : PseudoVMSLE_VX_M1_MASK,
7131 : PseudoVMSLE_VX_M2,
7132 : PseudoVMSLE_VX_M2_MASK,
7133 : PseudoVMSLE_VX_M4,
7134 : PseudoVMSLE_VX_M4_MASK,
7135 : PseudoVMSLE_VX_M8,
7136 : PseudoVMSLE_VX_M8_MASK,
7137 : PseudoVMSLE_VX_MF2,
7138 : PseudoVMSLE_VX_MF2_MASK,
7139 : PseudoVMSLE_VX_MF4,
7140 : PseudoVMSLE_VX_MF4_MASK,
7141 : PseudoVMSLE_VX_MF8,
7142 : PseudoVMSLE_VX_MF8_MASK,
7143 : PseudoVMSLTU_VI,
7144 : PseudoVMSLTU_VV_M1,
7145 : PseudoVMSLTU_VV_M1_MASK,
7146 : PseudoVMSLTU_VV_M2,
7147 : PseudoVMSLTU_VV_M2_MASK,
7148 : PseudoVMSLTU_VV_M4,
7149 : PseudoVMSLTU_VV_M4_MASK,
7150 : PseudoVMSLTU_VV_M8,
7151 : PseudoVMSLTU_VV_M8_MASK,
7152 : PseudoVMSLTU_VV_MF2,
7153 : PseudoVMSLTU_VV_MF2_MASK,
7154 : PseudoVMSLTU_VV_MF4,
7155 : PseudoVMSLTU_VV_MF4_MASK,
7156 : PseudoVMSLTU_VV_MF8,
7157 : PseudoVMSLTU_VV_MF8_MASK,
7158 : PseudoVMSLTU_VX_M1,
7159 : PseudoVMSLTU_VX_M1_MASK,
7160 : PseudoVMSLTU_VX_M2,
7161 : PseudoVMSLTU_VX_M2_MASK,
7162 : PseudoVMSLTU_VX_M4,
7163 : PseudoVMSLTU_VX_M4_MASK,
7164 : PseudoVMSLTU_VX_M8,
7165 : PseudoVMSLTU_VX_M8_MASK,
7166 : PseudoVMSLTU_VX_MF2,
7167 : PseudoVMSLTU_VX_MF2_MASK,
7168 : PseudoVMSLTU_VX_MF4,
7169 : PseudoVMSLTU_VX_MF4_MASK,
7170 : PseudoVMSLTU_VX_MF8,
7171 : PseudoVMSLTU_VX_MF8_MASK,
7172 : PseudoVMSLT_VI,
7173 : PseudoVMSLT_VV_M1,
7174 : PseudoVMSLT_VV_M1_MASK,
7175 : PseudoVMSLT_VV_M2,
7176 : PseudoVMSLT_VV_M2_MASK,
7177 : PseudoVMSLT_VV_M4,
7178 : PseudoVMSLT_VV_M4_MASK,
7179 : PseudoVMSLT_VV_M8,
7180 : PseudoVMSLT_VV_M8_MASK,
7181 : PseudoVMSLT_VV_MF2,
7182 : PseudoVMSLT_VV_MF2_MASK,
7183 : PseudoVMSLT_VV_MF4,
7184 : PseudoVMSLT_VV_MF4_MASK,
7185 : PseudoVMSLT_VV_MF8,
7186 : PseudoVMSLT_VV_MF8_MASK,
7187 : PseudoVMSLT_VX_M1,
7188 : PseudoVMSLT_VX_M1_MASK,
7189 : PseudoVMSLT_VX_M2,
7190 : PseudoVMSLT_VX_M2_MASK,
7191 : PseudoVMSLT_VX_M4,
7192 : PseudoVMSLT_VX_M4_MASK,
7193 : PseudoVMSLT_VX_M8,
7194 : PseudoVMSLT_VX_M8_MASK,
7195 : PseudoVMSLT_VX_MF2,
7196 : PseudoVMSLT_VX_MF2_MASK,
7197 : PseudoVMSLT_VX_MF4,
7198 : PseudoVMSLT_VX_MF4_MASK,
7199 : PseudoVMSLT_VX_MF8,
7200 : PseudoVMSLT_VX_MF8_MASK,
7201 : PseudoVMSNE_VI_M1,
7202 : PseudoVMSNE_VI_M1_MASK,
7203 : PseudoVMSNE_VI_M2,
7204 : PseudoVMSNE_VI_M2_MASK,
7205 : PseudoVMSNE_VI_M4,
7206 : PseudoVMSNE_VI_M4_MASK,
7207 : PseudoVMSNE_VI_M8,
7208 : PseudoVMSNE_VI_M8_MASK,
7209 : PseudoVMSNE_VI_MF2,
7210 : PseudoVMSNE_VI_MF2_MASK,
7211 : PseudoVMSNE_VI_MF4,
7212 : PseudoVMSNE_VI_MF4_MASK,
7213 : PseudoVMSNE_VI_MF8,
7214 : PseudoVMSNE_VI_MF8_MASK,
7215 : PseudoVMSNE_VV_M1,
7216 : PseudoVMSNE_VV_M1_MASK,
7217 : PseudoVMSNE_VV_M2,
7218 : PseudoVMSNE_VV_M2_MASK,
7219 : PseudoVMSNE_VV_M4,
7220 : PseudoVMSNE_VV_M4_MASK,
7221 : PseudoVMSNE_VV_M8,
7222 : PseudoVMSNE_VV_M8_MASK,
7223 : PseudoVMSNE_VV_MF2,
7224 : PseudoVMSNE_VV_MF2_MASK,
7225 : PseudoVMSNE_VV_MF4,
7226 : PseudoVMSNE_VV_MF4_MASK,
7227 : PseudoVMSNE_VV_MF8,
7228 : PseudoVMSNE_VV_MF8_MASK,
7229 : PseudoVMSNE_VX_M1,
7230 : PseudoVMSNE_VX_M1_MASK,
7231 : PseudoVMSNE_VX_M2,
7232 : PseudoVMSNE_VX_M2_MASK,
7233 : PseudoVMSNE_VX_M4,
7234 : PseudoVMSNE_VX_M4_MASK,
7235 : PseudoVMSNE_VX_M8,
7236 : PseudoVMSNE_VX_M8_MASK,
7237 : PseudoVMSNE_VX_MF2,
7238 : PseudoVMSNE_VX_MF2_MASK,
7239 : PseudoVMSNE_VX_MF4,
7240 : PseudoVMSNE_VX_MF4_MASK,
7241 : PseudoVMSNE_VX_MF8,
7242 : PseudoVMSNE_VX_MF8_MASK,
7243 : PseudoVMSOF_M_B1,
7244 : PseudoVMSOF_M_B16,
7245 : PseudoVMSOF_M_B16_MASK,
7246 : PseudoVMSOF_M_B1_MASK,
7247 : PseudoVMSOF_M_B2,
7248 : PseudoVMSOF_M_B2_MASK,
7249 : PseudoVMSOF_M_B32,
7250 : PseudoVMSOF_M_B32_MASK,
7251 : PseudoVMSOF_M_B4,
7252 : PseudoVMSOF_M_B4_MASK,
7253 : PseudoVMSOF_M_B64,
7254 : PseudoVMSOF_M_B64_MASK,
7255 : PseudoVMSOF_M_B8,
7256 : PseudoVMSOF_M_B8_MASK,
7257 : PseudoVMULHSU_VV_M1,
7258 : PseudoVMULHSU_VV_M1_MASK,
7259 : PseudoVMULHSU_VV_M2,
7260 : PseudoVMULHSU_VV_M2_MASK,
7261 : PseudoVMULHSU_VV_M4,
7262 : PseudoVMULHSU_VV_M4_MASK,
7263 : PseudoVMULHSU_VV_M8,
7264 : PseudoVMULHSU_VV_M8_MASK,
7265 : PseudoVMULHSU_VV_MF2,
7266 : PseudoVMULHSU_VV_MF2_MASK,
7267 : PseudoVMULHSU_VV_MF4,
7268 : PseudoVMULHSU_VV_MF4_MASK,
7269 : PseudoVMULHSU_VV_MF8,
7270 : PseudoVMULHSU_VV_MF8_MASK,
7271 : PseudoVMULHSU_VX_M1,
7272 : PseudoVMULHSU_VX_M1_MASK,
7273 : PseudoVMULHSU_VX_M2,
7274 : PseudoVMULHSU_VX_M2_MASK,
7275 : PseudoVMULHSU_VX_M4,
7276 : PseudoVMULHSU_VX_M4_MASK,
7277 : PseudoVMULHSU_VX_M8,
7278 : PseudoVMULHSU_VX_M8_MASK,
7279 : PseudoVMULHSU_VX_MF2,
7280 : PseudoVMULHSU_VX_MF2_MASK,
7281 : PseudoVMULHSU_VX_MF4,
7282 : PseudoVMULHSU_VX_MF4_MASK,
7283 : PseudoVMULHSU_VX_MF8,
7284 : PseudoVMULHSU_VX_MF8_MASK,
7285 : PseudoVMULHU_VV_M1,
7286 : PseudoVMULHU_VV_M1_MASK,
7287 : PseudoVMULHU_VV_M2,
7288 : PseudoVMULHU_VV_M2_MASK,
7289 : PseudoVMULHU_VV_M4,
7290 : PseudoVMULHU_VV_M4_MASK,
7291 : PseudoVMULHU_VV_M8,
7292 : PseudoVMULHU_VV_M8_MASK,
7293 : PseudoVMULHU_VV_MF2,
7294 : PseudoVMULHU_VV_MF2_MASK,
7295 : PseudoVMULHU_VV_MF4,
7296 : PseudoVMULHU_VV_MF4_MASK,
7297 : PseudoVMULHU_VV_MF8,
7298 : PseudoVMULHU_VV_MF8_MASK,
7299 : PseudoVMULHU_VX_M1,
7300 : PseudoVMULHU_VX_M1_MASK,
7301 : PseudoVMULHU_VX_M2,
7302 : PseudoVMULHU_VX_M2_MASK,
7303 : PseudoVMULHU_VX_M4,
7304 : PseudoVMULHU_VX_M4_MASK,
7305 : PseudoVMULHU_VX_M8,
7306 : PseudoVMULHU_VX_M8_MASK,
7307 : PseudoVMULHU_VX_MF2,
7308 : PseudoVMULHU_VX_MF2_MASK,
7309 : PseudoVMULHU_VX_MF4,
7310 : PseudoVMULHU_VX_MF4_MASK,
7311 : PseudoVMULHU_VX_MF8,
7312 : PseudoVMULHU_VX_MF8_MASK,
7313 : PseudoVMULH_VV_M1,
7314 : PseudoVMULH_VV_M1_MASK,
7315 : PseudoVMULH_VV_M2,
7316 : PseudoVMULH_VV_M2_MASK,
7317 : PseudoVMULH_VV_M4,
7318 : PseudoVMULH_VV_M4_MASK,
7319 : PseudoVMULH_VV_M8,
7320 : PseudoVMULH_VV_M8_MASK,
7321 : PseudoVMULH_VV_MF2,
7322 : PseudoVMULH_VV_MF2_MASK,
7323 : PseudoVMULH_VV_MF4,
7324 : PseudoVMULH_VV_MF4_MASK,
7325 : PseudoVMULH_VV_MF8,
7326 : PseudoVMULH_VV_MF8_MASK,
7327 : PseudoVMULH_VX_M1,
7328 : PseudoVMULH_VX_M1_MASK,
7329 : PseudoVMULH_VX_M2,
7330 : PseudoVMULH_VX_M2_MASK,
7331 : PseudoVMULH_VX_M4,
7332 : PseudoVMULH_VX_M4_MASK,
7333 : PseudoVMULH_VX_M8,
7334 : PseudoVMULH_VX_M8_MASK,
7335 : PseudoVMULH_VX_MF2,
7336 : PseudoVMULH_VX_MF2_MASK,
7337 : PseudoVMULH_VX_MF4,
7338 : PseudoVMULH_VX_MF4_MASK,
7339 : PseudoVMULH_VX_MF8,
7340 : PseudoVMULH_VX_MF8_MASK,
7341 : PseudoVMUL_VV_M1,
7342 : PseudoVMUL_VV_M1_MASK,
7343 : PseudoVMUL_VV_M2,
7344 : PseudoVMUL_VV_M2_MASK,
7345 : PseudoVMUL_VV_M4,
7346 : PseudoVMUL_VV_M4_MASK,
7347 : PseudoVMUL_VV_M8,
7348 : PseudoVMUL_VV_M8_MASK,
7349 : PseudoVMUL_VV_MF2,
7350 : PseudoVMUL_VV_MF2_MASK,
7351 : PseudoVMUL_VV_MF4,
7352 : PseudoVMUL_VV_MF4_MASK,
7353 : PseudoVMUL_VV_MF8,
7354 : PseudoVMUL_VV_MF8_MASK,
7355 : PseudoVMUL_VX_M1,
7356 : PseudoVMUL_VX_M1_MASK,
7357 : PseudoVMUL_VX_M2,
7358 : PseudoVMUL_VX_M2_MASK,
7359 : PseudoVMUL_VX_M4,
7360 : PseudoVMUL_VX_M4_MASK,
7361 : PseudoVMUL_VX_M8,
7362 : PseudoVMUL_VX_M8_MASK,
7363 : PseudoVMUL_VX_MF2,
7364 : PseudoVMUL_VX_MF2_MASK,
7365 : PseudoVMUL_VX_MF4,
7366 : PseudoVMUL_VX_MF4_MASK,
7367 : PseudoVMUL_VX_MF8,
7368 : PseudoVMUL_VX_MF8_MASK,
7369 : PseudoVMV_S_X,
7370 : PseudoVMV_V_I_M1,
7371 : PseudoVMV_V_I_M2,
7372 : PseudoVMV_V_I_M4,
7373 : PseudoVMV_V_I_M8,
7374 : PseudoVMV_V_I_MF2,
7375 : PseudoVMV_V_I_MF4,
7376 : PseudoVMV_V_I_MF8,
7377 : PseudoVMV_V_V_M1,
7378 : PseudoVMV_V_V_M2,
7379 : PseudoVMV_V_V_M4,
7380 : PseudoVMV_V_V_M8,
7381 : PseudoVMV_V_V_MF2,
7382 : PseudoVMV_V_V_MF4,
7383 : PseudoVMV_V_V_MF8,
7384 : PseudoVMV_V_X_M1,
7385 : PseudoVMV_V_X_M2,
7386 : PseudoVMV_V_X_M4,
7387 : PseudoVMV_V_X_M8,
7388 : PseudoVMV_V_X_MF2,
7389 : PseudoVMV_V_X_MF4,
7390 : PseudoVMV_V_X_MF8,
7391 : PseudoVMV_X_S,
7392 : PseudoVMXNOR_MM_M1,
7393 : PseudoVMXNOR_MM_M2,
7394 : PseudoVMXNOR_MM_M4,
7395 : PseudoVMXNOR_MM_M8,
7396 : PseudoVMXNOR_MM_MF2,
7397 : PseudoVMXNOR_MM_MF4,
7398 : PseudoVMXNOR_MM_MF8,
7399 : PseudoVMXOR_MM_M1,
7400 : PseudoVMXOR_MM_M2,
7401 : PseudoVMXOR_MM_M4,
7402 : PseudoVMXOR_MM_M8,
7403 : PseudoVMXOR_MM_MF2,
7404 : PseudoVMXOR_MM_MF4,
7405 : PseudoVMXOR_MM_MF8,
7406 : PseudoVNCLIPU_WI_M1,
7407 : PseudoVNCLIPU_WI_M1_MASK,
7408 : PseudoVNCLIPU_WI_M2,
7409 : PseudoVNCLIPU_WI_M2_MASK,
7410 : PseudoVNCLIPU_WI_M4,
7411 : PseudoVNCLIPU_WI_M4_MASK,
7412 : PseudoVNCLIPU_WI_MF2,
7413 : PseudoVNCLIPU_WI_MF2_MASK,
7414 : PseudoVNCLIPU_WI_MF4,
7415 : PseudoVNCLIPU_WI_MF4_MASK,
7416 : PseudoVNCLIPU_WI_MF8,
7417 : PseudoVNCLIPU_WI_MF8_MASK,
7418 : PseudoVNCLIPU_WV_M1,
7419 : PseudoVNCLIPU_WV_M1_MASK,
7420 : PseudoVNCLIPU_WV_M2,
7421 : PseudoVNCLIPU_WV_M2_MASK,
7422 : PseudoVNCLIPU_WV_M4,
7423 : PseudoVNCLIPU_WV_M4_MASK,
7424 : PseudoVNCLIPU_WV_MF2,
7425 : PseudoVNCLIPU_WV_MF2_MASK,
7426 : PseudoVNCLIPU_WV_MF4,
7427 : PseudoVNCLIPU_WV_MF4_MASK,
7428 : PseudoVNCLIPU_WV_MF8,
7429 : PseudoVNCLIPU_WV_MF8_MASK,
7430 : PseudoVNCLIPU_WX_M1,
7431 : PseudoVNCLIPU_WX_M1_MASK,
7432 : PseudoVNCLIPU_WX_M2,
7433 : PseudoVNCLIPU_WX_M2_MASK,
7434 : PseudoVNCLIPU_WX_M4,
7435 : PseudoVNCLIPU_WX_M4_MASK,
7436 : PseudoVNCLIPU_WX_MF2,
7437 : PseudoVNCLIPU_WX_MF2_MASK,
7438 : PseudoVNCLIPU_WX_MF4,
7439 : PseudoVNCLIPU_WX_MF4_MASK,
7440 : PseudoVNCLIPU_WX_MF8,
7441 : PseudoVNCLIPU_WX_MF8_MASK,
7442 : PseudoVNCLIP_WI_M1,
7443 : PseudoVNCLIP_WI_M1_MASK,
7444 : PseudoVNCLIP_WI_M2,
7445 : PseudoVNCLIP_WI_M2_MASK,
7446 : PseudoVNCLIP_WI_M4,
7447 : PseudoVNCLIP_WI_M4_MASK,
7448 : PseudoVNCLIP_WI_MF2,
7449 : PseudoVNCLIP_WI_MF2_MASK,
7450 : PseudoVNCLIP_WI_MF4,
7451 : PseudoVNCLIP_WI_MF4_MASK,
7452 : PseudoVNCLIP_WI_MF8,
7453 : PseudoVNCLIP_WI_MF8_MASK,
7454 : PseudoVNCLIP_WV_M1,
7455 : PseudoVNCLIP_WV_M1_MASK,
7456 : PseudoVNCLIP_WV_M2,
7457 : PseudoVNCLIP_WV_M2_MASK,
7458 : PseudoVNCLIP_WV_M4,
7459 : PseudoVNCLIP_WV_M4_MASK,
7460 : PseudoVNCLIP_WV_MF2,
7461 : PseudoVNCLIP_WV_MF2_MASK,
7462 : PseudoVNCLIP_WV_MF4,
7463 : PseudoVNCLIP_WV_MF4_MASK,
7464 : PseudoVNCLIP_WV_MF8,
7465 : PseudoVNCLIP_WV_MF8_MASK,
7466 : PseudoVNCLIP_WX_M1,
7467 : PseudoVNCLIP_WX_M1_MASK,
7468 : PseudoVNCLIP_WX_M2,
7469 : PseudoVNCLIP_WX_M2_MASK,
7470 : PseudoVNCLIP_WX_M4,
7471 : PseudoVNCLIP_WX_M4_MASK,
7472 : PseudoVNCLIP_WX_MF2,
7473 : PseudoVNCLIP_WX_MF2_MASK,
7474 : PseudoVNCLIP_WX_MF4,
7475 : PseudoVNCLIP_WX_MF4_MASK,
7476 : PseudoVNCLIP_WX_MF8,
7477 : PseudoVNCLIP_WX_MF8_MASK,
7478 : PseudoVNMSAC_VV_M1,
7479 : PseudoVNMSAC_VV_M1_MASK,
7480 : PseudoVNMSAC_VV_M2,
7481 : PseudoVNMSAC_VV_M2_MASK,
7482 : PseudoVNMSAC_VV_M4,
7483 : PseudoVNMSAC_VV_M4_MASK,
7484 : PseudoVNMSAC_VV_M8,
7485 : PseudoVNMSAC_VV_M8_MASK,
7486 : PseudoVNMSAC_VV_MF2,
7487 : PseudoVNMSAC_VV_MF2_MASK,
7488 : PseudoVNMSAC_VV_MF4,
7489 : PseudoVNMSAC_VV_MF4_MASK,
7490 : PseudoVNMSAC_VV_MF8,
7491 : PseudoVNMSAC_VV_MF8_MASK,
7492 : PseudoVNMSAC_VX_M1,
7493 : PseudoVNMSAC_VX_M1_MASK,
7494 : PseudoVNMSAC_VX_M2,
7495 : PseudoVNMSAC_VX_M2_MASK,
7496 : PseudoVNMSAC_VX_M4,
7497 : PseudoVNMSAC_VX_M4_MASK,
7498 : PseudoVNMSAC_VX_M8,
7499 : PseudoVNMSAC_VX_M8_MASK,
7500 : PseudoVNMSAC_VX_MF2,
7501 : PseudoVNMSAC_VX_MF2_MASK,
7502 : PseudoVNMSAC_VX_MF4,
7503 : PseudoVNMSAC_VX_MF4_MASK,
7504 : PseudoVNMSAC_VX_MF8,
7505 : PseudoVNMSAC_VX_MF8_MASK,
7506 : PseudoVNMSUB_VV_M1,
7507 : PseudoVNMSUB_VV_M1_MASK,
7508 : PseudoVNMSUB_VV_M2,
7509 : PseudoVNMSUB_VV_M2_MASK,
7510 : PseudoVNMSUB_VV_M4,
7511 : PseudoVNMSUB_VV_M4_MASK,
7512 : PseudoVNMSUB_VV_M8,
7513 : PseudoVNMSUB_VV_M8_MASK,
7514 : PseudoVNMSUB_VV_MF2,
7515 : PseudoVNMSUB_VV_MF2_MASK,
7516 : PseudoVNMSUB_VV_MF4,
7517 : PseudoVNMSUB_VV_MF4_MASK,
7518 : PseudoVNMSUB_VV_MF8,
7519 : PseudoVNMSUB_VV_MF8_MASK,
7520 : PseudoVNMSUB_VX_M1,
7521 : PseudoVNMSUB_VX_M1_MASK,
7522 : PseudoVNMSUB_VX_M2,
7523 : PseudoVNMSUB_VX_M2_MASK,
7524 : PseudoVNMSUB_VX_M4,
7525 : PseudoVNMSUB_VX_M4_MASK,
7526 : PseudoVNMSUB_VX_M8,
7527 : PseudoVNMSUB_VX_M8_MASK,
7528 : PseudoVNMSUB_VX_MF2,
7529 : PseudoVNMSUB_VX_MF2_MASK,
7530 : PseudoVNMSUB_VX_MF4,
7531 : PseudoVNMSUB_VX_MF4_MASK,
7532 : PseudoVNMSUB_VX_MF8,
7533 : PseudoVNMSUB_VX_MF8_MASK,
7534 : PseudoVNSRA_WI_M1,
7535 : PseudoVNSRA_WI_M1_MASK,
7536 : PseudoVNSRA_WI_M2,
7537 : PseudoVNSRA_WI_M2_MASK,
7538 : PseudoVNSRA_WI_M4,
7539 : PseudoVNSRA_WI_M4_MASK,
7540 : PseudoVNSRA_WI_MF2,
7541 : PseudoVNSRA_WI_MF2_MASK,
7542 : PseudoVNSRA_WI_MF4,
7543 : PseudoVNSRA_WI_MF4_MASK,
7544 : PseudoVNSRA_WI_MF8,
7545 : PseudoVNSRA_WI_MF8_MASK,
7546 : PseudoVNSRA_WV_M1,
7547 : PseudoVNSRA_WV_M1_MASK,
7548 : PseudoVNSRA_WV_M2,
7549 : PseudoVNSRA_WV_M2_MASK,
7550 : PseudoVNSRA_WV_M4,
7551 : PseudoVNSRA_WV_M4_MASK,
7552 : PseudoVNSRA_WV_MF2,
7553 : PseudoVNSRA_WV_MF2_MASK,
7554 : PseudoVNSRA_WV_MF4,
7555 : PseudoVNSRA_WV_MF4_MASK,
7556 : PseudoVNSRA_WV_MF8,
7557 : PseudoVNSRA_WV_MF8_MASK,
7558 : PseudoVNSRA_WX_M1,
7559 : PseudoVNSRA_WX_M1_MASK,
7560 : PseudoVNSRA_WX_M2,
7561 : PseudoVNSRA_WX_M2_MASK,
7562 : PseudoVNSRA_WX_M4,
7563 : PseudoVNSRA_WX_M4_MASK,
7564 : PseudoVNSRA_WX_MF2,
7565 : PseudoVNSRA_WX_MF2_MASK,
7566 : PseudoVNSRA_WX_MF4,
7567 : PseudoVNSRA_WX_MF4_MASK,
7568 : PseudoVNSRA_WX_MF8,
7569 : PseudoVNSRA_WX_MF8_MASK,
7570 : PseudoVNSRL_WI_M1,
7571 : PseudoVNSRL_WI_M1_MASK,
7572 : PseudoVNSRL_WI_M2,
7573 : PseudoVNSRL_WI_M2_MASK,
7574 : PseudoVNSRL_WI_M4,
7575 : PseudoVNSRL_WI_M4_MASK,
7576 : PseudoVNSRL_WI_MF2,
7577 : PseudoVNSRL_WI_MF2_MASK,
7578 : PseudoVNSRL_WI_MF4,
7579 : PseudoVNSRL_WI_MF4_MASK,
7580 : PseudoVNSRL_WI_MF8,
7581 : PseudoVNSRL_WI_MF8_MASK,
7582 : PseudoVNSRL_WV_M1,
7583 : PseudoVNSRL_WV_M1_MASK,
7584 : PseudoVNSRL_WV_M2,
7585 : PseudoVNSRL_WV_M2_MASK,
7586 : PseudoVNSRL_WV_M4,
7587 : PseudoVNSRL_WV_M4_MASK,
7588 : PseudoVNSRL_WV_MF2,
7589 : PseudoVNSRL_WV_MF2_MASK,
7590 : PseudoVNSRL_WV_MF4,
7591 : PseudoVNSRL_WV_MF4_MASK,
7592 : PseudoVNSRL_WV_MF8,
7593 : PseudoVNSRL_WV_MF8_MASK,
7594 : PseudoVNSRL_WX_M1,
7595 : PseudoVNSRL_WX_M1_MASK,
7596 : PseudoVNSRL_WX_M2,
7597 : PseudoVNSRL_WX_M2_MASK,
7598 : PseudoVNSRL_WX_M4,
7599 : PseudoVNSRL_WX_M4_MASK,
7600 : PseudoVNSRL_WX_MF2,
7601 : PseudoVNSRL_WX_MF2_MASK,
7602 : PseudoVNSRL_WX_MF4,
7603 : PseudoVNSRL_WX_MF4_MASK,
7604 : PseudoVNSRL_WX_MF8,
7605 : PseudoVNSRL_WX_MF8_MASK,
7606 : PseudoVOR_VI_M1,
7607 : PseudoVOR_VI_M1_MASK,
7608 : PseudoVOR_VI_M2,
7609 : PseudoVOR_VI_M2_MASK,
7610 : PseudoVOR_VI_M4,
7611 : PseudoVOR_VI_M4_MASK,
7612 : PseudoVOR_VI_M8,
7613 : PseudoVOR_VI_M8_MASK,
7614 : PseudoVOR_VI_MF2,
7615 : PseudoVOR_VI_MF2_MASK,
7616 : PseudoVOR_VI_MF4,
7617 : PseudoVOR_VI_MF4_MASK,
7618 : PseudoVOR_VI_MF8,
7619 : PseudoVOR_VI_MF8_MASK,
7620 : PseudoVOR_VV_M1,
7621 : PseudoVOR_VV_M1_MASK,
7622 : PseudoVOR_VV_M2,
7623 : PseudoVOR_VV_M2_MASK,
7624 : PseudoVOR_VV_M4,
7625 : PseudoVOR_VV_M4_MASK,
7626 : PseudoVOR_VV_M8,
7627 : PseudoVOR_VV_M8_MASK,
7628 : PseudoVOR_VV_MF2,
7629 : PseudoVOR_VV_MF2_MASK,
7630 : PseudoVOR_VV_MF4,
7631 : PseudoVOR_VV_MF4_MASK,
7632 : PseudoVOR_VV_MF8,
7633 : PseudoVOR_VV_MF8_MASK,
7634 : PseudoVOR_VX_M1,
7635 : PseudoVOR_VX_M1_MASK,
7636 : PseudoVOR_VX_M2,
7637 : PseudoVOR_VX_M2_MASK,
7638 : PseudoVOR_VX_M4,
7639 : PseudoVOR_VX_M4_MASK,
7640 : PseudoVOR_VX_M8,
7641 : PseudoVOR_VX_M8_MASK,
7642 : PseudoVOR_VX_MF2,
7643 : PseudoVOR_VX_MF2_MASK,
7644 : PseudoVOR_VX_MF4,
7645 : PseudoVOR_VX_MF4_MASK,
7646 : PseudoVOR_VX_MF8,
7647 : PseudoVOR_VX_MF8_MASK,
7648 : PseudoVQMACCSU_2x8x2_M1,
7649 : PseudoVQMACCSU_2x8x2_M2,
7650 : PseudoVQMACCSU_2x8x2_M4,
7651 : PseudoVQMACCSU_2x8x2_M8,
7652 : PseudoVQMACCSU_4x8x4_M1,
7653 : PseudoVQMACCSU_4x8x4_M2,
7654 : PseudoVQMACCSU_4x8x4_M4,
7655 : PseudoVQMACCSU_4x8x4_MF2,
7656 : PseudoVQMACCUS_2x8x2_M1,
7657 : PseudoVQMACCUS_2x8x2_M2,
7658 : PseudoVQMACCUS_2x8x2_M4,
7659 : PseudoVQMACCUS_2x8x2_M8,
7660 : PseudoVQMACCUS_4x8x4_M1,
7661 : PseudoVQMACCUS_4x8x4_M2,
7662 : PseudoVQMACCUS_4x8x4_M4,
7663 : PseudoVQMACCUS_4x8x4_MF2,
7664 : PseudoVQMACCU_2x8x2_M1,
7665 : PseudoVQMACCU_2x8x2_M2,
7666 : PseudoVQMACCU_2x8x2_M4,
7667 : PseudoVQMACCU_2x8x2_M8,
7668 : PseudoVQMACCU_4x8x4_M1,
7669 : PseudoVQMACCU_4x8x4_M2,
7670 : PseudoVQMACCU_4x8x4_M4,
7671 : PseudoVQMACCU_4x8x4_MF2,
7672 : PseudoVQMACC_2x8x2_M1,
7673 : PseudoVQMACC_2x8x2_M2,
7674 : PseudoVQMACC_2x8x2_M4,
7675 : PseudoVQMACC_2x8x2_M8,
7676 : PseudoVQMACC_4x8x4_M1,
7677 : PseudoVQMACC_4x8x4_M2,
7678 : PseudoVQMACC_4x8x4_M4,
7679 : PseudoVQMACC_4x8x4_MF2,
7680 : PseudoVREDAND_VS_M1_E16,
7681 : PseudoVREDAND_VS_M1_E16_MASK,
7682 : PseudoVREDAND_VS_M1_E32,
7683 : PseudoVREDAND_VS_M1_E32_MASK,
7684 : PseudoVREDAND_VS_M1_E64,
7685 : PseudoVREDAND_VS_M1_E64_MASK,
7686 : PseudoVREDAND_VS_M1_E8,
7687 : PseudoVREDAND_VS_M1_E8_MASK,
7688 : PseudoVREDAND_VS_M2_E16,
7689 : PseudoVREDAND_VS_M2_E16_MASK,
7690 : PseudoVREDAND_VS_M2_E32,
7691 : PseudoVREDAND_VS_M2_E32_MASK,
7692 : PseudoVREDAND_VS_M2_E64,
7693 : PseudoVREDAND_VS_M2_E64_MASK,
7694 : PseudoVREDAND_VS_M2_E8,
7695 : PseudoVREDAND_VS_M2_E8_MASK,
7696 : PseudoVREDAND_VS_M4_E16,
7697 : PseudoVREDAND_VS_M4_E16_MASK,
7698 : PseudoVREDAND_VS_M4_E32,
7699 : PseudoVREDAND_VS_M4_E32_MASK,
7700 : PseudoVREDAND_VS_M4_E64,
7701 : PseudoVREDAND_VS_M4_E64_MASK,
7702 : PseudoVREDAND_VS_M4_E8,
7703 : PseudoVREDAND_VS_M4_E8_MASK,
7704 : PseudoVREDAND_VS_M8_E16,
7705 : PseudoVREDAND_VS_M8_E16_MASK,
7706 : PseudoVREDAND_VS_M8_E32,
7707 : PseudoVREDAND_VS_M8_E32_MASK,
7708 : PseudoVREDAND_VS_M8_E64,
7709 : PseudoVREDAND_VS_M8_E64_MASK,
7710 : PseudoVREDAND_VS_M8_E8,
7711 : PseudoVREDAND_VS_M8_E8_MASK,
7712 : PseudoVREDAND_VS_MF2_E16,
7713 : PseudoVREDAND_VS_MF2_E16_MASK,
7714 : PseudoVREDAND_VS_MF2_E32,
7715 : PseudoVREDAND_VS_MF2_E32_MASK,
7716 : PseudoVREDAND_VS_MF2_E8,
7717 : PseudoVREDAND_VS_MF2_E8_MASK,
7718 : PseudoVREDAND_VS_MF4_E16,
7719 : PseudoVREDAND_VS_MF4_E16_MASK,
7720 : PseudoVREDAND_VS_MF4_E8,
7721 : PseudoVREDAND_VS_MF4_E8_MASK,
7722 : PseudoVREDAND_VS_MF8_E8,
7723 : PseudoVREDAND_VS_MF8_E8_MASK,
7724 : PseudoVREDMAXU_VS_M1_E16,
7725 : PseudoVREDMAXU_VS_M1_E16_MASK,
7726 : PseudoVREDMAXU_VS_M1_E32,
7727 : PseudoVREDMAXU_VS_M1_E32_MASK,
7728 : PseudoVREDMAXU_VS_M1_E64,
7729 : PseudoVREDMAXU_VS_M1_E64_MASK,
7730 : PseudoVREDMAXU_VS_M1_E8,
7731 : PseudoVREDMAXU_VS_M1_E8_MASK,
7732 : PseudoVREDMAXU_VS_M2_E16,
7733 : PseudoVREDMAXU_VS_M2_E16_MASK,
7734 : PseudoVREDMAXU_VS_M2_E32,
7735 : PseudoVREDMAXU_VS_M2_E32_MASK,
7736 : PseudoVREDMAXU_VS_M2_E64,
7737 : PseudoVREDMAXU_VS_M2_E64_MASK,
7738 : PseudoVREDMAXU_VS_M2_E8,
7739 : PseudoVREDMAXU_VS_M2_E8_MASK,
7740 : PseudoVREDMAXU_VS_M4_E16,
7741 : PseudoVREDMAXU_VS_M4_E16_MASK,
7742 : PseudoVREDMAXU_VS_M4_E32,
7743 : PseudoVREDMAXU_VS_M4_E32_MASK,
7744 : PseudoVREDMAXU_VS_M4_E64,
7745 : PseudoVREDMAXU_VS_M4_E64_MASK,
7746 : PseudoVREDMAXU_VS_M4_E8,
7747 : PseudoVREDMAXU_VS_M4_E8_MASK,
7748 : PseudoVREDMAXU_VS_M8_E16,
7749 : PseudoVREDMAXU_VS_M8_E16_MASK,
7750 : PseudoVREDMAXU_VS_M8_E32,
7751 : PseudoVREDMAXU_VS_M8_E32_MASK,
7752 : PseudoVREDMAXU_VS_M8_E64,
7753 : PseudoVREDMAXU_VS_M8_E64_MASK,
7754 : PseudoVREDMAXU_VS_M8_E8,
7755 : PseudoVREDMAXU_VS_M8_E8_MASK,
7756 : PseudoVREDMAXU_VS_MF2_E16,
7757 : PseudoVREDMAXU_VS_MF2_E16_MASK,
7758 : PseudoVREDMAXU_VS_MF2_E32,
7759 : PseudoVREDMAXU_VS_MF2_E32_MASK,
7760 : PseudoVREDMAXU_VS_MF2_E8,
7761 : PseudoVREDMAXU_VS_MF2_E8_MASK,
7762 : PseudoVREDMAXU_VS_MF4_E16,
7763 : PseudoVREDMAXU_VS_MF4_E16_MASK,
7764 : PseudoVREDMAXU_VS_MF4_E8,
7765 : PseudoVREDMAXU_VS_MF4_E8_MASK,
7766 : PseudoVREDMAXU_VS_MF8_E8,
7767 : PseudoVREDMAXU_VS_MF8_E8_MASK,
7768 : PseudoVREDMAX_VS_M1_E16,
7769 : PseudoVREDMAX_VS_M1_E16_MASK,
7770 : PseudoVREDMAX_VS_M1_E32,
7771 : PseudoVREDMAX_VS_M1_E32_MASK,
7772 : PseudoVREDMAX_VS_M1_E64,
7773 : PseudoVREDMAX_VS_M1_E64_MASK,
7774 : PseudoVREDMAX_VS_M1_E8,
7775 : PseudoVREDMAX_VS_M1_E8_MASK,
7776 : PseudoVREDMAX_VS_M2_E16,
7777 : PseudoVREDMAX_VS_M2_E16_MASK,
7778 : PseudoVREDMAX_VS_M2_E32,
7779 : PseudoVREDMAX_VS_M2_E32_MASK,
7780 : PseudoVREDMAX_VS_M2_E64,
7781 : PseudoVREDMAX_VS_M2_E64_MASK,
7782 : PseudoVREDMAX_VS_M2_E8,
7783 : PseudoVREDMAX_VS_M2_E8_MASK,
7784 : PseudoVREDMAX_VS_M4_E16,
7785 : PseudoVREDMAX_VS_M4_E16_MASK,
7786 : PseudoVREDMAX_VS_M4_E32,
7787 : PseudoVREDMAX_VS_M4_E32_MASK,
7788 : PseudoVREDMAX_VS_M4_E64,
7789 : PseudoVREDMAX_VS_M4_E64_MASK,
7790 : PseudoVREDMAX_VS_M4_E8,
7791 : PseudoVREDMAX_VS_M4_E8_MASK,
7792 : PseudoVREDMAX_VS_M8_E16,
7793 : PseudoVREDMAX_VS_M8_E16_MASK,
7794 : PseudoVREDMAX_VS_M8_E32,
7795 : PseudoVREDMAX_VS_M8_E32_MASK,
7796 : PseudoVREDMAX_VS_M8_E64,
7797 : PseudoVREDMAX_VS_M8_E64_MASK,
7798 : PseudoVREDMAX_VS_M8_E8,
7799 : PseudoVREDMAX_VS_M8_E8_MASK,
7800 : PseudoVREDMAX_VS_MF2_E16,
7801 : PseudoVREDMAX_VS_MF2_E16_MASK,
7802 : PseudoVREDMAX_VS_MF2_E32,
7803 : PseudoVREDMAX_VS_MF2_E32_MASK,
7804 : PseudoVREDMAX_VS_MF2_E8,
7805 : PseudoVREDMAX_VS_MF2_E8_MASK,
7806 : PseudoVREDMAX_VS_MF4_E16,
7807 : PseudoVREDMAX_VS_MF4_E16_MASK,
7808 : PseudoVREDMAX_VS_MF4_E8,
7809 : PseudoVREDMAX_VS_MF4_E8_MASK,
7810 : PseudoVREDMAX_VS_MF8_E8,
7811 : PseudoVREDMAX_VS_MF8_E8_MASK,
7812 : PseudoVREDMINU_VS_M1_E16,
7813 : PseudoVREDMINU_VS_M1_E16_MASK,
7814 : PseudoVREDMINU_VS_M1_E32,
7815 : PseudoVREDMINU_VS_M1_E32_MASK,
7816 : PseudoVREDMINU_VS_M1_E64,
7817 : PseudoVREDMINU_VS_M1_E64_MASK,
7818 : PseudoVREDMINU_VS_M1_E8,
7819 : PseudoVREDMINU_VS_M1_E8_MASK,
7820 : PseudoVREDMINU_VS_M2_E16,
7821 : PseudoVREDMINU_VS_M2_E16_MASK,
7822 : PseudoVREDMINU_VS_M2_E32,
7823 : PseudoVREDMINU_VS_M2_E32_MASK,
7824 : PseudoVREDMINU_VS_M2_E64,
7825 : PseudoVREDMINU_VS_M2_E64_MASK,
7826 : PseudoVREDMINU_VS_M2_E8,
7827 : PseudoVREDMINU_VS_M2_E8_MASK,
7828 : PseudoVREDMINU_VS_M4_E16,
7829 : PseudoVREDMINU_VS_M4_E16_MASK,
7830 : PseudoVREDMINU_VS_M4_E32,
7831 : PseudoVREDMINU_VS_M4_E32_MASK,
7832 : PseudoVREDMINU_VS_M4_E64,
7833 : PseudoVREDMINU_VS_M4_E64_MASK,
7834 : PseudoVREDMINU_VS_M4_E8,
7835 : PseudoVREDMINU_VS_M4_E8_MASK,
7836 : PseudoVREDMINU_VS_M8_E16,
7837 : PseudoVREDMINU_VS_M8_E16_MASK,
7838 : PseudoVREDMINU_VS_M8_E32,
7839 : PseudoVREDMINU_VS_M8_E32_MASK,
7840 : PseudoVREDMINU_VS_M8_E64,
7841 : PseudoVREDMINU_VS_M8_E64_MASK,
7842 : PseudoVREDMINU_VS_M8_E8,
7843 : PseudoVREDMINU_VS_M8_E8_MASK,
7844 : PseudoVREDMINU_VS_MF2_E16,
7845 : PseudoVREDMINU_VS_MF2_E16_MASK,
7846 : PseudoVREDMINU_VS_MF2_E32,
7847 : PseudoVREDMINU_VS_MF2_E32_MASK,
7848 : PseudoVREDMINU_VS_MF2_E8,
7849 : PseudoVREDMINU_VS_MF2_E8_MASK,
7850 : PseudoVREDMINU_VS_MF4_E16,
7851 : PseudoVREDMINU_VS_MF4_E16_MASK,
7852 : PseudoVREDMINU_VS_MF4_E8,
7853 : PseudoVREDMINU_VS_MF4_E8_MASK,
7854 : PseudoVREDMINU_VS_MF8_E8,
7855 : PseudoVREDMINU_VS_MF8_E8_MASK,
7856 : PseudoVREDMIN_VS_M1_E16,
7857 : PseudoVREDMIN_VS_M1_E16_MASK,
7858 : PseudoVREDMIN_VS_M1_E32,
7859 : PseudoVREDMIN_VS_M1_E32_MASK,
7860 : PseudoVREDMIN_VS_M1_E64,
7861 : PseudoVREDMIN_VS_M1_E64_MASK,
7862 : PseudoVREDMIN_VS_M1_E8,
7863 : PseudoVREDMIN_VS_M1_E8_MASK,
7864 : PseudoVREDMIN_VS_M2_E16,
7865 : PseudoVREDMIN_VS_M2_E16_MASK,
7866 : PseudoVREDMIN_VS_M2_E32,
7867 : PseudoVREDMIN_VS_M2_E32_MASK,
7868 : PseudoVREDMIN_VS_M2_E64,
7869 : PseudoVREDMIN_VS_M2_E64_MASK,
7870 : PseudoVREDMIN_VS_M2_E8,
7871 : PseudoVREDMIN_VS_M2_E8_MASK,
7872 : PseudoVREDMIN_VS_M4_E16,
7873 : PseudoVREDMIN_VS_M4_E16_MASK,
7874 : PseudoVREDMIN_VS_M4_E32,
7875 : PseudoVREDMIN_VS_M4_E32_MASK,
7876 : PseudoVREDMIN_VS_M4_E64,
7877 : PseudoVREDMIN_VS_M4_E64_MASK,
7878 : PseudoVREDMIN_VS_M4_E8,
7879 : PseudoVREDMIN_VS_M4_E8_MASK,
7880 : PseudoVREDMIN_VS_M8_E16,
7881 : PseudoVREDMIN_VS_M8_E16_MASK,
7882 : PseudoVREDMIN_VS_M8_E32,
7883 : PseudoVREDMIN_VS_M8_E32_MASK,
7884 : PseudoVREDMIN_VS_M8_E64,
7885 : PseudoVREDMIN_VS_M8_E64_MASK,
7886 : PseudoVREDMIN_VS_M8_E8,
7887 : PseudoVREDMIN_VS_M8_E8_MASK,
7888 : PseudoVREDMIN_VS_MF2_E16,
7889 : PseudoVREDMIN_VS_MF2_E16_MASK,
7890 : PseudoVREDMIN_VS_MF2_E32,
7891 : PseudoVREDMIN_VS_MF2_E32_MASK,
7892 : PseudoVREDMIN_VS_MF2_E8,
7893 : PseudoVREDMIN_VS_MF2_E8_MASK,
7894 : PseudoVREDMIN_VS_MF4_E16,
7895 : PseudoVREDMIN_VS_MF4_E16_MASK,
7896 : PseudoVREDMIN_VS_MF4_E8,
7897 : PseudoVREDMIN_VS_MF4_E8_MASK,
7898 : PseudoVREDMIN_VS_MF8_E8,
7899 : PseudoVREDMIN_VS_MF8_E8_MASK,
7900 : PseudoVREDOR_VS_M1_E16,
7901 : PseudoVREDOR_VS_M1_E16_MASK,
7902 : PseudoVREDOR_VS_M1_E32,
7903 : PseudoVREDOR_VS_M1_E32_MASK,
7904 : PseudoVREDOR_VS_M1_E64,
7905 : PseudoVREDOR_VS_M1_E64_MASK,
7906 : PseudoVREDOR_VS_M1_E8,
7907 : PseudoVREDOR_VS_M1_E8_MASK,
7908 : PseudoVREDOR_VS_M2_E16,
7909 : PseudoVREDOR_VS_M2_E16_MASK,
7910 : PseudoVREDOR_VS_M2_E32,
7911 : PseudoVREDOR_VS_M2_E32_MASK,
7912 : PseudoVREDOR_VS_M2_E64,
7913 : PseudoVREDOR_VS_M2_E64_MASK,
7914 : PseudoVREDOR_VS_M2_E8,
7915 : PseudoVREDOR_VS_M2_E8_MASK,
7916 : PseudoVREDOR_VS_M4_E16,
7917 : PseudoVREDOR_VS_M4_E16_MASK,
7918 : PseudoVREDOR_VS_M4_E32,
7919 : PseudoVREDOR_VS_M4_E32_MASK,
7920 : PseudoVREDOR_VS_M4_E64,
7921 : PseudoVREDOR_VS_M4_E64_MASK,
7922 : PseudoVREDOR_VS_M4_E8,
7923 : PseudoVREDOR_VS_M4_E8_MASK,
7924 : PseudoVREDOR_VS_M8_E16,
7925 : PseudoVREDOR_VS_M8_E16_MASK,
7926 : PseudoVREDOR_VS_M8_E32,
7927 : PseudoVREDOR_VS_M8_E32_MASK,
7928 : PseudoVREDOR_VS_M8_E64,
7929 : PseudoVREDOR_VS_M8_E64_MASK,
7930 : PseudoVREDOR_VS_M8_E8,
7931 : PseudoVREDOR_VS_M8_E8_MASK,
7932 : PseudoVREDOR_VS_MF2_E16,
7933 : PseudoVREDOR_VS_MF2_E16_MASK,
7934 : PseudoVREDOR_VS_MF2_E32,
7935 : PseudoVREDOR_VS_MF2_E32_MASK,
7936 : PseudoVREDOR_VS_MF2_E8,
7937 : PseudoVREDOR_VS_MF2_E8_MASK,
7938 : PseudoVREDOR_VS_MF4_E16,
7939 : PseudoVREDOR_VS_MF4_E16_MASK,
7940 : PseudoVREDOR_VS_MF4_E8,
7941 : PseudoVREDOR_VS_MF4_E8_MASK,
7942 : PseudoVREDOR_VS_MF8_E8,
7943 : PseudoVREDOR_VS_MF8_E8_MASK,
7944 : PseudoVREDSUM_VS_M1_E16,
7945 : PseudoVREDSUM_VS_M1_E16_MASK,
7946 : PseudoVREDSUM_VS_M1_E32,
7947 : PseudoVREDSUM_VS_M1_E32_MASK,
7948 : PseudoVREDSUM_VS_M1_E64,
7949 : PseudoVREDSUM_VS_M1_E64_MASK,
7950 : PseudoVREDSUM_VS_M1_E8,
7951 : PseudoVREDSUM_VS_M1_E8_MASK,
7952 : PseudoVREDSUM_VS_M2_E16,
7953 : PseudoVREDSUM_VS_M2_E16_MASK,
7954 : PseudoVREDSUM_VS_M2_E32,
7955 : PseudoVREDSUM_VS_M2_E32_MASK,
7956 : PseudoVREDSUM_VS_M2_E64,
7957 : PseudoVREDSUM_VS_M2_E64_MASK,
7958 : PseudoVREDSUM_VS_M2_E8,
7959 : PseudoVREDSUM_VS_M2_E8_MASK,
7960 : PseudoVREDSUM_VS_M4_E16,
7961 : PseudoVREDSUM_VS_M4_E16_MASK,
7962 : PseudoVREDSUM_VS_M4_E32,
7963 : PseudoVREDSUM_VS_M4_E32_MASK,
7964 : PseudoVREDSUM_VS_M4_E64,
7965 : PseudoVREDSUM_VS_M4_E64_MASK,
7966 : PseudoVREDSUM_VS_M4_E8,
7967 : PseudoVREDSUM_VS_M4_E8_MASK,
7968 : PseudoVREDSUM_VS_M8_E16,
7969 : PseudoVREDSUM_VS_M8_E16_MASK,
7970 : PseudoVREDSUM_VS_M8_E32,
7971 : PseudoVREDSUM_VS_M8_E32_MASK,
7972 : PseudoVREDSUM_VS_M8_E64,
7973 : PseudoVREDSUM_VS_M8_E64_MASK,
7974 : PseudoVREDSUM_VS_M8_E8,
7975 : PseudoVREDSUM_VS_M8_E8_MASK,
7976 : PseudoVREDSUM_VS_MF2_E16,
7977 : PseudoVREDSUM_VS_MF2_E16_MASK,
7978 : PseudoVREDSUM_VS_MF2_E32,
7979 : PseudoVREDSUM_VS_MF2_E32_MASK,
7980 : PseudoVREDSUM_VS_MF2_E8,
7981 : PseudoVREDSUM_VS_MF2_E8_MASK,
7982 : PseudoVREDSUM_VS_MF4_E16,
7983 : PseudoVREDSUM_VS_MF4_E16_MASK,
7984 : PseudoVREDSUM_VS_MF4_E8,
7985 : PseudoVREDSUM_VS_MF4_E8_MASK,
7986 : PseudoVREDSUM_VS_MF8_E8,
7987 : PseudoVREDSUM_VS_MF8_E8_MASK,
7988 : PseudoVREDXOR_VS_M1_E16,
7989 : PseudoVREDXOR_VS_M1_E16_MASK,
7990 : PseudoVREDXOR_VS_M1_E32,
7991 : PseudoVREDXOR_VS_M1_E32_MASK,
7992 : PseudoVREDXOR_VS_M1_E64,
7993 : PseudoVREDXOR_VS_M1_E64_MASK,
7994 : PseudoVREDXOR_VS_M1_E8,
7995 : PseudoVREDXOR_VS_M1_E8_MASK,
7996 : PseudoVREDXOR_VS_M2_E16,
7997 : PseudoVREDXOR_VS_M2_E16_MASK,
7998 : PseudoVREDXOR_VS_M2_E32,
7999 : PseudoVREDXOR_VS_M2_E32_MASK,
8000 : PseudoVREDXOR_VS_M2_E64,
8001 : PseudoVREDXOR_VS_M2_E64_MASK,
8002 : PseudoVREDXOR_VS_M2_E8,
8003 : PseudoVREDXOR_VS_M2_E8_MASK,
8004 : PseudoVREDXOR_VS_M4_E16,
8005 : PseudoVREDXOR_VS_M4_E16_MASK,
8006 : PseudoVREDXOR_VS_M4_E32,
8007 : PseudoVREDXOR_VS_M4_E32_MASK,
8008 : PseudoVREDXOR_VS_M4_E64,
8009 : PseudoVREDXOR_VS_M4_E64_MASK,
8010 : PseudoVREDXOR_VS_M4_E8,
8011 : PseudoVREDXOR_VS_M4_E8_MASK,
8012 : PseudoVREDXOR_VS_M8_E16,
8013 : PseudoVREDXOR_VS_M8_E16_MASK,
8014 : PseudoVREDXOR_VS_M8_E32,
8015 : PseudoVREDXOR_VS_M8_E32_MASK,
8016 : PseudoVREDXOR_VS_M8_E64,
8017 : PseudoVREDXOR_VS_M8_E64_MASK,
8018 : PseudoVREDXOR_VS_M8_E8,
8019 : PseudoVREDXOR_VS_M8_E8_MASK,
8020 : PseudoVREDXOR_VS_MF2_E16,
8021 : PseudoVREDXOR_VS_MF2_E16_MASK,
8022 : PseudoVREDXOR_VS_MF2_E32,
8023 : PseudoVREDXOR_VS_MF2_E32_MASK,
8024 : PseudoVREDXOR_VS_MF2_E8,
8025 : PseudoVREDXOR_VS_MF2_E8_MASK,
8026 : PseudoVREDXOR_VS_MF4_E16,
8027 : PseudoVREDXOR_VS_MF4_E16_MASK,
8028 : PseudoVREDXOR_VS_MF4_E8,
8029 : PseudoVREDXOR_VS_MF4_E8_MASK,
8030 : PseudoVREDXOR_VS_MF8_E8,
8031 : PseudoVREDXOR_VS_MF8_E8_MASK,
8032 : PseudoVRELOAD2_M1,
8033 : PseudoVRELOAD2_M2,
8034 : PseudoVRELOAD2_M4,
8035 : PseudoVRELOAD2_MF2,
8036 : PseudoVRELOAD2_MF4,
8037 : PseudoVRELOAD2_MF8,
8038 : PseudoVRELOAD3_M1,
8039 : PseudoVRELOAD3_M2,
8040 : PseudoVRELOAD3_MF2,
8041 : PseudoVRELOAD3_MF4,
8042 : PseudoVRELOAD3_MF8,
8043 : PseudoVRELOAD4_M1,
8044 : PseudoVRELOAD4_M2,
8045 : PseudoVRELOAD4_MF2,
8046 : PseudoVRELOAD4_MF4,
8047 : PseudoVRELOAD4_MF8,
8048 : PseudoVRELOAD5_M1,
8049 : PseudoVRELOAD5_MF2,
8050 : PseudoVRELOAD5_MF4,
8051 : PseudoVRELOAD5_MF8,
8052 : PseudoVRELOAD6_M1,
8053 : PseudoVRELOAD6_MF2,
8054 : PseudoVRELOAD6_MF4,
8055 : PseudoVRELOAD6_MF8,
8056 : PseudoVRELOAD7_M1,
8057 : PseudoVRELOAD7_MF2,
8058 : PseudoVRELOAD7_MF4,
8059 : PseudoVRELOAD7_MF8,
8060 : PseudoVRELOAD8_M1,
8061 : PseudoVRELOAD8_MF2,
8062 : PseudoVRELOAD8_MF4,
8063 : PseudoVRELOAD8_MF8,
8064 : PseudoVREMU_VV_M1_E16,
8065 : PseudoVREMU_VV_M1_E16_MASK,
8066 : PseudoVREMU_VV_M1_E32,
8067 : PseudoVREMU_VV_M1_E32_MASK,
8068 : PseudoVREMU_VV_M1_E64,
8069 : PseudoVREMU_VV_M1_E64_MASK,
8070 : PseudoVREMU_VV_M1_E8,
8071 : PseudoVREMU_VV_M1_E8_MASK,
8072 : PseudoVREMU_VV_M2_E16,
8073 : PseudoVREMU_VV_M2_E16_MASK,
8074 : PseudoVREMU_VV_M2_E32,
8075 : PseudoVREMU_VV_M2_E32_MASK,
8076 : PseudoVREMU_VV_M2_E64,
8077 : PseudoVREMU_VV_M2_E64_MASK,
8078 : PseudoVREMU_VV_M2_E8,
8079 : PseudoVREMU_VV_M2_E8_MASK,
8080 : PseudoVREMU_VV_M4_E16,
8081 : PseudoVREMU_VV_M4_E16_MASK,
8082 : PseudoVREMU_VV_M4_E32,
8083 : PseudoVREMU_VV_M4_E32_MASK,
8084 : PseudoVREMU_VV_M4_E64,
8085 : PseudoVREMU_VV_M4_E64_MASK,
8086 : PseudoVREMU_VV_M4_E8,
8087 : PseudoVREMU_VV_M4_E8_MASK,
8088 : PseudoVREMU_VV_M8_E16,
8089 : PseudoVREMU_VV_M8_E16_MASK,
8090 : PseudoVREMU_VV_M8_E32,
8091 : PseudoVREMU_VV_M8_E32_MASK,
8092 : PseudoVREMU_VV_M8_E64,
8093 : PseudoVREMU_VV_M8_E64_MASK,
8094 : PseudoVREMU_VV_M8_E8,
8095 : PseudoVREMU_VV_M8_E8_MASK,
8096 : PseudoVREMU_VV_MF2_E16,
8097 : PseudoVREMU_VV_MF2_E16_MASK,
8098 : PseudoVREMU_VV_MF2_E32,
8099 : PseudoVREMU_VV_MF2_E32_MASK,
8100 : PseudoVREMU_VV_MF2_E8,
8101 : PseudoVREMU_VV_MF2_E8_MASK,
8102 : PseudoVREMU_VV_MF4_E16,
8103 : PseudoVREMU_VV_MF4_E16_MASK,
8104 : PseudoVREMU_VV_MF4_E8,
8105 : PseudoVREMU_VV_MF4_E8_MASK,
8106 : PseudoVREMU_VV_MF8_E8,
8107 : PseudoVREMU_VV_MF8_E8_MASK,
8108 : PseudoVREMU_VX_M1_E16,
8109 : PseudoVREMU_VX_M1_E16_MASK,
8110 : PseudoVREMU_VX_M1_E32,
8111 : PseudoVREMU_VX_M1_E32_MASK,
8112 : PseudoVREMU_VX_M1_E64,
8113 : PseudoVREMU_VX_M1_E64_MASK,
8114 : PseudoVREMU_VX_M1_E8,
8115 : PseudoVREMU_VX_M1_E8_MASK,
8116 : PseudoVREMU_VX_M2_E16,
8117 : PseudoVREMU_VX_M2_E16_MASK,
8118 : PseudoVREMU_VX_M2_E32,
8119 : PseudoVREMU_VX_M2_E32_MASK,
8120 : PseudoVREMU_VX_M2_E64,
8121 : PseudoVREMU_VX_M2_E64_MASK,
8122 : PseudoVREMU_VX_M2_E8,
8123 : PseudoVREMU_VX_M2_E8_MASK,
8124 : PseudoVREMU_VX_M4_E16,
8125 : PseudoVREMU_VX_M4_E16_MASK,
8126 : PseudoVREMU_VX_M4_E32,
8127 : PseudoVREMU_VX_M4_E32_MASK,
8128 : PseudoVREMU_VX_M4_E64,
8129 : PseudoVREMU_VX_M4_E64_MASK,
8130 : PseudoVREMU_VX_M4_E8,
8131 : PseudoVREMU_VX_M4_E8_MASK,
8132 : PseudoVREMU_VX_M8_E16,
8133 : PseudoVREMU_VX_M8_E16_MASK,
8134 : PseudoVREMU_VX_M8_E32,
8135 : PseudoVREMU_VX_M8_E32_MASK,
8136 : PseudoVREMU_VX_M8_E64,
8137 : PseudoVREMU_VX_M8_E64_MASK,
8138 : PseudoVREMU_VX_M8_E8,
8139 : PseudoVREMU_VX_M8_E8_MASK,
8140 : PseudoVREMU_VX_MF2_E16,
8141 : PseudoVREMU_VX_MF2_E16_MASK,
8142 : PseudoVREMU_VX_MF2_E32,
8143 : PseudoVREMU_VX_MF2_E32_MASK,
8144 : PseudoVREMU_VX_MF2_E8,
8145 : PseudoVREMU_VX_MF2_E8_MASK,
8146 : PseudoVREMU_VX_MF4_E16,
8147 : PseudoVREMU_VX_MF4_E16_MASK,
8148 : PseudoVREMU_VX_MF4_E8,
8149 : PseudoVREMU_VX_MF4_E8_MASK,
8150 : PseudoVREMU_VX_MF8_E8,
8151 : PseudoVREMU_VX_MF8_E8_MASK,
8152 : PseudoVREM_VV_M1_E16,
8153 : PseudoVREM_VV_M1_E16_MASK,
8154 : PseudoVREM_VV_M1_E32,
8155 : PseudoVREM_VV_M1_E32_MASK,
8156 : PseudoVREM_VV_M1_E64,
8157 : PseudoVREM_VV_M1_E64_MASK,
8158 : PseudoVREM_VV_M1_E8,
8159 : PseudoVREM_VV_M1_E8_MASK,
8160 : PseudoVREM_VV_M2_E16,
8161 : PseudoVREM_VV_M2_E16_MASK,
8162 : PseudoVREM_VV_M2_E32,
8163 : PseudoVREM_VV_M2_E32_MASK,
8164 : PseudoVREM_VV_M2_E64,
8165 : PseudoVREM_VV_M2_E64_MASK,
8166 : PseudoVREM_VV_M2_E8,
8167 : PseudoVREM_VV_M2_E8_MASK,
8168 : PseudoVREM_VV_M4_E16,
8169 : PseudoVREM_VV_M4_E16_MASK,
8170 : PseudoVREM_VV_M4_E32,
8171 : PseudoVREM_VV_M4_E32_MASK,
8172 : PseudoVREM_VV_M4_E64,
8173 : PseudoVREM_VV_M4_E64_MASK,
8174 : PseudoVREM_VV_M4_E8,
8175 : PseudoVREM_VV_M4_E8_MASK,
8176 : PseudoVREM_VV_M8_E16,
8177 : PseudoVREM_VV_M8_E16_MASK,
8178 : PseudoVREM_VV_M8_E32,
8179 : PseudoVREM_VV_M8_E32_MASK,
8180 : PseudoVREM_VV_M8_E64,
8181 : PseudoVREM_VV_M8_E64_MASK,
8182 : PseudoVREM_VV_M8_E8,
8183 : PseudoVREM_VV_M8_E8_MASK,
8184 : PseudoVREM_VV_MF2_E16,
8185 : PseudoVREM_VV_MF2_E16_MASK,
8186 : PseudoVREM_VV_MF2_E32,
8187 : PseudoVREM_VV_MF2_E32_MASK,
8188 : PseudoVREM_VV_MF2_E8,
8189 : PseudoVREM_VV_MF2_E8_MASK,
8190 : PseudoVREM_VV_MF4_E16,
8191 : PseudoVREM_VV_MF4_E16_MASK,
8192 : PseudoVREM_VV_MF4_E8,
8193 : PseudoVREM_VV_MF4_E8_MASK,
8194 : PseudoVREM_VV_MF8_E8,
8195 : PseudoVREM_VV_MF8_E8_MASK,
8196 : PseudoVREM_VX_M1_E16,
8197 : PseudoVREM_VX_M1_E16_MASK,
8198 : PseudoVREM_VX_M1_E32,
8199 : PseudoVREM_VX_M1_E32_MASK,
8200 : PseudoVREM_VX_M1_E64,
8201 : PseudoVREM_VX_M1_E64_MASK,
8202 : PseudoVREM_VX_M1_E8,
8203 : PseudoVREM_VX_M1_E8_MASK,
8204 : PseudoVREM_VX_M2_E16,
8205 : PseudoVREM_VX_M2_E16_MASK,
8206 : PseudoVREM_VX_M2_E32,
8207 : PseudoVREM_VX_M2_E32_MASK,
8208 : PseudoVREM_VX_M2_E64,
8209 : PseudoVREM_VX_M2_E64_MASK,
8210 : PseudoVREM_VX_M2_E8,
8211 : PseudoVREM_VX_M2_E8_MASK,
8212 : PseudoVREM_VX_M4_E16,
8213 : PseudoVREM_VX_M4_E16_MASK,
8214 : PseudoVREM_VX_M4_E32,
8215 : PseudoVREM_VX_M4_E32_MASK,
8216 : PseudoVREM_VX_M4_E64,
8217 : PseudoVREM_VX_M4_E64_MASK,
8218 : PseudoVREM_VX_M4_E8,
8219 : PseudoVREM_VX_M4_E8_MASK,
8220 : PseudoVREM_VX_M8_E16,
8221 : PseudoVREM_VX_M8_E16_MASK,
8222 : PseudoVREM_VX_M8_E32,
8223 : PseudoVREM_VX_M8_E32_MASK,
8224 : PseudoVREM_VX_M8_E64,
8225 : PseudoVREM_VX_M8_E64_MASK,
8226 : PseudoVREM_VX_M8_E8,
8227 : PseudoVREM_VX_M8_E8_MASK,
8228 : PseudoVREM_VX_MF2_E16,
8229 : PseudoVREM_VX_MF2_E16_MASK,
8230 : PseudoVREM_VX_MF2_E32,
8231 : PseudoVREM_VX_MF2_E32_MASK,
8232 : PseudoVREM_VX_MF2_E8,
8233 : PseudoVREM_VX_MF2_E8_MASK,
8234 : PseudoVREM_VX_MF4_E16,
8235 : PseudoVREM_VX_MF4_E16_MASK,
8236 : PseudoVREM_VX_MF4_E8,
8237 : PseudoVREM_VX_MF4_E8_MASK,
8238 : PseudoVREM_VX_MF8_E8,
8239 : PseudoVREM_VX_MF8_E8_MASK,
8240 : PseudoVREV8_V_M1,
8241 : PseudoVREV8_V_M1_MASK,
8242 : PseudoVREV8_V_M2,
8243 : PseudoVREV8_V_M2_MASK,
8244 : PseudoVREV8_V_M4,
8245 : PseudoVREV8_V_M4_MASK,
8246 : PseudoVREV8_V_M8,
8247 : PseudoVREV8_V_M8_MASK,
8248 : PseudoVREV8_V_MF2,
8249 : PseudoVREV8_V_MF2_MASK,
8250 : PseudoVREV8_V_MF4,
8251 : PseudoVREV8_V_MF4_MASK,
8252 : PseudoVREV8_V_MF8,
8253 : PseudoVREV8_V_MF8_MASK,
8254 : PseudoVRGATHEREI16_VV_M1_E16_M1,
8255 : PseudoVRGATHEREI16_VV_M1_E16_M1_MASK,
8256 : PseudoVRGATHEREI16_VV_M1_E16_M2,
8257 : PseudoVRGATHEREI16_VV_M1_E16_M2_MASK,
8258 : PseudoVRGATHEREI16_VV_M1_E16_MF2,
8259 : PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK,
8260 : PseudoVRGATHEREI16_VV_M1_E16_MF4,
8261 : PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK,
8262 : PseudoVRGATHEREI16_VV_M1_E32_M1,
8263 : PseudoVRGATHEREI16_VV_M1_E32_M1_MASK,
8264 : PseudoVRGATHEREI16_VV_M1_E32_M2,
8265 : PseudoVRGATHEREI16_VV_M1_E32_M2_MASK,
8266 : PseudoVRGATHEREI16_VV_M1_E32_MF2,
8267 : PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK,
8268 : PseudoVRGATHEREI16_VV_M1_E32_MF4,
8269 : PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK,
8270 : PseudoVRGATHEREI16_VV_M1_E64_M1,
8271 : PseudoVRGATHEREI16_VV_M1_E64_M1_MASK,
8272 : PseudoVRGATHEREI16_VV_M1_E64_M2,
8273 : PseudoVRGATHEREI16_VV_M1_E64_M2_MASK,
8274 : PseudoVRGATHEREI16_VV_M1_E64_MF2,
8275 : PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK,
8276 : PseudoVRGATHEREI16_VV_M1_E64_MF4,
8277 : PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK,
8278 : PseudoVRGATHEREI16_VV_M1_E8_M1,
8279 : PseudoVRGATHEREI16_VV_M1_E8_M1_MASK,
8280 : PseudoVRGATHEREI16_VV_M1_E8_M2,
8281 : PseudoVRGATHEREI16_VV_M1_E8_M2_MASK,
8282 : PseudoVRGATHEREI16_VV_M1_E8_MF2,
8283 : PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK,
8284 : PseudoVRGATHEREI16_VV_M1_E8_MF4,
8285 : PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK,
8286 : PseudoVRGATHEREI16_VV_M2_E16_M1,
8287 : PseudoVRGATHEREI16_VV_M2_E16_M1_MASK,
8288 : PseudoVRGATHEREI16_VV_M2_E16_M2,
8289 : PseudoVRGATHEREI16_VV_M2_E16_M2_MASK,
8290 : PseudoVRGATHEREI16_VV_M2_E16_M4,
8291 : PseudoVRGATHEREI16_VV_M2_E16_M4_MASK,
8292 : PseudoVRGATHEREI16_VV_M2_E16_MF2,
8293 : PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK,
8294 : PseudoVRGATHEREI16_VV_M2_E32_M1,
8295 : PseudoVRGATHEREI16_VV_M2_E32_M1_MASK,
8296 : PseudoVRGATHEREI16_VV_M2_E32_M2,
8297 : PseudoVRGATHEREI16_VV_M2_E32_M2_MASK,
8298 : PseudoVRGATHEREI16_VV_M2_E32_M4,
8299 : PseudoVRGATHEREI16_VV_M2_E32_M4_MASK,
8300 : PseudoVRGATHEREI16_VV_M2_E32_MF2,
8301 : PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK,
8302 : PseudoVRGATHEREI16_VV_M2_E64_M1,
8303 : PseudoVRGATHEREI16_VV_M2_E64_M1_MASK,
8304 : PseudoVRGATHEREI16_VV_M2_E64_M2,
8305 : PseudoVRGATHEREI16_VV_M2_E64_M2_MASK,
8306 : PseudoVRGATHEREI16_VV_M2_E64_M4,
8307 : PseudoVRGATHEREI16_VV_M2_E64_M4_MASK,
8308 : PseudoVRGATHEREI16_VV_M2_E64_MF2,
8309 : PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK,
8310 : PseudoVRGATHEREI16_VV_M2_E8_M1,
8311 : PseudoVRGATHEREI16_VV_M2_E8_M1_MASK,
8312 : PseudoVRGATHEREI16_VV_M2_E8_M2,
8313 : PseudoVRGATHEREI16_VV_M2_E8_M2_MASK,
8314 : PseudoVRGATHEREI16_VV_M2_E8_M4,
8315 : PseudoVRGATHEREI16_VV_M2_E8_M4_MASK,
8316 : PseudoVRGATHEREI16_VV_M2_E8_MF2,
8317 : PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK,
8318 : PseudoVRGATHEREI16_VV_M4_E16_M1,
8319 : PseudoVRGATHEREI16_VV_M4_E16_M1_MASK,
8320 : PseudoVRGATHEREI16_VV_M4_E16_M2,
8321 : PseudoVRGATHEREI16_VV_M4_E16_M2_MASK,
8322 : PseudoVRGATHEREI16_VV_M4_E16_M4,
8323 : PseudoVRGATHEREI16_VV_M4_E16_M4_MASK,
8324 : PseudoVRGATHEREI16_VV_M4_E16_M8,
8325 : PseudoVRGATHEREI16_VV_M4_E16_M8_MASK,
8326 : PseudoVRGATHEREI16_VV_M4_E32_M1,
8327 : PseudoVRGATHEREI16_VV_M4_E32_M1_MASK,
8328 : PseudoVRGATHEREI16_VV_M4_E32_M2,
8329 : PseudoVRGATHEREI16_VV_M4_E32_M2_MASK,
8330 : PseudoVRGATHEREI16_VV_M4_E32_M4,
8331 : PseudoVRGATHEREI16_VV_M4_E32_M4_MASK,
8332 : PseudoVRGATHEREI16_VV_M4_E32_M8,
8333 : PseudoVRGATHEREI16_VV_M4_E32_M8_MASK,
8334 : PseudoVRGATHEREI16_VV_M4_E64_M1,
8335 : PseudoVRGATHEREI16_VV_M4_E64_M1_MASK,
8336 : PseudoVRGATHEREI16_VV_M4_E64_M2,
8337 : PseudoVRGATHEREI16_VV_M4_E64_M2_MASK,
8338 : PseudoVRGATHEREI16_VV_M4_E64_M4,
8339 : PseudoVRGATHEREI16_VV_M4_E64_M4_MASK,
8340 : PseudoVRGATHEREI16_VV_M4_E64_M8,
8341 : PseudoVRGATHEREI16_VV_M4_E64_M8_MASK,
8342 : PseudoVRGATHEREI16_VV_M4_E8_M1,
8343 : PseudoVRGATHEREI16_VV_M4_E8_M1_MASK,
8344 : PseudoVRGATHEREI16_VV_M4_E8_M2,
8345 : PseudoVRGATHEREI16_VV_M4_E8_M2_MASK,
8346 : PseudoVRGATHEREI16_VV_M4_E8_M4,
8347 : PseudoVRGATHEREI16_VV_M4_E8_M4_MASK,
8348 : PseudoVRGATHEREI16_VV_M4_E8_M8,
8349 : PseudoVRGATHEREI16_VV_M4_E8_M8_MASK,
8350 : PseudoVRGATHEREI16_VV_M8_E16_M2,
8351 : PseudoVRGATHEREI16_VV_M8_E16_M2_MASK,
8352 : PseudoVRGATHEREI16_VV_M8_E16_M4,
8353 : PseudoVRGATHEREI16_VV_M8_E16_M4_MASK,
8354 : PseudoVRGATHEREI16_VV_M8_E16_M8,
8355 : PseudoVRGATHEREI16_VV_M8_E16_M8_MASK,
8356 : PseudoVRGATHEREI16_VV_M8_E32_M2,
8357 : PseudoVRGATHEREI16_VV_M8_E32_M2_MASK,
8358 : PseudoVRGATHEREI16_VV_M8_E32_M4,
8359 : PseudoVRGATHEREI16_VV_M8_E32_M4_MASK,
8360 : PseudoVRGATHEREI16_VV_M8_E32_M8,
8361 : PseudoVRGATHEREI16_VV_M8_E32_M8_MASK,
8362 : PseudoVRGATHEREI16_VV_M8_E64_M2,
8363 : PseudoVRGATHEREI16_VV_M8_E64_M2_MASK,
8364 : PseudoVRGATHEREI16_VV_M8_E64_M4,
8365 : PseudoVRGATHEREI16_VV_M8_E64_M4_MASK,
8366 : PseudoVRGATHEREI16_VV_M8_E64_M8,
8367 : PseudoVRGATHEREI16_VV_M8_E64_M8_MASK,
8368 : PseudoVRGATHEREI16_VV_M8_E8_M2,
8369 : PseudoVRGATHEREI16_VV_M8_E8_M2_MASK,
8370 : PseudoVRGATHEREI16_VV_M8_E8_M4,
8371 : PseudoVRGATHEREI16_VV_M8_E8_M4_MASK,
8372 : PseudoVRGATHEREI16_VV_M8_E8_M8,
8373 : PseudoVRGATHEREI16_VV_M8_E8_M8_MASK,
8374 : PseudoVRGATHEREI16_VV_MF2_E16_M1,
8375 : PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK,
8376 : PseudoVRGATHEREI16_VV_MF2_E16_MF2,
8377 : PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK,
8378 : PseudoVRGATHEREI16_VV_MF2_E16_MF4,
8379 : PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK,
8380 : PseudoVRGATHEREI16_VV_MF2_E16_MF8,
8381 : PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK,
8382 : PseudoVRGATHEREI16_VV_MF2_E32_M1,
8383 : PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK,
8384 : PseudoVRGATHEREI16_VV_MF2_E32_MF2,
8385 : PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK,
8386 : PseudoVRGATHEREI16_VV_MF2_E32_MF4,
8387 : PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK,
8388 : PseudoVRGATHEREI16_VV_MF2_E32_MF8,
8389 : PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK,
8390 : PseudoVRGATHEREI16_VV_MF2_E8_M1,
8391 : PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK,
8392 : PseudoVRGATHEREI16_VV_MF2_E8_MF2,
8393 : PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK,
8394 : PseudoVRGATHEREI16_VV_MF2_E8_MF4,
8395 : PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK,
8396 : PseudoVRGATHEREI16_VV_MF2_E8_MF8,
8397 : PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK,
8398 : PseudoVRGATHEREI16_VV_MF4_E16_MF2,
8399 : PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK,
8400 : PseudoVRGATHEREI16_VV_MF4_E16_MF4,
8401 : PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK,
8402 : PseudoVRGATHEREI16_VV_MF4_E16_MF8,
8403 : PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK,
8404 : PseudoVRGATHEREI16_VV_MF4_E8_MF2,
8405 : PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK,
8406 : PseudoVRGATHEREI16_VV_MF4_E8_MF4,
8407 : PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK,
8408 : PseudoVRGATHEREI16_VV_MF4_E8_MF8,
8409 : PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK,
8410 : PseudoVRGATHEREI16_VV_MF8_E8_MF4,
8411 : PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK,
8412 : PseudoVRGATHEREI16_VV_MF8_E8_MF8,
8413 : PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK,
8414 : PseudoVRGATHER_VI_M1,
8415 : PseudoVRGATHER_VI_M1_MASK,
8416 : PseudoVRGATHER_VI_M2,
8417 : PseudoVRGATHER_VI_M2_MASK,
8418 : PseudoVRGATHER_VI_M4,
8419 : PseudoVRGATHER_VI_M4_MASK,
8420 : PseudoVRGATHER_VI_M8,
8421 : PseudoVRGATHER_VI_M8_MASK,
8422 : PseudoVRGATHER_VI_MF2,
8423 : PseudoVRGATHER_VI_MF2_MASK,
8424 : PseudoVRGATHER_VI_MF4,
8425 : PseudoVRGATHER_VI_MF4_MASK,
8426 : PseudoVRGATHER_VI_MF8,
8427 : PseudoVRGATHER_VI_MF8_MASK,
8428 : PseudoVRGATHER_VV_M1_E16,
8429 : PseudoVRGATHER_VV_M1_E16_MASK,
8430 : PseudoVRGATHER_VV_M1_E32,
8431 : PseudoVRGATHER_VV_M1_E32_MASK,
8432 : PseudoVRGATHER_VV_M1_E64,
8433 : PseudoVRGATHER_VV_M1_E64_MASK,
8434 : PseudoVRGATHER_VV_M1_E8,
8435 : PseudoVRGATHER_VV_M1_E8_MASK,
8436 : PseudoVRGATHER_VV_M2_E16,
8437 : PseudoVRGATHER_VV_M2_E16_MASK,
8438 : PseudoVRGATHER_VV_M2_E32,
8439 : PseudoVRGATHER_VV_M2_E32_MASK,
8440 : PseudoVRGATHER_VV_M2_E64,
8441 : PseudoVRGATHER_VV_M2_E64_MASK,
8442 : PseudoVRGATHER_VV_M2_E8,
8443 : PseudoVRGATHER_VV_M2_E8_MASK,
8444 : PseudoVRGATHER_VV_M4_E16,
8445 : PseudoVRGATHER_VV_M4_E16_MASK,
8446 : PseudoVRGATHER_VV_M4_E32,
8447 : PseudoVRGATHER_VV_M4_E32_MASK,
8448 : PseudoVRGATHER_VV_M4_E64,
8449 : PseudoVRGATHER_VV_M4_E64_MASK,
8450 : PseudoVRGATHER_VV_M4_E8,
8451 : PseudoVRGATHER_VV_M4_E8_MASK,
8452 : PseudoVRGATHER_VV_M8_E16,
8453 : PseudoVRGATHER_VV_M8_E16_MASK,
8454 : PseudoVRGATHER_VV_M8_E32,
8455 : PseudoVRGATHER_VV_M8_E32_MASK,
8456 : PseudoVRGATHER_VV_M8_E64,
8457 : PseudoVRGATHER_VV_M8_E64_MASK,
8458 : PseudoVRGATHER_VV_M8_E8,
8459 : PseudoVRGATHER_VV_M8_E8_MASK,
8460 : PseudoVRGATHER_VV_MF2_E16,
8461 : PseudoVRGATHER_VV_MF2_E16_MASK,
8462 : PseudoVRGATHER_VV_MF2_E32,
8463 : PseudoVRGATHER_VV_MF2_E32_MASK,
8464 : PseudoVRGATHER_VV_MF2_E8,
8465 : PseudoVRGATHER_VV_MF2_E8_MASK,
8466 : PseudoVRGATHER_VV_MF4_E16,
8467 : PseudoVRGATHER_VV_MF4_E16_MASK,
8468 : PseudoVRGATHER_VV_MF4_E8,
8469 : PseudoVRGATHER_VV_MF4_E8_MASK,
8470 : PseudoVRGATHER_VV_MF8_E8,
8471 : PseudoVRGATHER_VV_MF8_E8_MASK,
8472 : PseudoVRGATHER_VX_M1,
8473 : PseudoVRGATHER_VX_M1_MASK,
8474 : PseudoVRGATHER_VX_M2,
8475 : PseudoVRGATHER_VX_M2_MASK,
8476 : PseudoVRGATHER_VX_M4,
8477 : PseudoVRGATHER_VX_M4_MASK,
8478 : PseudoVRGATHER_VX_M8,
8479 : PseudoVRGATHER_VX_M8_MASK,
8480 : PseudoVRGATHER_VX_MF2,
8481 : PseudoVRGATHER_VX_MF2_MASK,
8482 : PseudoVRGATHER_VX_MF4,
8483 : PseudoVRGATHER_VX_MF4_MASK,
8484 : PseudoVRGATHER_VX_MF8,
8485 : PseudoVRGATHER_VX_MF8_MASK,
8486 : PseudoVROL_VV_M1,
8487 : PseudoVROL_VV_M1_MASK,
8488 : PseudoVROL_VV_M2,
8489 : PseudoVROL_VV_M2_MASK,
8490 : PseudoVROL_VV_M4,
8491 : PseudoVROL_VV_M4_MASK,
8492 : PseudoVROL_VV_M8,
8493 : PseudoVROL_VV_M8_MASK,
8494 : PseudoVROL_VV_MF2,
8495 : PseudoVROL_VV_MF2_MASK,
8496 : PseudoVROL_VV_MF4,
8497 : PseudoVROL_VV_MF4_MASK,
8498 : PseudoVROL_VV_MF8,
8499 : PseudoVROL_VV_MF8_MASK,
8500 : PseudoVROL_VX_M1,
8501 : PseudoVROL_VX_M1_MASK,
8502 : PseudoVROL_VX_M2,
8503 : PseudoVROL_VX_M2_MASK,
8504 : PseudoVROL_VX_M4,
8505 : PseudoVROL_VX_M4_MASK,
8506 : PseudoVROL_VX_M8,
8507 : PseudoVROL_VX_M8_MASK,
8508 : PseudoVROL_VX_MF2,
8509 : PseudoVROL_VX_MF2_MASK,
8510 : PseudoVROL_VX_MF4,
8511 : PseudoVROL_VX_MF4_MASK,
8512 : PseudoVROL_VX_MF8,
8513 : PseudoVROL_VX_MF8_MASK,
8514 : PseudoVROR_VI_M1,
8515 : PseudoVROR_VI_M1_MASK,
8516 : PseudoVROR_VI_M2,
8517 : PseudoVROR_VI_M2_MASK,
8518 : PseudoVROR_VI_M4,
8519 : PseudoVROR_VI_M4_MASK,
8520 : PseudoVROR_VI_M8,
8521 : PseudoVROR_VI_M8_MASK,
8522 : PseudoVROR_VI_MF2,
8523 : PseudoVROR_VI_MF2_MASK,
8524 : PseudoVROR_VI_MF4,
8525 : PseudoVROR_VI_MF4_MASK,
8526 : PseudoVROR_VI_MF8,
8527 : PseudoVROR_VI_MF8_MASK,
8528 : PseudoVROR_VV_M1,
8529 : PseudoVROR_VV_M1_MASK,
8530 : PseudoVROR_VV_M2,
8531 : PseudoVROR_VV_M2_MASK,
8532 : PseudoVROR_VV_M4,
8533 : PseudoVROR_VV_M4_MASK,
8534 : PseudoVROR_VV_M8,
8535 : PseudoVROR_VV_M8_MASK,
8536 : PseudoVROR_VV_MF2,
8537 : PseudoVROR_VV_MF2_MASK,
8538 : PseudoVROR_VV_MF4,
8539 : PseudoVROR_VV_MF4_MASK,
8540 : PseudoVROR_VV_MF8,
8541 : PseudoVROR_VV_MF8_MASK,
8542 : PseudoVROR_VX_M1,
8543 : PseudoVROR_VX_M1_MASK,
8544 : PseudoVROR_VX_M2,
8545 : PseudoVROR_VX_M2_MASK,
8546 : PseudoVROR_VX_M4,
8547 : PseudoVROR_VX_M4_MASK,
8548 : PseudoVROR_VX_M8,
8549 : PseudoVROR_VX_M8_MASK,
8550 : PseudoVROR_VX_MF2,
8551 : PseudoVROR_VX_MF2_MASK,
8552 : PseudoVROR_VX_MF4,
8553 : PseudoVROR_VX_MF4_MASK,
8554 : PseudoVROR_VX_MF8,
8555 : PseudoVROR_VX_MF8_MASK,
8556 : PseudoVRSUB_VI_M1,
8557 : PseudoVRSUB_VI_M1_MASK,
8558 : PseudoVRSUB_VI_M2,
8559 : PseudoVRSUB_VI_M2_MASK,
8560 : PseudoVRSUB_VI_M4,
8561 : PseudoVRSUB_VI_M4_MASK,
8562 : PseudoVRSUB_VI_M8,
8563 : PseudoVRSUB_VI_M8_MASK,
8564 : PseudoVRSUB_VI_MF2,
8565 : PseudoVRSUB_VI_MF2_MASK,
8566 : PseudoVRSUB_VI_MF4,
8567 : PseudoVRSUB_VI_MF4_MASK,
8568 : PseudoVRSUB_VI_MF8,
8569 : PseudoVRSUB_VI_MF8_MASK,
8570 : PseudoVRSUB_VX_M1,
8571 : PseudoVRSUB_VX_M1_MASK,
8572 : PseudoVRSUB_VX_M2,
8573 : PseudoVRSUB_VX_M2_MASK,
8574 : PseudoVRSUB_VX_M4,
8575 : PseudoVRSUB_VX_M4_MASK,
8576 : PseudoVRSUB_VX_M8,
8577 : PseudoVRSUB_VX_M8_MASK,
8578 : PseudoVRSUB_VX_MF2,
8579 : PseudoVRSUB_VX_MF2_MASK,
8580 : PseudoVRSUB_VX_MF4,
8581 : PseudoVRSUB_VX_MF4_MASK,
8582 : PseudoVRSUB_VX_MF8,
8583 : PseudoVRSUB_VX_MF8_MASK,
8584 : PseudoVSADDU_VI_M1,
8585 : PseudoVSADDU_VI_M1_MASK,
8586 : PseudoVSADDU_VI_M2,
8587 : PseudoVSADDU_VI_M2_MASK,
8588 : PseudoVSADDU_VI_M4,
8589 : PseudoVSADDU_VI_M4_MASK,
8590 : PseudoVSADDU_VI_M8,
8591 : PseudoVSADDU_VI_M8_MASK,
8592 : PseudoVSADDU_VI_MF2,
8593 : PseudoVSADDU_VI_MF2_MASK,
8594 : PseudoVSADDU_VI_MF4,
8595 : PseudoVSADDU_VI_MF4_MASK,
8596 : PseudoVSADDU_VI_MF8,
8597 : PseudoVSADDU_VI_MF8_MASK,
8598 : PseudoVSADDU_VV_M1,
8599 : PseudoVSADDU_VV_M1_MASK,
8600 : PseudoVSADDU_VV_M2,
8601 : PseudoVSADDU_VV_M2_MASK,
8602 : PseudoVSADDU_VV_M4,
8603 : PseudoVSADDU_VV_M4_MASK,
8604 : PseudoVSADDU_VV_M8,
8605 : PseudoVSADDU_VV_M8_MASK,
8606 : PseudoVSADDU_VV_MF2,
8607 : PseudoVSADDU_VV_MF2_MASK,
8608 : PseudoVSADDU_VV_MF4,
8609 : PseudoVSADDU_VV_MF4_MASK,
8610 : PseudoVSADDU_VV_MF8,
8611 : PseudoVSADDU_VV_MF8_MASK,
8612 : PseudoVSADDU_VX_M1,
8613 : PseudoVSADDU_VX_M1_MASK,
8614 : PseudoVSADDU_VX_M2,
8615 : PseudoVSADDU_VX_M2_MASK,
8616 : PseudoVSADDU_VX_M4,
8617 : PseudoVSADDU_VX_M4_MASK,
8618 : PseudoVSADDU_VX_M8,
8619 : PseudoVSADDU_VX_M8_MASK,
8620 : PseudoVSADDU_VX_MF2,
8621 : PseudoVSADDU_VX_MF2_MASK,
8622 : PseudoVSADDU_VX_MF4,
8623 : PseudoVSADDU_VX_MF4_MASK,
8624 : PseudoVSADDU_VX_MF8,
8625 : PseudoVSADDU_VX_MF8_MASK,
8626 : PseudoVSADD_VI_M1,
8627 : PseudoVSADD_VI_M1_MASK,
8628 : PseudoVSADD_VI_M2,
8629 : PseudoVSADD_VI_M2_MASK,
8630 : PseudoVSADD_VI_M4,
8631 : PseudoVSADD_VI_M4_MASK,
8632 : PseudoVSADD_VI_M8,
8633 : PseudoVSADD_VI_M8_MASK,
8634 : PseudoVSADD_VI_MF2,
8635 : PseudoVSADD_VI_MF2_MASK,
8636 : PseudoVSADD_VI_MF4,
8637 : PseudoVSADD_VI_MF4_MASK,
8638 : PseudoVSADD_VI_MF8,
8639 : PseudoVSADD_VI_MF8_MASK,
8640 : PseudoVSADD_VV_M1,
8641 : PseudoVSADD_VV_M1_MASK,
8642 : PseudoVSADD_VV_M2,
8643 : PseudoVSADD_VV_M2_MASK,
8644 : PseudoVSADD_VV_M4,
8645 : PseudoVSADD_VV_M4_MASK,
8646 : PseudoVSADD_VV_M8,
8647 : PseudoVSADD_VV_M8_MASK,
8648 : PseudoVSADD_VV_MF2,
8649 : PseudoVSADD_VV_MF2_MASK,
8650 : PseudoVSADD_VV_MF4,
8651 : PseudoVSADD_VV_MF4_MASK,
8652 : PseudoVSADD_VV_MF8,
8653 : PseudoVSADD_VV_MF8_MASK,
8654 : PseudoVSADD_VX_M1,
8655 : PseudoVSADD_VX_M1_MASK,
8656 : PseudoVSADD_VX_M2,
8657 : PseudoVSADD_VX_M2_MASK,
8658 : PseudoVSADD_VX_M4,
8659 : PseudoVSADD_VX_M4_MASK,
8660 : PseudoVSADD_VX_M8,
8661 : PseudoVSADD_VX_M8_MASK,
8662 : PseudoVSADD_VX_MF2,
8663 : PseudoVSADD_VX_MF2_MASK,
8664 : PseudoVSADD_VX_MF4,
8665 : PseudoVSADD_VX_MF4_MASK,
8666 : PseudoVSADD_VX_MF8,
8667 : PseudoVSADD_VX_MF8_MASK,
8668 : PseudoVSBC_VVM_M1,
8669 : PseudoVSBC_VVM_M2,
8670 : PseudoVSBC_VVM_M4,
8671 : PseudoVSBC_VVM_M8,
8672 : PseudoVSBC_VVM_MF2,
8673 : PseudoVSBC_VVM_MF4,
8674 : PseudoVSBC_VVM_MF8,
8675 : PseudoVSBC_VXM_M1,
8676 : PseudoVSBC_VXM_M2,
8677 : PseudoVSBC_VXM_M4,
8678 : PseudoVSBC_VXM_M8,
8679 : PseudoVSBC_VXM_MF2,
8680 : PseudoVSBC_VXM_MF4,
8681 : PseudoVSBC_VXM_MF8,
8682 : PseudoVSE16_V_M1,
8683 : PseudoVSE16_V_M1_MASK,
8684 : PseudoVSE16_V_M2,
8685 : PseudoVSE16_V_M2_MASK,
8686 : PseudoVSE16_V_M4,
8687 : PseudoVSE16_V_M4_MASK,
8688 : PseudoVSE16_V_M8,
8689 : PseudoVSE16_V_M8_MASK,
8690 : PseudoVSE16_V_MF2,
8691 : PseudoVSE16_V_MF2_MASK,
8692 : PseudoVSE16_V_MF4,
8693 : PseudoVSE16_V_MF4_MASK,
8694 : PseudoVSE32_V_M1,
8695 : PseudoVSE32_V_M1_MASK,
8696 : PseudoVSE32_V_M2,
8697 : PseudoVSE32_V_M2_MASK,
8698 : PseudoVSE32_V_M4,
8699 : PseudoVSE32_V_M4_MASK,
8700 : PseudoVSE32_V_M8,
8701 : PseudoVSE32_V_M8_MASK,
8702 : PseudoVSE32_V_MF2,
8703 : PseudoVSE32_V_MF2_MASK,
8704 : PseudoVSE64_V_M1,
8705 : PseudoVSE64_V_M1_MASK,
8706 : PseudoVSE64_V_M2,
8707 : PseudoVSE64_V_M2_MASK,
8708 : PseudoVSE64_V_M4,
8709 : PseudoVSE64_V_M4_MASK,
8710 : PseudoVSE64_V_M8,
8711 : PseudoVSE64_V_M8_MASK,
8712 : PseudoVSE8_V_M1,
8713 : PseudoVSE8_V_M1_MASK,
8714 : PseudoVSE8_V_M2,
8715 : PseudoVSE8_V_M2_MASK,
8716 : PseudoVSE8_V_M4,
8717 : PseudoVSE8_V_M4_MASK,
8718 : PseudoVSE8_V_M8,
8719 : PseudoVSE8_V_M8_MASK,
8720 : PseudoVSE8_V_MF2,
8721 : PseudoVSE8_V_MF2_MASK,
8722 : PseudoVSE8_V_MF4,
8723 : PseudoVSE8_V_MF4_MASK,
8724 : PseudoVSE8_V_MF8,
8725 : PseudoVSE8_V_MF8_MASK,
8726 : PseudoVSETIVLI,
8727 : PseudoVSETVLI,
8728 : PseudoVSETVLIX0,
8729 : PseudoVSEXT_VF2_M1,
8730 : PseudoVSEXT_VF2_M1_MASK,
8731 : PseudoVSEXT_VF2_M2,
8732 : PseudoVSEXT_VF2_M2_MASK,
8733 : PseudoVSEXT_VF2_M4,
8734 : PseudoVSEXT_VF2_M4_MASK,
8735 : PseudoVSEXT_VF2_M8,
8736 : PseudoVSEXT_VF2_M8_MASK,
8737 : PseudoVSEXT_VF2_MF2,
8738 : PseudoVSEXT_VF2_MF2_MASK,
8739 : PseudoVSEXT_VF2_MF4,
8740 : PseudoVSEXT_VF2_MF4_MASK,
8741 : PseudoVSEXT_VF4_M1,
8742 : PseudoVSEXT_VF4_M1_MASK,
8743 : PseudoVSEXT_VF4_M2,
8744 : PseudoVSEXT_VF4_M2_MASK,
8745 : PseudoVSEXT_VF4_M4,
8746 : PseudoVSEXT_VF4_M4_MASK,
8747 : PseudoVSEXT_VF4_M8,
8748 : PseudoVSEXT_VF4_M8_MASK,
8749 : PseudoVSEXT_VF4_MF2,
8750 : PseudoVSEXT_VF4_MF2_MASK,
8751 : PseudoVSEXT_VF8_M1,
8752 : PseudoVSEXT_VF8_M1_MASK,
8753 : PseudoVSEXT_VF8_M2,
8754 : PseudoVSEXT_VF8_M2_MASK,
8755 : PseudoVSEXT_VF8_M4,
8756 : PseudoVSEXT_VF8_M4_MASK,
8757 : PseudoVSEXT_VF8_M8,
8758 : PseudoVSEXT_VF8_M8_MASK,
8759 : PseudoVSHA2CH_VV_M1,
8760 : PseudoVSHA2CH_VV_M2,
8761 : PseudoVSHA2CH_VV_M4,
8762 : PseudoVSHA2CH_VV_M8,
8763 : PseudoVSHA2CH_VV_MF2,
8764 : PseudoVSHA2CL_VV_M1,
8765 : PseudoVSHA2CL_VV_M2,
8766 : PseudoVSHA2CL_VV_M4,
8767 : PseudoVSHA2CL_VV_M8,
8768 : PseudoVSHA2CL_VV_MF2,
8769 : PseudoVSHA2MS_VV_M1,
8770 : PseudoVSHA2MS_VV_M2,
8771 : PseudoVSHA2MS_VV_M4,
8772 : PseudoVSHA2MS_VV_M8,
8773 : PseudoVSHA2MS_VV_MF2,
8774 : PseudoVSLIDE1DOWN_VX_M1,
8775 : PseudoVSLIDE1DOWN_VX_M1_MASK,
8776 : PseudoVSLIDE1DOWN_VX_M2,
8777 : PseudoVSLIDE1DOWN_VX_M2_MASK,
8778 : PseudoVSLIDE1DOWN_VX_M4,
8779 : PseudoVSLIDE1DOWN_VX_M4_MASK,
8780 : PseudoVSLIDE1DOWN_VX_M8,
8781 : PseudoVSLIDE1DOWN_VX_M8_MASK,
8782 : PseudoVSLIDE1DOWN_VX_MF2,
8783 : PseudoVSLIDE1DOWN_VX_MF2_MASK,
8784 : PseudoVSLIDE1DOWN_VX_MF4,
8785 : PseudoVSLIDE1DOWN_VX_MF4_MASK,
8786 : PseudoVSLIDE1DOWN_VX_MF8,
8787 : PseudoVSLIDE1DOWN_VX_MF8_MASK,
8788 : PseudoVSLIDE1UP_VX_M1,
8789 : PseudoVSLIDE1UP_VX_M1_MASK,
8790 : PseudoVSLIDE1UP_VX_M2,
8791 : PseudoVSLIDE1UP_VX_M2_MASK,
8792 : PseudoVSLIDE1UP_VX_M4,
8793 : PseudoVSLIDE1UP_VX_M4_MASK,
8794 : PseudoVSLIDE1UP_VX_M8,
8795 : PseudoVSLIDE1UP_VX_M8_MASK,
8796 : PseudoVSLIDE1UP_VX_MF2,
8797 : PseudoVSLIDE1UP_VX_MF2_MASK,
8798 : PseudoVSLIDE1UP_VX_MF4,
8799 : PseudoVSLIDE1UP_VX_MF4_MASK,
8800 : PseudoVSLIDE1UP_VX_MF8,
8801 : PseudoVSLIDE1UP_VX_MF8_MASK,
8802 : PseudoVSLIDEDOWN_VI_M1,
8803 : PseudoVSLIDEDOWN_VI_M1_MASK,
8804 : PseudoVSLIDEDOWN_VI_M2,
8805 : PseudoVSLIDEDOWN_VI_M2_MASK,
8806 : PseudoVSLIDEDOWN_VI_M4,
8807 : PseudoVSLIDEDOWN_VI_M4_MASK,
8808 : PseudoVSLIDEDOWN_VI_M8,
8809 : PseudoVSLIDEDOWN_VI_M8_MASK,
8810 : PseudoVSLIDEDOWN_VI_MF2,
8811 : PseudoVSLIDEDOWN_VI_MF2_MASK,
8812 : PseudoVSLIDEDOWN_VI_MF4,
8813 : PseudoVSLIDEDOWN_VI_MF4_MASK,
8814 : PseudoVSLIDEDOWN_VI_MF8,
8815 : PseudoVSLIDEDOWN_VI_MF8_MASK,
8816 : PseudoVSLIDEDOWN_VX_M1,
8817 : PseudoVSLIDEDOWN_VX_M1_MASK,
8818 : PseudoVSLIDEDOWN_VX_M2,
8819 : PseudoVSLIDEDOWN_VX_M2_MASK,
8820 : PseudoVSLIDEDOWN_VX_M4,
8821 : PseudoVSLIDEDOWN_VX_M4_MASK,
8822 : PseudoVSLIDEDOWN_VX_M8,
8823 : PseudoVSLIDEDOWN_VX_M8_MASK,
8824 : PseudoVSLIDEDOWN_VX_MF2,
8825 : PseudoVSLIDEDOWN_VX_MF2_MASK,
8826 : PseudoVSLIDEDOWN_VX_MF4,
8827 : PseudoVSLIDEDOWN_VX_MF4_MASK,
8828 : PseudoVSLIDEDOWN_VX_MF8,
8829 : PseudoVSLIDEDOWN_VX_MF8_MASK,
8830 : PseudoVSLIDEUP_VI_M1,
8831 : PseudoVSLIDEUP_VI_M1_MASK,
8832 : PseudoVSLIDEUP_VI_M2,
8833 : PseudoVSLIDEUP_VI_M2_MASK,
8834 : PseudoVSLIDEUP_VI_M4,
8835 : PseudoVSLIDEUP_VI_M4_MASK,
8836 : PseudoVSLIDEUP_VI_M8,
8837 : PseudoVSLIDEUP_VI_M8_MASK,
8838 : PseudoVSLIDEUP_VI_MF2,
8839 : PseudoVSLIDEUP_VI_MF2_MASK,
8840 : PseudoVSLIDEUP_VI_MF4,
8841 : PseudoVSLIDEUP_VI_MF4_MASK,
8842 : PseudoVSLIDEUP_VI_MF8,
8843 : PseudoVSLIDEUP_VI_MF8_MASK,
8844 : PseudoVSLIDEUP_VX_M1,
8845 : PseudoVSLIDEUP_VX_M1_MASK,
8846 : PseudoVSLIDEUP_VX_M2,
8847 : PseudoVSLIDEUP_VX_M2_MASK,
8848 : PseudoVSLIDEUP_VX_M4,
8849 : PseudoVSLIDEUP_VX_M4_MASK,
8850 : PseudoVSLIDEUP_VX_M8,
8851 : PseudoVSLIDEUP_VX_M8_MASK,
8852 : PseudoVSLIDEUP_VX_MF2,
8853 : PseudoVSLIDEUP_VX_MF2_MASK,
8854 : PseudoVSLIDEUP_VX_MF4,
8855 : PseudoVSLIDEUP_VX_MF4_MASK,
8856 : PseudoVSLIDEUP_VX_MF8,
8857 : PseudoVSLIDEUP_VX_MF8_MASK,
8858 : PseudoVSLL_VI_M1,
8859 : PseudoVSLL_VI_M1_MASK,
8860 : PseudoVSLL_VI_M2,
8861 : PseudoVSLL_VI_M2_MASK,
8862 : PseudoVSLL_VI_M4,
8863 : PseudoVSLL_VI_M4_MASK,
8864 : PseudoVSLL_VI_M8,
8865 : PseudoVSLL_VI_M8_MASK,
8866 : PseudoVSLL_VI_MF2,
8867 : PseudoVSLL_VI_MF2_MASK,
8868 : PseudoVSLL_VI_MF4,
8869 : PseudoVSLL_VI_MF4_MASK,
8870 : PseudoVSLL_VI_MF8,
8871 : PseudoVSLL_VI_MF8_MASK,
8872 : PseudoVSLL_VV_M1,
8873 : PseudoVSLL_VV_M1_MASK,
8874 : PseudoVSLL_VV_M2,
8875 : PseudoVSLL_VV_M2_MASK,
8876 : PseudoVSLL_VV_M4,
8877 : PseudoVSLL_VV_M4_MASK,
8878 : PseudoVSLL_VV_M8,
8879 : PseudoVSLL_VV_M8_MASK,
8880 : PseudoVSLL_VV_MF2,
8881 : PseudoVSLL_VV_MF2_MASK,
8882 : PseudoVSLL_VV_MF4,
8883 : PseudoVSLL_VV_MF4_MASK,
8884 : PseudoVSLL_VV_MF8,
8885 : PseudoVSLL_VV_MF8_MASK,
8886 : PseudoVSLL_VX_M1,
8887 : PseudoVSLL_VX_M1_MASK,
8888 : PseudoVSLL_VX_M2,
8889 : PseudoVSLL_VX_M2_MASK,
8890 : PseudoVSLL_VX_M4,
8891 : PseudoVSLL_VX_M4_MASK,
8892 : PseudoVSLL_VX_M8,
8893 : PseudoVSLL_VX_M8_MASK,
8894 : PseudoVSLL_VX_MF2,
8895 : PseudoVSLL_VX_MF2_MASK,
8896 : PseudoVSLL_VX_MF4,
8897 : PseudoVSLL_VX_MF4_MASK,
8898 : PseudoVSLL_VX_MF8,
8899 : PseudoVSLL_VX_MF8_MASK,
8900 : PseudoVSM3C_VI_M1,
8901 : PseudoVSM3C_VI_M2,
8902 : PseudoVSM3C_VI_M4,
8903 : PseudoVSM3C_VI_M8,
8904 : PseudoVSM3C_VI_MF2,
8905 : PseudoVSM3ME_VV_M1,
8906 : PseudoVSM3ME_VV_M2,
8907 : PseudoVSM3ME_VV_M4,
8908 : PseudoVSM3ME_VV_M8,
8909 : PseudoVSM3ME_VV_MF2,
8910 : PseudoVSM4K_VI_M1,
8911 : PseudoVSM4K_VI_M2,
8912 : PseudoVSM4K_VI_M4,
8913 : PseudoVSM4K_VI_M8,
8914 : PseudoVSM4K_VI_MF2,
8915 : PseudoVSM4R_VS_M1_M1,
8916 : PseudoVSM4R_VS_M1_MF2,
8917 : PseudoVSM4R_VS_M1_MF4,
8918 : PseudoVSM4R_VS_M1_MF8,
8919 : PseudoVSM4R_VS_M2_M1,
8920 : PseudoVSM4R_VS_M2_M2,
8921 : PseudoVSM4R_VS_M2_MF2,
8922 : PseudoVSM4R_VS_M2_MF4,
8923 : PseudoVSM4R_VS_M2_MF8,
8924 : PseudoVSM4R_VS_M4_M1,
8925 : PseudoVSM4R_VS_M4_M2,
8926 : PseudoVSM4R_VS_M4_M4,
8927 : PseudoVSM4R_VS_M4_MF2,
8928 : PseudoVSM4R_VS_M4_MF4,
8929 : PseudoVSM4R_VS_M4_MF8,
8930 : PseudoVSM4R_VS_M8_M1,
8931 : PseudoVSM4R_VS_M8_M2,
8932 : PseudoVSM4R_VS_M8_M4,
8933 : PseudoVSM4R_VS_M8_MF2,
8934 : PseudoVSM4R_VS_M8_MF4,
8935 : PseudoVSM4R_VS_M8_MF8,
8936 : PseudoVSM4R_VS_MF2_MF2,
8937 : PseudoVSM4R_VS_MF2_MF4,
8938 : PseudoVSM4R_VS_MF2_MF8,
8939 : PseudoVSM4R_VV_M1,
8940 : PseudoVSM4R_VV_M2,
8941 : PseudoVSM4R_VV_M4,
8942 : PseudoVSM4R_VV_M8,
8943 : PseudoVSM4R_VV_MF2,
8944 : PseudoVSMUL_VV_M1,
8945 : PseudoVSMUL_VV_M1_MASK,
8946 : PseudoVSMUL_VV_M2,
8947 : PseudoVSMUL_VV_M2_MASK,
8948 : PseudoVSMUL_VV_M4,
8949 : PseudoVSMUL_VV_M4_MASK,
8950 : PseudoVSMUL_VV_M8,
8951 : PseudoVSMUL_VV_M8_MASK,
8952 : PseudoVSMUL_VV_MF2,
8953 : PseudoVSMUL_VV_MF2_MASK,
8954 : PseudoVSMUL_VV_MF4,
8955 : PseudoVSMUL_VV_MF4_MASK,
8956 : PseudoVSMUL_VV_MF8,
8957 : PseudoVSMUL_VV_MF8_MASK,
8958 : PseudoVSMUL_VX_M1,
8959 : PseudoVSMUL_VX_M1_MASK,
8960 : PseudoVSMUL_VX_M2,
8961 : PseudoVSMUL_VX_M2_MASK,
8962 : PseudoVSMUL_VX_M4,
8963 : PseudoVSMUL_VX_M4_MASK,
8964 : PseudoVSMUL_VX_M8,
8965 : PseudoVSMUL_VX_M8_MASK,
8966 : PseudoVSMUL_VX_MF2,
8967 : PseudoVSMUL_VX_MF2_MASK,
8968 : PseudoVSMUL_VX_MF4,
8969 : PseudoVSMUL_VX_MF4_MASK,
8970 : PseudoVSMUL_VX_MF8,
8971 : PseudoVSMUL_VX_MF8_MASK,
8972 : PseudoVSM_V_B1,
8973 : PseudoVSM_V_B16,
8974 : PseudoVSM_V_B2,
8975 : PseudoVSM_V_B32,
8976 : PseudoVSM_V_B4,
8977 : PseudoVSM_V_B64,
8978 : PseudoVSM_V_B8,
8979 : PseudoVSOXEI16_V_M1_M1,
8980 : PseudoVSOXEI16_V_M1_M1_MASK,
8981 : PseudoVSOXEI16_V_M1_M2,
8982 : PseudoVSOXEI16_V_M1_M2_MASK,
8983 : PseudoVSOXEI16_V_M1_M4,
8984 : PseudoVSOXEI16_V_M1_M4_MASK,
8985 : PseudoVSOXEI16_V_M1_MF2,
8986 : PseudoVSOXEI16_V_M1_MF2_MASK,
8987 : PseudoVSOXEI16_V_M2_M1,
8988 : PseudoVSOXEI16_V_M2_M1_MASK,
8989 : PseudoVSOXEI16_V_M2_M2,
8990 : PseudoVSOXEI16_V_M2_M2_MASK,
8991 : PseudoVSOXEI16_V_M2_M4,
8992 : PseudoVSOXEI16_V_M2_M4_MASK,
8993 : PseudoVSOXEI16_V_M2_M8,
8994 : PseudoVSOXEI16_V_M2_M8_MASK,
8995 : PseudoVSOXEI16_V_M4_M2,
8996 : PseudoVSOXEI16_V_M4_M2_MASK,
8997 : PseudoVSOXEI16_V_M4_M4,
8998 : PseudoVSOXEI16_V_M4_M4_MASK,
8999 : PseudoVSOXEI16_V_M4_M8,
9000 : PseudoVSOXEI16_V_M4_M8_MASK,
9001 : PseudoVSOXEI16_V_M8_M4,
9002 : PseudoVSOXEI16_V_M8_M4_MASK,
9003 : PseudoVSOXEI16_V_M8_M8,
9004 : PseudoVSOXEI16_V_M8_M8_MASK,
9005 : PseudoVSOXEI16_V_MF2_M1,
9006 : PseudoVSOXEI16_V_MF2_M1_MASK,
9007 : PseudoVSOXEI16_V_MF2_M2,
9008 : PseudoVSOXEI16_V_MF2_M2_MASK,
9009 : PseudoVSOXEI16_V_MF2_MF2,
9010 : PseudoVSOXEI16_V_MF2_MF2_MASK,
9011 : PseudoVSOXEI16_V_MF2_MF4,
9012 : PseudoVSOXEI16_V_MF2_MF4_MASK,
9013 : PseudoVSOXEI16_V_MF4_M1,
9014 : PseudoVSOXEI16_V_MF4_M1_MASK,
9015 : PseudoVSOXEI16_V_MF4_MF2,
9016 : PseudoVSOXEI16_V_MF4_MF2_MASK,
9017 : PseudoVSOXEI16_V_MF4_MF4,
9018 : PseudoVSOXEI16_V_MF4_MF4_MASK,
9019 : PseudoVSOXEI16_V_MF4_MF8,
9020 : PseudoVSOXEI16_V_MF4_MF8_MASK,
9021 : PseudoVSOXEI32_V_M1_M1,
9022 : PseudoVSOXEI32_V_M1_M1_MASK,
9023 : PseudoVSOXEI32_V_M1_M2,
9024 : PseudoVSOXEI32_V_M1_M2_MASK,
9025 : PseudoVSOXEI32_V_M1_MF2,
9026 : PseudoVSOXEI32_V_M1_MF2_MASK,
9027 : PseudoVSOXEI32_V_M1_MF4,
9028 : PseudoVSOXEI32_V_M1_MF4_MASK,
9029 : PseudoVSOXEI32_V_M2_M1,
9030 : PseudoVSOXEI32_V_M2_M1_MASK,
9031 : PseudoVSOXEI32_V_M2_M2,
9032 : PseudoVSOXEI32_V_M2_M2_MASK,
9033 : PseudoVSOXEI32_V_M2_M4,
9034 : PseudoVSOXEI32_V_M2_M4_MASK,
9035 : PseudoVSOXEI32_V_M2_MF2,
9036 : PseudoVSOXEI32_V_M2_MF2_MASK,
9037 : PseudoVSOXEI32_V_M4_M1,
9038 : PseudoVSOXEI32_V_M4_M1_MASK,
9039 : PseudoVSOXEI32_V_M4_M2,
9040 : PseudoVSOXEI32_V_M4_M2_MASK,
9041 : PseudoVSOXEI32_V_M4_M4,
9042 : PseudoVSOXEI32_V_M4_M4_MASK,
9043 : PseudoVSOXEI32_V_M4_M8,
9044 : PseudoVSOXEI32_V_M4_M8_MASK,
9045 : PseudoVSOXEI32_V_M8_M2,
9046 : PseudoVSOXEI32_V_M8_M2_MASK,
9047 : PseudoVSOXEI32_V_M8_M4,
9048 : PseudoVSOXEI32_V_M8_M4_MASK,
9049 : PseudoVSOXEI32_V_M8_M8,
9050 : PseudoVSOXEI32_V_M8_M8_MASK,
9051 : PseudoVSOXEI32_V_MF2_M1,
9052 : PseudoVSOXEI32_V_MF2_M1_MASK,
9053 : PseudoVSOXEI32_V_MF2_MF2,
9054 : PseudoVSOXEI32_V_MF2_MF2_MASK,
9055 : PseudoVSOXEI32_V_MF2_MF4,
9056 : PseudoVSOXEI32_V_MF2_MF4_MASK,
9057 : PseudoVSOXEI32_V_MF2_MF8,
9058 : PseudoVSOXEI32_V_MF2_MF8_MASK,
9059 : PseudoVSOXEI64_V_M1_M1,
9060 : PseudoVSOXEI64_V_M1_M1_MASK,
9061 : PseudoVSOXEI64_V_M1_MF2,
9062 : PseudoVSOXEI64_V_M1_MF2_MASK,
9063 : PseudoVSOXEI64_V_M1_MF4,
9064 : PseudoVSOXEI64_V_M1_MF4_MASK,
9065 : PseudoVSOXEI64_V_M1_MF8,
9066 : PseudoVSOXEI64_V_M1_MF8_MASK,
9067 : PseudoVSOXEI64_V_M2_M1,
9068 : PseudoVSOXEI64_V_M2_M1_MASK,
9069 : PseudoVSOXEI64_V_M2_M2,
9070 : PseudoVSOXEI64_V_M2_M2_MASK,
9071 : PseudoVSOXEI64_V_M2_MF2,
9072 : PseudoVSOXEI64_V_M2_MF2_MASK,
9073 : PseudoVSOXEI64_V_M2_MF4,
9074 : PseudoVSOXEI64_V_M2_MF4_MASK,
9075 : PseudoVSOXEI64_V_M4_M1,
9076 : PseudoVSOXEI64_V_M4_M1_MASK,
9077 : PseudoVSOXEI64_V_M4_M2,
9078 : PseudoVSOXEI64_V_M4_M2_MASK,
9079 : PseudoVSOXEI64_V_M4_M4,
9080 : PseudoVSOXEI64_V_M4_M4_MASK,
9081 : PseudoVSOXEI64_V_M4_MF2,
9082 : PseudoVSOXEI64_V_M4_MF2_MASK,
9083 : PseudoVSOXEI64_V_M8_M1,
9084 : PseudoVSOXEI64_V_M8_M1_MASK,
9085 : PseudoVSOXEI64_V_M8_M2,
9086 : PseudoVSOXEI64_V_M8_M2_MASK,
9087 : PseudoVSOXEI64_V_M8_M4,
9088 : PseudoVSOXEI64_V_M8_M4_MASK,
9089 : PseudoVSOXEI64_V_M8_M8,
9090 : PseudoVSOXEI64_V_M8_M8_MASK,
9091 : PseudoVSOXEI8_V_M1_M1,
9092 : PseudoVSOXEI8_V_M1_M1_MASK,
9093 : PseudoVSOXEI8_V_M1_M2,
9094 : PseudoVSOXEI8_V_M1_M2_MASK,
9095 : PseudoVSOXEI8_V_M1_M4,
9096 : PseudoVSOXEI8_V_M1_M4_MASK,
9097 : PseudoVSOXEI8_V_M1_M8,
9098 : PseudoVSOXEI8_V_M1_M8_MASK,
9099 : PseudoVSOXEI8_V_M2_M2,
9100 : PseudoVSOXEI8_V_M2_M2_MASK,
9101 : PseudoVSOXEI8_V_M2_M4,
9102 : PseudoVSOXEI8_V_M2_M4_MASK,
9103 : PseudoVSOXEI8_V_M2_M8,
9104 : PseudoVSOXEI8_V_M2_M8_MASK,
9105 : PseudoVSOXEI8_V_M4_M4,
9106 : PseudoVSOXEI8_V_M4_M4_MASK,
9107 : PseudoVSOXEI8_V_M4_M8,
9108 : PseudoVSOXEI8_V_M4_M8_MASK,
9109 : PseudoVSOXEI8_V_M8_M8,
9110 : PseudoVSOXEI8_V_M8_M8_MASK,
9111 : PseudoVSOXEI8_V_MF2_M1,
9112 : PseudoVSOXEI8_V_MF2_M1_MASK,
9113 : PseudoVSOXEI8_V_MF2_M2,
9114 : PseudoVSOXEI8_V_MF2_M2_MASK,
9115 : PseudoVSOXEI8_V_MF2_M4,
9116 : PseudoVSOXEI8_V_MF2_M4_MASK,
9117 : PseudoVSOXEI8_V_MF2_MF2,
9118 : PseudoVSOXEI8_V_MF2_MF2_MASK,
9119 : PseudoVSOXEI8_V_MF4_M1,
9120 : PseudoVSOXEI8_V_MF4_M1_MASK,
9121 : PseudoVSOXEI8_V_MF4_M2,
9122 : PseudoVSOXEI8_V_MF4_M2_MASK,
9123 : PseudoVSOXEI8_V_MF4_MF2,
9124 : PseudoVSOXEI8_V_MF4_MF2_MASK,
9125 : PseudoVSOXEI8_V_MF4_MF4,
9126 : PseudoVSOXEI8_V_MF4_MF4_MASK,
9127 : PseudoVSOXEI8_V_MF8_M1,
9128 : PseudoVSOXEI8_V_MF8_M1_MASK,
9129 : PseudoVSOXEI8_V_MF8_MF2,
9130 : PseudoVSOXEI8_V_MF8_MF2_MASK,
9131 : PseudoVSOXEI8_V_MF8_MF4,
9132 : PseudoVSOXEI8_V_MF8_MF4_MASK,
9133 : PseudoVSOXEI8_V_MF8_MF8,
9134 : PseudoVSOXEI8_V_MF8_MF8_MASK,
9135 : PseudoVSOXSEG2EI16_V_M1_M1,
9136 : PseudoVSOXSEG2EI16_V_M1_M1_MASK,
9137 : PseudoVSOXSEG2EI16_V_M1_M2,
9138 : PseudoVSOXSEG2EI16_V_M1_M2_MASK,
9139 : PseudoVSOXSEG2EI16_V_M1_M4,
9140 : PseudoVSOXSEG2EI16_V_M1_M4_MASK,
9141 : PseudoVSOXSEG2EI16_V_M1_MF2,
9142 : PseudoVSOXSEG2EI16_V_M1_MF2_MASK,
9143 : PseudoVSOXSEG2EI16_V_M2_M1,
9144 : PseudoVSOXSEG2EI16_V_M2_M1_MASK,
9145 : PseudoVSOXSEG2EI16_V_M2_M2,
9146 : PseudoVSOXSEG2EI16_V_M2_M2_MASK,
9147 : PseudoVSOXSEG2EI16_V_M2_M4,
9148 : PseudoVSOXSEG2EI16_V_M2_M4_MASK,
9149 : PseudoVSOXSEG2EI16_V_M4_M2,
9150 : PseudoVSOXSEG2EI16_V_M4_M2_MASK,
9151 : PseudoVSOXSEG2EI16_V_M4_M4,
9152 : PseudoVSOXSEG2EI16_V_M4_M4_MASK,
9153 : PseudoVSOXSEG2EI16_V_M8_M4,
9154 : PseudoVSOXSEG2EI16_V_M8_M4_MASK,
9155 : PseudoVSOXSEG2EI16_V_MF2_M1,
9156 : PseudoVSOXSEG2EI16_V_MF2_M1_MASK,
9157 : PseudoVSOXSEG2EI16_V_MF2_M2,
9158 : PseudoVSOXSEG2EI16_V_MF2_M2_MASK,
9159 : PseudoVSOXSEG2EI16_V_MF2_MF2,
9160 : PseudoVSOXSEG2EI16_V_MF2_MF2_MASK,
9161 : PseudoVSOXSEG2EI16_V_MF2_MF4,
9162 : PseudoVSOXSEG2EI16_V_MF2_MF4_MASK,
9163 : PseudoVSOXSEG2EI16_V_MF4_M1,
9164 : PseudoVSOXSEG2EI16_V_MF4_M1_MASK,
9165 : PseudoVSOXSEG2EI16_V_MF4_MF2,
9166 : PseudoVSOXSEG2EI16_V_MF4_MF2_MASK,
9167 : PseudoVSOXSEG2EI16_V_MF4_MF4,
9168 : PseudoVSOXSEG2EI16_V_MF4_MF4_MASK,
9169 : PseudoVSOXSEG2EI16_V_MF4_MF8,
9170 : PseudoVSOXSEG2EI16_V_MF4_MF8_MASK,
9171 : PseudoVSOXSEG2EI32_V_M1_M1,
9172 : PseudoVSOXSEG2EI32_V_M1_M1_MASK,
9173 : PseudoVSOXSEG2EI32_V_M1_M2,
9174 : PseudoVSOXSEG2EI32_V_M1_M2_MASK,
9175 : PseudoVSOXSEG2EI32_V_M1_MF2,
9176 : PseudoVSOXSEG2EI32_V_M1_MF2_MASK,
9177 : PseudoVSOXSEG2EI32_V_M1_MF4,
9178 : PseudoVSOXSEG2EI32_V_M1_MF4_MASK,
9179 : PseudoVSOXSEG2EI32_V_M2_M1,
9180 : PseudoVSOXSEG2EI32_V_M2_M1_MASK,
9181 : PseudoVSOXSEG2EI32_V_M2_M2,
9182 : PseudoVSOXSEG2EI32_V_M2_M2_MASK,
9183 : PseudoVSOXSEG2EI32_V_M2_M4,
9184 : PseudoVSOXSEG2EI32_V_M2_M4_MASK,
9185 : PseudoVSOXSEG2EI32_V_M2_MF2,
9186 : PseudoVSOXSEG2EI32_V_M2_MF2_MASK,
9187 : PseudoVSOXSEG2EI32_V_M4_M1,
9188 : PseudoVSOXSEG2EI32_V_M4_M1_MASK,
9189 : PseudoVSOXSEG2EI32_V_M4_M2,
9190 : PseudoVSOXSEG2EI32_V_M4_M2_MASK,
9191 : PseudoVSOXSEG2EI32_V_M4_M4,
9192 : PseudoVSOXSEG2EI32_V_M4_M4_MASK,
9193 : PseudoVSOXSEG2EI32_V_M8_M2,
9194 : PseudoVSOXSEG2EI32_V_M8_M2_MASK,
9195 : PseudoVSOXSEG2EI32_V_M8_M4,
9196 : PseudoVSOXSEG2EI32_V_M8_M4_MASK,
9197 : PseudoVSOXSEG2EI32_V_MF2_M1,
9198 : PseudoVSOXSEG2EI32_V_MF2_M1_MASK,
9199 : PseudoVSOXSEG2EI32_V_MF2_MF2,
9200 : PseudoVSOXSEG2EI32_V_MF2_MF2_MASK,
9201 : PseudoVSOXSEG2EI32_V_MF2_MF4,
9202 : PseudoVSOXSEG2EI32_V_MF2_MF4_MASK,
9203 : PseudoVSOXSEG2EI32_V_MF2_MF8,
9204 : PseudoVSOXSEG2EI32_V_MF2_MF8_MASK,
9205 : PseudoVSOXSEG2EI64_V_M1_M1,
9206 : PseudoVSOXSEG2EI64_V_M1_M1_MASK,
9207 : PseudoVSOXSEG2EI64_V_M1_MF2,
9208 : PseudoVSOXSEG2EI64_V_M1_MF2_MASK,
9209 : PseudoVSOXSEG2EI64_V_M1_MF4,
9210 : PseudoVSOXSEG2EI64_V_M1_MF4_MASK,
9211 : PseudoVSOXSEG2EI64_V_M1_MF8,
9212 : PseudoVSOXSEG2EI64_V_M1_MF8_MASK,
9213 : PseudoVSOXSEG2EI64_V_M2_M1,
9214 : PseudoVSOXSEG2EI64_V_M2_M1_MASK,
9215 : PseudoVSOXSEG2EI64_V_M2_M2,
9216 : PseudoVSOXSEG2EI64_V_M2_M2_MASK,
9217 : PseudoVSOXSEG2EI64_V_M2_MF2,
9218 : PseudoVSOXSEG2EI64_V_M2_MF2_MASK,
9219 : PseudoVSOXSEG2EI64_V_M2_MF4,
9220 : PseudoVSOXSEG2EI64_V_M2_MF4_MASK,
9221 : PseudoVSOXSEG2EI64_V_M4_M1,
9222 : PseudoVSOXSEG2EI64_V_M4_M1_MASK,
9223 : PseudoVSOXSEG2EI64_V_M4_M2,
9224 : PseudoVSOXSEG2EI64_V_M4_M2_MASK,
9225 : PseudoVSOXSEG2EI64_V_M4_M4,
9226 : PseudoVSOXSEG2EI64_V_M4_M4_MASK,
9227 : PseudoVSOXSEG2EI64_V_M4_MF2,
9228 : PseudoVSOXSEG2EI64_V_M4_MF2_MASK,
9229 : PseudoVSOXSEG2EI64_V_M8_M1,
9230 : PseudoVSOXSEG2EI64_V_M8_M1_MASK,
9231 : PseudoVSOXSEG2EI64_V_M8_M2,
9232 : PseudoVSOXSEG2EI64_V_M8_M2_MASK,
9233 : PseudoVSOXSEG2EI64_V_M8_M4,
9234 : PseudoVSOXSEG2EI64_V_M8_M4_MASK,
9235 : PseudoVSOXSEG2EI8_V_M1_M1,
9236 : PseudoVSOXSEG2EI8_V_M1_M1_MASK,
9237 : PseudoVSOXSEG2EI8_V_M1_M2,
9238 : PseudoVSOXSEG2EI8_V_M1_M2_MASK,
9239 : PseudoVSOXSEG2EI8_V_M1_M4,
9240 : PseudoVSOXSEG2EI8_V_M1_M4_MASK,
9241 : PseudoVSOXSEG2EI8_V_M2_M2,
9242 : PseudoVSOXSEG2EI8_V_M2_M2_MASK,
9243 : PseudoVSOXSEG2EI8_V_M2_M4,
9244 : PseudoVSOXSEG2EI8_V_M2_M4_MASK,
9245 : PseudoVSOXSEG2EI8_V_M4_M4,
9246 : PseudoVSOXSEG2EI8_V_M4_M4_MASK,
9247 : PseudoVSOXSEG2EI8_V_MF2_M1,
9248 : PseudoVSOXSEG2EI8_V_MF2_M1_MASK,
9249 : PseudoVSOXSEG2EI8_V_MF2_M2,
9250 : PseudoVSOXSEG2EI8_V_MF2_M2_MASK,
9251 : PseudoVSOXSEG2EI8_V_MF2_M4,
9252 : PseudoVSOXSEG2EI8_V_MF2_M4_MASK,
9253 : PseudoVSOXSEG2EI8_V_MF2_MF2,
9254 : PseudoVSOXSEG2EI8_V_MF2_MF2_MASK,
9255 : PseudoVSOXSEG2EI8_V_MF4_M1,
9256 : PseudoVSOXSEG2EI8_V_MF4_M1_MASK,
9257 : PseudoVSOXSEG2EI8_V_MF4_M2,
9258 : PseudoVSOXSEG2EI8_V_MF4_M2_MASK,
9259 : PseudoVSOXSEG2EI8_V_MF4_MF2,
9260 : PseudoVSOXSEG2EI8_V_MF4_MF2_MASK,
9261 : PseudoVSOXSEG2EI8_V_MF4_MF4,
9262 : PseudoVSOXSEG2EI8_V_MF4_MF4_MASK,
9263 : PseudoVSOXSEG2EI8_V_MF8_M1,
9264 : PseudoVSOXSEG2EI8_V_MF8_M1_MASK,
9265 : PseudoVSOXSEG2EI8_V_MF8_MF2,
9266 : PseudoVSOXSEG2EI8_V_MF8_MF2_MASK,
9267 : PseudoVSOXSEG2EI8_V_MF8_MF4,
9268 : PseudoVSOXSEG2EI8_V_MF8_MF4_MASK,
9269 : PseudoVSOXSEG2EI8_V_MF8_MF8,
9270 : PseudoVSOXSEG2EI8_V_MF8_MF8_MASK,
9271 : PseudoVSOXSEG3EI16_V_M1_M1,
9272 : PseudoVSOXSEG3EI16_V_M1_M1_MASK,
9273 : PseudoVSOXSEG3EI16_V_M1_M2,
9274 : PseudoVSOXSEG3EI16_V_M1_M2_MASK,
9275 : PseudoVSOXSEG3EI16_V_M1_MF2,
9276 : PseudoVSOXSEG3EI16_V_M1_MF2_MASK,
9277 : PseudoVSOXSEG3EI16_V_M2_M1,
9278 : PseudoVSOXSEG3EI16_V_M2_M1_MASK,
9279 : PseudoVSOXSEG3EI16_V_M2_M2,
9280 : PseudoVSOXSEG3EI16_V_M2_M2_MASK,
9281 : PseudoVSOXSEG3EI16_V_M4_M2,
9282 : PseudoVSOXSEG3EI16_V_M4_M2_MASK,
9283 : PseudoVSOXSEG3EI16_V_MF2_M1,
9284 : PseudoVSOXSEG3EI16_V_MF2_M1_MASK,
9285 : PseudoVSOXSEG3EI16_V_MF2_M2,
9286 : PseudoVSOXSEG3EI16_V_MF2_M2_MASK,
9287 : PseudoVSOXSEG3EI16_V_MF2_MF2,
9288 : PseudoVSOXSEG3EI16_V_MF2_MF2_MASK,
9289 : PseudoVSOXSEG3EI16_V_MF2_MF4,
9290 : PseudoVSOXSEG3EI16_V_MF2_MF4_MASK,
9291 : PseudoVSOXSEG3EI16_V_MF4_M1,
9292 : PseudoVSOXSEG3EI16_V_MF4_M1_MASK,
9293 : PseudoVSOXSEG3EI16_V_MF4_MF2,
9294 : PseudoVSOXSEG3EI16_V_MF4_MF2_MASK,
9295 : PseudoVSOXSEG3EI16_V_MF4_MF4,
9296 : PseudoVSOXSEG3EI16_V_MF4_MF4_MASK,
9297 : PseudoVSOXSEG3EI16_V_MF4_MF8,
9298 : PseudoVSOXSEG3EI16_V_MF4_MF8_MASK,
9299 : PseudoVSOXSEG3EI32_V_M1_M1,
9300 : PseudoVSOXSEG3EI32_V_M1_M1_MASK,
9301 : PseudoVSOXSEG3EI32_V_M1_M2,
9302 : PseudoVSOXSEG3EI32_V_M1_M2_MASK,
9303 : PseudoVSOXSEG3EI32_V_M1_MF2,
9304 : PseudoVSOXSEG3EI32_V_M1_MF2_MASK,
9305 : PseudoVSOXSEG3EI32_V_M1_MF4,
9306 : PseudoVSOXSEG3EI32_V_M1_MF4_MASK,
9307 : PseudoVSOXSEG3EI32_V_M2_M1,
9308 : PseudoVSOXSEG3EI32_V_M2_M1_MASK,
9309 : PseudoVSOXSEG3EI32_V_M2_M2,
9310 : PseudoVSOXSEG3EI32_V_M2_M2_MASK,
9311 : PseudoVSOXSEG3EI32_V_M2_MF2,
9312 : PseudoVSOXSEG3EI32_V_M2_MF2_MASK,
9313 : PseudoVSOXSEG3EI32_V_M4_M1,
9314 : PseudoVSOXSEG3EI32_V_M4_M1_MASK,
9315 : PseudoVSOXSEG3EI32_V_M4_M2,
9316 : PseudoVSOXSEG3EI32_V_M4_M2_MASK,
9317 : PseudoVSOXSEG3EI32_V_M8_M2,
9318 : PseudoVSOXSEG3EI32_V_M8_M2_MASK,
9319 : PseudoVSOXSEG3EI32_V_MF2_M1,
9320 : PseudoVSOXSEG3EI32_V_MF2_M1_MASK,
9321 : PseudoVSOXSEG3EI32_V_MF2_MF2,
9322 : PseudoVSOXSEG3EI32_V_MF2_MF2_MASK,
9323 : PseudoVSOXSEG3EI32_V_MF2_MF4,
9324 : PseudoVSOXSEG3EI32_V_MF2_MF4_MASK,
9325 : PseudoVSOXSEG3EI32_V_MF2_MF8,
9326 : PseudoVSOXSEG3EI32_V_MF2_MF8_MASK,
9327 : PseudoVSOXSEG3EI64_V_M1_M1,
9328 : PseudoVSOXSEG3EI64_V_M1_M1_MASK,
9329 : PseudoVSOXSEG3EI64_V_M1_MF2,
9330 : PseudoVSOXSEG3EI64_V_M1_MF2_MASK,
9331 : PseudoVSOXSEG3EI64_V_M1_MF4,
9332 : PseudoVSOXSEG3EI64_V_M1_MF4_MASK,
9333 : PseudoVSOXSEG3EI64_V_M1_MF8,
9334 : PseudoVSOXSEG3EI64_V_M1_MF8_MASK,
9335 : PseudoVSOXSEG3EI64_V_M2_M1,
9336 : PseudoVSOXSEG3EI64_V_M2_M1_MASK,
9337 : PseudoVSOXSEG3EI64_V_M2_M2,
9338 : PseudoVSOXSEG3EI64_V_M2_M2_MASK,
9339 : PseudoVSOXSEG3EI64_V_M2_MF2,
9340 : PseudoVSOXSEG3EI64_V_M2_MF2_MASK,
9341 : PseudoVSOXSEG3EI64_V_M2_MF4,
9342 : PseudoVSOXSEG3EI64_V_M2_MF4_MASK,
9343 : PseudoVSOXSEG3EI64_V_M4_M1,
9344 : PseudoVSOXSEG3EI64_V_M4_M1_MASK,
9345 : PseudoVSOXSEG3EI64_V_M4_M2,
9346 : PseudoVSOXSEG3EI64_V_M4_M2_MASK,
9347 : PseudoVSOXSEG3EI64_V_M4_MF2,
9348 : PseudoVSOXSEG3EI64_V_M4_MF2_MASK,
9349 : PseudoVSOXSEG3EI64_V_M8_M1,
9350 : PseudoVSOXSEG3EI64_V_M8_M1_MASK,
9351 : PseudoVSOXSEG3EI64_V_M8_M2,
9352 : PseudoVSOXSEG3EI64_V_M8_M2_MASK,
9353 : PseudoVSOXSEG3EI8_V_M1_M1,
9354 : PseudoVSOXSEG3EI8_V_M1_M1_MASK,
9355 : PseudoVSOXSEG3EI8_V_M1_M2,
9356 : PseudoVSOXSEG3EI8_V_M1_M2_MASK,
9357 : PseudoVSOXSEG3EI8_V_M2_M2,
9358 : PseudoVSOXSEG3EI8_V_M2_M2_MASK,
9359 : PseudoVSOXSEG3EI8_V_MF2_M1,
9360 : PseudoVSOXSEG3EI8_V_MF2_M1_MASK,
9361 : PseudoVSOXSEG3EI8_V_MF2_M2,
9362 : PseudoVSOXSEG3EI8_V_MF2_M2_MASK,
9363 : PseudoVSOXSEG3EI8_V_MF2_MF2,
9364 : PseudoVSOXSEG3EI8_V_MF2_MF2_MASK,
9365 : PseudoVSOXSEG3EI8_V_MF4_M1,
9366 : PseudoVSOXSEG3EI8_V_MF4_M1_MASK,
9367 : PseudoVSOXSEG3EI8_V_MF4_M2,
9368 : PseudoVSOXSEG3EI8_V_MF4_M2_MASK,
9369 : PseudoVSOXSEG3EI8_V_MF4_MF2,
9370 : PseudoVSOXSEG3EI8_V_MF4_MF2_MASK,
9371 : PseudoVSOXSEG3EI8_V_MF4_MF4,
9372 : PseudoVSOXSEG3EI8_V_MF4_MF4_MASK,
9373 : PseudoVSOXSEG3EI8_V_MF8_M1,
9374 : PseudoVSOXSEG3EI8_V_MF8_M1_MASK,
9375 : PseudoVSOXSEG3EI8_V_MF8_MF2,
9376 : PseudoVSOXSEG3EI8_V_MF8_MF2_MASK,
9377 : PseudoVSOXSEG3EI8_V_MF8_MF4,
9378 : PseudoVSOXSEG3EI8_V_MF8_MF4_MASK,
9379 : PseudoVSOXSEG3EI8_V_MF8_MF8,
9380 : PseudoVSOXSEG3EI8_V_MF8_MF8_MASK,
9381 : PseudoVSOXSEG4EI16_V_M1_M1,
9382 : PseudoVSOXSEG4EI16_V_M1_M1_MASK,
9383 : PseudoVSOXSEG4EI16_V_M1_M2,
9384 : PseudoVSOXSEG4EI16_V_M1_M2_MASK,
9385 : PseudoVSOXSEG4EI16_V_M1_MF2,
9386 : PseudoVSOXSEG4EI16_V_M1_MF2_MASK,
9387 : PseudoVSOXSEG4EI16_V_M2_M1,
9388 : PseudoVSOXSEG4EI16_V_M2_M1_MASK,
9389 : PseudoVSOXSEG4EI16_V_M2_M2,
9390 : PseudoVSOXSEG4EI16_V_M2_M2_MASK,
9391 : PseudoVSOXSEG4EI16_V_M4_M2,
9392 : PseudoVSOXSEG4EI16_V_M4_M2_MASK,
9393 : PseudoVSOXSEG4EI16_V_MF2_M1,
9394 : PseudoVSOXSEG4EI16_V_MF2_M1_MASK,
9395 : PseudoVSOXSEG4EI16_V_MF2_M2,
9396 : PseudoVSOXSEG4EI16_V_MF2_M2_MASK,
9397 : PseudoVSOXSEG4EI16_V_MF2_MF2,
9398 : PseudoVSOXSEG4EI16_V_MF2_MF2_MASK,
9399 : PseudoVSOXSEG4EI16_V_MF2_MF4,
9400 : PseudoVSOXSEG4EI16_V_MF2_MF4_MASK,
9401 : PseudoVSOXSEG4EI16_V_MF4_M1,
9402 : PseudoVSOXSEG4EI16_V_MF4_M1_MASK,
9403 : PseudoVSOXSEG4EI16_V_MF4_MF2,
9404 : PseudoVSOXSEG4EI16_V_MF4_MF2_MASK,
9405 : PseudoVSOXSEG4EI16_V_MF4_MF4,
9406 : PseudoVSOXSEG4EI16_V_MF4_MF4_MASK,
9407 : PseudoVSOXSEG4EI16_V_MF4_MF8,
9408 : PseudoVSOXSEG4EI16_V_MF4_MF8_MASK,
9409 : PseudoVSOXSEG4EI32_V_M1_M1,
9410 : PseudoVSOXSEG4EI32_V_M1_M1_MASK,
9411 : PseudoVSOXSEG4EI32_V_M1_M2,
9412 : PseudoVSOXSEG4EI32_V_M1_M2_MASK,
9413 : PseudoVSOXSEG4EI32_V_M1_MF2,
9414 : PseudoVSOXSEG4EI32_V_M1_MF2_MASK,
9415 : PseudoVSOXSEG4EI32_V_M1_MF4,
9416 : PseudoVSOXSEG4EI32_V_M1_MF4_MASK,
9417 : PseudoVSOXSEG4EI32_V_M2_M1,
9418 : PseudoVSOXSEG4EI32_V_M2_M1_MASK,
9419 : PseudoVSOXSEG4EI32_V_M2_M2,
9420 : PseudoVSOXSEG4EI32_V_M2_M2_MASK,
9421 : PseudoVSOXSEG4EI32_V_M2_MF2,
9422 : PseudoVSOXSEG4EI32_V_M2_MF2_MASK,
9423 : PseudoVSOXSEG4EI32_V_M4_M1,
9424 : PseudoVSOXSEG4EI32_V_M4_M1_MASK,
9425 : PseudoVSOXSEG4EI32_V_M4_M2,
9426 : PseudoVSOXSEG4EI32_V_M4_M2_MASK,
9427 : PseudoVSOXSEG4EI32_V_M8_M2,
9428 : PseudoVSOXSEG4EI32_V_M8_M2_MASK,
9429 : PseudoVSOXSEG4EI32_V_MF2_M1,
9430 : PseudoVSOXSEG4EI32_V_MF2_M1_MASK,
9431 : PseudoVSOXSEG4EI32_V_MF2_MF2,
9432 : PseudoVSOXSEG4EI32_V_MF2_MF2_MASK,
9433 : PseudoVSOXSEG4EI32_V_MF2_MF4,
9434 : PseudoVSOXSEG4EI32_V_MF2_MF4_MASK,
9435 : PseudoVSOXSEG4EI32_V_MF2_MF8,
9436 : PseudoVSOXSEG4EI32_V_MF2_MF8_MASK,
9437 : PseudoVSOXSEG4EI64_V_M1_M1,
9438 : PseudoVSOXSEG4EI64_V_M1_M1_MASK,
9439 : PseudoVSOXSEG4EI64_V_M1_MF2,
9440 : PseudoVSOXSEG4EI64_V_M1_MF2_MASK,
9441 : PseudoVSOXSEG4EI64_V_M1_MF4,
9442 : PseudoVSOXSEG4EI64_V_M1_MF4_MASK,
9443 : PseudoVSOXSEG4EI64_V_M1_MF8,
9444 : PseudoVSOXSEG4EI64_V_M1_MF8_MASK,
9445 : PseudoVSOXSEG4EI64_V_M2_M1,
9446 : PseudoVSOXSEG4EI64_V_M2_M1_MASK,
9447 : PseudoVSOXSEG4EI64_V_M2_M2,
9448 : PseudoVSOXSEG4EI64_V_M2_M2_MASK,
9449 : PseudoVSOXSEG4EI64_V_M2_MF2,
9450 : PseudoVSOXSEG4EI64_V_M2_MF2_MASK,
9451 : PseudoVSOXSEG4EI64_V_M2_MF4,
9452 : PseudoVSOXSEG4EI64_V_M2_MF4_MASK,
9453 : PseudoVSOXSEG4EI64_V_M4_M1,
9454 : PseudoVSOXSEG4EI64_V_M4_M1_MASK,
9455 : PseudoVSOXSEG4EI64_V_M4_M2,
9456 : PseudoVSOXSEG4EI64_V_M4_M2_MASK,
9457 : PseudoVSOXSEG4EI64_V_M4_MF2,
9458 : PseudoVSOXSEG4EI64_V_M4_MF2_MASK,
9459 : PseudoVSOXSEG4EI64_V_M8_M1,
9460 : PseudoVSOXSEG4EI64_V_M8_M1_MASK,
9461 : PseudoVSOXSEG4EI64_V_M8_M2,
9462 : PseudoVSOXSEG4EI64_V_M8_M2_MASK,
9463 : PseudoVSOXSEG4EI8_V_M1_M1,
9464 : PseudoVSOXSEG4EI8_V_M1_M1_MASK,
9465 : PseudoVSOXSEG4EI8_V_M1_M2,
9466 : PseudoVSOXSEG4EI8_V_M1_M2_MASK,
9467 : PseudoVSOXSEG4EI8_V_M2_M2,
9468 : PseudoVSOXSEG4EI8_V_M2_M2_MASK,
9469 : PseudoVSOXSEG4EI8_V_MF2_M1,
9470 : PseudoVSOXSEG4EI8_V_MF2_M1_MASK,
9471 : PseudoVSOXSEG4EI8_V_MF2_M2,
9472 : PseudoVSOXSEG4EI8_V_MF2_M2_MASK,
9473 : PseudoVSOXSEG4EI8_V_MF2_MF2,
9474 : PseudoVSOXSEG4EI8_V_MF2_MF2_MASK,
9475 : PseudoVSOXSEG4EI8_V_MF4_M1,
9476 : PseudoVSOXSEG4EI8_V_MF4_M1_MASK,
9477 : PseudoVSOXSEG4EI8_V_MF4_M2,
9478 : PseudoVSOXSEG4EI8_V_MF4_M2_MASK,
9479 : PseudoVSOXSEG4EI8_V_MF4_MF2,
9480 : PseudoVSOXSEG4EI8_V_MF4_MF2_MASK,
9481 : PseudoVSOXSEG4EI8_V_MF4_MF4,
9482 : PseudoVSOXSEG4EI8_V_MF4_MF4_MASK,
9483 : PseudoVSOXSEG4EI8_V_MF8_M1,
9484 : PseudoVSOXSEG4EI8_V_MF8_M1_MASK,
9485 : PseudoVSOXSEG4EI8_V_MF8_MF2,
9486 : PseudoVSOXSEG4EI8_V_MF8_MF2_MASK,
9487 : PseudoVSOXSEG4EI8_V_MF8_MF4,
9488 : PseudoVSOXSEG4EI8_V_MF8_MF4_MASK,
9489 : PseudoVSOXSEG4EI8_V_MF8_MF8,
9490 : PseudoVSOXSEG4EI8_V_MF8_MF8_MASK,
9491 : PseudoVSOXSEG5EI16_V_M1_M1,
9492 : PseudoVSOXSEG5EI16_V_M1_M1_MASK,
9493 : PseudoVSOXSEG5EI16_V_M1_MF2,
9494 : PseudoVSOXSEG5EI16_V_M1_MF2_MASK,
9495 : PseudoVSOXSEG5EI16_V_M2_M1,
9496 : PseudoVSOXSEG5EI16_V_M2_M1_MASK,
9497 : PseudoVSOXSEG5EI16_V_MF2_M1,
9498 : PseudoVSOXSEG5EI16_V_MF2_M1_MASK,
9499 : PseudoVSOXSEG5EI16_V_MF2_MF2,
9500 : PseudoVSOXSEG5EI16_V_MF2_MF2_MASK,
9501 : PseudoVSOXSEG5EI16_V_MF2_MF4,
9502 : PseudoVSOXSEG5EI16_V_MF2_MF4_MASK,
9503 : PseudoVSOXSEG5EI16_V_MF4_M1,
9504 : PseudoVSOXSEG5EI16_V_MF4_M1_MASK,
9505 : PseudoVSOXSEG5EI16_V_MF4_MF2,
9506 : PseudoVSOXSEG5EI16_V_MF4_MF2_MASK,
9507 : PseudoVSOXSEG5EI16_V_MF4_MF4,
9508 : PseudoVSOXSEG5EI16_V_MF4_MF4_MASK,
9509 : PseudoVSOXSEG5EI16_V_MF4_MF8,
9510 : PseudoVSOXSEG5EI16_V_MF4_MF8_MASK,
9511 : PseudoVSOXSEG5EI32_V_M1_M1,
9512 : PseudoVSOXSEG5EI32_V_M1_M1_MASK,
9513 : PseudoVSOXSEG5EI32_V_M1_MF2,
9514 : PseudoVSOXSEG5EI32_V_M1_MF2_MASK,
9515 : PseudoVSOXSEG5EI32_V_M1_MF4,
9516 : PseudoVSOXSEG5EI32_V_M1_MF4_MASK,
9517 : PseudoVSOXSEG5EI32_V_M2_M1,
9518 : PseudoVSOXSEG5EI32_V_M2_M1_MASK,
9519 : PseudoVSOXSEG5EI32_V_M2_MF2,
9520 : PseudoVSOXSEG5EI32_V_M2_MF2_MASK,
9521 : PseudoVSOXSEG5EI32_V_M4_M1,
9522 : PseudoVSOXSEG5EI32_V_M4_M1_MASK,
9523 : PseudoVSOXSEG5EI32_V_MF2_M1,
9524 : PseudoVSOXSEG5EI32_V_MF2_M1_MASK,
9525 : PseudoVSOXSEG5EI32_V_MF2_MF2,
9526 : PseudoVSOXSEG5EI32_V_MF2_MF2_MASK,
9527 : PseudoVSOXSEG5EI32_V_MF2_MF4,
9528 : PseudoVSOXSEG5EI32_V_MF2_MF4_MASK,
9529 : PseudoVSOXSEG5EI32_V_MF2_MF8,
9530 : PseudoVSOXSEG5EI32_V_MF2_MF8_MASK,
9531 : PseudoVSOXSEG5EI64_V_M1_M1,
9532 : PseudoVSOXSEG5EI64_V_M1_M1_MASK,
9533 : PseudoVSOXSEG5EI64_V_M1_MF2,
9534 : PseudoVSOXSEG5EI64_V_M1_MF2_MASK,
9535 : PseudoVSOXSEG5EI64_V_M1_MF4,
9536 : PseudoVSOXSEG5EI64_V_M1_MF4_MASK,
9537 : PseudoVSOXSEG5EI64_V_M1_MF8,
9538 : PseudoVSOXSEG5EI64_V_M1_MF8_MASK,
9539 : PseudoVSOXSEG5EI64_V_M2_M1,
9540 : PseudoVSOXSEG5EI64_V_M2_M1_MASK,
9541 : PseudoVSOXSEG5EI64_V_M2_MF2,
9542 : PseudoVSOXSEG5EI64_V_M2_MF2_MASK,
9543 : PseudoVSOXSEG5EI64_V_M2_MF4,
9544 : PseudoVSOXSEG5EI64_V_M2_MF4_MASK,
9545 : PseudoVSOXSEG5EI64_V_M4_M1,
9546 : PseudoVSOXSEG5EI64_V_M4_M1_MASK,
9547 : PseudoVSOXSEG5EI64_V_M4_MF2,
9548 : PseudoVSOXSEG5EI64_V_M4_MF2_MASK,
9549 : PseudoVSOXSEG5EI64_V_M8_M1,
9550 : PseudoVSOXSEG5EI64_V_M8_M1_MASK,
9551 : PseudoVSOXSEG5EI8_V_M1_M1,
9552 : PseudoVSOXSEG5EI8_V_M1_M1_MASK,
9553 : PseudoVSOXSEG5EI8_V_MF2_M1,
9554 : PseudoVSOXSEG5EI8_V_MF2_M1_MASK,
9555 : PseudoVSOXSEG5EI8_V_MF2_MF2,
9556 : PseudoVSOXSEG5EI8_V_MF2_MF2_MASK,
9557 : PseudoVSOXSEG5EI8_V_MF4_M1,
9558 : PseudoVSOXSEG5EI8_V_MF4_M1_MASK,
9559 : PseudoVSOXSEG5EI8_V_MF4_MF2,
9560 : PseudoVSOXSEG5EI8_V_MF4_MF2_MASK,
9561 : PseudoVSOXSEG5EI8_V_MF4_MF4,
9562 : PseudoVSOXSEG5EI8_V_MF4_MF4_MASK,
9563 : PseudoVSOXSEG5EI8_V_MF8_M1,
9564 : PseudoVSOXSEG5EI8_V_MF8_M1_MASK,
9565 : PseudoVSOXSEG5EI8_V_MF8_MF2,
9566 : PseudoVSOXSEG5EI8_V_MF8_MF2_MASK,
9567 : PseudoVSOXSEG5EI8_V_MF8_MF4,
9568 : PseudoVSOXSEG5EI8_V_MF8_MF4_MASK,
9569 : PseudoVSOXSEG5EI8_V_MF8_MF8,
9570 : PseudoVSOXSEG5EI8_V_MF8_MF8_MASK,
9571 : PseudoVSOXSEG6EI16_V_M1_M1,
9572 : PseudoVSOXSEG6EI16_V_M1_M1_MASK,
9573 : PseudoVSOXSEG6EI16_V_M1_MF2,
9574 : PseudoVSOXSEG6EI16_V_M1_MF2_MASK,
9575 : PseudoVSOXSEG6EI16_V_M2_M1,
9576 : PseudoVSOXSEG6EI16_V_M2_M1_MASK,
9577 : PseudoVSOXSEG6EI16_V_MF2_M1,
9578 : PseudoVSOXSEG6EI16_V_MF2_M1_MASK,
9579 : PseudoVSOXSEG6EI16_V_MF2_MF2,
9580 : PseudoVSOXSEG6EI16_V_MF2_MF2_MASK,
9581 : PseudoVSOXSEG6EI16_V_MF2_MF4,
9582 : PseudoVSOXSEG6EI16_V_MF2_MF4_MASK,
9583 : PseudoVSOXSEG6EI16_V_MF4_M1,
9584 : PseudoVSOXSEG6EI16_V_MF4_M1_MASK,
9585 : PseudoVSOXSEG6EI16_V_MF4_MF2,
9586 : PseudoVSOXSEG6EI16_V_MF4_MF2_MASK,
9587 : PseudoVSOXSEG6EI16_V_MF4_MF4,
9588 : PseudoVSOXSEG6EI16_V_MF4_MF4_MASK,
9589 : PseudoVSOXSEG6EI16_V_MF4_MF8,
9590 : PseudoVSOXSEG6EI16_V_MF4_MF8_MASK,
9591 : PseudoVSOXSEG6EI32_V_M1_M1,
9592 : PseudoVSOXSEG6EI32_V_M1_M1_MASK,
9593 : PseudoVSOXSEG6EI32_V_M1_MF2,
9594 : PseudoVSOXSEG6EI32_V_M1_MF2_MASK,
9595 : PseudoVSOXSEG6EI32_V_M1_MF4,
9596 : PseudoVSOXSEG6EI32_V_M1_MF4_MASK,
9597 : PseudoVSOXSEG6EI32_V_M2_M1,
9598 : PseudoVSOXSEG6EI32_V_M2_M1_MASK,
9599 : PseudoVSOXSEG6EI32_V_M2_MF2,
9600 : PseudoVSOXSEG6EI32_V_M2_MF2_MASK,
9601 : PseudoVSOXSEG6EI32_V_M4_M1,
9602 : PseudoVSOXSEG6EI32_V_M4_M1_MASK,
9603 : PseudoVSOXSEG6EI32_V_MF2_M1,
9604 : PseudoVSOXSEG6EI32_V_MF2_M1_MASK,
9605 : PseudoVSOXSEG6EI32_V_MF2_MF2,
9606 : PseudoVSOXSEG6EI32_V_MF2_MF2_MASK,
9607 : PseudoVSOXSEG6EI32_V_MF2_MF4,
9608 : PseudoVSOXSEG6EI32_V_MF2_MF4_MASK,
9609 : PseudoVSOXSEG6EI32_V_MF2_MF8,
9610 : PseudoVSOXSEG6EI32_V_MF2_MF8_MASK,
9611 : PseudoVSOXSEG6EI64_V_M1_M1,
9612 : PseudoVSOXSEG6EI64_V_M1_M1_MASK,
9613 : PseudoVSOXSEG6EI64_V_M1_MF2,
9614 : PseudoVSOXSEG6EI64_V_M1_MF2_MASK,
9615 : PseudoVSOXSEG6EI64_V_M1_MF4,
9616 : PseudoVSOXSEG6EI64_V_M1_MF4_MASK,
9617 : PseudoVSOXSEG6EI64_V_M1_MF8,
9618 : PseudoVSOXSEG6EI64_V_M1_MF8_MASK,
9619 : PseudoVSOXSEG6EI64_V_M2_M1,
9620 : PseudoVSOXSEG6EI64_V_M2_M1_MASK,
9621 : PseudoVSOXSEG6EI64_V_M2_MF2,
9622 : PseudoVSOXSEG6EI64_V_M2_MF2_MASK,
9623 : PseudoVSOXSEG6EI64_V_M2_MF4,
9624 : PseudoVSOXSEG6EI64_V_M2_MF4_MASK,
9625 : PseudoVSOXSEG6EI64_V_M4_M1,
9626 : PseudoVSOXSEG6EI64_V_M4_M1_MASK,
9627 : PseudoVSOXSEG6EI64_V_M4_MF2,
9628 : PseudoVSOXSEG6EI64_V_M4_MF2_MASK,
9629 : PseudoVSOXSEG6EI64_V_M8_M1,
9630 : PseudoVSOXSEG6EI64_V_M8_M1_MASK,
9631 : PseudoVSOXSEG6EI8_V_M1_M1,
9632 : PseudoVSOXSEG6EI8_V_M1_M1_MASK,
9633 : PseudoVSOXSEG6EI8_V_MF2_M1,
9634 : PseudoVSOXSEG6EI8_V_MF2_M1_MASK,
9635 : PseudoVSOXSEG6EI8_V_MF2_MF2,
9636 : PseudoVSOXSEG6EI8_V_MF2_MF2_MASK,
9637 : PseudoVSOXSEG6EI8_V_MF4_M1,
9638 : PseudoVSOXSEG6EI8_V_MF4_M1_MASK,
9639 : PseudoVSOXSEG6EI8_V_MF4_MF2,
9640 : PseudoVSOXSEG6EI8_V_MF4_MF2_MASK,
9641 : PseudoVSOXSEG6EI8_V_MF4_MF4,
9642 : PseudoVSOXSEG6EI8_V_MF4_MF4_MASK,
9643 : PseudoVSOXSEG6EI8_V_MF8_M1,
9644 : PseudoVSOXSEG6EI8_V_MF8_M1_MASK,
9645 : PseudoVSOXSEG6EI8_V_MF8_MF2,
9646 : PseudoVSOXSEG6EI8_V_MF8_MF2_MASK,
9647 : PseudoVSOXSEG6EI8_V_MF8_MF4,
9648 : PseudoVSOXSEG6EI8_V_MF8_MF4_MASK,
9649 : PseudoVSOXSEG6EI8_V_MF8_MF8,
9650 : PseudoVSOXSEG6EI8_V_MF8_MF8_MASK,
9651 : PseudoVSOXSEG7EI16_V_M1_M1,
9652 : PseudoVSOXSEG7EI16_V_M1_M1_MASK,
9653 : PseudoVSOXSEG7EI16_V_M1_MF2,
9654 : PseudoVSOXSEG7EI16_V_M1_MF2_MASK,
9655 : PseudoVSOXSEG7EI16_V_M2_M1,
9656 : PseudoVSOXSEG7EI16_V_M2_M1_MASK,
9657 : PseudoVSOXSEG7EI16_V_MF2_M1,
9658 : PseudoVSOXSEG7EI16_V_MF2_M1_MASK,
9659 : PseudoVSOXSEG7EI16_V_MF2_MF2,
9660 : PseudoVSOXSEG7EI16_V_MF2_MF2_MASK,
9661 : PseudoVSOXSEG7EI16_V_MF2_MF4,
9662 : PseudoVSOXSEG7EI16_V_MF2_MF4_MASK,
9663 : PseudoVSOXSEG7EI16_V_MF4_M1,
9664 : PseudoVSOXSEG7EI16_V_MF4_M1_MASK,
9665 : PseudoVSOXSEG7EI16_V_MF4_MF2,
9666 : PseudoVSOXSEG7EI16_V_MF4_MF2_MASK,
9667 : PseudoVSOXSEG7EI16_V_MF4_MF4,
9668 : PseudoVSOXSEG7EI16_V_MF4_MF4_MASK,
9669 : PseudoVSOXSEG7EI16_V_MF4_MF8,
9670 : PseudoVSOXSEG7EI16_V_MF4_MF8_MASK,
9671 : PseudoVSOXSEG7EI32_V_M1_M1,
9672 : PseudoVSOXSEG7EI32_V_M1_M1_MASK,
9673 : PseudoVSOXSEG7EI32_V_M1_MF2,
9674 : PseudoVSOXSEG7EI32_V_M1_MF2_MASK,
9675 : PseudoVSOXSEG7EI32_V_M1_MF4,
9676 : PseudoVSOXSEG7EI32_V_M1_MF4_MASK,
9677 : PseudoVSOXSEG7EI32_V_M2_M1,
9678 : PseudoVSOXSEG7EI32_V_M2_M1_MASK,
9679 : PseudoVSOXSEG7EI32_V_M2_MF2,
9680 : PseudoVSOXSEG7EI32_V_M2_MF2_MASK,
9681 : PseudoVSOXSEG7EI32_V_M4_M1,
9682 : PseudoVSOXSEG7EI32_V_M4_M1_MASK,
9683 : PseudoVSOXSEG7EI32_V_MF2_M1,
9684 : PseudoVSOXSEG7EI32_V_MF2_M1_MASK,
9685 : PseudoVSOXSEG7EI32_V_MF2_MF2,
9686 : PseudoVSOXSEG7EI32_V_MF2_MF2_MASK,
9687 : PseudoVSOXSEG7EI32_V_MF2_MF4,
9688 : PseudoVSOXSEG7EI32_V_MF2_MF4_MASK,
9689 : PseudoVSOXSEG7EI32_V_MF2_MF8,
9690 : PseudoVSOXSEG7EI32_V_MF2_MF8_MASK,
9691 : PseudoVSOXSEG7EI64_V_M1_M1,
9692 : PseudoVSOXSEG7EI64_V_M1_M1_MASK,
9693 : PseudoVSOXSEG7EI64_V_M1_MF2,
9694 : PseudoVSOXSEG7EI64_V_M1_MF2_MASK,
9695 : PseudoVSOXSEG7EI64_V_M1_MF4,
9696 : PseudoVSOXSEG7EI64_V_M1_MF4_MASK,
9697 : PseudoVSOXSEG7EI64_V_M1_MF8,
9698 : PseudoVSOXSEG7EI64_V_M1_MF8_MASK,
9699 : PseudoVSOXSEG7EI64_V_M2_M1,
9700 : PseudoVSOXSEG7EI64_V_M2_M1_MASK,
9701 : PseudoVSOXSEG7EI64_V_M2_MF2,
9702 : PseudoVSOXSEG7EI64_V_M2_MF2_MASK,
9703 : PseudoVSOXSEG7EI64_V_M2_MF4,
9704 : PseudoVSOXSEG7EI64_V_M2_MF4_MASK,
9705 : PseudoVSOXSEG7EI64_V_M4_M1,
9706 : PseudoVSOXSEG7EI64_V_M4_M1_MASK,
9707 : PseudoVSOXSEG7EI64_V_M4_MF2,
9708 : PseudoVSOXSEG7EI64_V_M4_MF2_MASK,
9709 : PseudoVSOXSEG7EI64_V_M8_M1,
9710 : PseudoVSOXSEG7EI64_V_M8_M1_MASK,
9711 : PseudoVSOXSEG7EI8_V_M1_M1,
9712 : PseudoVSOXSEG7EI8_V_M1_M1_MASK,
9713 : PseudoVSOXSEG7EI8_V_MF2_M1,
9714 : PseudoVSOXSEG7EI8_V_MF2_M1_MASK,
9715 : PseudoVSOXSEG7EI8_V_MF2_MF2,
9716 : PseudoVSOXSEG7EI8_V_MF2_MF2_MASK,
9717 : PseudoVSOXSEG7EI8_V_MF4_M1,
9718 : PseudoVSOXSEG7EI8_V_MF4_M1_MASK,
9719 : PseudoVSOXSEG7EI8_V_MF4_MF2,
9720 : PseudoVSOXSEG7EI8_V_MF4_MF2_MASK,
9721 : PseudoVSOXSEG7EI8_V_MF4_MF4,
9722 : PseudoVSOXSEG7EI8_V_MF4_MF4_MASK,
9723 : PseudoVSOXSEG7EI8_V_MF8_M1,
9724 : PseudoVSOXSEG7EI8_V_MF8_M1_MASK,
9725 : PseudoVSOXSEG7EI8_V_MF8_MF2,
9726 : PseudoVSOXSEG7EI8_V_MF8_MF2_MASK,
9727 : PseudoVSOXSEG7EI8_V_MF8_MF4,
9728 : PseudoVSOXSEG7EI8_V_MF8_MF4_MASK,
9729 : PseudoVSOXSEG7EI8_V_MF8_MF8,
9730 : PseudoVSOXSEG7EI8_V_MF8_MF8_MASK,
9731 : PseudoVSOXSEG8EI16_V_M1_M1,
9732 : PseudoVSOXSEG8EI16_V_M1_M1_MASK,
9733 : PseudoVSOXSEG8EI16_V_M1_MF2,
9734 : PseudoVSOXSEG8EI16_V_M1_MF2_MASK,
9735 : PseudoVSOXSEG8EI16_V_M2_M1,
9736 : PseudoVSOXSEG8EI16_V_M2_M1_MASK,
9737 : PseudoVSOXSEG8EI16_V_MF2_M1,
9738 : PseudoVSOXSEG8EI16_V_MF2_M1_MASK,
9739 : PseudoVSOXSEG8EI16_V_MF2_MF2,
9740 : PseudoVSOXSEG8EI16_V_MF2_MF2_MASK,
9741 : PseudoVSOXSEG8EI16_V_MF2_MF4,
9742 : PseudoVSOXSEG8EI16_V_MF2_MF4_MASK,
9743 : PseudoVSOXSEG8EI16_V_MF4_M1,
9744 : PseudoVSOXSEG8EI16_V_MF4_M1_MASK,
9745 : PseudoVSOXSEG8EI16_V_MF4_MF2,
9746 : PseudoVSOXSEG8EI16_V_MF4_MF2_MASK,
9747 : PseudoVSOXSEG8EI16_V_MF4_MF4,
9748 : PseudoVSOXSEG8EI16_V_MF4_MF4_MASK,
9749 : PseudoVSOXSEG8EI16_V_MF4_MF8,
9750 : PseudoVSOXSEG8EI16_V_MF4_MF8_MASK,
9751 : PseudoVSOXSEG8EI32_V_M1_M1,
9752 : PseudoVSOXSEG8EI32_V_M1_M1_MASK,
9753 : PseudoVSOXSEG8EI32_V_M1_MF2,
9754 : PseudoVSOXSEG8EI32_V_M1_MF2_MASK,
9755 : PseudoVSOXSEG8EI32_V_M1_MF4,
9756 : PseudoVSOXSEG8EI32_V_M1_MF4_MASK,
9757 : PseudoVSOXSEG8EI32_V_M2_M1,
9758 : PseudoVSOXSEG8EI32_V_M2_M1_MASK,
9759 : PseudoVSOXSEG8EI32_V_M2_MF2,
9760 : PseudoVSOXSEG8EI32_V_M2_MF2_MASK,
9761 : PseudoVSOXSEG8EI32_V_M4_M1,
9762 : PseudoVSOXSEG8EI32_V_M4_M1_MASK,
9763 : PseudoVSOXSEG8EI32_V_MF2_M1,
9764 : PseudoVSOXSEG8EI32_V_MF2_M1_MASK,
9765 : PseudoVSOXSEG8EI32_V_MF2_MF2,
9766 : PseudoVSOXSEG8EI32_V_MF2_MF2_MASK,
9767 : PseudoVSOXSEG8EI32_V_MF2_MF4,
9768 : PseudoVSOXSEG8EI32_V_MF2_MF4_MASK,
9769 : PseudoVSOXSEG8EI32_V_MF2_MF8,
9770 : PseudoVSOXSEG8EI32_V_MF2_MF8_MASK,
9771 : PseudoVSOXSEG8EI64_V_M1_M1,
9772 : PseudoVSOXSEG8EI64_V_M1_M1_MASK,
9773 : PseudoVSOXSEG8EI64_V_M1_MF2,
9774 : PseudoVSOXSEG8EI64_V_M1_MF2_MASK,
9775 : PseudoVSOXSEG8EI64_V_M1_MF4,
9776 : PseudoVSOXSEG8EI64_V_M1_MF4_MASK,
9777 : PseudoVSOXSEG8EI64_V_M1_MF8,
9778 : PseudoVSOXSEG8EI64_V_M1_MF8_MASK,
9779 : PseudoVSOXSEG8EI64_V_M2_M1,
9780 : PseudoVSOXSEG8EI64_V_M2_M1_MASK,
9781 : PseudoVSOXSEG8EI64_V_M2_MF2,
9782 : PseudoVSOXSEG8EI64_V_M2_MF2_MASK,
9783 : PseudoVSOXSEG8EI64_V_M2_MF4,
9784 : PseudoVSOXSEG8EI64_V_M2_MF4_MASK,
9785 : PseudoVSOXSEG8EI64_V_M4_M1,
9786 : PseudoVSOXSEG8EI64_V_M4_M1_MASK,
9787 : PseudoVSOXSEG8EI64_V_M4_MF2,
9788 : PseudoVSOXSEG8EI64_V_M4_MF2_MASK,
9789 : PseudoVSOXSEG8EI64_V_M8_M1,
9790 : PseudoVSOXSEG8EI64_V_M8_M1_MASK,
9791 : PseudoVSOXSEG8EI8_V_M1_M1,
9792 : PseudoVSOXSEG8EI8_V_M1_M1_MASK,
9793 : PseudoVSOXSEG8EI8_V_MF2_M1,
9794 : PseudoVSOXSEG8EI8_V_MF2_M1_MASK,
9795 : PseudoVSOXSEG8EI8_V_MF2_MF2,
9796 : PseudoVSOXSEG8EI8_V_MF2_MF2_MASK,
9797 : PseudoVSOXSEG8EI8_V_MF4_M1,
9798 : PseudoVSOXSEG8EI8_V_MF4_M1_MASK,
9799 : PseudoVSOXSEG8EI8_V_MF4_MF2,
9800 : PseudoVSOXSEG8EI8_V_MF4_MF2_MASK,
9801 : PseudoVSOXSEG8EI8_V_MF4_MF4,
9802 : PseudoVSOXSEG8EI8_V_MF4_MF4_MASK,
9803 : PseudoVSOXSEG8EI8_V_MF8_M1,
9804 : PseudoVSOXSEG8EI8_V_MF8_M1_MASK,
9805 : PseudoVSOXSEG8EI8_V_MF8_MF2,
9806 : PseudoVSOXSEG8EI8_V_MF8_MF2_MASK,
9807 : PseudoVSOXSEG8EI8_V_MF8_MF4,
9808 : PseudoVSOXSEG8EI8_V_MF8_MF4_MASK,
9809 : PseudoVSOXSEG8EI8_V_MF8_MF8,
9810 : PseudoVSOXSEG8EI8_V_MF8_MF8_MASK,
9811 : PseudoVSPILL2_M1,
9812 : PseudoVSPILL2_M2,
9813 : PseudoVSPILL2_M4,
9814 : PseudoVSPILL2_MF2,
9815 : PseudoVSPILL2_MF4,
9816 : PseudoVSPILL2_MF8,
9817 : PseudoVSPILL3_M1,
9818 : PseudoVSPILL3_M2,
9819 : PseudoVSPILL3_MF2,
9820 : PseudoVSPILL3_MF4,
9821 : PseudoVSPILL3_MF8,
9822 : PseudoVSPILL4_M1,
9823 : PseudoVSPILL4_M2,
9824 : PseudoVSPILL4_MF2,
9825 : PseudoVSPILL4_MF4,
9826 : PseudoVSPILL4_MF8,
9827 : PseudoVSPILL5_M1,
9828 : PseudoVSPILL5_MF2,
9829 : PseudoVSPILL5_MF4,
9830 : PseudoVSPILL5_MF8,
9831 : PseudoVSPILL6_M1,
9832 : PseudoVSPILL6_MF2,
9833 : PseudoVSPILL6_MF4,
9834 : PseudoVSPILL6_MF8,
9835 : PseudoVSPILL7_M1,
9836 : PseudoVSPILL7_MF2,
9837 : PseudoVSPILL7_MF4,
9838 : PseudoVSPILL7_MF8,
9839 : PseudoVSPILL8_M1,
9840 : PseudoVSPILL8_MF2,
9841 : PseudoVSPILL8_MF4,
9842 : PseudoVSPILL8_MF8,
9843 : PseudoVSRA_VI_M1,
9844 : PseudoVSRA_VI_M1_MASK,
9845 : PseudoVSRA_VI_M2,
9846 : PseudoVSRA_VI_M2_MASK,
9847 : PseudoVSRA_VI_M4,
9848 : PseudoVSRA_VI_M4_MASK,
9849 : PseudoVSRA_VI_M8,
9850 : PseudoVSRA_VI_M8_MASK,
9851 : PseudoVSRA_VI_MF2,
9852 : PseudoVSRA_VI_MF2_MASK,
9853 : PseudoVSRA_VI_MF4,
9854 : PseudoVSRA_VI_MF4_MASK,
9855 : PseudoVSRA_VI_MF8,
9856 : PseudoVSRA_VI_MF8_MASK,
9857 : PseudoVSRA_VV_M1,
9858 : PseudoVSRA_VV_M1_MASK,
9859 : PseudoVSRA_VV_M2,
9860 : PseudoVSRA_VV_M2_MASK,
9861 : PseudoVSRA_VV_M4,
9862 : PseudoVSRA_VV_M4_MASK,
9863 : PseudoVSRA_VV_M8,
9864 : PseudoVSRA_VV_M8_MASK,
9865 : PseudoVSRA_VV_MF2,
9866 : PseudoVSRA_VV_MF2_MASK,
9867 : PseudoVSRA_VV_MF4,
9868 : PseudoVSRA_VV_MF4_MASK,
9869 : PseudoVSRA_VV_MF8,
9870 : PseudoVSRA_VV_MF8_MASK,
9871 : PseudoVSRA_VX_M1,
9872 : PseudoVSRA_VX_M1_MASK,
9873 : PseudoVSRA_VX_M2,
9874 : PseudoVSRA_VX_M2_MASK,
9875 : PseudoVSRA_VX_M4,
9876 : PseudoVSRA_VX_M4_MASK,
9877 : PseudoVSRA_VX_M8,
9878 : PseudoVSRA_VX_M8_MASK,
9879 : PseudoVSRA_VX_MF2,
9880 : PseudoVSRA_VX_MF2_MASK,
9881 : PseudoVSRA_VX_MF4,
9882 : PseudoVSRA_VX_MF4_MASK,
9883 : PseudoVSRA_VX_MF8,
9884 : PseudoVSRA_VX_MF8_MASK,
9885 : PseudoVSRL_VI_M1,
9886 : PseudoVSRL_VI_M1_MASK,
9887 : PseudoVSRL_VI_M2,
9888 : PseudoVSRL_VI_M2_MASK,
9889 : PseudoVSRL_VI_M4,
9890 : PseudoVSRL_VI_M4_MASK,
9891 : PseudoVSRL_VI_M8,
9892 : PseudoVSRL_VI_M8_MASK,
9893 : PseudoVSRL_VI_MF2,
9894 : PseudoVSRL_VI_MF2_MASK,
9895 : PseudoVSRL_VI_MF4,
9896 : PseudoVSRL_VI_MF4_MASK,
9897 : PseudoVSRL_VI_MF8,
9898 : PseudoVSRL_VI_MF8_MASK,
9899 : PseudoVSRL_VV_M1,
9900 : PseudoVSRL_VV_M1_MASK,
9901 : PseudoVSRL_VV_M2,
9902 : PseudoVSRL_VV_M2_MASK,
9903 : PseudoVSRL_VV_M4,
9904 : PseudoVSRL_VV_M4_MASK,
9905 : PseudoVSRL_VV_M8,
9906 : PseudoVSRL_VV_M8_MASK,
9907 : PseudoVSRL_VV_MF2,
9908 : PseudoVSRL_VV_MF2_MASK,
9909 : PseudoVSRL_VV_MF4,
9910 : PseudoVSRL_VV_MF4_MASK,
9911 : PseudoVSRL_VV_MF8,
9912 : PseudoVSRL_VV_MF8_MASK,
9913 : PseudoVSRL_VX_M1,
9914 : PseudoVSRL_VX_M1_MASK,
9915 : PseudoVSRL_VX_M2,
9916 : PseudoVSRL_VX_M2_MASK,
9917 : PseudoVSRL_VX_M4,
9918 : PseudoVSRL_VX_M4_MASK,
9919 : PseudoVSRL_VX_M8,
9920 : PseudoVSRL_VX_M8_MASK,
9921 : PseudoVSRL_VX_MF2,
9922 : PseudoVSRL_VX_MF2_MASK,
9923 : PseudoVSRL_VX_MF4,
9924 : PseudoVSRL_VX_MF4_MASK,
9925 : PseudoVSRL_VX_MF8,
9926 : PseudoVSRL_VX_MF8_MASK,
9927 : PseudoVSSE16_V_M1,
9928 : PseudoVSSE16_V_M1_MASK,
9929 : PseudoVSSE16_V_M2,
9930 : PseudoVSSE16_V_M2_MASK,
9931 : PseudoVSSE16_V_M4,
9932 : PseudoVSSE16_V_M4_MASK,
9933 : PseudoVSSE16_V_M8,
9934 : PseudoVSSE16_V_M8_MASK,
9935 : PseudoVSSE16_V_MF2,
9936 : PseudoVSSE16_V_MF2_MASK,
9937 : PseudoVSSE16_V_MF4,
9938 : PseudoVSSE16_V_MF4_MASK,
9939 : PseudoVSSE32_V_M1,
9940 : PseudoVSSE32_V_M1_MASK,
9941 : PseudoVSSE32_V_M2,
9942 : PseudoVSSE32_V_M2_MASK,
9943 : PseudoVSSE32_V_M4,
9944 : PseudoVSSE32_V_M4_MASK,
9945 : PseudoVSSE32_V_M8,
9946 : PseudoVSSE32_V_M8_MASK,
9947 : PseudoVSSE32_V_MF2,
9948 : PseudoVSSE32_V_MF2_MASK,
9949 : PseudoVSSE64_V_M1,
9950 : PseudoVSSE64_V_M1_MASK,
9951 : PseudoVSSE64_V_M2,
9952 : PseudoVSSE64_V_M2_MASK,
9953 : PseudoVSSE64_V_M4,
9954 : PseudoVSSE64_V_M4_MASK,
9955 : PseudoVSSE64_V_M8,
9956 : PseudoVSSE64_V_M8_MASK,
9957 : PseudoVSSE8_V_M1,
9958 : PseudoVSSE8_V_M1_MASK,
9959 : PseudoVSSE8_V_M2,
9960 : PseudoVSSE8_V_M2_MASK,
9961 : PseudoVSSE8_V_M4,
9962 : PseudoVSSE8_V_M4_MASK,
9963 : PseudoVSSE8_V_M8,
9964 : PseudoVSSE8_V_M8_MASK,
9965 : PseudoVSSE8_V_MF2,
9966 : PseudoVSSE8_V_MF2_MASK,
9967 : PseudoVSSE8_V_MF4,
9968 : PseudoVSSE8_V_MF4_MASK,
9969 : PseudoVSSE8_V_MF8,
9970 : PseudoVSSE8_V_MF8_MASK,
9971 : PseudoVSSEG2E16_V_M1,
9972 : PseudoVSSEG2E16_V_M1_MASK,
9973 : PseudoVSSEG2E16_V_M2,
9974 : PseudoVSSEG2E16_V_M2_MASK,
9975 : PseudoVSSEG2E16_V_M4,
9976 : PseudoVSSEG2E16_V_M4_MASK,
9977 : PseudoVSSEG2E16_V_MF2,
9978 : PseudoVSSEG2E16_V_MF2_MASK,
9979 : PseudoVSSEG2E16_V_MF4,
9980 : PseudoVSSEG2E16_V_MF4_MASK,
9981 : PseudoVSSEG2E32_V_M1,
9982 : PseudoVSSEG2E32_V_M1_MASK,
9983 : PseudoVSSEG2E32_V_M2,
9984 : PseudoVSSEG2E32_V_M2_MASK,
9985 : PseudoVSSEG2E32_V_M4,
9986 : PseudoVSSEG2E32_V_M4_MASK,
9987 : PseudoVSSEG2E32_V_MF2,
9988 : PseudoVSSEG2E32_V_MF2_MASK,
9989 : PseudoVSSEG2E64_V_M1,
9990 : PseudoVSSEG2E64_V_M1_MASK,
9991 : PseudoVSSEG2E64_V_M2,
9992 : PseudoVSSEG2E64_V_M2_MASK,
9993 : PseudoVSSEG2E64_V_M4,
9994 : PseudoVSSEG2E64_V_M4_MASK,
9995 : PseudoVSSEG2E8_V_M1,
9996 : PseudoVSSEG2E8_V_M1_MASK,
9997 : PseudoVSSEG2E8_V_M2,
9998 : PseudoVSSEG2E8_V_M2_MASK,
9999 : PseudoVSSEG2E8_V_M4,
10000 : PseudoVSSEG2E8_V_M4_MASK,
10001 : PseudoVSSEG2E8_V_MF2,
10002 : PseudoVSSEG2E8_V_MF2_MASK,
10003 : PseudoVSSEG2E8_V_MF4,
10004 : PseudoVSSEG2E8_V_MF4_MASK,
10005 : PseudoVSSEG2E8_V_MF8,
10006 : PseudoVSSEG2E8_V_MF8_MASK,
10007 : PseudoVSSEG3E16_V_M1,
10008 : PseudoVSSEG3E16_V_M1_MASK,
10009 : PseudoVSSEG3E16_V_M2,
10010 : PseudoVSSEG3E16_V_M2_MASK,
10011 : PseudoVSSEG3E16_V_MF2,
10012 : PseudoVSSEG3E16_V_MF2_MASK,
10013 : PseudoVSSEG3E16_V_MF4,
10014 : PseudoVSSEG3E16_V_MF4_MASK,
10015 : PseudoVSSEG3E32_V_M1,
10016 : PseudoVSSEG3E32_V_M1_MASK,
10017 : PseudoVSSEG3E32_V_M2,
10018 : PseudoVSSEG3E32_V_M2_MASK,
10019 : PseudoVSSEG3E32_V_MF2,
10020 : PseudoVSSEG3E32_V_MF2_MASK,
10021 : PseudoVSSEG3E64_V_M1,
10022 : PseudoVSSEG3E64_V_M1_MASK,
10023 : PseudoVSSEG3E64_V_M2,
10024 : PseudoVSSEG3E64_V_M2_MASK,
10025 : PseudoVSSEG3E8_V_M1,
10026 : PseudoVSSEG3E8_V_M1_MASK,
10027 : PseudoVSSEG3E8_V_M2,
10028 : PseudoVSSEG3E8_V_M2_MASK,
10029 : PseudoVSSEG3E8_V_MF2,
10030 : PseudoVSSEG3E8_V_MF2_MASK,
10031 : PseudoVSSEG3E8_V_MF4,
10032 : PseudoVSSEG3E8_V_MF4_MASK,
10033 : PseudoVSSEG3E8_V_MF8,
10034 : PseudoVSSEG3E8_V_MF8_MASK,
10035 : PseudoVSSEG4E16_V_M1,
10036 : PseudoVSSEG4E16_V_M1_MASK,
10037 : PseudoVSSEG4E16_V_M2,
10038 : PseudoVSSEG4E16_V_M2_MASK,
10039 : PseudoVSSEG4E16_V_MF2,
10040 : PseudoVSSEG4E16_V_MF2_MASK,
10041 : PseudoVSSEG4E16_V_MF4,
10042 : PseudoVSSEG4E16_V_MF4_MASK,
10043 : PseudoVSSEG4E32_V_M1,
10044 : PseudoVSSEG4E32_V_M1_MASK,
10045 : PseudoVSSEG4E32_V_M2,
10046 : PseudoVSSEG4E32_V_M2_MASK,
10047 : PseudoVSSEG4E32_V_MF2,
10048 : PseudoVSSEG4E32_V_MF2_MASK,
10049 : PseudoVSSEG4E64_V_M1,
10050 : PseudoVSSEG4E64_V_M1_MASK,
10051 : PseudoVSSEG4E64_V_M2,
10052 : PseudoVSSEG4E64_V_M2_MASK,
10053 : PseudoVSSEG4E8_V_M1,
10054 : PseudoVSSEG4E8_V_M1_MASK,
10055 : PseudoVSSEG4E8_V_M2,
10056 : PseudoVSSEG4E8_V_M2_MASK,
10057 : PseudoVSSEG4E8_V_MF2,
10058 : PseudoVSSEG4E8_V_MF2_MASK,
10059 : PseudoVSSEG4E8_V_MF4,
10060 : PseudoVSSEG4E8_V_MF4_MASK,
10061 : PseudoVSSEG4E8_V_MF8,
10062 : PseudoVSSEG4E8_V_MF8_MASK,
10063 : PseudoVSSEG5E16_V_M1,
10064 : PseudoVSSEG5E16_V_M1_MASK,
10065 : PseudoVSSEG5E16_V_MF2,
10066 : PseudoVSSEG5E16_V_MF2_MASK,
10067 : PseudoVSSEG5E16_V_MF4,
10068 : PseudoVSSEG5E16_V_MF4_MASK,
10069 : PseudoVSSEG5E32_V_M1,
10070 : PseudoVSSEG5E32_V_M1_MASK,
10071 : PseudoVSSEG5E32_V_MF2,
10072 : PseudoVSSEG5E32_V_MF2_MASK,
10073 : PseudoVSSEG5E64_V_M1,
10074 : PseudoVSSEG5E64_V_M1_MASK,
10075 : PseudoVSSEG5E8_V_M1,
10076 : PseudoVSSEG5E8_V_M1_MASK,
10077 : PseudoVSSEG5E8_V_MF2,
10078 : PseudoVSSEG5E8_V_MF2_MASK,
10079 : PseudoVSSEG5E8_V_MF4,
10080 : PseudoVSSEG5E8_V_MF4_MASK,
10081 : PseudoVSSEG5E8_V_MF8,
10082 : PseudoVSSEG5E8_V_MF8_MASK,
10083 : PseudoVSSEG6E16_V_M1,
10084 : PseudoVSSEG6E16_V_M1_MASK,
10085 : PseudoVSSEG6E16_V_MF2,
10086 : PseudoVSSEG6E16_V_MF2_MASK,
10087 : PseudoVSSEG6E16_V_MF4,
10088 : PseudoVSSEG6E16_V_MF4_MASK,
10089 : PseudoVSSEG6E32_V_M1,
10090 : PseudoVSSEG6E32_V_M1_MASK,
10091 : PseudoVSSEG6E32_V_MF2,
10092 : PseudoVSSEG6E32_V_MF2_MASK,
10093 : PseudoVSSEG6E64_V_M1,
10094 : PseudoVSSEG6E64_V_M1_MASK,
10095 : PseudoVSSEG6E8_V_M1,
10096 : PseudoVSSEG6E8_V_M1_MASK,
10097 : PseudoVSSEG6E8_V_MF2,
10098 : PseudoVSSEG6E8_V_MF2_MASK,
10099 : PseudoVSSEG6E8_V_MF4,
10100 : PseudoVSSEG6E8_V_MF4_MASK,
10101 : PseudoVSSEG6E8_V_MF8,
10102 : PseudoVSSEG6E8_V_MF8_MASK,
10103 : PseudoVSSEG7E16_V_M1,
10104 : PseudoVSSEG7E16_V_M1_MASK,
10105 : PseudoVSSEG7E16_V_MF2,
10106 : PseudoVSSEG7E16_V_MF2_MASK,
10107 : PseudoVSSEG7E16_V_MF4,
10108 : PseudoVSSEG7E16_V_MF4_MASK,
10109 : PseudoVSSEG7E32_V_M1,
10110 : PseudoVSSEG7E32_V_M1_MASK,
10111 : PseudoVSSEG7E32_V_MF2,
10112 : PseudoVSSEG7E32_V_MF2_MASK,
10113 : PseudoVSSEG7E64_V_M1,
10114 : PseudoVSSEG7E64_V_M1_MASK,
10115 : PseudoVSSEG7E8_V_M1,
10116 : PseudoVSSEG7E8_V_M1_MASK,
10117 : PseudoVSSEG7E8_V_MF2,
10118 : PseudoVSSEG7E8_V_MF2_MASK,
10119 : PseudoVSSEG7E8_V_MF4,
10120 : PseudoVSSEG7E8_V_MF4_MASK,
10121 : PseudoVSSEG7E8_V_MF8,
10122 : PseudoVSSEG7E8_V_MF8_MASK,
10123 : PseudoVSSEG8E16_V_M1,
10124 : PseudoVSSEG8E16_V_M1_MASK,
10125 : PseudoVSSEG8E16_V_MF2,
10126 : PseudoVSSEG8E16_V_MF2_MASK,
10127 : PseudoVSSEG8E16_V_MF4,
10128 : PseudoVSSEG8E16_V_MF4_MASK,
10129 : PseudoVSSEG8E32_V_M1,
10130 : PseudoVSSEG8E32_V_M1_MASK,
10131 : PseudoVSSEG8E32_V_MF2,
10132 : PseudoVSSEG8E32_V_MF2_MASK,
10133 : PseudoVSSEG8E64_V_M1,
10134 : PseudoVSSEG8E64_V_M1_MASK,
10135 : PseudoVSSEG8E8_V_M1,
10136 : PseudoVSSEG8E8_V_M1_MASK,
10137 : PseudoVSSEG8E8_V_MF2,
10138 : PseudoVSSEG8E8_V_MF2_MASK,
10139 : PseudoVSSEG8E8_V_MF4,
10140 : PseudoVSSEG8E8_V_MF4_MASK,
10141 : PseudoVSSEG8E8_V_MF8,
10142 : PseudoVSSEG8E8_V_MF8_MASK,
10143 : PseudoVSSRA_VI_M1,
10144 : PseudoVSSRA_VI_M1_MASK,
10145 : PseudoVSSRA_VI_M2,
10146 : PseudoVSSRA_VI_M2_MASK,
10147 : PseudoVSSRA_VI_M4,
10148 : PseudoVSSRA_VI_M4_MASK,
10149 : PseudoVSSRA_VI_M8,
10150 : PseudoVSSRA_VI_M8_MASK,
10151 : PseudoVSSRA_VI_MF2,
10152 : PseudoVSSRA_VI_MF2_MASK,
10153 : PseudoVSSRA_VI_MF4,
10154 : PseudoVSSRA_VI_MF4_MASK,
10155 : PseudoVSSRA_VI_MF8,
10156 : PseudoVSSRA_VI_MF8_MASK,
10157 : PseudoVSSRA_VV_M1,
10158 : PseudoVSSRA_VV_M1_MASK,
10159 : PseudoVSSRA_VV_M2,
10160 : PseudoVSSRA_VV_M2_MASK,
10161 : PseudoVSSRA_VV_M4,
10162 : PseudoVSSRA_VV_M4_MASK,
10163 : PseudoVSSRA_VV_M8,
10164 : PseudoVSSRA_VV_M8_MASK,
10165 : PseudoVSSRA_VV_MF2,
10166 : PseudoVSSRA_VV_MF2_MASK,
10167 : PseudoVSSRA_VV_MF4,
10168 : PseudoVSSRA_VV_MF4_MASK,
10169 : PseudoVSSRA_VV_MF8,
10170 : PseudoVSSRA_VV_MF8_MASK,
10171 : PseudoVSSRA_VX_M1,
10172 : PseudoVSSRA_VX_M1_MASK,
10173 : PseudoVSSRA_VX_M2,
10174 : PseudoVSSRA_VX_M2_MASK,
10175 : PseudoVSSRA_VX_M4,
10176 : PseudoVSSRA_VX_M4_MASK,
10177 : PseudoVSSRA_VX_M8,
10178 : PseudoVSSRA_VX_M8_MASK,
10179 : PseudoVSSRA_VX_MF2,
10180 : PseudoVSSRA_VX_MF2_MASK,
10181 : PseudoVSSRA_VX_MF4,
10182 : PseudoVSSRA_VX_MF4_MASK,
10183 : PseudoVSSRA_VX_MF8,
10184 : PseudoVSSRA_VX_MF8_MASK,
10185 : PseudoVSSRL_VI_M1,
10186 : PseudoVSSRL_VI_M1_MASK,
10187 : PseudoVSSRL_VI_M2,
10188 : PseudoVSSRL_VI_M2_MASK,
10189 : PseudoVSSRL_VI_M4,
10190 : PseudoVSSRL_VI_M4_MASK,
10191 : PseudoVSSRL_VI_M8,
10192 : PseudoVSSRL_VI_M8_MASK,
10193 : PseudoVSSRL_VI_MF2,
10194 : PseudoVSSRL_VI_MF2_MASK,
10195 : PseudoVSSRL_VI_MF4,
10196 : PseudoVSSRL_VI_MF4_MASK,
10197 : PseudoVSSRL_VI_MF8,
10198 : PseudoVSSRL_VI_MF8_MASK,
10199 : PseudoVSSRL_VV_M1,
10200 : PseudoVSSRL_VV_M1_MASK,
10201 : PseudoVSSRL_VV_M2,
10202 : PseudoVSSRL_VV_M2_MASK,
10203 : PseudoVSSRL_VV_M4,
10204 : PseudoVSSRL_VV_M4_MASK,
10205 : PseudoVSSRL_VV_M8,
10206 : PseudoVSSRL_VV_M8_MASK,
10207 : PseudoVSSRL_VV_MF2,
10208 : PseudoVSSRL_VV_MF2_MASK,
10209 : PseudoVSSRL_VV_MF4,
10210 : PseudoVSSRL_VV_MF4_MASK,
10211 : PseudoVSSRL_VV_MF8,
10212 : PseudoVSSRL_VV_MF8_MASK,
10213 : PseudoVSSRL_VX_M1,
10214 : PseudoVSSRL_VX_M1_MASK,
10215 : PseudoVSSRL_VX_M2,
10216 : PseudoVSSRL_VX_M2_MASK,
10217 : PseudoVSSRL_VX_M4,
10218 : PseudoVSSRL_VX_M4_MASK,
10219 : PseudoVSSRL_VX_M8,
10220 : PseudoVSSRL_VX_M8_MASK,
10221 : PseudoVSSRL_VX_MF2,
10222 : PseudoVSSRL_VX_MF2_MASK,
10223 : PseudoVSSRL_VX_MF4,
10224 : PseudoVSSRL_VX_MF4_MASK,
10225 : PseudoVSSRL_VX_MF8,
10226 : PseudoVSSRL_VX_MF8_MASK,
10227 : PseudoVSSSEG2E16_V_M1,
10228 : PseudoVSSSEG2E16_V_M1_MASK,
10229 : PseudoVSSSEG2E16_V_M2,
10230 : PseudoVSSSEG2E16_V_M2_MASK,
10231 : PseudoVSSSEG2E16_V_M4,
10232 : PseudoVSSSEG2E16_V_M4_MASK,
10233 : PseudoVSSSEG2E16_V_MF2,
10234 : PseudoVSSSEG2E16_V_MF2_MASK,
10235 : PseudoVSSSEG2E16_V_MF4,
10236 : PseudoVSSSEG2E16_V_MF4_MASK,
10237 : PseudoVSSSEG2E32_V_M1,
10238 : PseudoVSSSEG2E32_V_M1_MASK,
10239 : PseudoVSSSEG2E32_V_M2,
10240 : PseudoVSSSEG2E32_V_M2_MASK,
10241 : PseudoVSSSEG2E32_V_M4,
10242 : PseudoVSSSEG2E32_V_M4_MASK,
10243 : PseudoVSSSEG2E32_V_MF2,
10244 : PseudoVSSSEG2E32_V_MF2_MASK,
10245 : PseudoVSSSEG2E64_V_M1,
10246 : PseudoVSSSEG2E64_V_M1_MASK,
10247 : PseudoVSSSEG2E64_V_M2,
10248 : PseudoVSSSEG2E64_V_M2_MASK,
10249 : PseudoVSSSEG2E64_V_M4,
10250 : PseudoVSSSEG2E64_V_M4_MASK,
10251 : PseudoVSSSEG2E8_V_M1,
10252 : PseudoVSSSEG2E8_V_M1_MASK,
10253 : PseudoVSSSEG2E8_V_M2,
10254 : PseudoVSSSEG2E8_V_M2_MASK,
10255 : PseudoVSSSEG2E8_V_M4,
10256 : PseudoVSSSEG2E8_V_M4_MASK,
10257 : PseudoVSSSEG2E8_V_MF2,
10258 : PseudoVSSSEG2E8_V_MF2_MASK,
10259 : PseudoVSSSEG2E8_V_MF4,
10260 : PseudoVSSSEG2E8_V_MF4_MASK,
10261 : PseudoVSSSEG2E8_V_MF8,
10262 : PseudoVSSSEG2E8_V_MF8_MASK,
10263 : PseudoVSSSEG3E16_V_M1,
10264 : PseudoVSSSEG3E16_V_M1_MASK,
10265 : PseudoVSSSEG3E16_V_M2,
10266 : PseudoVSSSEG3E16_V_M2_MASK,
10267 : PseudoVSSSEG3E16_V_MF2,
10268 : PseudoVSSSEG3E16_V_MF2_MASK,
10269 : PseudoVSSSEG3E16_V_MF4,
10270 : PseudoVSSSEG3E16_V_MF4_MASK,
10271 : PseudoVSSSEG3E32_V_M1,
10272 : PseudoVSSSEG3E32_V_M1_MASK,
10273 : PseudoVSSSEG3E32_V_M2,
10274 : PseudoVSSSEG3E32_V_M2_MASK,
10275 : PseudoVSSSEG3E32_V_MF2,
10276 : PseudoVSSSEG3E32_V_MF2_MASK,
10277 : PseudoVSSSEG3E64_V_M1,
10278 : PseudoVSSSEG3E64_V_M1_MASK,
10279 : PseudoVSSSEG3E64_V_M2,
10280 : PseudoVSSSEG3E64_V_M2_MASK,
10281 : PseudoVSSSEG3E8_V_M1,
10282 : PseudoVSSSEG3E8_V_M1_MASK,
10283 : PseudoVSSSEG3E8_V_M2,
10284 : PseudoVSSSEG3E8_V_M2_MASK,
10285 : PseudoVSSSEG3E8_V_MF2,
10286 : PseudoVSSSEG3E8_V_MF2_MASK,
10287 : PseudoVSSSEG3E8_V_MF4,
10288 : PseudoVSSSEG3E8_V_MF4_MASK,
10289 : PseudoVSSSEG3E8_V_MF8,
10290 : PseudoVSSSEG3E8_V_MF8_MASK,
10291 : PseudoVSSSEG4E16_V_M1,
10292 : PseudoVSSSEG4E16_V_M1_MASK,
10293 : PseudoVSSSEG4E16_V_M2,
10294 : PseudoVSSSEG4E16_V_M2_MASK,
10295 : PseudoVSSSEG4E16_V_MF2,
10296 : PseudoVSSSEG4E16_V_MF2_MASK,
10297 : PseudoVSSSEG4E16_V_MF4,
10298 : PseudoVSSSEG4E16_V_MF4_MASK,
10299 : PseudoVSSSEG4E32_V_M1,
10300 : PseudoVSSSEG4E32_V_M1_MASK,
10301 : PseudoVSSSEG4E32_V_M2,
10302 : PseudoVSSSEG4E32_V_M2_MASK,
10303 : PseudoVSSSEG4E32_V_MF2,
10304 : PseudoVSSSEG4E32_V_MF2_MASK,
10305 : PseudoVSSSEG4E64_V_M1,
10306 : PseudoVSSSEG4E64_V_M1_MASK,
10307 : PseudoVSSSEG4E64_V_M2,
10308 : PseudoVSSSEG4E64_V_M2_MASK,
10309 : PseudoVSSSEG4E8_V_M1,
10310 : PseudoVSSSEG4E8_V_M1_MASK,
10311 : PseudoVSSSEG4E8_V_M2,
10312 : PseudoVSSSEG4E8_V_M2_MASK,
10313 : PseudoVSSSEG4E8_V_MF2,
10314 : PseudoVSSSEG4E8_V_MF2_MASK,
10315 : PseudoVSSSEG4E8_V_MF4,
10316 : PseudoVSSSEG4E8_V_MF4_MASK,
10317 : PseudoVSSSEG4E8_V_MF8,
10318 : PseudoVSSSEG4E8_V_MF8_MASK,
10319 : PseudoVSSSEG5E16_V_M1,
10320 : PseudoVSSSEG5E16_V_M1_MASK,
10321 : PseudoVSSSEG5E16_V_MF2,
10322 : PseudoVSSSEG5E16_V_MF2_MASK,
10323 : PseudoVSSSEG5E16_V_MF4,
10324 : PseudoVSSSEG5E16_V_MF4_MASK,
10325 : PseudoVSSSEG5E32_V_M1,
10326 : PseudoVSSSEG5E32_V_M1_MASK,
10327 : PseudoVSSSEG5E32_V_MF2,
10328 : PseudoVSSSEG5E32_V_MF2_MASK,
10329 : PseudoVSSSEG5E64_V_M1,
10330 : PseudoVSSSEG5E64_V_M1_MASK,
10331 : PseudoVSSSEG5E8_V_M1,
10332 : PseudoVSSSEG5E8_V_M1_MASK,
10333 : PseudoVSSSEG5E8_V_MF2,
10334 : PseudoVSSSEG5E8_V_MF2_MASK,
10335 : PseudoVSSSEG5E8_V_MF4,
10336 : PseudoVSSSEG5E8_V_MF4_MASK,
10337 : PseudoVSSSEG5E8_V_MF8,
10338 : PseudoVSSSEG5E8_V_MF8_MASK,
10339 : PseudoVSSSEG6E16_V_M1,
10340 : PseudoVSSSEG6E16_V_M1_MASK,
10341 : PseudoVSSSEG6E16_V_MF2,
10342 : PseudoVSSSEG6E16_V_MF2_MASK,
10343 : PseudoVSSSEG6E16_V_MF4,
10344 : PseudoVSSSEG6E16_V_MF4_MASK,
10345 : PseudoVSSSEG6E32_V_M1,
10346 : PseudoVSSSEG6E32_V_M1_MASK,
10347 : PseudoVSSSEG6E32_V_MF2,
10348 : PseudoVSSSEG6E32_V_MF2_MASK,
10349 : PseudoVSSSEG6E64_V_M1,
10350 : PseudoVSSSEG6E64_V_M1_MASK,
10351 : PseudoVSSSEG6E8_V_M1,
10352 : PseudoVSSSEG6E8_V_M1_MASK,
10353 : PseudoVSSSEG6E8_V_MF2,
10354 : PseudoVSSSEG6E8_V_MF2_MASK,
10355 : PseudoVSSSEG6E8_V_MF4,
10356 : PseudoVSSSEG6E8_V_MF4_MASK,
10357 : PseudoVSSSEG6E8_V_MF8,
10358 : PseudoVSSSEG6E8_V_MF8_MASK,
10359 : PseudoVSSSEG7E16_V_M1,
10360 : PseudoVSSSEG7E16_V_M1_MASK,
10361 : PseudoVSSSEG7E16_V_MF2,
10362 : PseudoVSSSEG7E16_V_MF2_MASK,
10363 : PseudoVSSSEG7E16_V_MF4,
10364 : PseudoVSSSEG7E16_V_MF4_MASK,
10365 : PseudoVSSSEG7E32_V_M1,
10366 : PseudoVSSSEG7E32_V_M1_MASK,
10367 : PseudoVSSSEG7E32_V_MF2,
10368 : PseudoVSSSEG7E32_V_MF2_MASK,
10369 : PseudoVSSSEG7E64_V_M1,
10370 : PseudoVSSSEG7E64_V_M1_MASK,
10371 : PseudoVSSSEG7E8_V_M1,
10372 : PseudoVSSSEG7E8_V_M1_MASK,
10373 : PseudoVSSSEG7E8_V_MF2,
10374 : PseudoVSSSEG7E8_V_MF2_MASK,
10375 : PseudoVSSSEG7E8_V_MF4,
10376 : PseudoVSSSEG7E8_V_MF4_MASK,
10377 : PseudoVSSSEG7E8_V_MF8,
10378 : PseudoVSSSEG7E8_V_MF8_MASK,
10379 : PseudoVSSSEG8E16_V_M1,
10380 : PseudoVSSSEG8E16_V_M1_MASK,
10381 : PseudoVSSSEG8E16_V_MF2,
10382 : PseudoVSSSEG8E16_V_MF2_MASK,
10383 : PseudoVSSSEG8E16_V_MF4,
10384 : PseudoVSSSEG8E16_V_MF4_MASK,
10385 : PseudoVSSSEG8E32_V_M1,
10386 : PseudoVSSSEG8E32_V_M1_MASK,
10387 : PseudoVSSSEG8E32_V_MF2,
10388 : PseudoVSSSEG8E32_V_MF2_MASK,
10389 : PseudoVSSSEG8E64_V_M1,
10390 : PseudoVSSSEG8E64_V_M1_MASK,
10391 : PseudoVSSSEG8E8_V_M1,
10392 : PseudoVSSSEG8E8_V_M1_MASK,
10393 : PseudoVSSSEG8E8_V_MF2,
10394 : PseudoVSSSEG8E8_V_MF2_MASK,
10395 : PseudoVSSSEG8E8_V_MF4,
10396 : PseudoVSSSEG8E8_V_MF4_MASK,
10397 : PseudoVSSSEG8E8_V_MF8,
10398 : PseudoVSSSEG8E8_V_MF8_MASK,
10399 : PseudoVSSUBU_VV_M1,
10400 : PseudoVSSUBU_VV_M1_MASK,
10401 : PseudoVSSUBU_VV_M2,
10402 : PseudoVSSUBU_VV_M2_MASK,
10403 : PseudoVSSUBU_VV_M4,
10404 : PseudoVSSUBU_VV_M4_MASK,
10405 : PseudoVSSUBU_VV_M8,
10406 : PseudoVSSUBU_VV_M8_MASK,
10407 : PseudoVSSUBU_VV_MF2,
10408 : PseudoVSSUBU_VV_MF2_MASK,
10409 : PseudoVSSUBU_VV_MF4,
10410 : PseudoVSSUBU_VV_MF4_MASK,
10411 : PseudoVSSUBU_VV_MF8,
10412 : PseudoVSSUBU_VV_MF8_MASK,
10413 : PseudoVSSUBU_VX_M1,
10414 : PseudoVSSUBU_VX_M1_MASK,
10415 : PseudoVSSUBU_VX_M2,
10416 : PseudoVSSUBU_VX_M2_MASK,
10417 : PseudoVSSUBU_VX_M4,
10418 : PseudoVSSUBU_VX_M4_MASK,
10419 : PseudoVSSUBU_VX_M8,
10420 : PseudoVSSUBU_VX_M8_MASK,
10421 : PseudoVSSUBU_VX_MF2,
10422 : PseudoVSSUBU_VX_MF2_MASK,
10423 : PseudoVSSUBU_VX_MF4,
10424 : PseudoVSSUBU_VX_MF4_MASK,
10425 : PseudoVSSUBU_VX_MF8,
10426 : PseudoVSSUBU_VX_MF8_MASK,
10427 : PseudoVSSUB_VV_M1,
10428 : PseudoVSSUB_VV_M1_MASK,
10429 : PseudoVSSUB_VV_M2,
10430 : PseudoVSSUB_VV_M2_MASK,
10431 : PseudoVSSUB_VV_M4,
10432 : PseudoVSSUB_VV_M4_MASK,
10433 : PseudoVSSUB_VV_M8,
10434 : PseudoVSSUB_VV_M8_MASK,
10435 : PseudoVSSUB_VV_MF2,
10436 : PseudoVSSUB_VV_MF2_MASK,
10437 : PseudoVSSUB_VV_MF4,
10438 : PseudoVSSUB_VV_MF4_MASK,
10439 : PseudoVSSUB_VV_MF8,
10440 : PseudoVSSUB_VV_MF8_MASK,
10441 : PseudoVSSUB_VX_M1,
10442 : PseudoVSSUB_VX_M1_MASK,
10443 : PseudoVSSUB_VX_M2,
10444 : PseudoVSSUB_VX_M2_MASK,
10445 : PseudoVSSUB_VX_M4,
10446 : PseudoVSSUB_VX_M4_MASK,
10447 : PseudoVSSUB_VX_M8,
10448 : PseudoVSSUB_VX_M8_MASK,
10449 : PseudoVSSUB_VX_MF2,
10450 : PseudoVSSUB_VX_MF2_MASK,
10451 : PseudoVSSUB_VX_MF4,
10452 : PseudoVSSUB_VX_MF4_MASK,
10453 : PseudoVSSUB_VX_MF8,
10454 : PseudoVSSUB_VX_MF8_MASK,
10455 : PseudoVSUB_VV_M1,
10456 : PseudoVSUB_VV_M1_MASK,
10457 : PseudoVSUB_VV_M2,
10458 : PseudoVSUB_VV_M2_MASK,
10459 : PseudoVSUB_VV_M4,
10460 : PseudoVSUB_VV_M4_MASK,
10461 : PseudoVSUB_VV_M8,
10462 : PseudoVSUB_VV_M8_MASK,
10463 : PseudoVSUB_VV_MF2,
10464 : PseudoVSUB_VV_MF2_MASK,
10465 : PseudoVSUB_VV_MF4,
10466 : PseudoVSUB_VV_MF4_MASK,
10467 : PseudoVSUB_VV_MF8,
10468 : PseudoVSUB_VV_MF8_MASK,
10469 : PseudoVSUB_VX_M1,
10470 : PseudoVSUB_VX_M1_MASK,
10471 : PseudoVSUB_VX_M2,
10472 : PseudoVSUB_VX_M2_MASK,
10473 : PseudoVSUB_VX_M4,
10474 : PseudoVSUB_VX_M4_MASK,
10475 : PseudoVSUB_VX_M8,
10476 : PseudoVSUB_VX_M8_MASK,
10477 : PseudoVSUB_VX_MF2,
10478 : PseudoVSUB_VX_MF2_MASK,
10479 : PseudoVSUB_VX_MF4,
10480 : PseudoVSUB_VX_MF4_MASK,
10481 : PseudoVSUB_VX_MF8,
10482 : PseudoVSUB_VX_MF8_MASK,
10483 : PseudoVSUXEI16_V_M1_M1,
10484 : PseudoVSUXEI16_V_M1_M1_MASK,
10485 : PseudoVSUXEI16_V_M1_M2,
10486 : PseudoVSUXEI16_V_M1_M2_MASK,
10487 : PseudoVSUXEI16_V_M1_M4,
10488 : PseudoVSUXEI16_V_M1_M4_MASK,
10489 : PseudoVSUXEI16_V_M1_MF2,
10490 : PseudoVSUXEI16_V_M1_MF2_MASK,
10491 : PseudoVSUXEI16_V_M2_M1,
10492 : PseudoVSUXEI16_V_M2_M1_MASK,
10493 : PseudoVSUXEI16_V_M2_M2,
10494 : PseudoVSUXEI16_V_M2_M2_MASK,
10495 : PseudoVSUXEI16_V_M2_M4,
10496 : PseudoVSUXEI16_V_M2_M4_MASK,
10497 : PseudoVSUXEI16_V_M2_M8,
10498 : PseudoVSUXEI16_V_M2_M8_MASK,
10499 : PseudoVSUXEI16_V_M4_M2,
10500 : PseudoVSUXEI16_V_M4_M2_MASK,
10501 : PseudoVSUXEI16_V_M4_M4,
10502 : PseudoVSUXEI16_V_M4_M4_MASK,
10503 : PseudoVSUXEI16_V_M4_M8,
10504 : PseudoVSUXEI16_V_M4_M8_MASK,
10505 : PseudoVSUXEI16_V_M8_M4,
10506 : PseudoVSUXEI16_V_M8_M4_MASK,
10507 : PseudoVSUXEI16_V_M8_M8,
10508 : PseudoVSUXEI16_V_M8_M8_MASK,
10509 : PseudoVSUXEI16_V_MF2_M1,
10510 : PseudoVSUXEI16_V_MF2_M1_MASK,
10511 : PseudoVSUXEI16_V_MF2_M2,
10512 : PseudoVSUXEI16_V_MF2_M2_MASK,
10513 : PseudoVSUXEI16_V_MF2_MF2,
10514 : PseudoVSUXEI16_V_MF2_MF2_MASK,
10515 : PseudoVSUXEI16_V_MF2_MF4,
10516 : PseudoVSUXEI16_V_MF2_MF4_MASK,
10517 : PseudoVSUXEI16_V_MF4_M1,
10518 : PseudoVSUXEI16_V_MF4_M1_MASK,
10519 : PseudoVSUXEI16_V_MF4_MF2,
10520 : PseudoVSUXEI16_V_MF4_MF2_MASK,
10521 : PseudoVSUXEI16_V_MF4_MF4,
10522 : PseudoVSUXEI16_V_MF4_MF4_MASK,
10523 : PseudoVSUXEI16_V_MF4_MF8,
10524 : PseudoVSUXEI16_V_MF4_MF8_MASK,
10525 : PseudoVSUXEI32_V_M1_M1,
10526 : PseudoVSUXEI32_V_M1_M1_MASK,
10527 : PseudoVSUXEI32_V_M1_M2,
10528 : PseudoVSUXEI32_V_M1_M2_MASK,
10529 : PseudoVSUXEI32_V_M1_MF2,
10530 : PseudoVSUXEI32_V_M1_MF2_MASK,
10531 : PseudoVSUXEI32_V_M1_MF4,
10532 : PseudoVSUXEI32_V_M1_MF4_MASK,
10533 : PseudoVSUXEI32_V_M2_M1,
10534 : PseudoVSUXEI32_V_M2_M1_MASK,
10535 : PseudoVSUXEI32_V_M2_M2,
10536 : PseudoVSUXEI32_V_M2_M2_MASK,
10537 : PseudoVSUXEI32_V_M2_M4,
10538 : PseudoVSUXEI32_V_M2_M4_MASK,
10539 : PseudoVSUXEI32_V_M2_MF2,
10540 : PseudoVSUXEI32_V_M2_MF2_MASK,
10541 : PseudoVSUXEI32_V_M4_M1,
10542 : PseudoVSUXEI32_V_M4_M1_MASK,
10543 : PseudoVSUXEI32_V_M4_M2,
10544 : PseudoVSUXEI32_V_M4_M2_MASK,
10545 : PseudoVSUXEI32_V_M4_M4,
10546 : PseudoVSUXEI32_V_M4_M4_MASK,
10547 : PseudoVSUXEI32_V_M4_M8,
10548 : PseudoVSUXEI32_V_M4_M8_MASK,
10549 : PseudoVSUXEI32_V_M8_M2,
10550 : PseudoVSUXEI32_V_M8_M2_MASK,
10551 : PseudoVSUXEI32_V_M8_M4,
10552 : PseudoVSUXEI32_V_M8_M4_MASK,
10553 : PseudoVSUXEI32_V_M8_M8,
10554 : PseudoVSUXEI32_V_M8_M8_MASK,
10555 : PseudoVSUXEI32_V_MF2_M1,
10556 : PseudoVSUXEI32_V_MF2_M1_MASK,
10557 : PseudoVSUXEI32_V_MF2_MF2,
10558 : PseudoVSUXEI32_V_MF2_MF2_MASK,
10559 : PseudoVSUXEI32_V_MF2_MF4,
10560 : PseudoVSUXEI32_V_MF2_MF4_MASK,
10561 : PseudoVSUXEI32_V_MF2_MF8,
10562 : PseudoVSUXEI32_V_MF2_MF8_MASK,
10563 : PseudoVSUXEI64_V_M1_M1,
10564 : PseudoVSUXEI64_V_M1_M1_MASK,
10565 : PseudoVSUXEI64_V_M1_MF2,
10566 : PseudoVSUXEI64_V_M1_MF2_MASK,
10567 : PseudoVSUXEI64_V_M1_MF4,
10568 : PseudoVSUXEI64_V_M1_MF4_MASK,
10569 : PseudoVSUXEI64_V_M1_MF8,
10570 : PseudoVSUXEI64_V_M1_MF8_MASK,
10571 : PseudoVSUXEI64_V_M2_M1,
10572 : PseudoVSUXEI64_V_M2_M1_MASK,
10573 : PseudoVSUXEI64_V_M2_M2,
10574 : PseudoVSUXEI64_V_M2_M2_MASK,
10575 : PseudoVSUXEI64_V_M2_MF2,
10576 : PseudoVSUXEI64_V_M2_MF2_MASK,
10577 : PseudoVSUXEI64_V_M2_MF4,
10578 : PseudoVSUXEI64_V_M2_MF4_MASK,
10579 : PseudoVSUXEI64_V_M4_M1,
10580 : PseudoVSUXEI64_V_M4_M1_MASK,
10581 : PseudoVSUXEI64_V_M4_M2,
10582 : PseudoVSUXEI64_V_M4_M2_MASK,
10583 : PseudoVSUXEI64_V_M4_M4,
10584 : PseudoVSUXEI64_V_M4_M4_MASK,
10585 : PseudoVSUXEI64_V_M4_MF2,
10586 : PseudoVSUXEI64_V_M4_MF2_MASK,
10587 : PseudoVSUXEI64_V_M8_M1,
10588 : PseudoVSUXEI64_V_M8_M1_MASK,
10589 : PseudoVSUXEI64_V_M8_M2,
10590 : PseudoVSUXEI64_V_M8_M2_MASK,
10591 : PseudoVSUXEI64_V_M8_M4,
10592 : PseudoVSUXEI64_V_M8_M4_MASK,
10593 : PseudoVSUXEI64_V_M8_M8,
10594 : PseudoVSUXEI64_V_M8_M8_MASK,
10595 : PseudoVSUXEI8_V_M1_M1,
10596 : PseudoVSUXEI8_V_M1_M1_MASK,
10597 : PseudoVSUXEI8_V_M1_M2,
10598 : PseudoVSUXEI8_V_M1_M2_MASK,
10599 : PseudoVSUXEI8_V_M1_M4,
10600 : PseudoVSUXEI8_V_M1_M4_MASK,
10601 : PseudoVSUXEI8_V_M1_M8,
10602 : PseudoVSUXEI8_V_M1_M8_MASK,
10603 : PseudoVSUXEI8_V_M2_M2,
10604 : PseudoVSUXEI8_V_M2_M2_MASK,
10605 : PseudoVSUXEI8_V_M2_M4,
10606 : PseudoVSUXEI8_V_M2_M4_MASK,
10607 : PseudoVSUXEI8_V_M2_M8,
10608 : PseudoVSUXEI8_V_M2_M8_MASK,
10609 : PseudoVSUXEI8_V_M4_M4,
10610 : PseudoVSUXEI8_V_M4_M4_MASK,
10611 : PseudoVSUXEI8_V_M4_M8,
10612 : PseudoVSUXEI8_V_M4_M8_MASK,
10613 : PseudoVSUXEI8_V_M8_M8,
10614 : PseudoVSUXEI8_V_M8_M8_MASK,
10615 : PseudoVSUXEI8_V_MF2_M1,
10616 : PseudoVSUXEI8_V_MF2_M1_MASK,
10617 : PseudoVSUXEI8_V_MF2_M2,
10618 : PseudoVSUXEI8_V_MF2_M2_MASK,
10619 : PseudoVSUXEI8_V_MF2_M4,
10620 : PseudoVSUXEI8_V_MF2_M4_MASK,
10621 : PseudoVSUXEI8_V_MF2_MF2,
10622 : PseudoVSUXEI8_V_MF2_MF2_MASK,
10623 : PseudoVSUXEI8_V_MF4_M1,
10624 : PseudoVSUXEI8_V_MF4_M1_MASK,
10625 : PseudoVSUXEI8_V_MF4_M2,
10626 : PseudoVSUXEI8_V_MF4_M2_MASK,
10627 : PseudoVSUXEI8_V_MF4_MF2,
10628 : PseudoVSUXEI8_V_MF4_MF2_MASK,
10629 : PseudoVSUXEI8_V_MF4_MF4,
10630 : PseudoVSUXEI8_V_MF4_MF4_MASK,
10631 : PseudoVSUXEI8_V_MF8_M1,
10632 : PseudoVSUXEI8_V_MF8_M1_MASK,
10633 : PseudoVSUXEI8_V_MF8_MF2,
10634 : PseudoVSUXEI8_V_MF8_MF2_MASK,
10635 : PseudoVSUXEI8_V_MF8_MF4,
10636 : PseudoVSUXEI8_V_MF8_MF4_MASK,
10637 : PseudoVSUXEI8_V_MF8_MF8,
10638 : PseudoVSUXEI8_V_MF8_MF8_MASK,
10639 : PseudoVSUXSEG2EI16_V_M1_M1,
10640 : PseudoVSUXSEG2EI16_V_M1_M1_MASK,
10641 : PseudoVSUXSEG2EI16_V_M1_M2,
10642 : PseudoVSUXSEG2EI16_V_M1_M2_MASK,
10643 : PseudoVSUXSEG2EI16_V_M1_M4,
10644 : PseudoVSUXSEG2EI16_V_M1_M4_MASK,
10645 : PseudoVSUXSEG2EI16_V_M1_MF2,
10646 : PseudoVSUXSEG2EI16_V_M1_MF2_MASK,
10647 : PseudoVSUXSEG2EI16_V_M2_M1,
10648 : PseudoVSUXSEG2EI16_V_M2_M1_MASK,
10649 : PseudoVSUXSEG2EI16_V_M2_M2,
10650 : PseudoVSUXSEG2EI16_V_M2_M2_MASK,
10651 : PseudoVSUXSEG2EI16_V_M2_M4,
10652 : PseudoVSUXSEG2EI16_V_M2_M4_MASK,
10653 : PseudoVSUXSEG2EI16_V_M4_M2,
10654 : PseudoVSUXSEG2EI16_V_M4_M2_MASK,
10655 : PseudoVSUXSEG2EI16_V_M4_M4,
10656 : PseudoVSUXSEG2EI16_V_M4_M4_MASK,
10657 : PseudoVSUXSEG2EI16_V_M8_M4,
10658 : PseudoVSUXSEG2EI16_V_M8_M4_MASK,
10659 : PseudoVSUXSEG2EI16_V_MF2_M1,
10660 : PseudoVSUXSEG2EI16_V_MF2_M1_MASK,
10661 : PseudoVSUXSEG2EI16_V_MF2_M2,
10662 : PseudoVSUXSEG2EI16_V_MF2_M2_MASK,
10663 : PseudoVSUXSEG2EI16_V_MF2_MF2,
10664 : PseudoVSUXSEG2EI16_V_MF2_MF2_MASK,
10665 : PseudoVSUXSEG2EI16_V_MF2_MF4,
10666 : PseudoVSUXSEG2EI16_V_MF2_MF4_MASK,
10667 : PseudoVSUXSEG2EI16_V_MF4_M1,
10668 : PseudoVSUXSEG2EI16_V_MF4_M1_MASK,
10669 : PseudoVSUXSEG2EI16_V_MF4_MF2,
10670 : PseudoVSUXSEG2EI16_V_MF4_MF2_MASK,
10671 : PseudoVSUXSEG2EI16_V_MF4_MF4,
10672 : PseudoVSUXSEG2EI16_V_MF4_MF4_MASK,
10673 : PseudoVSUXSEG2EI16_V_MF4_MF8,
10674 : PseudoVSUXSEG2EI16_V_MF4_MF8_MASK,
10675 : PseudoVSUXSEG2EI32_V_M1_M1,
10676 : PseudoVSUXSEG2EI32_V_M1_M1_MASK,
10677 : PseudoVSUXSEG2EI32_V_M1_M2,
10678 : PseudoVSUXSEG2EI32_V_M1_M2_MASK,
10679 : PseudoVSUXSEG2EI32_V_M1_MF2,
10680 : PseudoVSUXSEG2EI32_V_M1_MF2_MASK,
10681 : PseudoVSUXSEG2EI32_V_M1_MF4,
10682 : PseudoVSUXSEG2EI32_V_M1_MF4_MASK,
10683 : PseudoVSUXSEG2EI32_V_M2_M1,
10684 : PseudoVSUXSEG2EI32_V_M2_M1_MASK,
10685 : PseudoVSUXSEG2EI32_V_M2_M2,
10686 : PseudoVSUXSEG2EI32_V_M2_M2_MASK,
10687 : PseudoVSUXSEG2EI32_V_M2_M4,
10688 : PseudoVSUXSEG2EI32_V_M2_M4_MASK,
10689 : PseudoVSUXSEG2EI32_V_M2_MF2,
10690 : PseudoVSUXSEG2EI32_V_M2_MF2_MASK,
10691 : PseudoVSUXSEG2EI32_V_M4_M1,
10692 : PseudoVSUXSEG2EI32_V_M4_M1_MASK,
10693 : PseudoVSUXSEG2EI32_V_M4_M2,
10694 : PseudoVSUXSEG2EI32_V_M4_M2_MASK,
10695 : PseudoVSUXSEG2EI32_V_M4_M4,
10696 : PseudoVSUXSEG2EI32_V_M4_M4_MASK,
10697 : PseudoVSUXSEG2EI32_V_M8_M2,
10698 : PseudoVSUXSEG2EI32_V_M8_M2_MASK,
10699 : PseudoVSUXSEG2EI32_V_M8_M4,
10700 : PseudoVSUXSEG2EI32_V_M8_M4_MASK,
10701 : PseudoVSUXSEG2EI32_V_MF2_M1,
10702 : PseudoVSUXSEG2EI32_V_MF2_M1_MASK,
10703 : PseudoVSUXSEG2EI32_V_MF2_MF2,
10704 : PseudoVSUXSEG2EI32_V_MF2_MF2_MASK,
10705 : PseudoVSUXSEG2EI32_V_MF2_MF4,
10706 : PseudoVSUXSEG2EI32_V_MF2_MF4_MASK,
10707 : PseudoVSUXSEG2EI32_V_MF2_MF8,
10708 : PseudoVSUXSEG2EI32_V_MF2_MF8_MASK,
10709 : PseudoVSUXSEG2EI64_V_M1_M1,
10710 : PseudoVSUXSEG2EI64_V_M1_M1_MASK,
10711 : PseudoVSUXSEG2EI64_V_M1_MF2,
10712 : PseudoVSUXSEG2EI64_V_M1_MF2_MASK,
10713 : PseudoVSUXSEG2EI64_V_M1_MF4,
10714 : PseudoVSUXSEG2EI64_V_M1_MF4_MASK,
10715 : PseudoVSUXSEG2EI64_V_M1_MF8,
10716 : PseudoVSUXSEG2EI64_V_M1_MF8_MASK,
10717 : PseudoVSUXSEG2EI64_V_M2_M1,
10718 : PseudoVSUXSEG2EI64_V_M2_M1_MASK,
10719 : PseudoVSUXSEG2EI64_V_M2_M2,
10720 : PseudoVSUXSEG2EI64_V_M2_M2_MASK,
10721 : PseudoVSUXSEG2EI64_V_M2_MF2,
10722 : PseudoVSUXSEG2EI64_V_M2_MF2_MASK,
10723 : PseudoVSUXSEG2EI64_V_M2_MF4,
10724 : PseudoVSUXSEG2EI64_V_M2_MF4_MASK,
10725 : PseudoVSUXSEG2EI64_V_M4_M1,
10726 : PseudoVSUXSEG2EI64_V_M4_M1_MASK,
10727 : PseudoVSUXSEG2EI64_V_M4_M2,
10728 : PseudoVSUXSEG2EI64_V_M4_M2_MASK,
10729 : PseudoVSUXSEG2EI64_V_M4_M4,
10730 : PseudoVSUXSEG2EI64_V_M4_M4_MASK,
10731 : PseudoVSUXSEG2EI64_V_M4_MF2,
10732 : PseudoVSUXSEG2EI64_V_M4_MF2_MASK,
10733 : PseudoVSUXSEG2EI64_V_M8_M1,
10734 : PseudoVSUXSEG2EI64_V_M8_M1_MASK,
10735 : PseudoVSUXSEG2EI64_V_M8_M2,
10736 : PseudoVSUXSEG2EI64_V_M8_M2_MASK,
10737 : PseudoVSUXSEG2EI64_V_M8_M4,
10738 : PseudoVSUXSEG2EI64_V_M8_M4_MASK,
10739 : PseudoVSUXSEG2EI8_V_M1_M1,
10740 : PseudoVSUXSEG2EI8_V_M1_M1_MASK,
10741 : PseudoVSUXSEG2EI8_V_M1_M2,
10742 : PseudoVSUXSEG2EI8_V_M1_M2_MASK,
10743 : PseudoVSUXSEG2EI8_V_M1_M4,
10744 : PseudoVSUXSEG2EI8_V_M1_M4_MASK,
10745 : PseudoVSUXSEG2EI8_V_M2_M2,
10746 : PseudoVSUXSEG2EI8_V_M2_M2_MASK,
10747 : PseudoVSUXSEG2EI8_V_M2_M4,
10748 : PseudoVSUXSEG2EI8_V_M2_M4_MASK,
10749 : PseudoVSUXSEG2EI8_V_M4_M4,
10750 : PseudoVSUXSEG2EI8_V_M4_M4_MASK,
10751 : PseudoVSUXSEG2EI8_V_MF2_M1,
10752 : PseudoVSUXSEG2EI8_V_MF2_M1_MASK,
10753 : PseudoVSUXSEG2EI8_V_MF2_M2,
10754 : PseudoVSUXSEG2EI8_V_MF2_M2_MASK,
10755 : PseudoVSUXSEG2EI8_V_MF2_M4,
10756 : PseudoVSUXSEG2EI8_V_MF2_M4_MASK,
10757 : PseudoVSUXSEG2EI8_V_MF2_MF2,
10758 : PseudoVSUXSEG2EI8_V_MF2_MF2_MASK,
10759 : PseudoVSUXSEG2EI8_V_MF4_M1,
10760 : PseudoVSUXSEG2EI8_V_MF4_M1_MASK,
10761 : PseudoVSUXSEG2EI8_V_MF4_M2,
10762 : PseudoVSUXSEG2EI8_V_MF4_M2_MASK,
10763 : PseudoVSUXSEG2EI8_V_MF4_MF2,
10764 : PseudoVSUXSEG2EI8_V_MF4_MF2_MASK,
10765 : PseudoVSUXSEG2EI8_V_MF4_MF4,
10766 : PseudoVSUXSEG2EI8_V_MF4_MF4_MASK,
10767 : PseudoVSUXSEG2EI8_V_MF8_M1,
10768 : PseudoVSUXSEG2EI8_V_MF8_M1_MASK,
10769 : PseudoVSUXSEG2EI8_V_MF8_MF2,
10770 : PseudoVSUXSEG2EI8_V_MF8_MF2_MASK,
10771 : PseudoVSUXSEG2EI8_V_MF8_MF4,
10772 : PseudoVSUXSEG2EI8_V_MF8_MF4_MASK,
10773 : PseudoVSUXSEG2EI8_V_MF8_MF8,
10774 : PseudoVSUXSEG2EI8_V_MF8_MF8_MASK,
10775 : PseudoVSUXSEG3EI16_V_M1_M1,
10776 : PseudoVSUXSEG3EI16_V_M1_M1_MASK,
10777 : PseudoVSUXSEG3EI16_V_M1_M2,
10778 : PseudoVSUXSEG3EI16_V_M1_M2_MASK,
10779 : PseudoVSUXSEG3EI16_V_M1_MF2,
10780 : PseudoVSUXSEG3EI16_V_M1_MF2_MASK,
10781 : PseudoVSUXSEG3EI16_V_M2_M1,
10782 : PseudoVSUXSEG3EI16_V_M2_M1_MASK,
10783 : PseudoVSUXSEG3EI16_V_M2_M2,
10784 : PseudoVSUXSEG3EI16_V_M2_M2_MASK,
10785 : PseudoVSUXSEG3EI16_V_M4_M2,
10786 : PseudoVSUXSEG3EI16_V_M4_M2_MASK,
10787 : PseudoVSUXSEG3EI16_V_MF2_M1,
10788 : PseudoVSUXSEG3EI16_V_MF2_M1_MASK,
10789 : PseudoVSUXSEG3EI16_V_MF2_M2,
10790 : PseudoVSUXSEG3EI16_V_MF2_M2_MASK,
10791 : PseudoVSUXSEG3EI16_V_MF2_MF2,
10792 : PseudoVSUXSEG3EI16_V_MF2_MF2_MASK,
10793 : PseudoVSUXSEG3EI16_V_MF2_MF4,
10794 : PseudoVSUXSEG3EI16_V_MF2_MF4_MASK,
10795 : PseudoVSUXSEG3EI16_V_MF4_M1,
10796 : PseudoVSUXSEG3EI16_V_MF4_M1_MASK,
10797 : PseudoVSUXSEG3EI16_V_MF4_MF2,
10798 : PseudoVSUXSEG3EI16_V_MF4_MF2_MASK,
10799 : PseudoVSUXSEG3EI16_V_MF4_MF4,
10800 : PseudoVSUXSEG3EI16_V_MF4_MF4_MASK,
10801 : PseudoVSUXSEG3EI16_V_MF4_MF8,
10802 : PseudoVSUXSEG3EI16_V_MF4_MF8_MASK,
10803 : PseudoVSUXSEG3EI32_V_M1_M1,
10804 : PseudoVSUXSEG3EI32_V_M1_M1_MASK,
10805 : PseudoVSUXSEG3EI32_V_M1_M2,
10806 : PseudoVSUXSEG3EI32_V_M1_M2_MASK,
10807 : PseudoVSUXSEG3EI32_V_M1_MF2,
10808 : PseudoVSUXSEG3EI32_V_M1_MF2_MASK,
10809 : PseudoVSUXSEG3EI32_V_M1_MF4,
10810 : PseudoVSUXSEG3EI32_V_M1_MF4_MASK,
10811 : PseudoVSUXSEG3EI32_V_M2_M1,
10812 : PseudoVSUXSEG3EI32_V_M2_M1_MASK,
10813 : PseudoVSUXSEG3EI32_V_M2_M2,
10814 : PseudoVSUXSEG3EI32_V_M2_M2_MASK,
10815 : PseudoVSUXSEG3EI32_V_M2_MF2,
10816 : PseudoVSUXSEG3EI32_V_M2_MF2_MASK,
10817 : PseudoVSUXSEG3EI32_V_M4_M1,
10818 : PseudoVSUXSEG3EI32_V_M4_M1_MASK,
10819 : PseudoVSUXSEG3EI32_V_M4_M2,
10820 : PseudoVSUXSEG3EI32_V_M4_M2_MASK,
10821 : PseudoVSUXSEG3EI32_V_M8_M2,
10822 : PseudoVSUXSEG3EI32_V_M8_M2_MASK,
10823 : PseudoVSUXSEG3EI32_V_MF2_M1,
10824 : PseudoVSUXSEG3EI32_V_MF2_M1_MASK,
10825 : PseudoVSUXSEG3EI32_V_MF2_MF2,
10826 : PseudoVSUXSEG3EI32_V_MF2_MF2_MASK,
10827 : PseudoVSUXSEG3EI32_V_MF2_MF4,
10828 : PseudoVSUXSEG3EI32_V_MF2_MF4_MASK,
10829 : PseudoVSUXSEG3EI32_V_MF2_MF8,
10830 : PseudoVSUXSEG3EI32_V_MF2_MF8_MASK,
10831 : PseudoVSUXSEG3EI64_V_M1_M1,
10832 : PseudoVSUXSEG3EI64_V_M1_M1_MASK,
10833 : PseudoVSUXSEG3EI64_V_M1_MF2,
10834 : PseudoVSUXSEG3EI64_V_M1_MF2_MASK,
10835 : PseudoVSUXSEG3EI64_V_M1_MF4,
10836 : PseudoVSUXSEG3EI64_V_M1_MF4_MASK,
10837 : PseudoVSUXSEG3EI64_V_M1_MF8,
10838 : PseudoVSUXSEG3EI64_V_M1_MF8_MASK,
10839 : PseudoVSUXSEG3EI64_V_M2_M1,
10840 : PseudoVSUXSEG3EI64_V_M2_M1_MASK,
10841 : PseudoVSUXSEG3EI64_V_M2_M2,
10842 : PseudoVSUXSEG3EI64_V_M2_M2_MASK,
10843 : PseudoVSUXSEG3EI64_V_M2_MF2,
10844 : PseudoVSUXSEG3EI64_V_M2_MF2_MASK,
10845 : PseudoVSUXSEG3EI64_V_M2_MF4,
10846 : PseudoVSUXSEG3EI64_V_M2_MF4_MASK,
10847 : PseudoVSUXSEG3EI64_V_M4_M1,
10848 : PseudoVSUXSEG3EI64_V_M4_M1_MASK,
10849 : PseudoVSUXSEG3EI64_V_M4_M2,
10850 : PseudoVSUXSEG3EI64_V_M4_M2_MASK,
10851 : PseudoVSUXSEG3EI64_V_M4_MF2,
10852 : PseudoVSUXSEG3EI64_V_M4_MF2_MASK,
10853 : PseudoVSUXSEG3EI64_V_M8_M1,
10854 : PseudoVSUXSEG3EI64_V_M8_M1_MASK,
10855 : PseudoVSUXSEG3EI64_V_M8_M2,
10856 : PseudoVSUXSEG3EI64_V_M8_M2_MASK,
10857 : PseudoVSUXSEG3EI8_V_M1_M1,
10858 : PseudoVSUXSEG3EI8_V_M1_M1_MASK,
10859 : PseudoVSUXSEG3EI8_V_M1_M2,
10860 : PseudoVSUXSEG3EI8_V_M1_M2_MASK,
10861 : PseudoVSUXSEG3EI8_V_M2_M2,
10862 : PseudoVSUXSEG3EI8_V_M2_M2_MASK,
10863 : PseudoVSUXSEG3EI8_V_MF2_M1,
10864 : PseudoVSUXSEG3EI8_V_MF2_M1_MASK,
10865 : PseudoVSUXSEG3EI8_V_MF2_M2,
10866 : PseudoVSUXSEG3EI8_V_MF2_M2_MASK,
10867 : PseudoVSUXSEG3EI8_V_MF2_MF2,
10868 : PseudoVSUXSEG3EI8_V_MF2_MF2_MASK,
10869 : PseudoVSUXSEG3EI8_V_MF4_M1,
10870 : PseudoVSUXSEG3EI8_V_MF4_M1_MASK,
10871 : PseudoVSUXSEG3EI8_V_MF4_M2,
10872 : PseudoVSUXSEG3EI8_V_MF4_M2_MASK,
10873 : PseudoVSUXSEG3EI8_V_MF4_MF2,
10874 : PseudoVSUXSEG3EI8_V_MF4_MF2_MASK,
10875 : PseudoVSUXSEG3EI8_V_MF4_MF4,
10876 : PseudoVSUXSEG3EI8_V_MF4_MF4_MASK,
10877 : PseudoVSUXSEG3EI8_V_MF8_M1,
10878 : PseudoVSUXSEG3EI8_V_MF8_M1_MASK,
10879 : PseudoVSUXSEG3EI8_V_MF8_MF2,
10880 : PseudoVSUXSEG3EI8_V_MF8_MF2_MASK,
10881 : PseudoVSUXSEG3EI8_V_MF8_MF4,
10882 : PseudoVSUXSEG3EI8_V_MF8_MF4_MASK,
10883 : PseudoVSUXSEG3EI8_V_MF8_MF8,
10884 : PseudoVSUXSEG3EI8_V_MF8_MF8_MASK,
10885 : PseudoVSUXSEG4EI16_V_M1_M1,
10886 : PseudoVSUXSEG4EI16_V_M1_M1_MASK,
10887 : PseudoVSUXSEG4EI16_V_M1_M2,
10888 : PseudoVSUXSEG4EI16_V_M1_M2_MASK,
10889 : PseudoVSUXSEG4EI16_V_M1_MF2,
10890 : PseudoVSUXSEG4EI16_V_M1_MF2_MASK,
10891 : PseudoVSUXSEG4EI16_V_M2_M1,
10892 : PseudoVSUXSEG4EI16_V_M2_M1_MASK,
10893 : PseudoVSUXSEG4EI16_V_M2_M2,
10894 : PseudoVSUXSEG4EI16_V_M2_M2_MASK,
10895 : PseudoVSUXSEG4EI16_V_M4_M2,
10896 : PseudoVSUXSEG4EI16_V_M4_M2_MASK,
10897 : PseudoVSUXSEG4EI16_V_MF2_M1,
10898 : PseudoVSUXSEG4EI16_V_MF2_M1_MASK,
10899 : PseudoVSUXSEG4EI16_V_MF2_M2,
10900 : PseudoVSUXSEG4EI16_V_MF2_M2_MASK,
10901 : PseudoVSUXSEG4EI16_V_MF2_MF2,
10902 : PseudoVSUXSEG4EI16_V_MF2_MF2_MASK,
10903 : PseudoVSUXSEG4EI16_V_MF2_MF4,
10904 : PseudoVSUXSEG4EI16_V_MF2_MF4_MASK,
10905 : PseudoVSUXSEG4EI16_V_MF4_M1,
10906 : PseudoVSUXSEG4EI16_V_MF4_M1_MASK,
10907 : PseudoVSUXSEG4EI16_V_MF4_MF2,
10908 : PseudoVSUXSEG4EI16_V_MF4_MF2_MASK,
10909 : PseudoVSUXSEG4EI16_V_MF4_MF4,
10910 : PseudoVSUXSEG4EI16_V_MF4_MF4_MASK,
10911 : PseudoVSUXSEG4EI16_V_MF4_MF8,
10912 : PseudoVSUXSEG4EI16_V_MF4_MF8_MASK,
10913 : PseudoVSUXSEG4EI32_V_M1_M1,
10914 : PseudoVSUXSEG4EI32_V_M1_M1_MASK,
10915 : PseudoVSUXSEG4EI32_V_M1_M2,
10916 : PseudoVSUXSEG4EI32_V_M1_M2_MASK,
10917 : PseudoVSUXSEG4EI32_V_M1_MF2,
10918 : PseudoVSUXSEG4EI32_V_M1_MF2_MASK,
10919 : PseudoVSUXSEG4EI32_V_M1_MF4,
10920 : PseudoVSUXSEG4EI32_V_M1_MF4_MASK,
10921 : PseudoVSUXSEG4EI32_V_M2_M1,
10922 : PseudoVSUXSEG4EI32_V_M2_M1_MASK,
10923 : PseudoVSUXSEG4EI32_V_M2_M2,
10924 : PseudoVSUXSEG4EI32_V_M2_M2_MASK,
10925 : PseudoVSUXSEG4EI32_V_M2_MF2,
10926 : PseudoVSUXSEG4EI32_V_M2_MF2_MASK,
10927 : PseudoVSUXSEG4EI32_V_M4_M1,
10928 : PseudoVSUXSEG4EI32_V_M4_M1_MASK,
10929 : PseudoVSUXSEG4EI32_V_M4_M2,
10930 : PseudoVSUXSEG4EI32_V_M4_M2_MASK,
10931 : PseudoVSUXSEG4EI32_V_M8_M2,
10932 : PseudoVSUXSEG4EI32_V_M8_M2_MASK,
10933 : PseudoVSUXSEG4EI32_V_MF2_M1,
10934 : PseudoVSUXSEG4EI32_V_MF2_M1_MASK,
10935 : PseudoVSUXSEG4EI32_V_MF2_MF2,
10936 : PseudoVSUXSEG4EI32_V_MF2_MF2_MASK,
10937 : PseudoVSUXSEG4EI32_V_MF2_MF4,
10938 : PseudoVSUXSEG4EI32_V_MF2_MF4_MASK,
10939 : PseudoVSUXSEG4EI32_V_MF2_MF8,
10940 : PseudoVSUXSEG4EI32_V_MF2_MF8_MASK,
10941 : PseudoVSUXSEG4EI64_V_M1_M1,
10942 : PseudoVSUXSEG4EI64_V_M1_M1_MASK,
10943 : PseudoVSUXSEG4EI64_V_M1_MF2,
10944 : PseudoVSUXSEG4EI64_V_M1_MF2_MASK,
10945 : PseudoVSUXSEG4EI64_V_M1_MF4,
10946 : PseudoVSUXSEG4EI64_V_M1_MF4_MASK,
10947 : PseudoVSUXSEG4EI64_V_M1_MF8,
10948 : PseudoVSUXSEG4EI64_V_M1_MF8_MASK,
10949 : PseudoVSUXSEG4EI64_V_M2_M1,
10950 : PseudoVSUXSEG4EI64_V_M2_M1_MASK,
10951 : PseudoVSUXSEG4EI64_V_M2_M2,
10952 : PseudoVSUXSEG4EI64_V_M2_M2_MASK,
10953 : PseudoVSUXSEG4EI64_V_M2_MF2,
10954 : PseudoVSUXSEG4EI64_V_M2_MF2_MASK,
10955 : PseudoVSUXSEG4EI64_V_M2_MF4,
10956 : PseudoVSUXSEG4EI64_V_M2_MF4_MASK,
10957 : PseudoVSUXSEG4EI64_V_M4_M1,
10958 : PseudoVSUXSEG4EI64_V_M4_M1_MASK,
10959 : PseudoVSUXSEG4EI64_V_M4_M2,
10960 : PseudoVSUXSEG4EI64_V_M4_M2_MASK,
10961 : PseudoVSUXSEG4EI64_V_M4_MF2,
10962 : PseudoVSUXSEG4EI64_V_M4_MF2_MASK,
10963 : PseudoVSUXSEG4EI64_V_M8_M1,
10964 : PseudoVSUXSEG4EI64_V_M8_M1_MASK,
10965 : PseudoVSUXSEG4EI64_V_M8_M2,
10966 : PseudoVSUXSEG4EI64_V_M8_M2_MASK,
10967 : PseudoVSUXSEG4EI8_V_M1_M1,
10968 : PseudoVSUXSEG4EI8_V_M1_M1_MASK,
10969 : PseudoVSUXSEG4EI8_V_M1_M2,
10970 : PseudoVSUXSEG4EI8_V_M1_M2_MASK,
10971 : PseudoVSUXSEG4EI8_V_M2_M2,
10972 : PseudoVSUXSEG4EI8_V_M2_M2_MASK,
10973 : PseudoVSUXSEG4EI8_V_MF2_M1,
10974 : PseudoVSUXSEG4EI8_V_MF2_M1_MASK,
10975 : PseudoVSUXSEG4EI8_V_MF2_M2,
10976 : PseudoVSUXSEG4EI8_V_MF2_M2_MASK,
10977 : PseudoVSUXSEG4EI8_V_MF2_MF2,
10978 : PseudoVSUXSEG4EI8_V_MF2_MF2_MASK,
10979 : PseudoVSUXSEG4EI8_V_MF4_M1,
10980 : PseudoVSUXSEG4EI8_V_MF4_M1_MASK,
10981 : PseudoVSUXSEG4EI8_V_MF4_M2,
10982 : PseudoVSUXSEG4EI8_V_MF4_M2_MASK,
10983 : PseudoVSUXSEG4EI8_V_MF4_MF2,
10984 : PseudoVSUXSEG4EI8_V_MF4_MF2_MASK,
10985 : PseudoVSUXSEG4EI8_V_MF4_MF4,
10986 : PseudoVSUXSEG4EI8_V_MF4_MF4_MASK,
10987 : PseudoVSUXSEG4EI8_V_MF8_M1,
10988 : PseudoVSUXSEG4EI8_V_MF8_M1_MASK,
10989 : PseudoVSUXSEG4EI8_V_MF8_MF2,
10990 : PseudoVSUXSEG4EI8_V_MF8_MF2_MASK,
10991 : PseudoVSUXSEG4EI8_V_MF8_MF4,
10992 : PseudoVSUXSEG4EI8_V_MF8_MF4_MASK,
10993 : PseudoVSUXSEG4EI8_V_MF8_MF8,
10994 : PseudoVSUXSEG4EI8_V_MF8_MF8_MASK,
10995 : PseudoVSUXSEG5EI16_V_M1_M1,
10996 : PseudoVSUXSEG5EI16_V_M1_M1_MASK,
10997 : PseudoVSUXSEG5EI16_V_M1_MF2,
10998 : PseudoVSUXSEG5EI16_V_M1_MF2_MASK,
10999 : PseudoVSUXSEG5EI16_V_M2_M1,
11000 : PseudoVSUXSEG5EI16_V_M2_M1_MASK,
11001 : PseudoVSUXSEG5EI16_V_MF2_M1,
11002 : PseudoVSUXSEG5EI16_V_MF2_M1_MASK,
11003 : PseudoVSUXSEG5EI16_V_MF2_MF2,
11004 : PseudoVSUXSEG5EI16_V_MF2_MF2_MASK,
11005 : PseudoVSUXSEG5EI16_V_MF2_MF4,
11006 : PseudoVSUXSEG5EI16_V_MF2_MF4_MASK,
11007 : PseudoVSUXSEG5EI16_V_MF4_M1,
11008 : PseudoVSUXSEG5EI16_V_MF4_M1_MASK,
11009 : PseudoVSUXSEG5EI16_V_MF4_MF2,
11010 : PseudoVSUXSEG5EI16_V_MF4_MF2_MASK,
11011 : PseudoVSUXSEG5EI16_V_MF4_MF4,
11012 : PseudoVSUXSEG5EI16_V_MF4_MF4_MASK,
11013 : PseudoVSUXSEG5EI16_V_MF4_MF8,
11014 : PseudoVSUXSEG5EI16_V_MF4_MF8_MASK,
11015 : PseudoVSUXSEG5EI32_V_M1_M1,
11016 : PseudoVSUXSEG5EI32_V_M1_M1_MASK,
11017 : PseudoVSUXSEG5EI32_V_M1_MF2,
11018 : PseudoVSUXSEG5EI32_V_M1_MF2_MASK,
11019 : PseudoVSUXSEG5EI32_V_M1_MF4,
11020 : PseudoVSUXSEG5EI32_V_M1_MF4_MASK,
11021 : PseudoVSUXSEG5EI32_V_M2_M1,
11022 : PseudoVSUXSEG5EI32_V_M2_M1_MASK,
11023 : PseudoVSUXSEG5EI32_V_M2_MF2,
11024 : PseudoVSUXSEG5EI32_V_M2_MF2_MASK,
11025 : PseudoVSUXSEG5EI32_V_M4_M1,
11026 : PseudoVSUXSEG5EI32_V_M4_M1_MASK,
11027 : PseudoVSUXSEG5EI32_V_MF2_M1,
11028 : PseudoVSUXSEG5EI32_V_MF2_M1_MASK,
11029 : PseudoVSUXSEG5EI32_V_MF2_MF2,
11030 : PseudoVSUXSEG5EI32_V_MF2_MF2_MASK,
11031 : PseudoVSUXSEG5EI32_V_MF2_MF4,
11032 : PseudoVSUXSEG5EI32_V_MF2_MF4_MASK,
11033 : PseudoVSUXSEG5EI32_V_MF2_MF8,
11034 : PseudoVSUXSEG5EI32_V_MF2_MF8_MASK,
11035 : PseudoVSUXSEG5EI64_V_M1_M1,
11036 : PseudoVSUXSEG5EI64_V_M1_M1_MASK,
11037 : PseudoVSUXSEG5EI64_V_M1_MF2,
11038 : PseudoVSUXSEG5EI64_V_M1_MF2_MASK,
11039 : PseudoVSUXSEG5EI64_V_M1_MF4,
11040 : PseudoVSUXSEG5EI64_V_M1_MF4_MASK,
11041 : PseudoVSUXSEG5EI64_V_M1_MF8,
11042 : PseudoVSUXSEG5EI64_V_M1_MF8_MASK,
11043 : PseudoVSUXSEG5EI64_V_M2_M1,
11044 : PseudoVSUXSEG5EI64_V_M2_M1_MASK,
11045 : PseudoVSUXSEG5EI64_V_M2_MF2,
11046 : PseudoVSUXSEG5EI64_V_M2_MF2_MASK,
11047 : PseudoVSUXSEG5EI64_V_M2_MF4,
11048 : PseudoVSUXSEG5EI64_V_M2_MF4_MASK,
11049 : PseudoVSUXSEG5EI64_V_M4_M1,
11050 : PseudoVSUXSEG5EI64_V_M4_M1_MASK,
11051 : PseudoVSUXSEG5EI64_V_M4_MF2,
11052 : PseudoVSUXSEG5EI64_V_M4_MF2_MASK,
11053 : PseudoVSUXSEG5EI64_V_M8_M1,
11054 : PseudoVSUXSEG5EI64_V_M8_M1_MASK,
11055 : PseudoVSUXSEG5EI8_V_M1_M1,
11056 : PseudoVSUXSEG5EI8_V_M1_M1_MASK,
11057 : PseudoVSUXSEG5EI8_V_MF2_M1,
11058 : PseudoVSUXSEG5EI8_V_MF2_M1_MASK,
11059 : PseudoVSUXSEG5EI8_V_MF2_MF2,
11060 : PseudoVSUXSEG5EI8_V_MF2_MF2_MASK,
11061 : PseudoVSUXSEG5EI8_V_MF4_M1,
11062 : PseudoVSUXSEG5EI8_V_MF4_M1_MASK,
11063 : PseudoVSUXSEG5EI8_V_MF4_MF2,
11064 : PseudoVSUXSEG5EI8_V_MF4_MF2_MASK,
11065 : PseudoVSUXSEG5EI8_V_MF4_MF4,
11066 : PseudoVSUXSEG5EI8_V_MF4_MF4_MASK,
11067 : PseudoVSUXSEG5EI8_V_MF8_M1,
11068 : PseudoVSUXSEG5EI8_V_MF8_M1_MASK,
11069 : PseudoVSUXSEG5EI8_V_MF8_MF2,
11070 : PseudoVSUXSEG5EI8_V_MF8_MF2_MASK,
11071 : PseudoVSUXSEG5EI8_V_MF8_MF4,
11072 : PseudoVSUXSEG5EI8_V_MF8_MF4_MASK,
11073 : PseudoVSUXSEG5EI8_V_MF8_MF8,
11074 : PseudoVSUXSEG5EI8_V_MF8_MF8_MASK,
11075 : PseudoVSUXSEG6EI16_V_M1_M1,
11076 : PseudoVSUXSEG6EI16_V_M1_M1_MASK,
11077 : PseudoVSUXSEG6EI16_V_M1_MF2,
11078 : PseudoVSUXSEG6EI16_V_M1_MF2_MASK,
11079 : PseudoVSUXSEG6EI16_V_M2_M1,
11080 : PseudoVSUXSEG6EI16_V_M2_M1_MASK,
11081 : PseudoVSUXSEG6EI16_V_MF2_M1,
11082 : PseudoVSUXSEG6EI16_V_MF2_M1_MASK,
11083 : PseudoVSUXSEG6EI16_V_MF2_MF2,
11084 : PseudoVSUXSEG6EI16_V_MF2_MF2_MASK,
11085 : PseudoVSUXSEG6EI16_V_MF2_MF4,
11086 : PseudoVSUXSEG6EI16_V_MF2_MF4_MASK,
11087 : PseudoVSUXSEG6EI16_V_MF4_M1,
11088 : PseudoVSUXSEG6EI16_V_MF4_M1_MASK,
11089 : PseudoVSUXSEG6EI16_V_MF4_MF2,
11090 : PseudoVSUXSEG6EI16_V_MF4_MF2_MASK,
11091 : PseudoVSUXSEG6EI16_V_MF4_MF4,
11092 : PseudoVSUXSEG6EI16_V_MF4_MF4_MASK,
11093 : PseudoVSUXSEG6EI16_V_MF4_MF8,
11094 : PseudoVSUXSEG6EI16_V_MF4_MF8_MASK,
11095 : PseudoVSUXSEG6EI32_V_M1_M1,
11096 : PseudoVSUXSEG6EI32_V_M1_M1_MASK,
11097 : PseudoVSUXSEG6EI32_V_M1_MF2,
11098 : PseudoVSUXSEG6EI32_V_M1_MF2_MASK,
11099 : PseudoVSUXSEG6EI32_V_M1_MF4,
11100 : PseudoVSUXSEG6EI32_V_M1_MF4_MASK,
11101 : PseudoVSUXSEG6EI32_V_M2_M1,
11102 : PseudoVSUXSEG6EI32_V_M2_M1_MASK,
11103 : PseudoVSUXSEG6EI32_V_M2_MF2,
11104 : PseudoVSUXSEG6EI32_V_M2_MF2_MASK,
11105 : PseudoVSUXSEG6EI32_V_M4_M1,
11106 : PseudoVSUXSEG6EI32_V_M4_M1_MASK,
11107 : PseudoVSUXSEG6EI32_V_MF2_M1,
11108 : PseudoVSUXSEG6EI32_V_MF2_M1_MASK,
11109 : PseudoVSUXSEG6EI32_V_MF2_MF2,
11110 : PseudoVSUXSEG6EI32_V_MF2_MF2_MASK,
11111 : PseudoVSUXSEG6EI32_V_MF2_MF4,
11112 : PseudoVSUXSEG6EI32_V_MF2_MF4_MASK,
11113 : PseudoVSUXSEG6EI32_V_MF2_MF8,
11114 : PseudoVSUXSEG6EI32_V_MF2_MF8_MASK,
11115 : PseudoVSUXSEG6EI64_V_M1_M1,
11116 : PseudoVSUXSEG6EI64_V_M1_M1_MASK,
11117 : PseudoVSUXSEG6EI64_V_M1_MF2,
11118 : PseudoVSUXSEG6EI64_V_M1_MF2_MASK,
11119 : PseudoVSUXSEG6EI64_V_M1_MF4,
11120 : PseudoVSUXSEG6EI64_V_M1_MF4_MASK,
11121 : PseudoVSUXSEG6EI64_V_M1_MF8,
11122 : PseudoVSUXSEG6EI64_V_M1_MF8_MASK,
11123 : PseudoVSUXSEG6EI64_V_M2_M1,
11124 : PseudoVSUXSEG6EI64_V_M2_M1_MASK,
11125 : PseudoVSUXSEG6EI64_V_M2_MF2,
11126 : PseudoVSUXSEG6EI64_V_M2_MF2_MASK,
11127 : PseudoVSUXSEG6EI64_V_M2_MF4,
11128 : PseudoVSUXSEG6EI64_V_M2_MF4_MASK,
11129 : PseudoVSUXSEG6EI64_V_M4_M1,
11130 : PseudoVSUXSEG6EI64_V_M4_M1_MASK,
11131 : PseudoVSUXSEG6EI64_V_M4_MF2,
11132 : PseudoVSUXSEG6EI64_V_M4_MF2_MASK,
11133 : PseudoVSUXSEG6EI64_V_M8_M1,
11134 : PseudoVSUXSEG6EI64_V_M8_M1_MASK,
11135 : PseudoVSUXSEG6EI8_V_M1_M1,
11136 : PseudoVSUXSEG6EI8_V_M1_M1_MASK,
11137 : PseudoVSUXSEG6EI8_V_MF2_M1,
11138 : PseudoVSUXSEG6EI8_V_MF2_M1_MASK,
11139 : PseudoVSUXSEG6EI8_V_MF2_MF2,
11140 : PseudoVSUXSEG6EI8_V_MF2_MF2_MASK,
11141 : PseudoVSUXSEG6EI8_V_MF4_M1,
11142 : PseudoVSUXSEG6EI8_V_MF4_M1_MASK,
11143 : PseudoVSUXSEG6EI8_V_MF4_MF2,
11144 : PseudoVSUXSEG6EI8_V_MF4_MF2_MASK,
11145 : PseudoVSUXSEG6EI8_V_MF4_MF4,
11146 : PseudoVSUXSEG6EI8_V_MF4_MF4_MASK,
11147 : PseudoVSUXSEG6EI8_V_MF8_M1,
11148 : PseudoVSUXSEG6EI8_V_MF8_M1_MASK,
11149 : PseudoVSUXSEG6EI8_V_MF8_MF2,
11150 : PseudoVSUXSEG6EI8_V_MF8_MF2_MASK,
11151 : PseudoVSUXSEG6EI8_V_MF8_MF4,
11152 : PseudoVSUXSEG6EI8_V_MF8_MF4_MASK,
11153 : PseudoVSUXSEG6EI8_V_MF8_MF8,
11154 : PseudoVSUXSEG6EI8_V_MF8_MF8_MASK,
11155 : PseudoVSUXSEG7EI16_V_M1_M1,
11156 : PseudoVSUXSEG7EI16_V_M1_M1_MASK,
11157 : PseudoVSUXSEG7EI16_V_M1_MF2,
11158 : PseudoVSUXSEG7EI16_V_M1_MF2_MASK,
11159 : PseudoVSUXSEG7EI16_V_M2_M1,
11160 : PseudoVSUXSEG7EI16_V_M2_M1_MASK,
11161 : PseudoVSUXSEG7EI16_V_MF2_M1,
11162 : PseudoVSUXSEG7EI16_V_MF2_M1_MASK,
11163 : PseudoVSUXSEG7EI16_V_MF2_MF2,
11164 : PseudoVSUXSEG7EI16_V_MF2_MF2_MASK,
11165 : PseudoVSUXSEG7EI16_V_MF2_MF4,
11166 : PseudoVSUXSEG7EI16_V_MF2_MF4_MASK,
11167 : PseudoVSUXSEG7EI16_V_MF4_M1,
11168 : PseudoVSUXSEG7EI16_V_MF4_M1_MASK,
11169 : PseudoVSUXSEG7EI16_V_MF4_MF2,
11170 : PseudoVSUXSEG7EI16_V_MF4_MF2_MASK,
11171 : PseudoVSUXSEG7EI16_V_MF4_MF4,
11172 : PseudoVSUXSEG7EI16_V_MF4_MF4_MASK,
11173 : PseudoVSUXSEG7EI16_V_MF4_MF8,
11174 : PseudoVSUXSEG7EI16_V_MF4_MF8_MASK,
11175 : PseudoVSUXSEG7EI32_V_M1_M1,
11176 : PseudoVSUXSEG7EI32_V_M1_M1_MASK,
11177 : PseudoVSUXSEG7EI32_V_M1_MF2,
11178 : PseudoVSUXSEG7EI32_V_M1_MF2_MASK,
11179 : PseudoVSUXSEG7EI32_V_M1_MF4,
11180 : PseudoVSUXSEG7EI32_V_M1_MF4_MASK,
11181 : PseudoVSUXSEG7EI32_V_M2_M1,
11182 : PseudoVSUXSEG7EI32_V_M2_M1_MASK,
11183 : PseudoVSUXSEG7EI32_V_M2_MF2,
11184 : PseudoVSUXSEG7EI32_V_M2_MF2_MASK,
11185 : PseudoVSUXSEG7EI32_V_M4_M1,
11186 : PseudoVSUXSEG7EI32_V_M4_M1_MASK,
11187 : PseudoVSUXSEG7EI32_V_MF2_M1,
11188 : PseudoVSUXSEG7EI32_V_MF2_M1_MASK,
11189 : PseudoVSUXSEG7EI32_V_MF2_MF2,
11190 : PseudoVSUXSEG7EI32_V_MF2_MF2_MASK,
11191 : PseudoVSUXSEG7EI32_V_MF2_MF4,
11192 : PseudoVSUXSEG7EI32_V_MF2_MF4_MASK,
11193 : PseudoVSUXSEG7EI32_V_MF2_MF8,
11194 : PseudoVSUXSEG7EI32_V_MF2_MF8_MASK,
11195 : PseudoVSUXSEG7EI64_V_M1_M1,
11196 : PseudoVSUXSEG7EI64_V_M1_M1_MASK,
11197 : PseudoVSUXSEG7EI64_V_M1_MF2,
11198 : PseudoVSUXSEG7EI64_V_M1_MF2_MASK,
11199 : PseudoVSUXSEG7EI64_V_M1_MF4,
11200 : PseudoVSUXSEG7EI64_V_M1_MF4_MASK,
11201 : PseudoVSUXSEG7EI64_V_M1_MF8,
11202 : PseudoVSUXSEG7EI64_V_M1_MF8_MASK,
11203 : PseudoVSUXSEG7EI64_V_M2_M1,
11204 : PseudoVSUXSEG7EI64_V_M2_M1_MASK,
11205 : PseudoVSUXSEG7EI64_V_M2_MF2,
11206 : PseudoVSUXSEG7EI64_V_M2_MF2_MASK,
11207 : PseudoVSUXSEG7EI64_V_M2_MF4,
11208 : PseudoVSUXSEG7EI64_V_M2_MF4_MASK,
11209 : PseudoVSUXSEG7EI64_V_M4_M1,
11210 : PseudoVSUXSEG7EI64_V_M4_M1_MASK,
11211 : PseudoVSUXSEG7EI64_V_M4_MF2,
11212 : PseudoVSUXSEG7EI64_V_M4_MF2_MASK,
11213 : PseudoVSUXSEG7EI64_V_M8_M1,
11214 : PseudoVSUXSEG7EI64_V_M8_M1_MASK,
11215 : PseudoVSUXSEG7EI8_V_M1_M1,
11216 : PseudoVSUXSEG7EI8_V_M1_M1_MASK,
11217 : PseudoVSUXSEG7EI8_V_MF2_M1,
11218 : PseudoVSUXSEG7EI8_V_MF2_M1_MASK,
11219 : PseudoVSUXSEG7EI8_V_MF2_MF2,
11220 : PseudoVSUXSEG7EI8_V_MF2_MF2_MASK,
11221 : PseudoVSUXSEG7EI8_V_MF4_M1,
11222 : PseudoVSUXSEG7EI8_V_MF4_M1_MASK,
11223 : PseudoVSUXSEG7EI8_V_MF4_MF2,
11224 : PseudoVSUXSEG7EI8_V_MF4_MF2_MASK,
11225 : PseudoVSUXSEG7EI8_V_MF4_MF4,
11226 : PseudoVSUXSEG7EI8_V_MF4_MF4_MASK,
11227 : PseudoVSUXSEG7EI8_V_MF8_M1,
11228 : PseudoVSUXSEG7EI8_V_MF8_M1_MASK,
11229 : PseudoVSUXSEG7EI8_V_MF8_MF2,
11230 : PseudoVSUXSEG7EI8_V_MF8_MF2_MASK,
11231 : PseudoVSUXSEG7EI8_V_MF8_MF4,
11232 : PseudoVSUXSEG7EI8_V_MF8_MF4_MASK,
11233 : PseudoVSUXSEG7EI8_V_MF8_MF8,
11234 : PseudoVSUXSEG7EI8_V_MF8_MF8_MASK,
11235 : PseudoVSUXSEG8EI16_V_M1_M1,
11236 : PseudoVSUXSEG8EI16_V_M1_M1_MASK,
11237 : PseudoVSUXSEG8EI16_V_M1_MF2,
11238 : PseudoVSUXSEG8EI16_V_M1_MF2_MASK,
11239 : PseudoVSUXSEG8EI16_V_M2_M1,
11240 : PseudoVSUXSEG8EI16_V_M2_M1_MASK,
11241 : PseudoVSUXSEG8EI16_V_MF2_M1,
11242 : PseudoVSUXSEG8EI16_V_MF2_M1_MASK,
11243 : PseudoVSUXSEG8EI16_V_MF2_MF2,
11244 : PseudoVSUXSEG8EI16_V_MF2_MF2_MASK,
11245 : PseudoVSUXSEG8EI16_V_MF2_MF4,
11246 : PseudoVSUXSEG8EI16_V_MF2_MF4_MASK,
11247 : PseudoVSUXSEG8EI16_V_MF4_M1,
11248 : PseudoVSUXSEG8EI16_V_MF4_M1_MASK,
11249 : PseudoVSUXSEG8EI16_V_MF4_MF2,
11250 : PseudoVSUXSEG8EI16_V_MF4_MF2_MASK,
11251 : PseudoVSUXSEG8EI16_V_MF4_MF4,
11252 : PseudoVSUXSEG8EI16_V_MF4_MF4_MASK,
11253 : PseudoVSUXSEG8EI16_V_MF4_MF8,
11254 : PseudoVSUXSEG8EI16_V_MF4_MF8_MASK,
11255 : PseudoVSUXSEG8EI32_V_M1_M1,
11256 : PseudoVSUXSEG8EI32_V_M1_M1_MASK,
11257 : PseudoVSUXSEG8EI32_V_M1_MF2,
11258 : PseudoVSUXSEG8EI32_V_M1_MF2_MASK,
11259 : PseudoVSUXSEG8EI32_V_M1_MF4,
11260 : PseudoVSUXSEG8EI32_V_M1_MF4_MASK,
11261 : PseudoVSUXSEG8EI32_V_M2_M1,
11262 : PseudoVSUXSEG8EI32_V_M2_M1_MASK,
11263 : PseudoVSUXSEG8EI32_V_M2_MF2,
11264 : PseudoVSUXSEG8EI32_V_M2_MF2_MASK,
11265 : PseudoVSUXSEG8EI32_V_M4_M1,
11266 : PseudoVSUXSEG8EI32_V_M4_M1_MASK,
11267 : PseudoVSUXSEG8EI32_V_MF2_M1,
11268 : PseudoVSUXSEG8EI32_V_MF2_M1_MASK,
11269 : PseudoVSUXSEG8EI32_V_MF2_MF2,
11270 : PseudoVSUXSEG8EI32_V_MF2_MF2_MASK,
11271 : PseudoVSUXSEG8EI32_V_MF2_MF4,
11272 : PseudoVSUXSEG8EI32_V_MF2_MF4_MASK,
11273 : PseudoVSUXSEG8EI32_V_MF2_MF8,
11274 : PseudoVSUXSEG8EI32_V_MF2_MF8_MASK,
11275 : PseudoVSUXSEG8EI64_V_M1_M1,
11276 : PseudoVSUXSEG8EI64_V_M1_M1_MASK,
11277 : PseudoVSUXSEG8EI64_V_M1_MF2,
11278 : PseudoVSUXSEG8EI64_V_M1_MF2_MASK,
11279 : PseudoVSUXSEG8EI64_V_M1_MF4,
11280 : PseudoVSUXSEG8EI64_V_M1_MF4_MASK,
11281 : PseudoVSUXSEG8EI64_V_M1_MF8,
11282 : PseudoVSUXSEG8EI64_V_M1_MF8_MASK,
11283 : PseudoVSUXSEG8EI64_V_M2_M1,
11284 : PseudoVSUXSEG8EI64_V_M2_M1_MASK,
11285 : PseudoVSUXSEG8EI64_V_M2_MF2,
11286 : PseudoVSUXSEG8EI64_V_M2_MF2_MASK,
11287 : PseudoVSUXSEG8EI64_V_M2_MF4,
11288 : PseudoVSUXSEG8EI64_V_M2_MF4_MASK,
11289 : PseudoVSUXSEG8EI64_V_M4_M1,
11290 : PseudoVSUXSEG8EI64_V_M4_M1_MASK,
11291 : PseudoVSUXSEG8EI64_V_M4_MF2,
11292 : PseudoVSUXSEG8EI64_V_M4_MF2_MASK,
11293 : PseudoVSUXSEG8EI64_V_M8_M1,
11294 : PseudoVSUXSEG8EI64_V_M8_M1_MASK,
11295 : PseudoVSUXSEG8EI8_V_M1_M1,
11296 : PseudoVSUXSEG8EI8_V_M1_M1_MASK,
11297 : PseudoVSUXSEG8EI8_V_MF2_M1,
11298 : PseudoVSUXSEG8EI8_V_MF2_M1_MASK,
11299 : PseudoVSUXSEG8EI8_V_MF2_MF2,
11300 : PseudoVSUXSEG8EI8_V_MF2_MF2_MASK,
11301 : PseudoVSUXSEG8EI8_V_MF4_M1,
11302 : PseudoVSUXSEG8EI8_V_MF4_M1_MASK,
11303 : PseudoVSUXSEG8EI8_V_MF4_MF2,
11304 : PseudoVSUXSEG8EI8_V_MF4_MF2_MASK,
11305 : PseudoVSUXSEG8EI8_V_MF4_MF4,
11306 : PseudoVSUXSEG8EI8_V_MF4_MF4_MASK,
11307 : PseudoVSUXSEG8EI8_V_MF8_M1,
11308 : PseudoVSUXSEG8EI8_V_MF8_M1_MASK,
11309 : PseudoVSUXSEG8EI8_V_MF8_MF2,
11310 : PseudoVSUXSEG8EI8_V_MF8_MF2_MASK,
11311 : PseudoVSUXSEG8EI8_V_MF8_MF4,
11312 : PseudoVSUXSEG8EI8_V_MF8_MF4_MASK,
11313 : PseudoVSUXSEG8EI8_V_MF8_MF8,
11314 : PseudoVSUXSEG8EI8_V_MF8_MF8_MASK,
11315 : PseudoVWADDU_VV_M1,
11316 : PseudoVWADDU_VV_M1_MASK,
11317 : PseudoVWADDU_VV_M2,
11318 : PseudoVWADDU_VV_M2_MASK,
11319 : PseudoVWADDU_VV_M4,
11320 : PseudoVWADDU_VV_M4_MASK,
11321 : PseudoVWADDU_VV_MF2,
11322 : PseudoVWADDU_VV_MF2_MASK,
11323 : PseudoVWADDU_VV_MF4,
11324 : PseudoVWADDU_VV_MF4_MASK,
11325 : PseudoVWADDU_VV_MF8,
11326 : PseudoVWADDU_VV_MF8_MASK,
11327 : PseudoVWADDU_VX_M1,
11328 : PseudoVWADDU_VX_M1_MASK,
11329 : PseudoVWADDU_VX_M2,
11330 : PseudoVWADDU_VX_M2_MASK,
11331 : PseudoVWADDU_VX_M4,
11332 : PseudoVWADDU_VX_M4_MASK,
11333 : PseudoVWADDU_VX_MF2,
11334 : PseudoVWADDU_VX_MF2_MASK,
11335 : PseudoVWADDU_VX_MF4,
11336 : PseudoVWADDU_VX_MF4_MASK,
11337 : PseudoVWADDU_VX_MF8,
11338 : PseudoVWADDU_VX_MF8_MASK,
11339 : PseudoVWADDU_WV_M1,
11340 : PseudoVWADDU_WV_M1_MASK,
11341 : PseudoVWADDU_WV_M1_MASK_TIED,
11342 : PseudoVWADDU_WV_M1_TIED,
11343 : PseudoVWADDU_WV_M2,
11344 : PseudoVWADDU_WV_M2_MASK,
11345 : PseudoVWADDU_WV_M2_MASK_TIED,
11346 : PseudoVWADDU_WV_M2_TIED,
11347 : PseudoVWADDU_WV_M4,
11348 : PseudoVWADDU_WV_M4_MASK,
11349 : PseudoVWADDU_WV_M4_MASK_TIED,
11350 : PseudoVWADDU_WV_M4_TIED,
11351 : PseudoVWADDU_WV_MF2,
11352 : PseudoVWADDU_WV_MF2_MASK,
11353 : PseudoVWADDU_WV_MF2_MASK_TIED,
11354 : PseudoVWADDU_WV_MF2_TIED,
11355 : PseudoVWADDU_WV_MF4,
11356 : PseudoVWADDU_WV_MF4_MASK,
11357 : PseudoVWADDU_WV_MF4_MASK_TIED,
11358 : PseudoVWADDU_WV_MF4_TIED,
11359 : PseudoVWADDU_WV_MF8,
11360 : PseudoVWADDU_WV_MF8_MASK,
11361 : PseudoVWADDU_WV_MF8_MASK_TIED,
11362 : PseudoVWADDU_WV_MF8_TIED,
11363 : PseudoVWADDU_WX_M1,
11364 : PseudoVWADDU_WX_M1_MASK,
11365 : PseudoVWADDU_WX_M2,
11366 : PseudoVWADDU_WX_M2_MASK,
11367 : PseudoVWADDU_WX_M4,
11368 : PseudoVWADDU_WX_M4_MASK,
11369 : PseudoVWADDU_WX_MF2,
11370 : PseudoVWADDU_WX_MF2_MASK,
11371 : PseudoVWADDU_WX_MF4,
11372 : PseudoVWADDU_WX_MF4_MASK,
11373 : PseudoVWADDU_WX_MF8,
11374 : PseudoVWADDU_WX_MF8_MASK,
11375 : PseudoVWADD_VV_M1,
11376 : PseudoVWADD_VV_M1_MASK,
11377 : PseudoVWADD_VV_M2,
11378 : PseudoVWADD_VV_M2_MASK,
11379 : PseudoVWADD_VV_M4,
11380 : PseudoVWADD_VV_M4_MASK,
11381 : PseudoVWADD_VV_MF2,
11382 : PseudoVWADD_VV_MF2_MASK,
11383 : PseudoVWADD_VV_MF4,
11384 : PseudoVWADD_VV_MF4_MASK,
11385 : PseudoVWADD_VV_MF8,
11386 : PseudoVWADD_VV_MF8_MASK,
11387 : PseudoVWADD_VX_M1,
11388 : PseudoVWADD_VX_M1_MASK,
11389 : PseudoVWADD_VX_M2,
11390 : PseudoVWADD_VX_M2_MASK,
11391 : PseudoVWADD_VX_M4,
11392 : PseudoVWADD_VX_M4_MASK,
11393 : PseudoVWADD_VX_MF2,
11394 : PseudoVWADD_VX_MF2_MASK,
11395 : PseudoVWADD_VX_MF4,
11396 : PseudoVWADD_VX_MF4_MASK,
11397 : PseudoVWADD_VX_MF8,
11398 : PseudoVWADD_VX_MF8_MASK,
11399 : PseudoVWADD_WV_M1,
11400 : PseudoVWADD_WV_M1_MASK,
11401 : PseudoVWADD_WV_M1_MASK_TIED,
11402 : PseudoVWADD_WV_M1_TIED,
11403 : PseudoVWADD_WV_M2,
11404 : PseudoVWADD_WV_M2_MASK,
11405 : PseudoVWADD_WV_M2_MASK_TIED,
11406 : PseudoVWADD_WV_M2_TIED,
11407 : PseudoVWADD_WV_M4,
11408 : PseudoVWADD_WV_M4_MASK,
11409 : PseudoVWADD_WV_M4_MASK_TIED,
11410 : PseudoVWADD_WV_M4_TIED,
11411 : PseudoVWADD_WV_MF2,
11412 : PseudoVWADD_WV_MF2_MASK,
11413 : PseudoVWADD_WV_MF2_MASK_TIED,
11414 : PseudoVWADD_WV_MF2_TIED,
11415 : PseudoVWADD_WV_MF4,
11416 : PseudoVWADD_WV_MF4_MASK,
11417 : PseudoVWADD_WV_MF4_MASK_TIED,
11418 : PseudoVWADD_WV_MF4_TIED,
11419 : PseudoVWADD_WV_MF8,
11420 : PseudoVWADD_WV_MF8_MASK,
11421 : PseudoVWADD_WV_MF8_MASK_TIED,
11422 : PseudoVWADD_WV_MF8_TIED,
11423 : PseudoVWADD_WX_M1,
11424 : PseudoVWADD_WX_M1_MASK,
11425 : PseudoVWADD_WX_M2,
11426 : PseudoVWADD_WX_M2_MASK,
11427 : PseudoVWADD_WX_M4,
11428 : PseudoVWADD_WX_M4_MASK,
11429 : PseudoVWADD_WX_MF2,
11430 : PseudoVWADD_WX_MF2_MASK,
11431 : PseudoVWADD_WX_MF4,
11432 : PseudoVWADD_WX_MF4_MASK,
11433 : PseudoVWADD_WX_MF8,
11434 : PseudoVWADD_WX_MF8_MASK,
11435 : PseudoVWMACCSU_VV_M1,
11436 : PseudoVWMACCSU_VV_M1_MASK,
11437 : PseudoVWMACCSU_VV_M2,
11438 : PseudoVWMACCSU_VV_M2_MASK,
11439 : PseudoVWMACCSU_VV_M4,
11440 : PseudoVWMACCSU_VV_M4_MASK,
11441 : PseudoVWMACCSU_VV_MF2,
11442 : PseudoVWMACCSU_VV_MF2_MASK,
11443 : PseudoVWMACCSU_VV_MF4,
11444 : PseudoVWMACCSU_VV_MF4_MASK,
11445 : PseudoVWMACCSU_VV_MF8,
11446 : PseudoVWMACCSU_VV_MF8_MASK,
11447 : PseudoVWMACCSU_VX_M1,
11448 : PseudoVWMACCSU_VX_M1_MASK,
11449 : PseudoVWMACCSU_VX_M2,
11450 : PseudoVWMACCSU_VX_M2_MASK,
11451 : PseudoVWMACCSU_VX_M4,
11452 : PseudoVWMACCSU_VX_M4_MASK,
11453 : PseudoVWMACCSU_VX_MF2,
11454 : PseudoVWMACCSU_VX_MF2_MASK,
11455 : PseudoVWMACCSU_VX_MF4,
11456 : PseudoVWMACCSU_VX_MF4_MASK,
11457 : PseudoVWMACCSU_VX_MF8,
11458 : PseudoVWMACCSU_VX_MF8_MASK,
11459 : PseudoVWMACCUS_VX_M1,
11460 : PseudoVWMACCUS_VX_M1_MASK,
11461 : PseudoVWMACCUS_VX_M2,
11462 : PseudoVWMACCUS_VX_M2_MASK,
11463 : PseudoVWMACCUS_VX_M4,
11464 : PseudoVWMACCUS_VX_M4_MASK,
11465 : PseudoVWMACCUS_VX_MF2,
11466 : PseudoVWMACCUS_VX_MF2_MASK,
11467 : PseudoVWMACCUS_VX_MF4,
11468 : PseudoVWMACCUS_VX_MF4_MASK,
11469 : PseudoVWMACCUS_VX_MF8,
11470 : PseudoVWMACCUS_VX_MF8_MASK,
11471 : PseudoVWMACCU_VV_M1,
11472 : PseudoVWMACCU_VV_M1_MASK,
11473 : PseudoVWMACCU_VV_M2,
11474 : PseudoVWMACCU_VV_M2_MASK,
11475 : PseudoVWMACCU_VV_M4,
11476 : PseudoVWMACCU_VV_M4_MASK,
11477 : PseudoVWMACCU_VV_MF2,
11478 : PseudoVWMACCU_VV_MF2_MASK,
11479 : PseudoVWMACCU_VV_MF4,
11480 : PseudoVWMACCU_VV_MF4_MASK,
11481 : PseudoVWMACCU_VV_MF8,
11482 : PseudoVWMACCU_VV_MF8_MASK,
11483 : PseudoVWMACCU_VX_M1,
11484 : PseudoVWMACCU_VX_M1_MASK,
11485 : PseudoVWMACCU_VX_M2,
11486 : PseudoVWMACCU_VX_M2_MASK,
11487 : PseudoVWMACCU_VX_M4,
11488 : PseudoVWMACCU_VX_M4_MASK,
11489 : PseudoVWMACCU_VX_MF2,
11490 : PseudoVWMACCU_VX_MF2_MASK,
11491 : PseudoVWMACCU_VX_MF4,
11492 : PseudoVWMACCU_VX_MF4_MASK,
11493 : PseudoVWMACCU_VX_MF8,
11494 : PseudoVWMACCU_VX_MF8_MASK,
11495 : PseudoVWMACC_VV_M1,
11496 : PseudoVWMACC_VV_M1_MASK,
11497 : PseudoVWMACC_VV_M2,
11498 : PseudoVWMACC_VV_M2_MASK,
11499 : PseudoVWMACC_VV_M4,
11500 : PseudoVWMACC_VV_M4_MASK,
11501 : PseudoVWMACC_VV_MF2,
11502 : PseudoVWMACC_VV_MF2_MASK,
11503 : PseudoVWMACC_VV_MF4,
11504 : PseudoVWMACC_VV_MF4_MASK,
11505 : PseudoVWMACC_VV_MF8,
11506 : PseudoVWMACC_VV_MF8_MASK,
11507 : PseudoVWMACC_VX_M1,
11508 : PseudoVWMACC_VX_M1_MASK,
11509 : PseudoVWMACC_VX_M2,
11510 : PseudoVWMACC_VX_M2_MASK,
11511 : PseudoVWMACC_VX_M4,
11512 : PseudoVWMACC_VX_M4_MASK,
11513 : PseudoVWMACC_VX_MF2,
11514 : PseudoVWMACC_VX_MF2_MASK,
11515 : PseudoVWMACC_VX_MF4,
11516 : PseudoVWMACC_VX_MF4_MASK,
11517 : PseudoVWMACC_VX_MF8,
11518 : PseudoVWMACC_VX_MF8_MASK,
11519 : PseudoVWMULSU_VV_M1,
11520 : PseudoVWMULSU_VV_M1_MASK,
11521 : PseudoVWMULSU_VV_M2,
11522 : PseudoVWMULSU_VV_M2_MASK,
11523 : PseudoVWMULSU_VV_M4,
11524 : PseudoVWMULSU_VV_M4_MASK,
11525 : PseudoVWMULSU_VV_MF2,
11526 : PseudoVWMULSU_VV_MF2_MASK,
11527 : PseudoVWMULSU_VV_MF4,
11528 : PseudoVWMULSU_VV_MF4_MASK,
11529 : PseudoVWMULSU_VV_MF8,
11530 : PseudoVWMULSU_VV_MF8_MASK,
11531 : PseudoVWMULSU_VX_M1,
11532 : PseudoVWMULSU_VX_M1_MASK,
11533 : PseudoVWMULSU_VX_M2,
11534 : PseudoVWMULSU_VX_M2_MASK,
11535 : PseudoVWMULSU_VX_M4,
11536 : PseudoVWMULSU_VX_M4_MASK,
11537 : PseudoVWMULSU_VX_MF2,
11538 : PseudoVWMULSU_VX_MF2_MASK,
11539 : PseudoVWMULSU_VX_MF4,
11540 : PseudoVWMULSU_VX_MF4_MASK,
11541 : PseudoVWMULSU_VX_MF8,
11542 : PseudoVWMULSU_VX_MF8_MASK,
11543 : PseudoVWMULU_VV_M1,
11544 : PseudoVWMULU_VV_M1_MASK,
11545 : PseudoVWMULU_VV_M2,
11546 : PseudoVWMULU_VV_M2_MASK,
11547 : PseudoVWMULU_VV_M4,
11548 : PseudoVWMULU_VV_M4_MASK,
11549 : PseudoVWMULU_VV_MF2,
11550 : PseudoVWMULU_VV_MF2_MASK,
11551 : PseudoVWMULU_VV_MF4,
11552 : PseudoVWMULU_VV_MF4_MASK,
11553 : PseudoVWMULU_VV_MF8,
11554 : PseudoVWMULU_VV_MF8_MASK,
11555 : PseudoVWMULU_VX_M1,
11556 : PseudoVWMULU_VX_M1_MASK,
11557 : PseudoVWMULU_VX_M2,
11558 : PseudoVWMULU_VX_M2_MASK,
11559 : PseudoVWMULU_VX_M4,
11560 : PseudoVWMULU_VX_M4_MASK,
11561 : PseudoVWMULU_VX_MF2,
11562 : PseudoVWMULU_VX_MF2_MASK,
11563 : PseudoVWMULU_VX_MF4,
11564 : PseudoVWMULU_VX_MF4_MASK,
11565 : PseudoVWMULU_VX_MF8,
11566 : PseudoVWMULU_VX_MF8_MASK,
11567 : PseudoVWMUL_VV_M1,
11568 : PseudoVWMUL_VV_M1_MASK,
11569 : PseudoVWMUL_VV_M2,
11570 : PseudoVWMUL_VV_M2_MASK,
11571 : PseudoVWMUL_VV_M4,
11572 : PseudoVWMUL_VV_M4_MASK,
11573 : PseudoVWMUL_VV_MF2,
11574 : PseudoVWMUL_VV_MF2_MASK,
11575 : PseudoVWMUL_VV_MF4,
11576 : PseudoVWMUL_VV_MF4_MASK,
11577 : PseudoVWMUL_VV_MF8,
11578 : PseudoVWMUL_VV_MF8_MASK,
11579 : PseudoVWMUL_VX_M1,
11580 : PseudoVWMUL_VX_M1_MASK,
11581 : PseudoVWMUL_VX_M2,
11582 : PseudoVWMUL_VX_M2_MASK,
11583 : PseudoVWMUL_VX_M4,
11584 : PseudoVWMUL_VX_M4_MASK,
11585 : PseudoVWMUL_VX_MF2,
11586 : PseudoVWMUL_VX_MF2_MASK,
11587 : PseudoVWMUL_VX_MF4,
11588 : PseudoVWMUL_VX_MF4_MASK,
11589 : PseudoVWMUL_VX_MF8,
11590 : PseudoVWMUL_VX_MF8_MASK,
11591 : PseudoVWREDSUMU_VS_M1_E16,
11592 : PseudoVWREDSUMU_VS_M1_E16_MASK,
11593 : PseudoVWREDSUMU_VS_M1_E32,
11594 : PseudoVWREDSUMU_VS_M1_E32_MASK,
11595 : PseudoVWREDSUMU_VS_M1_E8,
11596 : PseudoVWREDSUMU_VS_M1_E8_MASK,
11597 : PseudoVWREDSUMU_VS_M2_E16,
11598 : PseudoVWREDSUMU_VS_M2_E16_MASK,
11599 : PseudoVWREDSUMU_VS_M2_E32,
11600 : PseudoVWREDSUMU_VS_M2_E32_MASK,
11601 : PseudoVWREDSUMU_VS_M2_E8,
11602 : PseudoVWREDSUMU_VS_M2_E8_MASK,
11603 : PseudoVWREDSUMU_VS_M4_E16,
11604 : PseudoVWREDSUMU_VS_M4_E16_MASK,
11605 : PseudoVWREDSUMU_VS_M4_E32,
11606 : PseudoVWREDSUMU_VS_M4_E32_MASK,
11607 : PseudoVWREDSUMU_VS_M4_E8,
11608 : PseudoVWREDSUMU_VS_M4_E8_MASK,
11609 : PseudoVWREDSUMU_VS_M8_E16,
11610 : PseudoVWREDSUMU_VS_M8_E16_MASK,
11611 : PseudoVWREDSUMU_VS_M8_E32,
11612 : PseudoVWREDSUMU_VS_M8_E32_MASK,
11613 : PseudoVWREDSUMU_VS_M8_E8,
11614 : PseudoVWREDSUMU_VS_M8_E8_MASK,
11615 : PseudoVWREDSUMU_VS_MF2_E16,
11616 : PseudoVWREDSUMU_VS_MF2_E16_MASK,
11617 : PseudoVWREDSUMU_VS_MF2_E32,
11618 : PseudoVWREDSUMU_VS_MF2_E32_MASK,
11619 : PseudoVWREDSUMU_VS_MF2_E8,
11620 : PseudoVWREDSUMU_VS_MF2_E8_MASK,
11621 : PseudoVWREDSUMU_VS_MF4_E16,
11622 : PseudoVWREDSUMU_VS_MF4_E16_MASK,
11623 : PseudoVWREDSUMU_VS_MF4_E8,
11624 : PseudoVWREDSUMU_VS_MF4_E8_MASK,
11625 : PseudoVWREDSUMU_VS_MF8_E8,
11626 : PseudoVWREDSUMU_VS_MF8_E8_MASK,
11627 : PseudoVWREDSUM_VS_M1_E16,
11628 : PseudoVWREDSUM_VS_M1_E16_MASK,
11629 : PseudoVWREDSUM_VS_M1_E32,
11630 : PseudoVWREDSUM_VS_M1_E32_MASK,
11631 : PseudoVWREDSUM_VS_M1_E8,
11632 : PseudoVWREDSUM_VS_M1_E8_MASK,
11633 : PseudoVWREDSUM_VS_M2_E16,
11634 : PseudoVWREDSUM_VS_M2_E16_MASK,
11635 : PseudoVWREDSUM_VS_M2_E32,
11636 : PseudoVWREDSUM_VS_M2_E32_MASK,
11637 : PseudoVWREDSUM_VS_M2_E8,
11638 : PseudoVWREDSUM_VS_M2_E8_MASK,
11639 : PseudoVWREDSUM_VS_M4_E16,
11640 : PseudoVWREDSUM_VS_M4_E16_MASK,
11641 : PseudoVWREDSUM_VS_M4_E32,
11642 : PseudoVWREDSUM_VS_M4_E32_MASK,
11643 : PseudoVWREDSUM_VS_M4_E8,
11644 : PseudoVWREDSUM_VS_M4_E8_MASK,
11645 : PseudoVWREDSUM_VS_M8_E16,
11646 : PseudoVWREDSUM_VS_M8_E16_MASK,
11647 : PseudoVWREDSUM_VS_M8_E32,
11648 : PseudoVWREDSUM_VS_M8_E32_MASK,
11649 : PseudoVWREDSUM_VS_M8_E8,
11650 : PseudoVWREDSUM_VS_M8_E8_MASK,
11651 : PseudoVWREDSUM_VS_MF2_E16,
11652 : PseudoVWREDSUM_VS_MF2_E16_MASK,
11653 : PseudoVWREDSUM_VS_MF2_E32,
11654 : PseudoVWREDSUM_VS_MF2_E32_MASK,
11655 : PseudoVWREDSUM_VS_MF2_E8,
11656 : PseudoVWREDSUM_VS_MF2_E8_MASK,
11657 : PseudoVWREDSUM_VS_MF4_E16,
11658 : PseudoVWREDSUM_VS_MF4_E16_MASK,
11659 : PseudoVWREDSUM_VS_MF4_E8,
11660 : PseudoVWREDSUM_VS_MF4_E8_MASK,
11661 : PseudoVWREDSUM_VS_MF8_E8,
11662 : PseudoVWREDSUM_VS_MF8_E8_MASK,
11663 : PseudoVWSLL_VI_M1,
11664 : PseudoVWSLL_VI_M1_MASK,
11665 : PseudoVWSLL_VI_M2,
11666 : PseudoVWSLL_VI_M2_MASK,
11667 : PseudoVWSLL_VI_M4,
11668 : PseudoVWSLL_VI_M4_MASK,
11669 : PseudoVWSLL_VI_MF2,
11670 : PseudoVWSLL_VI_MF2_MASK,
11671 : PseudoVWSLL_VI_MF4,
11672 : PseudoVWSLL_VI_MF4_MASK,
11673 : PseudoVWSLL_VI_MF8,
11674 : PseudoVWSLL_VI_MF8_MASK,
11675 : PseudoVWSLL_VV_M1,
11676 : PseudoVWSLL_VV_M1_MASK,
11677 : PseudoVWSLL_VV_M2,
11678 : PseudoVWSLL_VV_M2_MASK,
11679 : PseudoVWSLL_VV_M4,
11680 : PseudoVWSLL_VV_M4_MASK,
11681 : PseudoVWSLL_VV_MF2,
11682 : PseudoVWSLL_VV_MF2_MASK,
11683 : PseudoVWSLL_VV_MF4,
11684 : PseudoVWSLL_VV_MF4_MASK,
11685 : PseudoVWSLL_VV_MF8,
11686 : PseudoVWSLL_VV_MF8_MASK,
11687 : PseudoVWSLL_VX_M1,
11688 : PseudoVWSLL_VX_M1_MASK,
11689 : PseudoVWSLL_VX_M2,
11690 : PseudoVWSLL_VX_M2_MASK,
11691 : PseudoVWSLL_VX_M4,
11692 : PseudoVWSLL_VX_M4_MASK,
11693 : PseudoVWSLL_VX_MF2,
11694 : PseudoVWSLL_VX_MF2_MASK,
11695 : PseudoVWSLL_VX_MF4,
11696 : PseudoVWSLL_VX_MF4_MASK,
11697 : PseudoVWSLL_VX_MF8,
11698 : PseudoVWSLL_VX_MF8_MASK,
11699 : PseudoVWSUBU_VV_M1,
11700 : PseudoVWSUBU_VV_M1_MASK,
11701 : PseudoVWSUBU_VV_M2,
11702 : PseudoVWSUBU_VV_M2_MASK,
11703 : PseudoVWSUBU_VV_M4,
11704 : PseudoVWSUBU_VV_M4_MASK,
11705 : PseudoVWSUBU_VV_MF2,
11706 : PseudoVWSUBU_VV_MF2_MASK,
11707 : PseudoVWSUBU_VV_MF4,
11708 : PseudoVWSUBU_VV_MF4_MASK,
11709 : PseudoVWSUBU_VV_MF8,
11710 : PseudoVWSUBU_VV_MF8_MASK,
11711 : PseudoVWSUBU_VX_M1,
11712 : PseudoVWSUBU_VX_M1_MASK,
11713 : PseudoVWSUBU_VX_M2,
11714 : PseudoVWSUBU_VX_M2_MASK,
11715 : PseudoVWSUBU_VX_M4,
11716 : PseudoVWSUBU_VX_M4_MASK,
11717 : PseudoVWSUBU_VX_MF2,
11718 : PseudoVWSUBU_VX_MF2_MASK,
11719 : PseudoVWSUBU_VX_MF4,
11720 : PseudoVWSUBU_VX_MF4_MASK,
11721 : PseudoVWSUBU_VX_MF8,
11722 : PseudoVWSUBU_VX_MF8_MASK,
11723 : PseudoVWSUBU_WV_M1,
11724 : PseudoVWSUBU_WV_M1_MASK,
11725 : PseudoVWSUBU_WV_M1_MASK_TIED,
11726 : PseudoVWSUBU_WV_M1_TIED,
11727 : PseudoVWSUBU_WV_M2,
11728 : PseudoVWSUBU_WV_M2_MASK,
11729 : PseudoVWSUBU_WV_M2_MASK_TIED,
11730 : PseudoVWSUBU_WV_M2_TIED,
11731 : PseudoVWSUBU_WV_M4,
11732 : PseudoVWSUBU_WV_M4_MASK,
11733 : PseudoVWSUBU_WV_M4_MASK_TIED,
11734 : PseudoVWSUBU_WV_M4_TIED,
11735 : PseudoVWSUBU_WV_MF2,
11736 : PseudoVWSUBU_WV_MF2_MASK,
11737 : PseudoVWSUBU_WV_MF2_MASK_TIED,
11738 : PseudoVWSUBU_WV_MF2_TIED,
11739 : PseudoVWSUBU_WV_MF4,
11740 : PseudoVWSUBU_WV_MF4_MASK,
11741 : PseudoVWSUBU_WV_MF4_MASK_TIED,
11742 : PseudoVWSUBU_WV_MF4_TIED,
11743 : PseudoVWSUBU_WV_MF8,
11744 : PseudoVWSUBU_WV_MF8_MASK,
11745 : PseudoVWSUBU_WV_MF8_MASK_TIED,
11746 : PseudoVWSUBU_WV_MF8_TIED,
11747 : PseudoVWSUBU_WX_M1,
11748 : PseudoVWSUBU_WX_M1_MASK,
11749 : PseudoVWSUBU_WX_M2,
11750 : PseudoVWSUBU_WX_M2_MASK,
11751 : PseudoVWSUBU_WX_M4,
11752 : PseudoVWSUBU_WX_M4_MASK,
11753 : PseudoVWSUBU_WX_MF2,
11754 : PseudoVWSUBU_WX_MF2_MASK,
11755 : PseudoVWSUBU_WX_MF4,
11756 : PseudoVWSUBU_WX_MF4_MASK,
11757 : PseudoVWSUBU_WX_MF8,
11758 : PseudoVWSUBU_WX_MF8_MASK,
11759 : PseudoVWSUB_VV_M1,
11760 : PseudoVWSUB_VV_M1_MASK,
11761 : PseudoVWSUB_VV_M2,
11762 : PseudoVWSUB_VV_M2_MASK,
11763 : PseudoVWSUB_VV_M4,
11764 : PseudoVWSUB_VV_M4_MASK,
11765 : PseudoVWSUB_VV_MF2,
11766 : PseudoVWSUB_VV_MF2_MASK,
11767 : PseudoVWSUB_VV_MF4,
11768 : PseudoVWSUB_VV_MF4_MASK,
11769 : PseudoVWSUB_VV_MF8,
11770 : PseudoVWSUB_VV_MF8_MASK,
11771 : PseudoVWSUB_VX_M1,
11772 : PseudoVWSUB_VX_M1_MASK,
11773 : PseudoVWSUB_VX_M2,
11774 : PseudoVWSUB_VX_M2_MASK,
11775 : PseudoVWSUB_VX_M4,
11776 : PseudoVWSUB_VX_M4_MASK,
11777 : PseudoVWSUB_VX_MF2,
11778 : PseudoVWSUB_VX_MF2_MASK,
11779 : PseudoVWSUB_VX_MF4,
11780 : PseudoVWSUB_VX_MF4_MASK,
11781 : PseudoVWSUB_VX_MF8,
11782 : PseudoVWSUB_VX_MF8_MASK,
11783 : PseudoVWSUB_WV_M1,
11784 : PseudoVWSUB_WV_M1_MASK,
11785 : PseudoVWSUB_WV_M1_MASK_TIED,
11786 : PseudoVWSUB_WV_M1_TIED,
11787 : PseudoVWSUB_WV_M2,
11788 : PseudoVWSUB_WV_M2_MASK,
11789 : PseudoVWSUB_WV_M2_MASK_TIED,
11790 : PseudoVWSUB_WV_M2_TIED,
11791 : PseudoVWSUB_WV_M4,
11792 : PseudoVWSUB_WV_M4_MASK,
11793 : PseudoVWSUB_WV_M4_MASK_TIED,
11794 : PseudoVWSUB_WV_M4_TIED,
11795 : PseudoVWSUB_WV_MF2,
11796 : PseudoVWSUB_WV_MF2_MASK,
11797 : PseudoVWSUB_WV_MF2_MASK_TIED,
11798 : PseudoVWSUB_WV_MF2_TIED,
11799 : PseudoVWSUB_WV_MF4,
11800 : PseudoVWSUB_WV_MF4_MASK,
11801 : PseudoVWSUB_WV_MF4_MASK_TIED,
11802 : PseudoVWSUB_WV_MF4_TIED,
11803 : PseudoVWSUB_WV_MF8,
11804 : PseudoVWSUB_WV_MF8_MASK,
11805 : PseudoVWSUB_WV_MF8_MASK_TIED,
11806 : PseudoVWSUB_WV_MF8_TIED,
11807 : PseudoVWSUB_WX_M1,
11808 : PseudoVWSUB_WX_M1_MASK,
11809 : PseudoVWSUB_WX_M2,
11810 : PseudoVWSUB_WX_M2_MASK,
11811 : PseudoVWSUB_WX_M4,
11812 : PseudoVWSUB_WX_M4_MASK,
11813 : PseudoVWSUB_WX_MF2,
11814 : PseudoVWSUB_WX_MF2_MASK,
11815 : PseudoVWSUB_WX_MF4,
11816 : PseudoVWSUB_WX_MF4_MASK,
11817 : PseudoVWSUB_WX_MF8,
11818 : PseudoVWSUB_WX_MF8_MASK,
11819 : PseudoVXOR_VI_M1,
11820 : PseudoVXOR_VI_M1_MASK,
11821 : PseudoVXOR_VI_M2,
11822 : PseudoVXOR_VI_M2_MASK,
11823 : PseudoVXOR_VI_M4,
11824 : PseudoVXOR_VI_M4_MASK,
11825 : PseudoVXOR_VI_M8,
11826 : PseudoVXOR_VI_M8_MASK,
11827 : PseudoVXOR_VI_MF2,
11828 : PseudoVXOR_VI_MF2_MASK,
11829 : PseudoVXOR_VI_MF4,
11830 : PseudoVXOR_VI_MF4_MASK,
11831 : PseudoVXOR_VI_MF8,
11832 : PseudoVXOR_VI_MF8_MASK,
11833 : PseudoVXOR_VV_M1,
11834 : PseudoVXOR_VV_M1_MASK,
11835 : PseudoVXOR_VV_M2,
11836 : PseudoVXOR_VV_M2_MASK,
11837 : PseudoVXOR_VV_M4,
11838 : PseudoVXOR_VV_M4_MASK,
11839 : PseudoVXOR_VV_M8,
11840 : PseudoVXOR_VV_M8_MASK,
11841 : PseudoVXOR_VV_MF2,
11842 : PseudoVXOR_VV_MF2_MASK,
11843 : PseudoVXOR_VV_MF4,
11844 : PseudoVXOR_VV_MF4_MASK,
11845 : PseudoVXOR_VV_MF8,
11846 : PseudoVXOR_VV_MF8_MASK,
11847 : PseudoVXOR_VX_M1,
11848 : PseudoVXOR_VX_M1_MASK,
11849 : PseudoVXOR_VX_M2,
11850 : PseudoVXOR_VX_M2_MASK,
11851 : PseudoVXOR_VX_M4,
11852 : PseudoVXOR_VX_M4_MASK,
11853 : PseudoVXOR_VX_M8,
11854 : PseudoVXOR_VX_M8_MASK,
11855 : PseudoVXOR_VX_MF2,
11856 : PseudoVXOR_VX_MF2_MASK,
11857 : PseudoVXOR_VX_MF4,
11858 : PseudoVXOR_VX_MF4_MASK,
11859 : PseudoVXOR_VX_MF8,
11860 : PseudoVXOR_VX_MF8_MASK,
11861 : PseudoVZEXT_VF2_M1,
11862 : PseudoVZEXT_VF2_M1_MASK,
11863 : PseudoVZEXT_VF2_M2,
11864 : PseudoVZEXT_VF2_M2_MASK,
11865 : PseudoVZEXT_VF2_M4,
11866 : PseudoVZEXT_VF2_M4_MASK,
11867 : PseudoVZEXT_VF2_M8,
11868 : PseudoVZEXT_VF2_M8_MASK,
11869 : PseudoVZEXT_VF2_MF2,
11870 : PseudoVZEXT_VF2_MF2_MASK,
11871 : PseudoVZEXT_VF2_MF4,
11872 : PseudoVZEXT_VF2_MF4_MASK,
11873 : PseudoVZEXT_VF4_M1,
11874 : PseudoVZEXT_VF4_M1_MASK,
11875 : PseudoVZEXT_VF4_M2,
11876 : PseudoVZEXT_VF4_M2_MASK,
11877 : PseudoVZEXT_VF4_M4,
11878 : PseudoVZEXT_VF4_M4_MASK,
11879 : PseudoVZEXT_VF4_M8,
11880 : PseudoVZEXT_VF4_M8_MASK,
11881 : PseudoVZEXT_VF4_MF2,
11882 : PseudoVZEXT_VF4_MF2_MASK,
11883 : PseudoVZEXT_VF8_M1,
11884 : PseudoVZEXT_VF8_M1_MASK,
11885 : PseudoVZEXT_VF8_M2,
11886 : PseudoVZEXT_VF8_M2_MASK,
11887 : PseudoVZEXT_VF8_M4,
11888 : PseudoVZEXT_VF8_M4_MASK,
11889 : PseudoVZEXT_VF8_M8,
11890 : PseudoVZEXT_VF8_M8_MASK,
11891 : PseudoZEXT_H,
11892 : PseudoZEXT_W,
11893 : ReadCounterWide,
11894 : ReadFFLAGS,
11895 : ReadFRM,
11896 : Select_FPR16INX_Using_CC_GPR,
11897 : Select_FPR16_Using_CC_GPR,
11898 : Select_FPR32INX_Using_CC_GPR,
11899 : Select_FPR32_Using_CC_GPR,
11900 : Select_FPR64IN32X_Using_CC_GPR,
11901 : Select_FPR64INX_Using_CC_GPR,
11902 : Select_FPR64_Using_CC_GPR,
11903 : Select_GPR_Using_CC_GPR,
11904 : Select_GPR_Using_CC_Imm,
11905 : SplitF64Pseudo,
11906 : SwapFRMImm,
11907 : WriteFFLAGS,
11908 : WriteFRM,
11909 : WriteFRMImm,
11910 : WriteVXRMImm,
11911 : ADD,
11912 : ADDI,
11913 : ADDIW,
11914 : ADDW,
11915 : ADD_UW,
11916 : AES32DSI,
11917 : AES32DSMI,
11918 : AES32ESI,
11919 : AES32ESMI,
11920 : AES64DS,
11921 : AES64DSM,
11922 : AES64ES,
11923 : AES64ESM,
11924 : AES64IM,
11925 : AES64KS1I,
11926 : AES64KS2,
11927 : AMOADD_B,
11928 : AMOADD_B_AQ,
11929 : AMOADD_B_AQ_RL,
11930 : AMOADD_B_RL,
11931 : AMOADD_D,
11932 : AMOADD_D_AQ,
11933 : AMOADD_D_AQ_RL,
11934 : AMOADD_D_RL,
11935 : AMOADD_H,
11936 : AMOADD_H_AQ,
11937 : AMOADD_H_AQ_RL,
11938 : AMOADD_H_RL,
11939 : AMOADD_W,
11940 : AMOADD_W_AQ,
11941 : AMOADD_W_AQ_RL,
11942 : AMOADD_W_RL,
11943 : AMOAND_B,
11944 : AMOAND_B_AQ,
11945 : AMOAND_B_AQ_RL,
11946 : AMOAND_B_RL,
11947 : AMOAND_D,
11948 : AMOAND_D_AQ,
11949 : AMOAND_D_AQ_RL,
11950 : AMOAND_D_RL,
11951 : AMOAND_H,
11952 : AMOAND_H_AQ,
11953 : AMOAND_H_AQ_RL,
11954 : AMOAND_H_RL,
11955 : AMOAND_W,
11956 : AMOAND_W_AQ,
11957 : AMOAND_W_AQ_RL,
11958 : AMOAND_W_RL,
11959 : AMOCAS_B,
11960 : AMOCAS_B_AQ,
11961 : AMOCAS_B_AQ_RL,
11962 : AMOCAS_B_RL,
11963 : AMOCAS_D_RV32,
11964 : AMOCAS_D_RV32_AQ,
11965 : AMOCAS_D_RV32_AQ_RL,
11966 : AMOCAS_D_RV32_RL,
11967 : AMOCAS_D_RV64,
11968 : AMOCAS_D_RV64_AQ,
11969 : AMOCAS_D_RV64_AQ_RL,
11970 : AMOCAS_D_RV64_RL,
11971 : AMOCAS_H,
11972 : AMOCAS_H_AQ,
11973 : AMOCAS_H_AQ_RL,
11974 : AMOCAS_H_RL,
11975 : AMOCAS_Q,
11976 : AMOCAS_Q_AQ,
11977 : AMOCAS_Q_AQ_RL,
11978 : AMOCAS_Q_RL,
11979 : AMOCAS_W,
11980 : AMOCAS_W_AQ,
11981 : AMOCAS_W_AQ_RL,
11982 : AMOCAS_W_RL,
11983 : AMOMAXU_B,
11984 : AMOMAXU_B_AQ,
11985 : AMOMAXU_B_AQ_RL,
11986 : AMOMAXU_B_RL,
11987 : AMOMAXU_D,
11988 : AMOMAXU_D_AQ,
11989 : AMOMAXU_D_AQ_RL,
11990 : AMOMAXU_D_RL,
11991 : AMOMAXU_H,
11992 : AMOMAXU_H_AQ,
11993 : AMOMAXU_H_AQ_RL,
11994 : AMOMAXU_H_RL,
11995 : AMOMAXU_W,
11996 : AMOMAXU_W_AQ,
11997 : AMOMAXU_W_AQ_RL,
11998 : AMOMAXU_W_RL,
11999 : AMOMAX_B,
12000 : AMOMAX_B_AQ,
12001 : AMOMAX_B_AQ_RL,
12002 : AMOMAX_B_RL,
12003 : AMOMAX_D,
12004 : AMOMAX_D_AQ,
12005 : AMOMAX_D_AQ_RL,
12006 : AMOMAX_D_RL,
12007 : AMOMAX_H,
12008 : AMOMAX_H_AQ,
12009 : AMOMAX_H_AQ_RL,
12010 : AMOMAX_H_RL,
12011 : AMOMAX_W,
12012 : AMOMAX_W_AQ,
12013 : AMOMAX_W_AQ_RL,
12014 : AMOMAX_W_RL,
12015 : AMOMINU_B,
12016 : AMOMINU_B_AQ,
12017 : AMOMINU_B_AQ_RL,
12018 : AMOMINU_B_RL,
12019 : AMOMINU_D,
12020 : AMOMINU_D_AQ,
12021 : AMOMINU_D_AQ_RL,
12022 : AMOMINU_D_RL,
12023 : AMOMINU_H,
12024 : AMOMINU_H_AQ,
12025 : AMOMINU_H_AQ_RL,
12026 : AMOMINU_H_RL,
12027 : AMOMINU_W,
12028 : AMOMINU_W_AQ,
12029 : AMOMINU_W_AQ_RL,
12030 : AMOMINU_W_RL,
12031 : AMOMIN_B,
12032 : AMOMIN_B_AQ,
12033 : AMOMIN_B_AQ_RL,
12034 : AMOMIN_B_RL,
12035 : AMOMIN_D,
12036 : AMOMIN_D_AQ,
12037 : AMOMIN_D_AQ_RL,
12038 : AMOMIN_D_RL,
12039 : AMOMIN_H,
12040 : AMOMIN_H_AQ,
12041 : AMOMIN_H_AQ_RL,
12042 : AMOMIN_H_RL,
12043 : AMOMIN_W,
12044 : AMOMIN_W_AQ,
12045 : AMOMIN_W_AQ_RL,
12046 : AMOMIN_W_RL,
12047 : AMOOR_B,
12048 : AMOOR_B_AQ,
12049 : AMOOR_B_AQ_RL,
12050 : AMOOR_B_RL,
12051 : AMOOR_D,
12052 : AMOOR_D_AQ,
12053 : AMOOR_D_AQ_RL,
12054 : AMOOR_D_RL,
12055 : AMOOR_H,
12056 : AMOOR_H_AQ,
12057 : AMOOR_H_AQ_RL,
12058 : AMOOR_H_RL,
12059 : AMOOR_W,
12060 : AMOOR_W_AQ,
12061 : AMOOR_W_AQ_RL,
12062 : AMOOR_W_RL,
12063 : AMOSWAP_B,
12064 : AMOSWAP_B_AQ,
12065 : AMOSWAP_B_AQ_RL,
12066 : AMOSWAP_B_RL,
12067 : AMOSWAP_D,
12068 : AMOSWAP_D_AQ,
12069 : AMOSWAP_D_AQ_RL,
12070 : AMOSWAP_D_RL,
12071 : AMOSWAP_H,
12072 : AMOSWAP_H_AQ,
12073 : AMOSWAP_H_AQ_RL,
12074 : AMOSWAP_H_RL,
12075 : AMOSWAP_W,
12076 : AMOSWAP_W_AQ,
12077 : AMOSWAP_W_AQ_RL,
12078 : AMOSWAP_W_RL,
12079 : AMOXOR_B,
12080 : AMOXOR_B_AQ,
12081 : AMOXOR_B_AQ_RL,
12082 : AMOXOR_B_RL,
12083 : AMOXOR_D,
12084 : AMOXOR_D_AQ,
12085 : AMOXOR_D_AQ_RL,
12086 : AMOXOR_D_RL,
12087 : AMOXOR_H,
12088 : AMOXOR_H_AQ,
12089 : AMOXOR_H_AQ_RL,
12090 : AMOXOR_H_RL,
12091 : AMOXOR_W,
12092 : AMOXOR_W_AQ,
12093 : AMOXOR_W_AQ_RL,
12094 : AMOXOR_W_RL,
12095 : AND,
12096 : ANDI,
12097 : ANDN,
12098 : AUIPC,
12099 : BCLR,
12100 : BCLRI,
12101 : BEQ,
12102 : BEXT,
12103 : BEXTI,
12104 : BGE,
12105 : BGEU,
12106 : BINV,
12107 : BINVI,
12108 : BLT,
12109 : BLTU,
12110 : BNE,
12111 : BREV8,
12112 : BSET,
12113 : BSETI,
12114 : CBO_CLEAN,
12115 : CBO_FLUSH,
12116 : CBO_INVAL,
12117 : CBO_ZERO,
12118 : CLMUL,
12119 : CLMULH,
12120 : CLMULR,
12121 : CLZ,
12122 : CLZW,
12123 : CM_JALT,
12124 : CM_JT,
12125 : CM_MVA01S,
12126 : CM_MVSA01,
12127 : CM_POP,
12128 : CM_POPRET,
12129 : CM_POPRETZ,
12130 : CM_PUSH,
12131 : CPOP,
12132 : CPOPW,
12133 : CSRRC,
12134 : CSRRCI,
12135 : CSRRS,
12136 : CSRRSI,
12137 : CSRRW,
12138 : CSRRWI,
12139 : CTZ,
12140 : CTZW,
12141 : CV_ABS,
12142 : CV_ABS_B,
12143 : CV_ABS_H,
12144 : CV_ADDN,
12145 : CV_ADDNR,
12146 : CV_ADDRN,
12147 : CV_ADDRNR,
12148 : CV_ADDUN,
12149 : CV_ADDUNR,
12150 : CV_ADDURN,
12151 : CV_ADDURNR,
12152 : CV_ADD_B,
12153 : CV_ADD_DIV2,
12154 : CV_ADD_DIV4,
12155 : CV_ADD_DIV8,
12156 : CV_ADD_H,
12157 : CV_ADD_SCI_B,
12158 : CV_ADD_SCI_H,
12159 : CV_ADD_SC_B,
12160 : CV_ADD_SC_H,
12161 : CV_AND_B,
12162 : CV_AND_H,
12163 : CV_AND_SCI_B,
12164 : CV_AND_SCI_H,
12165 : CV_AND_SC_B,
12166 : CV_AND_SC_H,
12167 : CV_AVGU_B,
12168 : CV_AVGU_H,
12169 : CV_AVGU_SCI_B,
12170 : CV_AVGU_SCI_H,
12171 : CV_AVGU_SC_B,
12172 : CV_AVGU_SC_H,
12173 : CV_AVG_B,
12174 : CV_AVG_H,
12175 : CV_AVG_SCI_B,
12176 : CV_AVG_SCI_H,
12177 : CV_AVG_SC_B,
12178 : CV_AVG_SC_H,
12179 : CV_BCLR,
12180 : CV_BCLRR,
12181 : CV_BEQIMM,
12182 : CV_BITREV,
12183 : CV_BNEIMM,
12184 : CV_BSET,
12185 : CV_BSETR,
12186 : CV_CLB,
12187 : CV_CLIP,
12188 : CV_CLIPR,
12189 : CV_CLIPU,
12190 : CV_CLIPUR,
12191 : CV_CMPEQ_B,
12192 : CV_CMPEQ_H,
12193 : CV_CMPEQ_SCI_B,
12194 : CV_CMPEQ_SCI_H,
12195 : CV_CMPEQ_SC_B,
12196 : CV_CMPEQ_SC_H,
12197 : CV_CMPGEU_B,
12198 : CV_CMPGEU_H,
12199 : CV_CMPGEU_SCI_B,
12200 : CV_CMPGEU_SCI_H,
12201 : CV_CMPGEU_SC_B,
12202 : CV_CMPGEU_SC_H,
12203 : CV_CMPGE_B,
12204 : CV_CMPGE_H,
12205 : CV_CMPGE_SCI_B,
12206 : CV_CMPGE_SCI_H,
12207 : CV_CMPGE_SC_B,
12208 : CV_CMPGE_SC_H,
12209 : CV_CMPGTU_B,
12210 : CV_CMPGTU_H,
12211 : CV_CMPGTU_SCI_B,
12212 : CV_CMPGTU_SCI_H,
12213 : CV_CMPGTU_SC_B,
12214 : CV_CMPGTU_SC_H,
12215 : CV_CMPGT_B,
12216 : CV_CMPGT_H,
12217 : CV_CMPGT_SCI_B,
12218 : CV_CMPGT_SCI_H,
12219 : CV_CMPGT_SC_B,
12220 : CV_CMPGT_SC_H,
12221 : CV_CMPLEU_B,
12222 : CV_CMPLEU_H,
12223 : CV_CMPLEU_SCI_B,
12224 : CV_CMPLEU_SCI_H,
12225 : CV_CMPLEU_SC_B,
12226 : CV_CMPLEU_SC_H,
12227 : CV_CMPLE_B,
12228 : CV_CMPLE_H,
12229 : CV_CMPLE_SCI_B,
12230 : CV_CMPLE_SCI_H,
12231 : CV_CMPLE_SC_B,
12232 : CV_CMPLE_SC_H,
12233 : CV_CMPLTU_B,
12234 : CV_CMPLTU_H,
12235 : CV_CMPLTU_SCI_B,
12236 : CV_CMPLTU_SCI_H,
12237 : CV_CMPLTU_SC_B,
12238 : CV_CMPLTU_SC_H,
12239 : CV_CMPLT_B,
12240 : CV_CMPLT_H,
12241 : CV_CMPLT_SCI_B,
12242 : CV_CMPLT_SCI_H,
12243 : CV_CMPLT_SC_B,
12244 : CV_CMPLT_SC_H,
12245 : CV_CMPNE_B,
12246 : CV_CMPNE_H,
12247 : CV_CMPNE_SCI_B,
12248 : CV_CMPNE_SCI_H,
12249 : CV_CMPNE_SC_B,
12250 : CV_CMPNE_SC_H,
12251 : CV_CNT,
12252 : CV_CPLXCONJ,
12253 : CV_CPLXMUL_I,
12254 : CV_CPLXMUL_I_DIV2,
12255 : CV_CPLXMUL_I_DIV4,
12256 : CV_CPLXMUL_I_DIV8,
12257 : CV_CPLXMUL_R,
12258 : CV_CPLXMUL_R_DIV2,
12259 : CV_CPLXMUL_R_DIV4,
12260 : CV_CPLXMUL_R_DIV8,
12261 : CV_DOTSP_B,
12262 : CV_DOTSP_H,
12263 : CV_DOTSP_SCI_B,
12264 : CV_DOTSP_SCI_H,
12265 : CV_DOTSP_SC_B,
12266 : CV_DOTSP_SC_H,
12267 : CV_DOTUP_B,
12268 : CV_DOTUP_H,
12269 : CV_DOTUP_SCI_B,
12270 : CV_DOTUP_SCI_H,
12271 : CV_DOTUP_SC_B,
12272 : CV_DOTUP_SC_H,
12273 : CV_DOTUSP_B,
12274 : CV_DOTUSP_H,
12275 : CV_DOTUSP_SCI_B,
12276 : CV_DOTUSP_SCI_H,
12277 : CV_DOTUSP_SC_B,
12278 : CV_DOTUSP_SC_H,
12279 : CV_ELW,
12280 : CV_EXTBS,
12281 : CV_EXTBZ,
12282 : CV_EXTHS,
12283 : CV_EXTHZ,
12284 : CV_EXTRACT,
12285 : CV_EXTRACTR,
12286 : CV_EXTRACTU,
12287 : CV_EXTRACTUR,
12288 : CV_EXTRACTU_B,
12289 : CV_EXTRACTU_H,
12290 : CV_EXTRACT_B,
12291 : CV_EXTRACT_H,
12292 : CV_FF1,
12293 : CV_FL1,
12294 : CV_INSERT,
12295 : CV_INSERTR,
12296 : CV_INSERT_B,
12297 : CV_INSERT_H,
12298 : CV_LBU_ri_inc,
12299 : CV_LBU_rr,
12300 : CV_LBU_rr_inc,
12301 : CV_LB_ri_inc,
12302 : CV_LB_rr,
12303 : CV_LB_rr_inc,
12304 : CV_LHU_ri_inc,
12305 : CV_LHU_rr,
12306 : CV_LHU_rr_inc,
12307 : CV_LH_ri_inc,
12308 : CV_LH_rr,
12309 : CV_LH_rr_inc,
12310 : CV_LW_ri_inc,
12311 : CV_LW_rr,
12312 : CV_LW_rr_inc,
12313 : CV_MAC,
12314 : CV_MACHHSN,
12315 : CV_MACHHSRN,
12316 : CV_MACHHUN,
12317 : CV_MACHHURN,
12318 : CV_MACSN,
12319 : CV_MACSRN,
12320 : CV_MACUN,
12321 : CV_MACURN,
12322 : CV_MAX,
12323 : CV_MAXU,
12324 : CV_MAXU_B,
12325 : CV_MAXU_H,
12326 : CV_MAXU_SCI_B,
12327 : CV_MAXU_SCI_H,
12328 : CV_MAXU_SC_B,
12329 : CV_MAXU_SC_H,
12330 : CV_MAX_B,
12331 : CV_MAX_H,
12332 : CV_MAX_SCI_B,
12333 : CV_MAX_SCI_H,
12334 : CV_MAX_SC_B,
12335 : CV_MAX_SC_H,
12336 : CV_MIN,
12337 : CV_MINU,
12338 : CV_MINU_B,
12339 : CV_MINU_H,
12340 : CV_MINU_SCI_B,
12341 : CV_MINU_SCI_H,
12342 : CV_MINU_SC_B,
12343 : CV_MINU_SC_H,
12344 : CV_MIN_B,
12345 : CV_MIN_H,
12346 : CV_MIN_SCI_B,
12347 : CV_MIN_SCI_H,
12348 : CV_MIN_SC_B,
12349 : CV_MIN_SC_H,
12350 : CV_MSU,
12351 : CV_MULHHSN,
12352 : CV_MULHHSRN,
12353 : CV_MULHHUN,
12354 : CV_MULHHURN,
12355 : CV_MULSN,
12356 : CV_MULSRN,
12357 : CV_MULUN,
12358 : CV_MULURN,
12359 : CV_OR_B,
12360 : CV_OR_H,
12361 : CV_OR_SCI_B,
12362 : CV_OR_SCI_H,
12363 : CV_OR_SC_B,
12364 : CV_OR_SC_H,
12365 : CV_PACK,
12366 : CV_PACKHI_B,
12367 : CV_PACKLO_B,
12368 : CV_PACK_H,
12369 : CV_ROR,
12370 : CV_SB_ri_inc,
12371 : CV_SB_rr,
12372 : CV_SB_rr_inc,
12373 : CV_SDOTSP_B,
12374 : CV_SDOTSP_H,
12375 : CV_SDOTSP_SCI_B,
12376 : CV_SDOTSP_SCI_H,
12377 : CV_SDOTSP_SC_B,
12378 : CV_SDOTSP_SC_H,
12379 : CV_SDOTUP_B,
12380 : CV_SDOTUP_H,
12381 : CV_SDOTUP_SCI_B,
12382 : CV_SDOTUP_SCI_H,
12383 : CV_SDOTUP_SC_B,
12384 : CV_SDOTUP_SC_H,
12385 : CV_SDOTUSP_B,
12386 : CV_SDOTUSP_H,
12387 : CV_SDOTUSP_SCI_B,
12388 : CV_SDOTUSP_SCI_H,
12389 : CV_SDOTUSP_SC_B,
12390 : CV_SDOTUSP_SC_H,
12391 : CV_SHUFFLE2_B,
12392 : CV_SHUFFLE2_H,
12393 : CV_SHUFFLEI0_SCI_B,
12394 : CV_SHUFFLEI1_SCI_B,
12395 : CV_SHUFFLEI2_SCI_B,
12396 : CV_SHUFFLEI3_SCI_B,
12397 : CV_SHUFFLE_B,
12398 : CV_SHUFFLE_H,
12399 : CV_SHUFFLE_SCI_H,
12400 : CV_SH_ri_inc,
12401 : CV_SH_rr,
12402 : CV_SH_rr_inc,
12403 : CV_SLET,
12404 : CV_SLETU,
12405 : CV_SLL_B,
12406 : CV_SLL_H,
12407 : CV_SLL_SCI_B,
12408 : CV_SLL_SCI_H,
12409 : CV_SLL_SC_B,
12410 : CV_SLL_SC_H,
12411 : CV_SRA_B,
12412 : CV_SRA_H,
12413 : CV_SRA_SCI_B,
12414 : CV_SRA_SCI_H,
12415 : CV_SRA_SC_B,
12416 : CV_SRA_SC_H,
12417 : CV_SRL_B,
12418 : CV_SRL_H,
12419 : CV_SRL_SCI_B,
12420 : CV_SRL_SCI_H,
12421 : CV_SRL_SC_B,
12422 : CV_SRL_SC_H,
12423 : CV_SUBN,
12424 : CV_SUBNR,
12425 : CV_SUBRN,
12426 : CV_SUBRNR,
12427 : CV_SUBROTMJ,
12428 : CV_SUBROTMJ_DIV2,
12429 : CV_SUBROTMJ_DIV4,
12430 : CV_SUBROTMJ_DIV8,
12431 : CV_SUBUN,
12432 : CV_SUBUNR,
12433 : CV_SUBURN,
12434 : CV_SUBURNR,
12435 : CV_SUB_B,
12436 : CV_SUB_DIV2,
12437 : CV_SUB_DIV4,
12438 : CV_SUB_DIV8,
12439 : CV_SUB_H,
12440 : CV_SUB_SCI_B,
12441 : CV_SUB_SCI_H,
12442 : CV_SUB_SC_B,
12443 : CV_SUB_SC_H,
12444 : CV_SW_ri_inc,
12445 : CV_SW_rr,
12446 : CV_SW_rr_inc,
12447 : CV_XOR_B,
12448 : CV_XOR_H,
12449 : CV_XOR_SCI_B,
12450 : CV_XOR_SCI_H,
12451 : CV_XOR_SC_B,
12452 : CV_XOR_SC_H,
12453 : CZERO_EQZ,
12454 : CZERO_NEZ,
12455 : C_ADD,
12456 : C_ADDI,
12457 : C_ADDI16SP,
12458 : C_ADDI4SPN,
12459 : C_ADDIW,
12460 : C_ADDI_HINT_IMM_ZERO,
12461 : C_ADDI_NOP,
12462 : C_ADDW,
12463 : C_ADD_HINT,
12464 : C_AND,
12465 : C_ANDI,
12466 : C_BEQZ,
12467 : C_BNEZ,
12468 : C_EBREAK,
12469 : C_FLD,
12470 : C_FLDSP,
12471 : C_FLW,
12472 : C_FLWSP,
12473 : C_FSD,
12474 : C_FSDSP,
12475 : C_FSW,
12476 : C_FSWSP,
12477 : C_J,
12478 : C_JAL,
12479 : C_JALR,
12480 : C_JR,
12481 : C_LBU,
12482 : C_LD,
12483 : C_LDSP,
12484 : C_LH,
12485 : C_LHU,
12486 : C_LI,
12487 : C_LI_HINT,
12488 : C_LUI,
12489 : C_LUI_HINT,
12490 : C_LW,
12491 : C_LWSP,
12492 : C_MOP1,
12493 : C_MOP11,
12494 : C_MOP13,
12495 : C_MOP15,
12496 : C_MOP3,
12497 : C_MOP5,
12498 : C_MOP7,
12499 : C_MOP9,
12500 : C_MUL,
12501 : C_MV,
12502 : C_MV_HINT,
12503 : C_NOP,
12504 : C_NOP_HINT,
12505 : C_NOT,
12506 : C_OR,
12507 : C_SB,
12508 : C_SD,
12509 : C_SDSP,
12510 : C_SEXT_B,
12511 : C_SEXT_H,
12512 : C_SH,
12513 : C_SLLI,
12514 : C_SLLI64_HINT,
12515 : C_SLLI_HINT,
12516 : C_SRAI,
12517 : C_SRAI64_HINT,
12518 : C_SRLI,
12519 : C_SRLI64_HINT,
12520 : C_SSPOPCHK,
12521 : C_SSPUSH,
12522 : C_SUB,
12523 : C_SUBW,
12524 : C_SW,
12525 : C_SWSP,
12526 : C_UNIMP,
12527 : C_XOR,
12528 : C_ZEXT_B,
12529 : C_ZEXT_H,
12530 : C_ZEXT_W,
12531 : DIV,
12532 : DIVU,
12533 : DIVUW,
12534 : DIVW,
12535 : DRET,
12536 : EBREAK,
12537 : ECALL,
12538 : FADD_D,
12539 : FADD_D_IN32X,
12540 : FADD_D_INX,
12541 : FADD_H,
12542 : FADD_H_INX,
12543 : FADD_S,
12544 : FADD_S_INX,
12545 : FCLASS_D,
12546 : FCLASS_D_IN32X,
12547 : FCLASS_D_INX,
12548 : FCLASS_H,
12549 : FCLASS_H_INX,
12550 : FCLASS_S,
12551 : FCLASS_S_INX,
12552 : FCVTMOD_W_D,
12553 : FCVT_BF16_S,
12554 : FCVT_D_H,
12555 : FCVT_D_H_IN32X,
12556 : FCVT_D_H_INX,
12557 : FCVT_D_L,
12558 : FCVT_D_LU,
12559 : FCVT_D_LU_INX,
12560 : FCVT_D_L_INX,
12561 : FCVT_D_S,
12562 : FCVT_D_S_IN32X,
12563 : FCVT_D_S_INX,
12564 : FCVT_D_W,
12565 : FCVT_D_WU,
12566 : FCVT_D_WU_IN32X,
12567 : FCVT_D_WU_INX,
12568 : FCVT_D_W_IN32X,
12569 : FCVT_D_W_INX,
12570 : FCVT_H_D,
12571 : FCVT_H_D_IN32X,
12572 : FCVT_H_D_INX,
12573 : FCVT_H_L,
12574 : FCVT_H_LU,
12575 : FCVT_H_LU_INX,
12576 : FCVT_H_L_INX,
12577 : FCVT_H_S,
12578 : FCVT_H_S_INX,
12579 : FCVT_H_W,
12580 : FCVT_H_WU,
12581 : FCVT_H_WU_INX,
12582 : FCVT_H_W_INX,
12583 : FCVT_LU_D,
12584 : FCVT_LU_D_INX,
12585 : FCVT_LU_H,
12586 : FCVT_LU_H_INX,
12587 : FCVT_LU_S,
12588 : FCVT_LU_S_INX,
12589 : FCVT_L_D,
12590 : FCVT_L_D_INX,
12591 : FCVT_L_H,
12592 : FCVT_L_H_INX,
12593 : FCVT_L_S,
12594 : FCVT_L_S_INX,
12595 : FCVT_S_BF16,
12596 : FCVT_S_D,
12597 : FCVT_S_D_IN32X,
12598 : FCVT_S_D_INX,
12599 : FCVT_S_H,
12600 : FCVT_S_H_INX,
12601 : FCVT_S_L,
12602 : FCVT_S_LU,
12603 : FCVT_S_LU_INX,
12604 : FCVT_S_L_INX,
12605 : FCVT_S_W,
12606 : FCVT_S_WU,
12607 : FCVT_S_WU_INX,
12608 : FCVT_S_W_INX,
12609 : FCVT_WU_D,
12610 : FCVT_WU_D_IN32X,
12611 : FCVT_WU_D_INX,
12612 : FCVT_WU_H,
12613 : FCVT_WU_H_INX,
12614 : FCVT_WU_S,
12615 : FCVT_WU_S_INX,
12616 : FCVT_W_D,
12617 : FCVT_W_D_IN32X,
12618 : FCVT_W_D_INX,
12619 : FCVT_W_H,
12620 : FCVT_W_H_INX,
12621 : FCVT_W_S,
12622 : FCVT_W_S_INX,
12623 : FDIV_D,
12624 : FDIV_D_IN32X,
12625 : FDIV_D_INX,
12626 : FDIV_H,
12627 : FDIV_H_INX,
12628 : FDIV_S,
12629 : FDIV_S_INX,
12630 : FENCE,
12631 : FENCE_I,
12632 : FENCE_TSO,
12633 : FEQ_D,
12634 : FEQ_D_IN32X,
12635 : FEQ_D_INX,
12636 : FEQ_H,
12637 : FEQ_H_INX,
12638 : FEQ_S,
12639 : FEQ_S_INX,
12640 : FLD,
12641 : FLEQ_D,
12642 : FLEQ_H,
12643 : FLEQ_S,
12644 : FLE_D,
12645 : FLE_D_IN32X,
12646 : FLE_D_INX,
12647 : FLE_H,
12648 : FLE_H_INX,
12649 : FLE_S,
12650 : FLE_S_INX,
12651 : FLH,
12652 : FLI_D,
12653 : FLI_H,
12654 : FLI_S,
12655 : FLTQ_D,
12656 : FLTQ_H,
12657 : FLTQ_S,
12658 : FLT_D,
12659 : FLT_D_IN32X,
12660 : FLT_D_INX,
12661 : FLT_H,
12662 : FLT_H_INX,
12663 : FLT_S,
12664 : FLT_S_INX,
12665 : FLW,
12666 : FMADD_D,
12667 : FMADD_D_IN32X,
12668 : FMADD_D_INX,
12669 : FMADD_H,
12670 : FMADD_H_INX,
12671 : FMADD_S,
12672 : FMADD_S_INX,
12673 : FMAXM_D,
12674 : FMAXM_H,
12675 : FMAXM_S,
12676 : FMAX_D,
12677 : FMAX_D_IN32X,
12678 : FMAX_D_INX,
12679 : FMAX_H,
12680 : FMAX_H_INX,
12681 : FMAX_S,
12682 : FMAX_S_INX,
12683 : FMINM_D,
12684 : FMINM_H,
12685 : FMINM_S,
12686 : FMIN_D,
12687 : FMIN_D_IN32X,
12688 : FMIN_D_INX,
12689 : FMIN_H,
12690 : FMIN_H_INX,
12691 : FMIN_S,
12692 : FMIN_S_INX,
12693 : FMSUB_D,
12694 : FMSUB_D_IN32X,
12695 : FMSUB_D_INX,
12696 : FMSUB_H,
12697 : FMSUB_H_INX,
12698 : FMSUB_S,
12699 : FMSUB_S_INX,
12700 : FMUL_D,
12701 : FMUL_D_IN32X,
12702 : FMUL_D_INX,
12703 : FMUL_H,
12704 : FMUL_H_INX,
12705 : FMUL_S,
12706 : FMUL_S_INX,
12707 : FMVH_X_D,
12708 : FMVP_D_X,
12709 : FMV_D_X,
12710 : FMV_H_X,
12711 : FMV_W_X,
12712 : FMV_X_D,
12713 : FMV_X_H,
12714 : FMV_X_W,
12715 : FMV_X_W_FPR64,
12716 : FNMADD_D,
12717 : FNMADD_D_IN32X,
12718 : FNMADD_D_INX,
12719 : FNMADD_H,
12720 : FNMADD_H_INX,
12721 : FNMADD_S,
12722 : FNMADD_S_INX,
12723 : FNMSUB_D,
12724 : FNMSUB_D_IN32X,
12725 : FNMSUB_D_INX,
12726 : FNMSUB_H,
12727 : FNMSUB_H_INX,
12728 : FNMSUB_S,
12729 : FNMSUB_S_INX,
12730 : FROUNDNX_D,
12731 : FROUNDNX_H,
12732 : FROUNDNX_S,
12733 : FROUND_D,
12734 : FROUND_H,
12735 : FROUND_S,
12736 : FSD,
12737 : FSGNJN_D,
12738 : FSGNJN_D_IN32X,
12739 : FSGNJN_D_INX,
12740 : FSGNJN_H,
12741 : FSGNJN_H_INX,
12742 : FSGNJN_S,
12743 : FSGNJN_S_INX,
12744 : FSGNJX_D,
12745 : FSGNJX_D_IN32X,
12746 : FSGNJX_D_INX,
12747 : FSGNJX_H,
12748 : FSGNJX_H_INX,
12749 : FSGNJX_S,
12750 : FSGNJX_S_INX,
12751 : FSGNJ_D,
12752 : FSGNJ_D_IN32X,
12753 : FSGNJ_D_INX,
12754 : FSGNJ_H,
12755 : FSGNJ_H_INX,
12756 : FSGNJ_S,
12757 : FSGNJ_S_INX,
12758 : FSH,
12759 : FSQRT_D,
12760 : FSQRT_D_IN32X,
12761 : FSQRT_D_INX,
12762 : FSQRT_H,
12763 : FSQRT_H_INX,
12764 : FSQRT_S,
12765 : FSQRT_S_INX,
12766 : FSUB_D,
12767 : FSUB_D_IN32X,
12768 : FSUB_D_INX,
12769 : FSUB_H,
12770 : FSUB_H_INX,
12771 : FSUB_S,
12772 : FSUB_S_INX,
12773 : FSW,
12774 : HFENCE_GVMA,
12775 : HFENCE_VVMA,
12776 : HINVAL_GVMA,
12777 : HINVAL_VVMA,
12778 : HLVX_HU,
12779 : HLVX_WU,
12780 : HLV_B,
12781 : HLV_BU,
12782 : HLV_D,
12783 : HLV_H,
12784 : HLV_HU,
12785 : HLV_W,
12786 : HLV_WU,
12787 : HSV_B,
12788 : HSV_D,
12789 : HSV_H,
12790 : HSV_W,
12791 : Insn16,
12792 : Insn32,
12793 : InsnB,
12794 : InsnCA,
12795 : InsnCB,
12796 : InsnCI,
12797 : InsnCIW,
12798 : InsnCJ,
12799 : InsnCL,
12800 : InsnCR,
12801 : InsnCS,
12802 : InsnCSS,
12803 : InsnI,
12804 : InsnI_Mem,
12805 : InsnJ,
12806 : InsnR,
12807 : InsnR4,
12808 : InsnS,
12809 : InsnU,
12810 : JAL,
12811 : JALR,
12812 : LB,
12813 : LBU,
12814 : LB_AQ,
12815 : LB_AQ_RL,
12816 : LD,
12817 : LD_AQ,
12818 : LD_AQ_RL,
12819 : LH,
12820 : LHU,
12821 : LH_AQ,
12822 : LH_AQ_RL,
12823 : LR_D,
12824 : LR_D_AQ,
12825 : LR_D_AQ_RL,
12826 : LR_D_RL,
12827 : LR_W,
12828 : LR_W_AQ,
12829 : LR_W_AQ_RL,
12830 : LR_W_RL,
12831 : LUI,
12832 : LW,
12833 : LWU,
12834 : LW_AQ,
12835 : LW_AQ_RL,
12836 : MAX,
12837 : MAXU,
12838 : MIN,
12839 : MINU,
12840 : MOPR0,
12841 : MOPR1,
12842 : MOPR10,
12843 : MOPR11,
12844 : MOPR12,
12845 : MOPR13,
12846 : MOPR14,
12847 : MOPR15,
12848 : MOPR16,
12849 : MOPR17,
12850 : MOPR18,
12851 : MOPR19,
12852 : MOPR2,
12853 : MOPR20,
12854 : MOPR21,
12855 : MOPR22,
12856 : MOPR23,
12857 : MOPR24,
12858 : MOPR25,
12859 : MOPR26,
12860 : MOPR27,
12861 : MOPR28,
12862 : MOPR29,
12863 : MOPR3,
12864 : MOPR30,
12865 : MOPR31,
12866 : MOPR4,
12867 : MOPR5,
12868 : MOPR6,
12869 : MOPR7,
12870 : MOPR8,
12871 : MOPR9,
12872 : MOPRR0,
12873 : MOPRR1,
12874 : MOPRR2,
12875 : MOPRR3,
12876 : MOPRR4,
12877 : MOPRR5,
12878 : MOPRR6,
12879 : MOPRR7,
12880 : MRET,
12881 : MUL,
12882 : MULH,
12883 : MULHSU,
12884 : MULHU,
12885 : MULW,
12886 : OR,
12887 : ORC_B,
12888 : ORI,
12889 : ORN,
12890 : PACK,
12891 : PACKH,
12892 : PACKW,
12893 : PREFETCH_I,
12894 : PREFETCH_R,
12895 : PREFETCH_W,
12896 : QK_C_LBU,
12897 : QK_C_LBUSP,
12898 : QK_C_LHU,
12899 : QK_C_LHUSP,
12900 : QK_C_SB,
12901 : QK_C_SBSP,
12902 : QK_C_SH,
12903 : QK_C_SHSP,
12904 : REM,
12905 : REMU,
12906 : REMUW,
12907 : REMW,
12908 : REV8_RV32,
12909 : REV8_RV64,
12910 : ROL,
12911 : ROLW,
12912 : ROR,
12913 : RORI,
12914 : RORIW,
12915 : RORW,
12916 : SB,
12917 : SB_AQ_RL,
12918 : SB_RL,
12919 : SC_D,
12920 : SC_D_AQ,
12921 : SC_D_AQ_RL,
12922 : SC_D_RL,
12923 : SC_W,
12924 : SC_W_AQ,
12925 : SC_W_AQ_RL,
12926 : SC_W_RL,
12927 : SD,
12928 : SD_AQ_RL,
12929 : SD_RL,
12930 : SEXT_B,
12931 : SEXT_H,
12932 : SFENCE_INVAL_IR,
12933 : SFENCE_VMA,
12934 : SFENCE_W_INVAL,
12935 : SF_CDISCARD_D_L1,
12936 : SF_CEASE,
12937 : SF_CFLUSH_D_L1,
12938 : SH,
12939 : SH1ADD,
12940 : SH1ADD_UW,
12941 : SH2ADD,
12942 : SH2ADD_UW,
12943 : SH3ADD,
12944 : SH3ADD_UW,
12945 : SHA256SIG0,
12946 : SHA256SIG1,
12947 : SHA256SUM0,
12948 : SHA256SUM1,
12949 : SHA512SIG0,
12950 : SHA512SIG0H,
12951 : SHA512SIG0L,
12952 : SHA512SIG1,
12953 : SHA512SIG1H,
12954 : SHA512SIG1L,
12955 : SHA512SUM0,
12956 : SHA512SUM0R,
12957 : SHA512SUM1,
12958 : SHA512SUM1R,
12959 : SH_AQ_RL,
12960 : SH_RL,
12961 : SINVAL_VMA,
12962 : SLL,
12963 : SLLI,
12964 : SLLIW,
12965 : SLLI_UW,
12966 : SLLW,
12967 : SLT,
12968 : SLTI,
12969 : SLTIU,
12970 : SLTU,
12971 : SM3P0,
12972 : SM3P1,
12973 : SM4ED,
12974 : SM4KS,
12975 : SRA,
12976 : SRAI,
12977 : SRAIW,
12978 : SRAW,
12979 : SRET,
12980 : SRL,
12981 : SRLI,
12982 : SRLIW,
12983 : SRLW,
12984 : SSAMOSWAP_D,
12985 : SSAMOSWAP_D_AQ,
12986 : SSAMOSWAP_D_AQ_RL,
12987 : SSAMOSWAP_D_RL,
12988 : SSAMOSWAP_W,
12989 : SSAMOSWAP_W_AQ,
12990 : SSAMOSWAP_W_AQ_RL,
12991 : SSAMOSWAP_W_RL,
12992 : SSPOPCHK,
12993 : SSPUSH,
12994 : SSRDP,
12995 : SUB,
12996 : SUBW,
12997 : SW,
12998 : SW_AQ_RL,
12999 : SW_RL,
13000 : THVdotVMAQASU_VV,
13001 : THVdotVMAQASU_VX,
13002 : THVdotVMAQAUS_VX,
13003 : THVdotVMAQAU_VV,
13004 : THVdotVMAQAU_VX,
13005 : THVdotVMAQA_VV,
13006 : THVdotVMAQA_VX,
13007 : TH_ADDSL,
13008 : TH_DCACHE_CALL,
13009 : TH_DCACHE_CIALL,
13010 : TH_DCACHE_CIPA,
13011 : TH_DCACHE_CISW,
13012 : TH_DCACHE_CIVA,
13013 : TH_DCACHE_CPA,
13014 : TH_DCACHE_CPAL1,
13015 : TH_DCACHE_CSW,
13016 : TH_DCACHE_CVA,
13017 : TH_DCACHE_CVAL1,
13018 : TH_DCACHE_IALL,
13019 : TH_DCACHE_IPA,
13020 : TH_DCACHE_ISW,
13021 : TH_DCACHE_IVA,
13022 : TH_EXT,
13023 : TH_EXTU,
13024 : TH_FF0,
13025 : TH_FF1,
13026 : TH_FLRD,
13027 : TH_FLRW,
13028 : TH_FLURD,
13029 : TH_FLURW,
13030 : TH_FSRD,
13031 : TH_FSRW,
13032 : TH_FSURD,
13033 : TH_FSURW,
13034 : TH_ICACHE_IALL,
13035 : TH_ICACHE_IALLS,
13036 : TH_ICACHE_IPA,
13037 : TH_ICACHE_IVA,
13038 : TH_L2CACHE_CALL,
13039 : TH_L2CACHE_CIALL,
13040 : TH_L2CACHE_IALL,
13041 : TH_LBIA,
13042 : TH_LBIB,
13043 : TH_LBUIA,
13044 : TH_LBUIB,
13045 : TH_LDD,
13046 : TH_LDIA,
13047 : TH_LDIB,
13048 : TH_LHIA,
13049 : TH_LHIB,
13050 : TH_LHUIA,
13051 : TH_LHUIB,
13052 : TH_LRB,
13053 : TH_LRBU,
13054 : TH_LRD,
13055 : TH_LRH,
13056 : TH_LRHU,
13057 : TH_LRW,
13058 : TH_LRWU,
13059 : TH_LURB,
13060 : TH_LURBU,
13061 : TH_LURD,
13062 : TH_LURH,
13063 : TH_LURHU,
13064 : TH_LURW,
13065 : TH_LURWU,
13066 : TH_LWD,
13067 : TH_LWIA,
13068 : TH_LWIB,
13069 : TH_LWUD,
13070 : TH_LWUIA,
13071 : TH_LWUIB,
13072 : TH_MULA,
13073 : TH_MULAH,
13074 : TH_MULAW,
13075 : TH_MULS,
13076 : TH_MULSH,
13077 : TH_MULSW,
13078 : TH_MVEQZ,
13079 : TH_MVNEZ,
13080 : TH_REV,
13081 : TH_REVW,
13082 : TH_SBIA,
13083 : TH_SBIB,
13084 : TH_SDD,
13085 : TH_SDIA,
13086 : TH_SDIB,
13087 : TH_SFENCE_VMAS,
13088 : TH_SHIA,
13089 : TH_SHIB,
13090 : TH_SRB,
13091 : TH_SRD,
13092 : TH_SRH,
13093 : TH_SRRI,
13094 : TH_SRRIW,
13095 : TH_SRW,
13096 : TH_SURB,
13097 : TH_SURD,
13098 : TH_SURH,
13099 : TH_SURW,
13100 : TH_SWD,
13101 : TH_SWIA,
13102 : TH_SWIB,
13103 : TH_SYNC,
13104 : TH_SYNC_I,
13105 : TH_SYNC_IS,
13106 : TH_SYNC_S,
13107 : TH_TST,
13108 : TH_TSTNBZ,
13109 : UNIMP,
13110 : UNZIP_RV32,
13111 : VAADDU_VV,
13112 : VAADDU_VX,
13113 : VAADD_VV,
13114 : VAADD_VX,
13115 : VADC_VIM,
13116 : VADC_VVM,
13117 : VADC_VXM,
13118 : VADD_VI,
13119 : VADD_VV,
13120 : VADD_VX,
13121 : VAESDF_VS,
13122 : VAESDF_VV,
13123 : VAESDM_VS,
13124 : VAESDM_VV,
13125 : VAESEF_VS,
13126 : VAESEF_VV,
13127 : VAESEM_VS,
13128 : VAESEM_VV,
13129 : VAESKF1_VI,
13130 : VAESKF2_VI,
13131 : VAESZ_VS,
13132 : VANDN_VV,
13133 : VANDN_VX,
13134 : VAND_VI,
13135 : VAND_VV,
13136 : VAND_VX,
13137 : VASUBU_VV,
13138 : VASUBU_VX,
13139 : VASUB_VV,
13140 : VASUB_VX,
13141 : VBREV8_V,
13142 : VBREV_V,
13143 : VCLMULH_VV,
13144 : VCLMULH_VX,
13145 : VCLMUL_VV,
13146 : VCLMUL_VX,
13147 : VCLZ_V,
13148 : VCOMPRESS_VM,
13149 : VCPOP_M,
13150 : VCPOP_V,
13151 : VCTZ_V,
13152 : VC_FV,
13153 : VC_FVV,
13154 : VC_FVW,
13155 : VC_I,
13156 : VC_IV,
13157 : VC_IVV,
13158 : VC_IVW,
13159 : VC_VV,
13160 : VC_VVV,
13161 : VC_VVW,
13162 : VC_V_FV,
13163 : VC_V_FVV,
13164 : VC_V_FVW,
13165 : VC_V_I,
13166 : VC_V_IV,
13167 : VC_V_IVV,
13168 : VC_V_IVW,
13169 : VC_V_VV,
13170 : VC_V_VVV,
13171 : VC_V_VVW,
13172 : VC_V_X,
13173 : VC_V_XV,
13174 : VC_V_XVV,
13175 : VC_V_XVW,
13176 : VC_X,
13177 : VC_XV,
13178 : VC_XVV,
13179 : VC_XVW,
13180 : VDIVU_VV,
13181 : VDIVU_VX,
13182 : VDIV_VV,
13183 : VDIV_VX,
13184 : VFADD_VF,
13185 : VFADD_VV,
13186 : VFCLASS_V,
13187 : VFCVT_F_XU_V,
13188 : VFCVT_F_X_V,
13189 : VFCVT_RTZ_XU_F_V,
13190 : VFCVT_RTZ_X_F_V,
13191 : VFCVT_XU_F_V,
13192 : VFCVT_X_F_V,
13193 : VFDIV_VF,
13194 : VFDIV_VV,
13195 : VFIRST_M,
13196 : VFMACC_VF,
13197 : VFMACC_VV,
13198 : VFMADD_VF,
13199 : VFMADD_VV,
13200 : VFMAX_VF,
13201 : VFMAX_VV,
13202 : VFMERGE_VFM,
13203 : VFMIN_VF,
13204 : VFMIN_VV,
13205 : VFMSAC_VF,
13206 : VFMSAC_VV,
13207 : VFMSUB_VF,
13208 : VFMSUB_VV,
13209 : VFMUL_VF,
13210 : VFMUL_VV,
13211 : VFMV_F_S,
13212 : VFMV_S_F,
13213 : VFMV_V_F,
13214 : VFNCVTBF16_F_F_W,
13215 : VFNCVT_F_F_W,
13216 : VFNCVT_F_XU_W,
13217 : VFNCVT_F_X_W,
13218 : VFNCVT_ROD_F_F_W,
13219 : VFNCVT_RTZ_XU_F_W,
13220 : VFNCVT_RTZ_X_F_W,
13221 : VFNCVT_XU_F_W,
13222 : VFNCVT_X_F_W,
13223 : VFNMACC_VF,
13224 : VFNMACC_VV,
13225 : VFNMADD_VF,
13226 : VFNMADD_VV,
13227 : VFNMSAC_VF,
13228 : VFNMSAC_VV,
13229 : VFNMSUB_VF,
13230 : VFNMSUB_VV,
13231 : VFNRCLIP_XU_F_QF,
13232 : VFNRCLIP_X_F_QF,
13233 : VFRDIV_VF,
13234 : VFREC7_V,
13235 : VFREDMAX_VS,
13236 : VFREDMIN_VS,
13237 : VFREDOSUM_VS,
13238 : VFREDUSUM_VS,
13239 : VFRSQRT7_V,
13240 : VFRSUB_VF,
13241 : VFSGNJN_VF,
13242 : VFSGNJN_VV,
13243 : VFSGNJX_VF,
13244 : VFSGNJX_VV,
13245 : VFSGNJ_VF,
13246 : VFSGNJ_VV,
13247 : VFSLIDE1DOWN_VF,
13248 : VFSLIDE1UP_VF,
13249 : VFSQRT_V,
13250 : VFSUB_VF,
13251 : VFSUB_VV,
13252 : VFWADD_VF,
13253 : VFWADD_VV,
13254 : VFWADD_WF,
13255 : VFWADD_WV,
13256 : VFWCVTBF16_F_F_V,
13257 : VFWCVT_F_F_V,
13258 : VFWCVT_F_XU_V,
13259 : VFWCVT_F_X_V,
13260 : VFWCVT_RTZ_XU_F_V,
13261 : VFWCVT_RTZ_X_F_V,
13262 : VFWCVT_XU_F_V,
13263 : VFWCVT_X_F_V,
13264 : VFWMACCBF16_VF,
13265 : VFWMACCBF16_VV,
13266 : VFWMACC_4x4x4,
13267 : VFWMACC_VF,
13268 : VFWMACC_VV,
13269 : VFWMSAC_VF,
13270 : VFWMSAC_VV,
13271 : VFWMUL_VF,
13272 : VFWMUL_VV,
13273 : VFWNMACC_VF,
13274 : VFWNMACC_VV,
13275 : VFWNMSAC_VF,
13276 : VFWNMSAC_VV,
13277 : VFWREDOSUM_VS,
13278 : VFWREDUSUM_VS,
13279 : VFWSUB_VF,
13280 : VFWSUB_VV,
13281 : VFWSUB_WF,
13282 : VFWSUB_WV,
13283 : VGHSH_VV,
13284 : VGMUL_VV,
13285 : VID_V,
13286 : VIOTA_M,
13287 : VL1RE16_V,
13288 : VL1RE32_V,
13289 : VL1RE64_V,
13290 : VL1RE8_V,
13291 : VL2RE16_V,
13292 : VL2RE32_V,
13293 : VL2RE64_V,
13294 : VL2RE8_V,
13295 : VL4RE16_V,
13296 : VL4RE32_V,
13297 : VL4RE64_V,
13298 : VL4RE8_V,
13299 : VL8RE16_V,
13300 : VL8RE32_V,
13301 : VL8RE64_V,
13302 : VL8RE8_V,
13303 : VLE16FF_V,
13304 : VLE16_V,
13305 : VLE32FF_V,
13306 : VLE32_V,
13307 : VLE64FF_V,
13308 : VLE64_V,
13309 : VLE8FF_V,
13310 : VLE8_V,
13311 : VLM_V,
13312 : VLOXEI16_V,
13313 : VLOXEI32_V,
13314 : VLOXEI64_V,
13315 : VLOXEI8_V,
13316 : VLOXSEG2EI16_V,
13317 : VLOXSEG2EI32_V,
13318 : VLOXSEG2EI64_V,
13319 : VLOXSEG2EI8_V,
13320 : VLOXSEG3EI16_V,
13321 : VLOXSEG3EI32_V,
13322 : VLOXSEG3EI64_V,
13323 : VLOXSEG3EI8_V,
13324 : VLOXSEG4EI16_V,
13325 : VLOXSEG4EI32_V,
13326 : VLOXSEG4EI64_V,
13327 : VLOXSEG4EI8_V,
13328 : VLOXSEG5EI16_V,
13329 : VLOXSEG5EI32_V,
13330 : VLOXSEG5EI64_V,
13331 : VLOXSEG5EI8_V,
13332 : VLOXSEG6EI16_V,
13333 : VLOXSEG6EI32_V,
13334 : VLOXSEG6EI64_V,
13335 : VLOXSEG6EI8_V,
13336 : VLOXSEG7EI16_V,
13337 : VLOXSEG7EI32_V,
13338 : VLOXSEG7EI64_V,
13339 : VLOXSEG7EI8_V,
13340 : VLOXSEG8EI16_V,
13341 : VLOXSEG8EI32_V,
13342 : VLOXSEG8EI64_V,
13343 : VLOXSEG8EI8_V,
13344 : VLSE16_V,
13345 : VLSE32_V,
13346 : VLSE64_V,
13347 : VLSE8_V,
13348 : VLSEG2E16FF_V,
13349 : VLSEG2E16_V,
13350 : VLSEG2E32FF_V,
13351 : VLSEG2E32_V,
13352 : VLSEG2E64FF_V,
13353 : VLSEG2E64_V,
13354 : VLSEG2E8FF_V,
13355 : VLSEG2E8_V,
13356 : VLSEG3E16FF_V,
13357 : VLSEG3E16_V,
13358 : VLSEG3E32FF_V,
13359 : VLSEG3E32_V,
13360 : VLSEG3E64FF_V,
13361 : VLSEG3E64_V,
13362 : VLSEG3E8FF_V,
13363 : VLSEG3E8_V,
13364 : VLSEG4E16FF_V,
13365 : VLSEG4E16_V,
13366 : VLSEG4E32FF_V,
13367 : VLSEG4E32_V,
13368 : VLSEG4E64FF_V,
13369 : VLSEG4E64_V,
13370 : VLSEG4E8FF_V,
13371 : VLSEG4E8_V,
13372 : VLSEG5E16FF_V,
13373 : VLSEG5E16_V,
13374 : VLSEG5E32FF_V,
13375 : VLSEG5E32_V,
13376 : VLSEG5E64FF_V,
13377 : VLSEG5E64_V,
13378 : VLSEG5E8FF_V,
13379 : VLSEG5E8_V,
13380 : VLSEG6E16FF_V,
13381 : VLSEG6E16_V,
13382 : VLSEG6E32FF_V,
13383 : VLSEG6E32_V,
13384 : VLSEG6E64FF_V,
13385 : VLSEG6E64_V,
13386 : VLSEG6E8FF_V,
13387 : VLSEG6E8_V,
13388 : VLSEG7E16FF_V,
13389 : VLSEG7E16_V,
13390 : VLSEG7E32FF_V,
13391 : VLSEG7E32_V,
13392 : VLSEG7E64FF_V,
13393 : VLSEG7E64_V,
13394 : VLSEG7E8FF_V,
13395 : VLSEG7E8_V,
13396 : VLSEG8E16FF_V,
13397 : VLSEG8E16_V,
13398 : VLSEG8E32FF_V,
13399 : VLSEG8E32_V,
13400 : VLSEG8E64FF_V,
13401 : VLSEG8E64_V,
13402 : VLSEG8E8FF_V,
13403 : VLSEG8E8_V,
13404 : VLSSEG2E16_V,
13405 : VLSSEG2E32_V,
13406 : VLSSEG2E64_V,
13407 : VLSSEG2E8_V,
13408 : VLSSEG3E16_V,
13409 : VLSSEG3E32_V,
13410 : VLSSEG3E64_V,
13411 : VLSSEG3E8_V,
13412 : VLSSEG4E16_V,
13413 : VLSSEG4E32_V,
13414 : VLSSEG4E64_V,
13415 : VLSSEG4E8_V,
13416 : VLSSEG5E16_V,
13417 : VLSSEG5E32_V,
13418 : VLSSEG5E64_V,
13419 : VLSSEG5E8_V,
13420 : VLSSEG6E16_V,
13421 : VLSSEG6E32_V,
13422 : VLSSEG6E64_V,
13423 : VLSSEG6E8_V,
13424 : VLSSEG7E16_V,
13425 : VLSSEG7E32_V,
13426 : VLSSEG7E64_V,
13427 : VLSSEG7E8_V,
13428 : VLSSEG8E16_V,
13429 : VLSSEG8E32_V,
13430 : VLSSEG8E64_V,
13431 : VLSSEG8E8_V,
13432 : VLUXEI16_V,
13433 : VLUXEI32_V,
13434 : VLUXEI64_V,
13435 : VLUXEI8_V,
13436 : VLUXSEG2EI16_V,
13437 : VLUXSEG2EI32_V,
13438 : VLUXSEG2EI64_V,
13439 : VLUXSEG2EI8_V,
13440 : VLUXSEG3EI16_V,
13441 : VLUXSEG3EI32_V,
13442 : VLUXSEG3EI64_V,
13443 : VLUXSEG3EI8_V,
13444 : VLUXSEG4EI16_V,
13445 : VLUXSEG4EI32_V,
13446 : VLUXSEG4EI64_V,
13447 : VLUXSEG4EI8_V,
13448 : VLUXSEG5EI16_V,
13449 : VLUXSEG5EI32_V,
13450 : VLUXSEG5EI64_V,
13451 : VLUXSEG5EI8_V,
13452 : VLUXSEG6EI16_V,
13453 : VLUXSEG6EI32_V,
13454 : VLUXSEG6EI64_V,
13455 : VLUXSEG6EI8_V,
13456 : VLUXSEG7EI16_V,
13457 : VLUXSEG7EI32_V,
13458 : VLUXSEG7EI64_V,
13459 : VLUXSEG7EI8_V,
13460 : VLUXSEG8EI16_V,
13461 : VLUXSEG8EI32_V,
13462 : VLUXSEG8EI64_V,
13463 : VLUXSEG8EI8_V,
13464 : VMACC_VV,
13465 : VMACC_VX,
13466 : VMADC_VI,
13467 : VMADC_VIM,
13468 : VMADC_VV,
13469 : VMADC_VVM,
13470 : VMADC_VX,
13471 : VMADC_VXM,
13472 : VMADD_VV,
13473 : VMADD_VX,
13474 : VMANDN_MM,
13475 : VMAND_MM,
13476 : VMAXU_VV,
13477 : VMAXU_VX,
13478 : VMAX_VV,
13479 : VMAX_VX,
13480 : VMERGE_VIM,
13481 : VMERGE_VVM,
13482 : VMERGE_VXM,
13483 : VMFEQ_VF,
13484 : VMFEQ_VV,
13485 : VMFGE_VF,
13486 : VMFGT_VF,
13487 : VMFLE_VF,
13488 : VMFLE_VV,
13489 : VMFLT_VF,
13490 : VMFLT_VV,
13491 : VMFNE_VF,
13492 : VMFNE_VV,
13493 : VMINU_VV,
13494 : VMINU_VX,
13495 : VMIN_VV,
13496 : VMIN_VX,
13497 : VMNAND_MM,
13498 : VMNOR_MM,
13499 : VMORN_MM,
13500 : VMOR_MM,
13501 : VMSBC_VV,
13502 : VMSBC_VVM,
13503 : VMSBC_VX,
13504 : VMSBC_VXM,
13505 : VMSBF_M,
13506 : VMSEQ_VI,
13507 : VMSEQ_VV,
13508 : VMSEQ_VX,
13509 : VMSGTU_VI,
13510 : VMSGTU_VX,
13511 : VMSGT_VI,
13512 : VMSGT_VX,
13513 : VMSIF_M,
13514 : VMSLEU_VI,
13515 : VMSLEU_VV,
13516 : VMSLEU_VX,
13517 : VMSLE_VI,
13518 : VMSLE_VV,
13519 : VMSLE_VX,
13520 : VMSLTU_VV,
13521 : VMSLTU_VX,
13522 : VMSLT_VV,
13523 : VMSLT_VX,
13524 : VMSNE_VI,
13525 : VMSNE_VV,
13526 : VMSNE_VX,
13527 : VMSOF_M,
13528 : VMULHSU_VV,
13529 : VMULHSU_VX,
13530 : VMULHU_VV,
13531 : VMULHU_VX,
13532 : VMULH_VV,
13533 : VMULH_VX,
13534 : VMUL_VV,
13535 : VMUL_VX,
13536 : VMV1R_V,
13537 : VMV2R_V,
13538 : VMV4R_V,
13539 : VMV8R_V,
13540 : VMV_S_X,
13541 : VMV_V_I,
13542 : VMV_V_V,
13543 : VMV_V_X,
13544 : VMV_X_S,
13545 : VMXNOR_MM,
13546 : VMXOR_MM,
13547 : VNCLIPU_WI,
13548 : VNCLIPU_WV,
13549 : VNCLIPU_WX,
13550 : VNCLIP_WI,
13551 : VNCLIP_WV,
13552 : VNCLIP_WX,
13553 : VNMSAC_VV,
13554 : VNMSAC_VX,
13555 : VNMSUB_VV,
13556 : VNMSUB_VX,
13557 : VNSRA_WI,
13558 : VNSRA_WV,
13559 : VNSRA_WX,
13560 : VNSRL_WI,
13561 : VNSRL_WV,
13562 : VNSRL_WX,
13563 : VOR_VI,
13564 : VOR_VV,
13565 : VOR_VX,
13566 : VQMACCSU_2x8x2,
13567 : VQMACCSU_4x8x4,
13568 : VQMACCUS_2x8x2,
13569 : VQMACCUS_4x8x4,
13570 : VQMACCU_2x8x2,
13571 : VQMACCU_4x8x4,
13572 : VQMACC_2x8x2,
13573 : VQMACC_4x8x4,
13574 : VREDAND_VS,
13575 : VREDMAXU_VS,
13576 : VREDMAX_VS,
13577 : VREDMINU_VS,
13578 : VREDMIN_VS,
13579 : VREDOR_VS,
13580 : VREDSUM_VS,
13581 : VREDXOR_VS,
13582 : VREMU_VV,
13583 : VREMU_VX,
13584 : VREM_VV,
13585 : VREM_VX,
13586 : VREV8_V,
13587 : VRGATHEREI16_VV,
13588 : VRGATHER_VI,
13589 : VRGATHER_VV,
13590 : VRGATHER_VX,
13591 : VROL_VV,
13592 : VROL_VX,
13593 : VROR_VI,
13594 : VROR_VV,
13595 : VROR_VX,
13596 : VRSUB_VI,
13597 : VRSUB_VX,
13598 : VS1R_V,
13599 : VS2R_V,
13600 : VS4R_V,
13601 : VS8R_V,
13602 : VSADDU_VI,
13603 : VSADDU_VV,
13604 : VSADDU_VX,
13605 : VSADD_VI,
13606 : VSADD_VV,
13607 : VSADD_VX,
13608 : VSBC_VVM,
13609 : VSBC_VXM,
13610 : VSE16_V,
13611 : VSE32_V,
13612 : VSE64_V,
13613 : VSE8_V,
13614 : VSETIVLI,
13615 : VSETVL,
13616 : VSETVLI,
13617 : VSEXT_VF2,
13618 : VSEXT_VF4,
13619 : VSEXT_VF8,
13620 : VSHA2CH_VV,
13621 : VSHA2CL_VV,
13622 : VSHA2MS_VV,
13623 : VSLIDE1DOWN_VX,
13624 : VSLIDE1UP_VX,
13625 : VSLIDEDOWN_VI,
13626 : VSLIDEDOWN_VX,
13627 : VSLIDEUP_VI,
13628 : VSLIDEUP_VX,
13629 : VSLL_VI,
13630 : VSLL_VV,
13631 : VSLL_VX,
13632 : VSM3C_VI,
13633 : VSM3ME_VV,
13634 : VSM4K_VI,
13635 : VSM4R_VS,
13636 : VSM4R_VV,
13637 : VSMUL_VV,
13638 : VSMUL_VX,
13639 : VSM_V,
13640 : VSOXEI16_V,
13641 : VSOXEI32_V,
13642 : VSOXEI64_V,
13643 : VSOXEI8_V,
13644 : VSOXSEG2EI16_V,
13645 : VSOXSEG2EI32_V,
13646 : VSOXSEG2EI64_V,
13647 : VSOXSEG2EI8_V,
13648 : VSOXSEG3EI16_V,
13649 : VSOXSEG3EI32_V,
13650 : VSOXSEG3EI64_V,
13651 : VSOXSEG3EI8_V,
13652 : VSOXSEG4EI16_V,
13653 : VSOXSEG4EI32_V,
13654 : VSOXSEG4EI64_V,
13655 : VSOXSEG4EI8_V,
13656 : VSOXSEG5EI16_V,
13657 : VSOXSEG5EI32_V,
13658 : VSOXSEG5EI64_V,
13659 : VSOXSEG5EI8_V,
13660 : VSOXSEG6EI16_V,
13661 : VSOXSEG6EI32_V,
13662 : VSOXSEG6EI64_V,
13663 : VSOXSEG6EI8_V,
13664 : VSOXSEG7EI16_V,
13665 : VSOXSEG7EI32_V,
13666 : VSOXSEG7EI64_V,
13667 : VSOXSEG7EI8_V,
13668 : VSOXSEG8EI16_V,
13669 : VSOXSEG8EI32_V,
13670 : VSOXSEG8EI64_V,
13671 : VSOXSEG8EI8_V,
13672 : VSRA_VI,
13673 : VSRA_VV,
13674 : VSRA_VX,
13675 : VSRL_VI,
13676 : VSRL_VV,
13677 : VSRL_VX,
13678 : VSSE16_V,
13679 : VSSE32_V,
13680 : VSSE64_V,
13681 : VSSE8_V,
13682 : VSSEG2E16_V,
13683 : VSSEG2E32_V,
13684 : VSSEG2E64_V,
13685 : VSSEG2E8_V,
13686 : VSSEG3E16_V,
13687 : VSSEG3E32_V,
13688 : VSSEG3E64_V,
13689 : VSSEG3E8_V,
13690 : VSSEG4E16_V,
13691 : VSSEG4E32_V,
13692 : VSSEG4E64_V,
13693 : VSSEG4E8_V,
13694 : VSSEG5E16_V,
13695 : VSSEG5E32_V,
13696 : VSSEG5E64_V,
13697 : VSSEG5E8_V,
13698 : VSSEG6E16_V,
13699 : VSSEG6E32_V,
13700 : VSSEG6E64_V,
13701 : VSSEG6E8_V,
13702 : VSSEG7E16_V,
13703 : VSSEG7E32_V,
13704 : VSSEG7E64_V,
13705 : VSSEG7E8_V,
13706 : VSSEG8E16_V,
13707 : VSSEG8E32_V,
13708 : VSSEG8E64_V,
13709 : VSSEG8E8_V,
13710 : VSSRA_VI,
13711 : VSSRA_VV,
13712 : VSSRA_VX,
13713 : VSSRL_VI,
13714 : VSSRL_VV,
13715 : VSSRL_VX,
13716 : VSSSEG2E16_V,
13717 : VSSSEG2E32_V,
13718 : VSSSEG2E64_V,
13719 : VSSSEG2E8_V,
13720 : VSSSEG3E16_V,
13721 : VSSSEG3E32_V,
13722 : VSSSEG3E64_V,
13723 : VSSSEG3E8_V,
13724 : VSSSEG4E16_V,
13725 : VSSSEG4E32_V,
13726 : VSSSEG4E64_V,
13727 : VSSSEG4E8_V,
13728 : VSSSEG5E16_V,
13729 : VSSSEG5E32_V,
13730 : VSSSEG5E64_V,
13731 : VSSSEG5E8_V,
13732 : VSSSEG6E16_V,
13733 : VSSSEG6E32_V,
13734 : VSSSEG6E64_V,
13735 : VSSSEG6E8_V,
13736 : VSSSEG7E16_V,
13737 : VSSSEG7E32_V,
13738 : VSSSEG7E64_V,
13739 : VSSSEG7E8_V,
13740 : VSSSEG8E16_V,
13741 : VSSSEG8E32_V,
13742 : VSSSEG8E64_V,
13743 : VSSSEG8E8_V,
13744 : VSSUBU_VV,
13745 : VSSUBU_VX,
13746 : VSSUB_VV,
13747 : VSSUB_VX,
13748 : VSUB_VV,
13749 : VSUB_VX,
13750 : VSUXEI16_V,
13751 : VSUXEI32_V,
13752 : VSUXEI64_V,
13753 : VSUXEI8_V,
13754 : VSUXSEG2EI16_V,
13755 : VSUXSEG2EI32_V,
13756 : VSUXSEG2EI64_V,
13757 : VSUXSEG2EI8_V,
13758 : VSUXSEG3EI16_V,
13759 : VSUXSEG3EI32_V,
13760 : VSUXSEG3EI64_V,
13761 : VSUXSEG3EI8_V,
13762 : VSUXSEG4EI16_V,
13763 : VSUXSEG4EI32_V,
13764 : VSUXSEG4EI64_V,
13765 : VSUXSEG4EI8_V,
13766 : VSUXSEG5EI16_V,
13767 : VSUXSEG5EI32_V,
13768 : VSUXSEG5EI64_V,
13769 : VSUXSEG5EI8_V,
13770 : VSUXSEG6EI16_V,
13771 : VSUXSEG6EI32_V,
13772 : VSUXSEG6EI64_V,
13773 : VSUXSEG6EI8_V,
13774 : VSUXSEG7EI16_V,
13775 : VSUXSEG7EI32_V,
13776 : VSUXSEG7EI64_V,
13777 : VSUXSEG7EI8_V,
13778 : VSUXSEG8EI16_V,
13779 : VSUXSEG8EI32_V,
13780 : VSUXSEG8EI64_V,
13781 : VSUXSEG8EI8_V,
13782 : VT_MASKC,
13783 : VT_MASKCN,
13784 : VWADDU_VV,
13785 : VWADDU_VX,
13786 : VWADDU_WV,
13787 : VWADDU_WX,
13788 : VWADD_VV,
13789 : VWADD_VX,
13790 : VWADD_WV,
13791 : VWADD_WX,
13792 : VWMACCSU_VV,
13793 : VWMACCSU_VX,
13794 : VWMACCUS_VX,
13795 : VWMACCU_VV,
13796 : VWMACCU_VX,
13797 : VWMACC_VV,
13798 : VWMACC_VX,
13799 : VWMULSU_VV,
13800 : VWMULSU_VX,
13801 : VWMULU_VV,
13802 : VWMULU_VX,
13803 : VWMUL_VV,
13804 : VWMUL_VX,
13805 : VWREDSUMU_VS,
13806 : VWREDSUM_VS,
13807 : VWSLL_VI,
13808 : VWSLL_VV,
13809 : VWSLL_VX,
13810 : VWSUBU_VV,
13811 : VWSUBU_VX,
13812 : VWSUBU_WV,
13813 : VWSUBU_WX,
13814 : VWSUB_VV,
13815 : VWSUB_VX,
13816 : VWSUB_WV,
13817 : VWSUB_WX,
13818 : VXOR_VI,
13819 : VXOR_VV,
13820 : VXOR_VX,
13821 : VZEXT_VF2,
13822 : VZEXT_VF4,
13823 : VZEXT_VF8,
13824 : WFI,
13825 : WRS_NTO,
13826 : WRS_STO,
13827 : XNOR,
13828 : XOR,
13829 : XORI,
13830 : XPERM4,
13831 : XPERM8,
13832 : ZEXT_H_RV32,
13833 : ZEXT_H_RV64,
13834 : ZIP_RV32,
13835 : INSTRUCTION_LIST_END,
13836 : UNKNOWN(u64),
13837 : }
13838 :
13839 : impl From<u64> for Opcode {
13840 0 : fn from(value: u64) -> Self {
13841 0 : match value {
13842 0 : 0 => Opcode::PHI,
13843 0 : 1 => Opcode::INLINEASM,
13844 0 : 2 => Opcode::INLINEASM_BR,
13845 0 : 3 => Opcode::CFI_INSTRUCTION,
13846 0 : 4 => Opcode::EH_LABEL,
13847 0 : 5 => Opcode::GC_LABEL,
13848 0 : 6 => Opcode::ANNOTATION_LABEL,
13849 0 : 7 => Opcode::KILL,
13850 0 : 8 => Opcode::EXTRACT_SUBREG,
13851 0 : 9 => Opcode::INSERT_SUBREG,
13852 0 : 10 => Opcode::IMPLICIT_DEF,
13853 0 : 11 => Opcode::SUBREG_TO_REG,
13854 0 : 12 => Opcode::COPY_TO_REGCLASS,
13855 0 : 13 => Opcode::DBG_VALUE,
13856 0 : 14 => Opcode::DBG_VALUE_LIST,
13857 0 : 15 => Opcode::DBG_INSTR_REF,
13858 0 : 16 => Opcode::DBG_PHI,
13859 0 : 17 => Opcode::DBG_LABEL,
13860 0 : 18 => Opcode::REG_SEQUENCE,
13861 0 : 19 => Opcode::COPY,
13862 0 : 20 => Opcode::BUNDLE,
13863 0 : 21 => Opcode::LIFETIME_START,
13864 0 : 22 => Opcode::LIFETIME_END,
13865 0 : 23 => Opcode::PSEUDO_PROBE,
13866 0 : 24 => Opcode::ARITH_FENCE,
13867 0 : 25 => Opcode::STACKMAP,
13868 0 : 26 => Opcode::FENTRY_CALL,
13869 0 : 27 => Opcode::PATCHPOINT,
13870 0 : 28 => Opcode::LOAD_STACK_GUARD,
13871 0 : 29 => Opcode::PREALLOCATED_SETUP,
13872 0 : 30 => Opcode::PREALLOCATED_ARG,
13873 0 : 31 => Opcode::STATEPOINT,
13874 0 : 32 => Opcode::LOCAL_ESCAPE,
13875 0 : 33 => Opcode::FAULTING_OP,
13876 0 : 34 => Opcode::PATCHABLE_OP,
13877 0 : 35 => Opcode::PATCHABLE_FUNCTION_ENTER,
13878 0 : 36 => Opcode::PATCHABLE_RET,
13879 0 : 37 => Opcode::PATCHABLE_FUNCTION_EXIT,
13880 0 : 38 => Opcode::PATCHABLE_TAIL_CALL,
13881 0 : 39 => Opcode::PATCHABLE_EVENT_CALL,
13882 0 : 40 => Opcode::PATCHABLE_TYPED_EVENT_CALL,
13883 0 : 41 => Opcode::ICALL_BRANCH_FUNNEL,
13884 0 : 42 => Opcode::MEMBARRIER,
13885 0 : 43 => Opcode::JUMP_TABLE_DEBUG_INFO,
13886 0 : 44 => Opcode::CONVERGENCECTRL_ENTRY,
13887 0 : 45 => Opcode::CONVERGENCECTRL_ANCHOR,
13888 0 : 46 => Opcode::CONVERGENCECTRL_LOOP,
13889 0 : 47 => Opcode::CONVERGENCECTRL_GLUE,
13890 0 : 48 => Opcode::G_ASSERT_SEXT,
13891 0 : 49 => Opcode::G_ASSERT_ZEXT,
13892 0 : 50 => Opcode::G_ASSERT_ALIGN,
13893 0 : 51 => Opcode::G_ADD,
13894 0 : 52 => Opcode::G_SUB,
13895 0 : 53 => Opcode::G_MUL,
13896 0 : 54 => Opcode::G_SDIV,
13897 0 : 55 => Opcode::G_UDIV,
13898 0 : 56 => Opcode::G_SREM,
13899 0 : 57 => Opcode::G_UREM,
13900 0 : 58 => Opcode::G_SDIVREM,
13901 0 : 59 => Opcode::G_UDIVREM,
13902 0 : 60 => Opcode::G_AND,
13903 0 : 61 => Opcode::G_OR,
13904 0 : 62 => Opcode::G_XOR,
13905 0 : 63 => Opcode::G_IMPLICIT_DEF,
13906 0 : 64 => Opcode::G_PHI,
13907 0 : 65 => Opcode::G_FRAME_INDEX,
13908 0 : 66 => Opcode::G_GLOBAL_VALUE,
13909 0 : 67 => Opcode::G_PTRAUTH_GLOBAL_VALUE,
13910 0 : 68 => Opcode::G_CONSTANT_POOL,
13911 0 : 69 => Opcode::G_EXTRACT,
13912 0 : 70 => Opcode::G_UNMERGE_VALUES,
13913 0 : 71 => Opcode::G_INSERT,
13914 0 : 72 => Opcode::G_MERGE_VALUES,
13915 0 : 73 => Opcode::G_BUILD_VECTOR,
13916 0 : 74 => Opcode::G_BUILD_VECTOR_TRUNC,
13917 0 : 75 => Opcode::G_CONCAT_VECTORS,
13918 0 : 76 => Opcode::G_PTRTOINT,
13919 0 : 77 => Opcode::G_INTTOPTR,
13920 0 : 78 => Opcode::G_BITCAST,
13921 0 : 79 => Opcode::G_FREEZE,
13922 0 : 80 => Opcode::G_CONSTANT_FOLD_BARRIER,
13923 0 : 81 => Opcode::G_INTRINSIC_FPTRUNC_ROUND,
13924 0 : 82 => Opcode::G_INTRINSIC_TRUNC,
13925 0 : 83 => Opcode::G_INTRINSIC_ROUND,
13926 0 : 84 => Opcode::G_INTRINSIC_LRINT,
13927 0 : 85 => Opcode::G_INTRINSIC_LLRINT,
13928 0 : 86 => Opcode::G_INTRINSIC_ROUNDEVEN,
13929 0 : 87 => Opcode::G_READCYCLECOUNTER,
13930 0 : 88 => Opcode::G_READSTEADYCOUNTER,
13931 0 : 89 => Opcode::G_LOAD,
13932 0 : 90 => Opcode::G_SEXTLOAD,
13933 0 : 91 => Opcode::G_ZEXTLOAD,
13934 0 : 92 => Opcode::G_INDEXED_LOAD,
13935 0 : 93 => Opcode::G_INDEXED_SEXTLOAD,
13936 0 : 94 => Opcode::G_INDEXED_ZEXTLOAD,
13937 0 : 95 => Opcode::G_STORE,
13938 0 : 96 => Opcode::G_INDEXED_STORE,
13939 0 : 97 => Opcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS,
13940 0 : 98 => Opcode::G_ATOMIC_CMPXCHG,
13941 0 : 99 => Opcode::G_ATOMICRMW_XCHG,
13942 0 : 100 => Opcode::G_ATOMICRMW_ADD,
13943 0 : 101 => Opcode::G_ATOMICRMW_SUB,
13944 0 : 102 => Opcode::G_ATOMICRMW_AND,
13945 0 : 103 => Opcode::G_ATOMICRMW_NAND,
13946 0 : 104 => Opcode::G_ATOMICRMW_OR,
13947 0 : 105 => Opcode::G_ATOMICRMW_XOR,
13948 0 : 106 => Opcode::G_ATOMICRMW_MAX,
13949 0 : 107 => Opcode::G_ATOMICRMW_MIN,
13950 0 : 108 => Opcode::G_ATOMICRMW_UMAX,
13951 0 : 109 => Opcode::G_ATOMICRMW_UMIN,
13952 0 : 110 => Opcode::G_ATOMICRMW_FADD,
13953 0 : 111 => Opcode::G_ATOMICRMW_FSUB,
13954 0 : 112 => Opcode::G_ATOMICRMW_FMAX,
13955 0 : 113 => Opcode::G_ATOMICRMW_FMIN,
13956 0 : 114 => Opcode::G_ATOMICRMW_UINC_WRAP,
13957 0 : 115 => Opcode::G_ATOMICRMW_UDEC_WRAP,
13958 0 : 116 => Opcode::G_FENCE,
13959 0 : 117 => Opcode::G_PREFETCH,
13960 0 : 118 => Opcode::G_BRCOND,
13961 0 : 119 => Opcode::G_BRINDIRECT,
13962 0 : 120 => Opcode::G_INVOKE_REGION_START,
13963 0 : 121 => Opcode::G_INTRINSIC,
13964 0 : 122 => Opcode::G_INTRINSIC_W_SIDE_EFFECTS,
13965 0 : 123 => Opcode::G_INTRINSIC_CONVERGENT,
13966 0 : 124 => Opcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS,
13967 0 : 125 => Opcode::G_ANYEXT,
13968 0 : 126 => Opcode::G_TRUNC,
13969 0 : 127 => Opcode::G_CONSTANT,
13970 0 : 128 => Opcode::G_FCONSTANT,
13971 0 : 129 => Opcode::G_VASTART,
13972 0 : 130 => Opcode::G_VAARG,
13973 0 : 131 => Opcode::G_SEXT,
13974 0 : 132 => Opcode::G_SEXT_INREG,
13975 0 : 133 => Opcode::G_ZEXT,
13976 0 : 134 => Opcode::G_SHL,
13977 0 : 135 => Opcode::G_LSHR,
13978 0 : 136 => Opcode::G_ASHR,
13979 0 : 137 => Opcode::G_FSHL,
13980 0 : 138 => Opcode::G_FSHR,
13981 0 : 139 => Opcode::G_ROTR,
13982 0 : 140 => Opcode::G_ROTL,
13983 0 : 141 => Opcode::G_ICMP,
13984 0 : 142 => Opcode::G_FCMP,
13985 0 : 143 => Opcode::G_SCMP,
13986 0 : 144 => Opcode::G_UCMP,
13987 0 : 145 => Opcode::G_SELECT,
13988 0 : 146 => Opcode::G_UADDO,
13989 0 : 147 => Opcode::G_UADDE,
13990 0 : 148 => Opcode::G_USUBO,
13991 0 : 149 => Opcode::G_USUBE,
13992 0 : 150 => Opcode::G_SADDO,
13993 0 : 151 => Opcode::G_SADDE,
13994 0 : 152 => Opcode::G_SSUBO,
13995 0 : 153 => Opcode::G_SSUBE,
13996 0 : 154 => Opcode::G_UMULO,
13997 0 : 155 => Opcode::G_SMULO,
13998 0 : 156 => Opcode::G_UMULH,
13999 0 : 157 => Opcode::G_SMULH,
14000 0 : 158 => Opcode::G_UADDSAT,
14001 0 : 159 => Opcode::G_SADDSAT,
14002 0 : 160 => Opcode::G_USUBSAT,
14003 0 : 161 => Opcode::G_SSUBSAT,
14004 0 : 162 => Opcode::G_USHLSAT,
14005 0 : 163 => Opcode::G_SSHLSAT,
14006 0 : 164 => Opcode::G_SMULFIX,
14007 0 : 165 => Opcode::G_UMULFIX,
14008 0 : 166 => Opcode::G_SMULFIXSAT,
14009 0 : 167 => Opcode::G_UMULFIXSAT,
14010 0 : 168 => Opcode::G_SDIVFIX,
14011 0 : 169 => Opcode::G_UDIVFIX,
14012 0 : 170 => Opcode::G_SDIVFIXSAT,
14013 0 : 171 => Opcode::G_UDIVFIXSAT,
14014 0 : 172 => Opcode::G_FADD,
14015 0 : 173 => Opcode::G_FSUB,
14016 0 : 174 => Opcode::G_FMUL,
14017 0 : 175 => Opcode::G_FMA,
14018 0 : 176 => Opcode::G_FMAD,
14019 0 : 177 => Opcode::G_FDIV,
14020 0 : 178 => Opcode::G_FREM,
14021 0 : 179 => Opcode::G_FPOW,
14022 0 : 180 => Opcode::G_FPOWI,
14023 0 : 181 => Opcode::G_FEXP,
14024 0 : 182 => Opcode::G_FEXP2,
14025 0 : 183 => Opcode::G_FEXP10,
14026 0 : 184 => Opcode::G_FLOG,
14027 0 : 185 => Opcode::G_FLOG2,
14028 0 : 186 => Opcode::G_FLOG10,
14029 0 : 187 => Opcode::G_FLDEXP,
14030 0 : 188 => Opcode::G_FFREXP,
14031 0 : 189 => Opcode::G_FNEG,
14032 0 : 190 => Opcode::G_FPEXT,
14033 0 : 191 => Opcode::G_FPTRUNC,
14034 0 : 192 => Opcode::G_FPTOSI,
14035 0 : 193 => Opcode::G_FPTOUI,
14036 0 : 194 => Opcode::G_SITOFP,
14037 0 : 195 => Opcode::G_UITOFP,
14038 0 : 196 => Opcode::G_FABS,
14039 0 : 197 => Opcode::G_FCOPYSIGN,
14040 0 : 198 => Opcode::G_IS_FPCLASS,
14041 0 : 199 => Opcode::G_FCANONICALIZE,
14042 0 : 200 => Opcode::G_FMINNUM,
14043 0 : 201 => Opcode::G_FMAXNUM,
14044 0 : 202 => Opcode::G_FMINNUM_IEEE,
14045 0 : 203 => Opcode::G_FMAXNUM_IEEE,
14046 0 : 204 => Opcode::G_FMINIMUM,
14047 0 : 205 => Opcode::G_FMAXIMUM,
14048 0 : 206 => Opcode::G_GET_FPENV,
14049 0 : 207 => Opcode::G_SET_FPENV,
14050 0 : 208 => Opcode::G_RESET_FPENV,
14051 0 : 209 => Opcode::G_GET_FPMODE,
14052 0 : 210 => Opcode::G_SET_FPMODE,
14053 0 : 211 => Opcode::G_RESET_FPMODE,
14054 0 : 212 => Opcode::G_PTR_ADD,
14055 0 : 213 => Opcode::G_PTRMASK,
14056 0 : 214 => Opcode::G_SMIN,
14057 0 : 215 => Opcode::G_SMAX,
14058 0 : 216 => Opcode::G_UMIN,
14059 0 : 217 => Opcode::G_UMAX,
14060 0 : 218 => Opcode::G_ABS,
14061 0 : 219 => Opcode::G_LROUND,
14062 0 : 220 => Opcode::G_LLROUND,
14063 0 : 221 => Opcode::G_BR,
14064 0 : 222 => Opcode::G_BRJT,
14065 0 : 223 => Opcode::G_VSCALE,
14066 0 : 224 => Opcode::G_INSERT_SUBVECTOR,
14067 0 : 225 => Opcode::G_EXTRACT_SUBVECTOR,
14068 0 : 226 => Opcode::G_INSERT_VECTOR_ELT,
14069 0 : 227 => Opcode::G_EXTRACT_VECTOR_ELT,
14070 0 : 228 => Opcode::G_SHUFFLE_VECTOR,
14071 0 : 229 => Opcode::G_SPLAT_VECTOR,
14072 0 : 230 => Opcode::G_VECTOR_COMPRESS,
14073 0 : 231 => Opcode::G_CTTZ,
14074 0 : 232 => Opcode::G_CTTZ_ZERO_UNDEF,
14075 0 : 233 => Opcode::G_CTLZ,
14076 0 : 234 => Opcode::G_CTLZ_ZERO_UNDEF,
14077 0 : 235 => Opcode::G_CTPOP,
14078 0 : 236 => Opcode::G_BSWAP,
14079 0 : 237 => Opcode::G_BITREVERSE,
14080 0 : 238 => Opcode::G_FCEIL,
14081 0 : 239 => Opcode::G_FCOS,
14082 0 : 240 => Opcode::G_FSIN,
14083 0 : 241 => Opcode::G_FTAN,
14084 0 : 242 => Opcode::G_FACOS,
14085 0 : 243 => Opcode::G_FASIN,
14086 0 : 244 => Opcode::G_FATAN,
14087 0 : 245 => Opcode::G_FCOSH,
14088 0 : 246 => Opcode::G_FSINH,
14089 0 : 247 => Opcode::G_FTANH,
14090 0 : 248 => Opcode::G_FSQRT,
14091 0 : 249 => Opcode::G_FFLOOR,
14092 0 : 250 => Opcode::G_FRINT,
14093 0 : 251 => Opcode::G_FNEARBYINT,
14094 0 : 252 => Opcode::G_ADDRSPACE_CAST,
14095 0 : 253 => Opcode::G_BLOCK_ADDR,
14096 0 : 254 => Opcode::G_JUMP_TABLE,
14097 0 : 255 => Opcode::G_DYN_STACKALLOC,
14098 0 : 256 => Opcode::G_STACKSAVE,
14099 0 : 257 => Opcode::G_STACKRESTORE,
14100 0 : 258 => Opcode::G_STRICT_FADD,
14101 0 : 259 => Opcode::G_STRICT_FSUB,
14102 0 : 260 => Opcode::G_STRICT_FMUL,
14103 0 : 261 => Opcode::G_STRICT_FDIV,
14104 0 : 262 => Opcode::G_STRICT_FREM,
14105 0 : 263 => Opcode::G_STRICT_FMA,
14106 0 : 264 => Opcode::G_STRICT_FSQRT,
14107 0 : 265 => Opcode::G_STRICT_FLDEXP,
14108 0 : 266 => Opcode::G_READ_REGISTER,
14109 0 : 267 => Opcode::G_WRITE_REGISTER,
14110 0 : 268 => Opcode::G_MEMCPY,
14111 0 : 269 => Opcode::G_MEMCPY_INLINE,
14112 0 : 270 => Opcode::G_MEMMOVE,
14113 0 : 271 => Opcode::G_MEMSET,
14114 0 : 272 => Opcode::G_BZERO,
14115 0 : 273 => Opcode::G_TRAP,
14116 0 : 274 => Opcode::G_DEBUGTRAP,
14117 0 : 275 => Opcode::G_UBSANTRAP,
14118 0 : 276 => Opcode::G_VECREDUCE_SEQ_FADD,
14119 0 : 277 => Opcode::G_VECREDUCE_SEQ_FMUL,
14120 0 : 278 => Opcode::G_VECREDUCE_FADD,
14121 0 : 279 => Opcode::G_VECREDUCE_FMUL,
14122 0 : 280 => Opcode::G_VECREDUCE_FMAX,
14123 0 : 281 => Opcode::G_VECREDUCE_FMIN,
14124 0 : 282 => Opcode::G_VECREDUCE_FMAXIMUM,
14125 0 : 283 => Opcode::G_VECREDUCE_FMINIMUM,
14126 0 : 284 => Opcode::G_VECREDUCE_ADD,
14127 0 : 285 => Opcode::G_VECREDUCE_MUL,
14128 0 : 286 => Opcode::G_VECREDUCE_AND,
14129 0 : 287 => Opcode::G_VECREDUCE_OR,
14130 0 : 288 => Opcode::G_VECREDUCE_XOR,
14131 0 : 289 => Opcode::G_VECREDUCE_SMAX,
14132 0 : 290 => Opcode::G_VECREDUCE_SMIN,
14133 0 : 291 => Opcode::G_VECREDUCE_UMAX,
14134 0 : 292 => Opcode::G_VECREDUCE_UMIN,
14135 0 : 293 => Opcode::G_SBFX,
14136 0 : 294 => Opcode::G_UBFX,
14137 0 : 295 => Opcode::ADJCALLSTACKDOWN,
14138 0 : 296 => Opcode::ADJCALLSTACKUP,
14139 0 : 297 => Opcode::BuildPairF64Pseudo,
14140 0 : 298 => Opcode::G_FCLASS,
14141 0 : 299 => Opcode::G_READ_VLENB,
14142 0 : 300 => Opcode::G_SPLAT_VECTOR_SPLIT_I64_VL,
14143 0 : 301 => Opcode::G_VMCLR_VL,
14144 0 : 302 => Opcode::G_VMSET_VL,
14145 0 : 303 => Opcode::HWASAN_CHECK_MEMACCESS_SHORTGRANULES,
14146 0 : 304 => Opcode::KCFI_CHECK,
14147 0 : 305 => Opcode::PseudoAddTPRel,
14148 0 : 306 => Opcode::PseudoAtomicLoadNand32,
14149 0 : 307 => Opcode::PseudoAtomicLoadNand64,
14150 0 : 308 => Opcode::PseudoBR,
14151 0 : 309 => Opcode::PseudoBRIND,
14152 0 : 310 => Opcode::PseudoBRINDNonX7,
14153 0 : 311 => Opcode::PseudoBRINDX7,
14154 0 : 312 => Opcode::PseudoCALL,
14155 0 : 313 => Opcode::PseudoCALLIndirect,
14156 0 : 314 => Opcode::PseudoCALLIndirectNonX7,
14157 0 : 315 => Opcode::PseudoCALLReg,
14158 0 : 316 => Opcode::PseudoCCADD,
14159 0 : 317 => Opcode::PseudoCCADDI,
14160 0 : 318 => Opcode::PseudoCCADDIW,
14161 0 : 319 => Opcode::PseudoCCADDW,
14162 0 : 320 => Opcode::PseudoCCAND,
14163 0 : 321 => Opcode::PseudoCCANDI,
14164 0 : 322 => Opcode::PseudoCCANDN,
14165 0 : 323 => Opcode::PseudoCCMOVGPR,
14166 0 : 324 => Opcode::PseudoCCMOVGPRNoX0,
14167 0 : 325 => Opcode::PseudoCCOR,
14168 0 : 326 => Opcode::PseudoCCORI,
14169 0 : 327 => Opcode::PseudoCCORN,
14170 0 : 328 => Opcode::PseudoCCSLL,
14171 0 : 329 => Opcode::PseudoCCSLLI,
14172 0 : 330 => Opcode::PseudoCCSLLIW,
14173 0 : 331 => Opcode::PseudoCCSLLW,
14174 0 : 332 => Opcode::PseudoCCSRA,
14175 0 : 333 => Opcode::PseudoCCSRAI,
14176 0 : 334 => Opcode::PseudoCCSRAIW,
14177 0 : 335 => Opcode::PseudoCCSRAW,
14178 0 : 336 => Opcode::PseudoCCSRL,
14179 0 : 337 => Opcode::PseudoCCSRLI,
14180 0 : 338 => Opcode::PseudoCCSRLIW,
14181 0 : 339 => Opcode::PseudoCCSRLW,
14182 0 : 340 => Opcode::PseudoCCSUB,
14183 0 : 341 => Opcode::PseudoCCSUBW,
14184 0 : 342 => Opcode::PseudoCCXNOR,
14185 0 : 343 => Opcode::PseudoCCXOR,
14186 0 : 344 => Opcode::PseudoCCXORI,
14187 0 : 345 => Opcode::PseudoCmpXchg32,
14188 0 : 346 => Opcode::PseudoCmpXchg64,
14189 0 : 347 => Opcode::PseudoFLD,
14190 0 : 348 => Opcode::PseudoFLH,
14191 0 : 349 => Opcode::PseudoFLW,
14192 0 : 350 => Opcode::PseudoFROUND_D,
14193 0 : 351 => Opcode::PseudoFROUND_D_IN32X,
14194 0 : 352 => Opcode::PseudoFROUND_D_INX,
14195 0 : 353 => Opcode::PseudoFROUND_H,
14196 0 : 354 => Opcode::PseudoFROUND_H_INX,
14197 0 : 355 => Opcode::PseudoFROUND_S,
14198 0 : 356 => Opcode::PseudoFROUND_S_INX,
14199 0 : 357 => Opcode::PseudoFSD,
14200 0 : 358 => Opcode::PseudoFSH,
14201 0 : 359 => Opcode::PseudoFSW,
14202 0 : 360 => Opcode::PseudoJump,
14203 0 : 361 => Opcode::PseudoLA,
14204 0 : 362 => Opcode::PseudoLAImm,
14205 0 : 363 => Opcode::PseudoLA_TLSDESC,
14206 0 : 364 => Opcode::PseudoLA_TLS_GD,
14207 0 : 365 => Opcode::PseudoLA_TLS_IE,
14208 0 : 366 => Opcode::PseudoLB,
14209 0 : 367 => Opcode::PseudoLBU,
14210 0 : 368 => Opcode::PseudoLD,
14211 0 : 369 => Opcode::PseudoLGA,
14212 0 : 370 => Opcode::PseudoLH,
14213 0 : 371 => Opcode::PseudoLHU,
14214 0 : 372 => Opcode::PseudoLI,
14215 0 : 373 => Opcode::PseudoLLA,
14216 0 : 374 => Opcode::PseudoLLAImm,
14217 0 : 375 => Opcode::PseudoLW,
14218 0 : 376 => Opcode::PseudoLWU,
14219 0 : 377 => Opcode::PseudoLongBEQ,
14220 0 : 378 => Opcode::PseudoLongBGE,
14221 0 : 379 => Opcode::PseudoLongBGEU,
14222 0 : 380 => Opcode::PseudoLongBLT,
14223 0 : 381 => Opcode::PseudoLongBLTU,
14224 0 : 382 => Opcode::PseudoLongBNE,
14225 0 : 383 => Opcode::PseudoMaskedAtomicLoadAdd32,
14226 0 : 384 => Opcode::PseudoMaskedAtomicLoadMax32,
14227 0 : 385 => Opcode::PseudoMaskedAtomicLoadMin32,
14228 0 : 386 => Opcode::PseudoMaskedAtomicLoadNand32,
14229 0 : 387 => Opcode::PseudoMaskedAtomicLoadSub32,
14230 0 : 388 => Opcode::PseudoMaskedAtomicLoadUMax32,
14231 0 : 389 => Opcode::PseudoMaskedAtomicLoadUMin32,
14232 0 : 390 => Opcode::PseudoMaskedAtomicSwap32,
14233 0 : 391 => Opcode::PseudoMaskedCmpXchg32,
14234 0 : 392 => Opcode::PseudoMovAddr,
14235 0 : 393 => Opcode::PseudoMovImm,
14236 0 : 394 => Opcode::PseudoQuietFLE_D,
14237 0 : 395 => Opcode::PseudoQuietFLE_D_IN32X,
14238 0 : 396 => Opcode::PseudoQuietFLE_D_INX,
14239 0 : 397 => Opcode::PseudoQuietFLE_H,
14240 0 : 398 => Opcode::PseudoQuietFLE_H_INX,
14241 0 : 399 => Opcode::PseudoQuietFLE_S,
14242 0 : 400 => Opcode::PseudoQuietFLE_S_INX,
14243 0 : 401 => Opcode::PseudoQuietFLT_D,
14244 0 : 402 => Opcode::PseudoQuietFLT_D_IN32X,
14245 0 : 403 => Opcode::PseudoQuietFLT_D_INX,
14246 0 : 404 => Opcode::PseudoQuietFLT_H,
14247 0 : 405 => Opcode::PseudoQuietFLT_H_INX,
14248 0 : 406 => Opcode::PseudoQuietFLT_S,
14249 0 : 407 => Opcode::PseudoQuietFLT_S_INX,
14250 0 : 408 => Opcode::PseudoRET,
14251 0 : 409 => Opcode::PseudoRV32ZdinxLD,
14252 0 : 410 => Opcode::PseudoRV32ZdinxSD,
14253 0 : 411 => Opcode::PseudoRVVInitUndefM1,
14254 0 : 412 => Opcode::PseudoRVVInitUndefM2,
14255 0 : 413 => Opcode::PseudoRVVInitUndefM4,
14256 0 : 414 => Opcode::PseudoRVVInitUndefM8,
14257 0 : 415 => Opcode::PseudoReadVL,
14258 0 : 416 => Opcode::PseudoReadVLENB,
14259 0 : 417 => Opcode::PseudoSB,
14260 0 : 418 => Opcode::PseudoSD,
14261 0 : 419 => Opcode::PseudoSEXT_B,
14262 0 : 420 => Opcode::PseudoSEXT_H,
14263 0 : 421 => Opcode::PseudoSH,
14264 0 : 422 => Opcode::PseudoSW,
14265 0 : 423 => Opcode::PseudoTAIL,
14266 0 : 424 => Opcode::PseudoTAILIndirect,
14267 0 : 425 => Opcode::PseudoTAILIndirectNonX7,
14268 0 : 426 => Opcode::PseudoTHVdotVMAQASU_VV_M1,
14269 0 : 427 => Opcode::PseudoTHVdotVMAQASU_VV_M1_MASK,
14270 0 : 428 => Opcode::PseudoTHVdotVMAQASU_VV_M2,
14271 0 : 429 => Opcode::PseudoTHVdotVMAQASU_VV_M2_MASK,
14272 0 : 430 => Opcode::PseudoTHVdotVMAQASU_VV_M4,
14273 0 : 431 => Opcode::PseudoTHVdotVMAQASU_VV_M4_MASK,
14274 0 : 432 => Opcode::PseudoTHVdotVMAQASU_VV_M8,
14275 0 : 433 => Opcode::PseudoTHVdotVMAQASU_VV_M8_MASK,
14276 0 : 434 => Opcode::PseudoTHVdotVMAQASU_VV_MF2,
14277 0 : 435 => Opcode::PseudoTHVdotVMAQASU_VV_MF2_MASK,
14278 0 : 436 => Opcode::PseudoTHVdotVMAQASU_VX_M1,
14279 0 : 437 => Opcode::PseudoTHVdotVMAQASU_VX_M1_MASK,
14280 0 : 438 => Opcode::PseudoTHVdotVMAQASU_VX_M2,
14281 0 : 439 => Opcode::PseudoTHVdotVMAQASU_VX_M2_MASK,
14282 0 : 440 => Opcode::PseudoTHVdotVMAQASU_VX_M4,
14283 0 : 441 => Opcode::PseudoTHVdotVMAQASU_VX_M4_MASK,
14284 0 : 442 => Opcode::PseudoTHVdotVMAQASU_VX_M8,
14285 0 : 443 => Opcode::PseudoTHVdotVMAQASU_VX_M8_MASK,
14286 0 : 444 => Opcode::PseudoTHVdotVMAQASU_VX_MF2,
14287 0 : 445 => Opcode::PseudoTHVdotVMAQASU_VX_MF2_MASK,
14288 0 : 446 => Opcode::PseudoTHVdotVMAQAUS_VX_M1,
14289 0 : 447 => Opcode::PseudoTHVdotVMAQAUS_VX_M1_MASK,
14290 0 : 448 => Opcode::PseudoTHVdotVMAQAUS_VX_M2,
14291 0 : 449 => Opcode::PseudoTHVdotVMAQAUS_VX_M2_MASK,
14292 0 : 450 => Opcode::PseudoTHVdotVMAQAUS_VX_M4,
14293 0 : 451 => Opcode::PseudoTHVdotVMAQAUS_VX_M4_MASK,
14294 0 : 452 => Opcode::PseudoTHVdotVMAQAUS_VX_M8,
14295 0 : 453 => Opcode::PseudoTHVdotVMAQAUS_VX_M8_MASK,
14296 0 : 454 => Opcode::PseudoTHVdotVMAQAUS_VX_MF2,
14297 0 : 455 => Opcode::PseudoTHVdotVMAQAUS_VX_MF2_MASK,
14298 0 : 456 => Opcode::PseudoTHVdotVMAQAU_VV_M1,
14299 0 : 457 => Opcode::PseudoTHVdotVMAQAU_VV_M1_MASK,
14300 0 : 458 => Opcode::PseudoTHVdotVMAQAU_VV_M2,
14301 0 : 459 => Opcode::PseudoTHVdotVMAQAU_VV_M2_MASK,
14302 0 : 460 => Opcode::PseudoTHVdotVMAQAU_VV_M4,
14303 0 : 461 => Opcode::PseudoTHVdotVMAQAU_VV_M4_MASK,
14304 0 : 462 => Opcode::PseudoTHVdotVMAQAU_VV_M8,
14305 0 : 463 => Opcode::PseudoTHVdotVMAQAU_VV_M8_MASK,
14306 0 : 464 => Opcode::PseudoTHVdotVMAQAU_VV_MF2,
14307 0 : 465 => Opcode::PseudoTHVdotVMAQAU_VV_MF2_MASK,
14308 0 : 466 => Opcode::PseudoTHVdotVMAQAU_VX_M1,
14309 0 : 467 => Opcode::PseudoTHVdotVMAQAU_VX_M1_MASK,
14310 0 : 468 => Opcode::PseudoTHVdotVMAQAU_VX_M2,
14311 0 : 469 => Opcode::PseudoTHVdotVMAQAU_VX_M2_MASK,
14312 0 : 470 => Opcode::PseudoTHVdotVMAQAU_VX_M4,
14313 0 : 471 => Opcode::PseudoTHVdotVMAQAU_VX_M4_MASK,
14314 0 : 472 => Opcode::PseudoTHVdotVMAQAU_VX_M8,
14315 0 : 473 => Opcode::PseudoTHVdotVMAQAU_VX_M8_MASK,
14316 0 : 474 => Opcode::PseudoTHVdotVMAQAU_VX_MF2,
14317 0 : 475 => Opcode::PseudoTHVdotVMAQAU_VX_MF2_MASK,
14318 0 : 476 => Opcode::PseudoTHVdotVMAQA_VV_M1,
14319 0 : 477 => Opcode::PseudoTHVdotVMAQA_VV_M1_MASK,
14320 0 : 478 => Opcode::PseudoTHVdotVMAQA_VV_M2,
14321 0 : 479 => Opcode::PseudoTHVdotVMAQA_VV_M2_MASK,
14322 0 : 480 => Opcode::PseudoTHVdotVMAQA_VV_M4,
14323 0 : 481 => Opcode::PseudoTHVdotVMAQA_VV_M4_MASK,
14324 0 : 482 => Opcode::PseudoTHVdotVMAQA_VV_M8,
14325 0 : 483 => Opcode::PseudoTHVdotVMAQA_VV_M8_MASK,
14326 0 : 484 => Opcode::PseudoTHVdotVMAQA_VV_MF2,
14327 0 : 485 => Opcode::PseudoTHVdotVMAQA_VV_MF2_MASK,
14328 0 : 486 => Opcode::PseudoTHVdotVMAQA_VX_M1,
14329 0 : 487 => Opcode::PseudoTHVdotVMAQA_VX_M1_MASK,
14330 0 : 488 => Opcode::PseudoTHVdotVMAQA_VX_M2,
14331 0 : 489 => Opcode::PseudoTHVdotVMAQA_VX_M2_MASK,
14332 0 : 490 => Opcode::PseudoTHVdotVMAQA_VX_M4,
14333 0 : 491 => Opcode::PseudoTHVdotVMAQA_VX_M4_MASK,
14334 0 : 492 => Opcode::PseudoTHVdotVMAQA_VX_M8,
14335 0 : 493 => Opcode::PseudoTHVdotVMAQA_VX_M8_MASK,
14336 0 : 494 => Opcode::PseudoTHVdotVMAQA_VX_MF2,
14337 0 : 495 => Opcode::PseudoTHVdotVMAQA_VX_MF2_MASK,
14338 0 : 496 => Opcode::PseudoTLSDESCCall,
14339 0 : 497 => Opcode::PseudoVAADDU_VV_M1,
14340 0 : 498 => Opcode::PseudoVAADDU_VV_M1_MASK,
14341 0 : 499 => Opcode::PseudoVAADDU_VV_M2,
14342 0 : 500 => Opcode::PseudoVAADDU_VV_M2_MASK,
14343 0 : 501 => Opcode::PseudoVAADDU_VV_M4,
14344 0 : 502 => Opcode::PseudoVAADDU_VV_M4_MASK,
14345 0 : 503 => Opcode::PseudoVAADDU_VV_M8,
14346 0 : 504 => Opcode::PseudoVAADDU_VV_M8_MASK,
14347 0 : 505 => Opcode::PseudoVAADDU_VV_MF2,
14348 0 : 506 => Opcode::PseudoVAADDU_VV_MF2_MASK,
14349 0 : 507 => Opcode::PseudoVAADDU_VV_MF4,
14350 0 : 508 => Opcode::PseudoVAADDU_VV_MF4_MASK,
14351 0 : 509 => Opcode::PseudoVAADDU_VV_MF8,
14352 0 : 510 => Opcode::PseudoVAADDU_VV_MF8_MASK,
14353 0 : 511 => Opcode::PseudoVAADDU_VX_M1,
14354 0 : 512 => Opcode::PseudoVAADDU_VX_M1_MASK,
14355 0 : 513 => Opcode::PseudoVAADDU_VX_M2,
14356 0 : 514 => Opcode::PseudoVAADDU_VX_M2_MASK,
14357 0 : 515 => Opcode::PseudoVAADDU_VX_M4,
14358 0 : 516 => Opcode::PseudoVAADDU_VX_M4_MASK,
14359 0 : 517 => Opcode::PseudoVAADDU_VX_M8,
14360 0 : 518 => Opcode::PseudoVAADDU_VX_M8_MASK,
14361 0 : 519 => Opcode::PseudoVAADDU_VX_MF2,
14362 0 : 520 => Opcode::PseudoVAADDU_VX_MF2_MASK,
14363 0 : 521 => Opcode::PseudoVAADDU_VX_MF4,
14364 0 : 522 => Opcode::PseudoVAADDU_VX_MF4_MASK,
14365 0 : 523 => Opcode::PseudoVAADDU_VX_MF8,
14366 0 : 524 => Opcode::PseudoVAADDU_VX_MF8_MASK,
14367 0 : 525 => Opcode::PseudoVAADD_VV_M1,
14368 0 : 526 => Opcode::PseudoVAADD_VV_M1_MASK,
14369 0 : 527 => Opcode::PseudoVAADD_VV_M2,
14370 0 : 528 => Opcode::PseudoVAADD_VV_M2_MASK,
14371 0 : 529 => Opcode::PseudoVAADD_VV_M4,
14372 0 : 530 => Opcode::PseudoVAADD_VV_M4_MASK,
14373 0 : 531 => Opcode::PseudoVAADD_VV_M8,
14374 0 : 532 => Opcode::PseudoVAADD_VV_M8_MASK,
14375 0 : 533 => Opcode::PseudoVAADD_VV_MF2,
14376 0 : 534 => Opcode::PseudoVAADD_VV_MF2_MASK,
14377 0 : 535 => Opcode::PseudoVAADD_VV_MF4,
14378 0 : 536 => Opcode::PseudoVAADD_VV_MF4_MASK,
14379 0 : 537 => Opcode::PseudoVAADD_VV_MF8,
14380 0 : 538 => Opcode::PseudoVAADD_VV_MF8_MASK,
14381 0 : 539 => Opcode::PseudoVAADD_VX_M1,
14382 0 : 540 => Opcode::PseudoVAADD_VX_M1_MASK,
14383 0 : 541 => Opcode::PseudoVAADD_VX_M2,
14384 0 : 542 => Opcode::PseudoVAADD_VX_M2_MASK,
14385 0 : 543 => Opcode::PseudoVAADD_VX_M4,
14386 0 : 544 => Opcode::PseudoVAADD_VX_M4_MASK,
14387 0 : 545 => Opcode::PseudoVAADD_VX_M8,
14388 0 : 546 => Opcode::PseudoVAADD_VX_M8_MASK,
14389 0 : 547 => Opcode::PseudoVAADD_VX_MF2,
14390 0 : 548 => Opcode::PseudoVAADD_VX_MF2_MASK,
14391 0 : 549 => Opcode::PseudoVAADD_VX_MF4,
14392 0 : 550 => Opcode::PseudoVAADD_VX_MF4_MASK,
14393 0 : 551 => Opcode::PseudoVAADD_VX_MF8,
14394 0 : 552 => Opcode::PseudoVAADD_VX_MF8_MASK,
14395 0 : 553 => Opcode::PseudoVADC_VIM_M1,
14396 0 : 554 => Opcode::PseudoVADC_VIM_M2,
14397 0 : 555 => Opcode::PseudoVADC_VIM_M4,
14398 0 : 556 => Opcode::PseudoVADC_VIM_M8,
14399 0 : 557 => Opcode::PseudoVADC_VIM_MF2,
14400 0 : 558 => Opcode::PseudoVADC_VIM_MF4,
14401 0 : 559 => Opcode::PseudoVADC_VIM_MF8,
14402 0 : 560 => Opcode::PseudoVADC_VVM_M1,
14403 0 : 561 => Opcode::PseudoVADC_VVM_M2,
14404 0 : 562 => Opcode::PseudoVADC_VVM_M4,
14405 0 : 563 => Opcode::PseudoVADC_VVM_M8,
14406 0 : 564 => Opcode::PseudoVADC_VVM_MF2,
14407 0 : 565 => Opcode::PseudoVADC_VVM_MF4,
14408 0 : 566 => Opcode::PseudoVADC_VVM_MF8,
14409 0 : 567 => Opcode::PseudoVADC_VXM_M1,
14410 0 : 568 => Opcode::PseudoVADC_VXM_M2,
14411 0 : 569 => Opcode::PseudoVADC_VXM_M4,
14412 0 : 570 => Opcode::PseudoVADC_VXM_M8,
14413 0 : 571 => Opcode::PseudoVADC_VXM_MF2,
14414 0 : 572 => Opcode::PseudoVADC_VXM_MF4,
14415 0 : 573 => Opcode::PseudoVADC_VXM_MF8,
14416 0 : 574 => Opcode::PseudoVADD_VI_M1,
14417 0 : 575 => Opcode::PseudoVADD_VI_M1_MASK,
14418 0 : 576 => Opcode::PseudoVADD_VI_M2,
14419 0 : 577 => Opcode::PseudoVADD_VI_M2_MASK,
14420 0 : 578 => Opcode::PseudoVADD_VI_M4,
14421 0 : 579 => Opcode::PseudoVADD_VI_M4_MASK,
14422 0 : 580 => Opcode::PseudoVADD_VI_M8,
14423 0 : 581 => Opcode::PseudoVADD_VI_M8_MASK,
14424 0 : 582 => Opcode::PseudoVADD_VI_MF2,
14425 0 : 583 => Opcode::PseudoVADD_VI_MF2_MASK,
14426 0 : 584 => Opcode::PseudoVADD_VI_MF4,
14427 0 : 585 => Opcode::PseudoVADD_VI_MF4_MASK,
14428 0 : 586 => Opcode::PseudoVADD_VI_MF8,
14429 0 : 587 => Opcode::PseudoVADD_VI_MF8_MASK,
14430 0 : 588 => Opcode::PseudoVADD_VV_M1,
14431 0 : 589 => Opcode::PseudoVADD_VV_M1_MASK,
14432 0 : 590 => Opcode::PseudoVADD_VV_M2,
14433 0 : 591 => Opcode::PseudoVADD_VV_M2_MASK,
14434 0 : 592 => Opcode::PseudoVADD_VV_M4,
14435 0 : 593 => Opcode::PseudoVADD_VV_M4_MASK,
14436 0 : 594 => Opcode::PseudoVADD_VV_M8,
14437 0 : 595 => Opcode::PseudoVADD_VV_M8_MASK,
14438 0 : 596 => Opcode::PseudoVADD_VV_MF2,
14439 0 : 597 => Opcode::PseudoVADD_VV_MF2_MASK,
14440 0 : 598 => Opcode::PseudoVADD_VV_MF4,
14441 0 : 599 => Opcode::PseudoVADD_VV_MF4_MASK,
14442 0 : 600 => Opcode::PseudoVADD_VV_MF8,
14443 0 : 601 => Opcode::PseudoVADD_VV_MF8_MASK,
14444 0 : 602 => Opcode::PseudoVADD_VX_M1,
14445 0 : 603 => Opcode::PseudoVADD_VX_M1_MASK,
14446 0 : 604 => Opcode::PseudoVADD_VX_M2,
14447 0 : 605 => Opcode::PseudoVADD_VX_M2_MASK,
14448 0 : 606 => Opcode::PseudoVADD_VX_M4,
14449 0 : 607 => Opcode::PseudoVADD_VX_M4_MASK,
14450 0 : 608 => Opcode::PseudoVADD_VX_M8,
14451 0 : 609 => Opcode::PseudoVADD_VX_M8_MASK,
14452 0 : 610 => Opcode::PseudoVADD_VX_MF2,
14453 0 : 611 => Opcode::PseudoVADD_VX_MF2_MASK,
14454 0 : 612 => Opcode::PseudoVADD_VX_MF4,
14455 0 : 613 => Opcode::PseudoVADD_VX_MF4_MASK,
14456 0 : 614 => Opcode::PseudoVADD_VX_MF8,
14457 0 : 615 => Opcode::PseudoVADD_VX_MF8_MASK,
14458 0 : 616 => Opcode::PseudoVAESDF_VS_M1_M1,
14459 0 : 617 => Opcode::PseudoVAESDF_VS_M1_MF2,
14460 0 : 618 => Opcode::PseudoVAESDF_VS_M1_MF4,
14461 0 : 619 => Opcode::PseudoVAESDF_VS_M1_MF8,
14462 0 : 620 => Opcode::PseudoVAESDF_VS_M2_M1,
14463 0 : 621 => Opcode::PseudoVAESDF_VS_M2_M2,
14464 0 : 622 => Opcode::PseudoVAESDF_VS_M2_MF2,
14465 0 : 623 => Opcode::PseudoVAESDF_VS_M2_MF4,
14466 0 : 624 => Opcode::PseudoVAESDF_VS_M2_MF8,
14467 0 : 625 => Opcode::PseudoVAESDF_VS_M4_M1,
14468 0 : 626 => Opcode::PseudoVAESDF_VS_M4_M2,
14469 0 : 627 => Opcode::PseudoVAESDF_VS_M4_M4,
14470 0 : 628 => Opcode::PseudoVAESDF_VS_M4_MF2,
14471 0 : 629 => Opcode::PseudoVAESDF_VS_M4_MF4,
14472 0 : 630 => Opcode::PseudoVAESDF_VS_M4_MF8,
14473 0 : 631 => Opcode::PseudoVAESDF_VS_M8_M1,
14474 0 : 632 => Opcode::PseudoVAESDF_VS_M8_M2,
14475 0 : 633 => Opcode::PseudoVAESDF_VS_M8_M4,
14476 0 : 634 => Opcode::PseudoVAESDF_VS_M8_MF2,
14477 0 : 635 => Opcode::PseudoVAESDF_VS_M8_MF4,
14478 0 : 636 => Opcode::PseudoVAESDF_VS_M8_MF8,
14479 0 : 637 => Opcode::PseudoVAESDF_VS_MF2_MF2,
14480 0 : 638 => Opcode::PseudoVAESDF_VS_MF2_MF4,
14481 0 : 639 => Opcode::PseudoVAESDF_VS_MF2_MF8,
14482 0 : 640 => Opcode::PseudoVAESDF_VV_M1,
14483 0 : 641 => Opcode::PseudoVAESDF_VV_M2,
14484 0 : 642 => Opcode::PseudoVAESDF_VV_M4,
14485 0 : 643 => Opcode::PseudoVAESDF_VV_M8,
14486 0 : 644 => Opcode::PseudoVAESDF_VV_MF2,
14487 0 : 645 => Opcode::PseudoVAESDM_VS_M1_M1,
14488 0 : 646 => Opcode::PseudoVAESDM_VS_M1_MF2,
14489 0 : 647 => Opcode::PseudoVAESDM_VS_M1_MF4,
14490 0 : 648 => Opcode::PseudoVAESDM_VS_M1_MF8,
14491 0 : 649 => Opcode::PseudoVAESDM_VS_M2_M1,
14492 0 : 650 => Opcode::PseudoVAESDM_VS_M2_M2,
14493 0 : 651 => Opcode::PseudoVAESDM_VS_M2_MF2,
14494 0 : 652 => Opcode::PseudoVAESDM_VS_M2_MF4,
14495 0 : 653 => Opcode::PseudoVAESDM_VS_M2_MF8,
14496 0 : 654 => Opcode::PseudoVAESDM_VS_M4_M1,
14497 0 : 655 => Opcode::PseudoVAESDM_VS_M4_M2,
14498 0 : 656 => Opcode::PseudoVAESDM_VS_M4_M4,
14499 0 : 657 => Opcode::PseudoVAESDM_VS_M4_MF2,
14500 0 : 658 => Opcode::PseudoVAESDM_VS_M4_MF4,
14501 0 : 659 => Opcode::PseudoVAESDM_VS_M4_MF8,
14502 0 : 660 => Opcode::PseudoVAESDM_VS_M8_M1,
14503 0 : 661 => Opcode::PseudoVAESDM_VS_M8_M2,
14504 0 : 662 => Opcode::PseudoVAESDM_VS_M8_M4,
14505 0 : 663 => Opcode::PseudoVAESDM_VS_M8_MF2,
14506 0 : 664 => Opcode::PseudoVAESDM_VS_M8_MF4,
14507 0 : 665 => Opcode::PseudoVAESDM_VS_M8_MF8,
14508 0 : 666 => Opcode::PseudoVAESDM_VS_MF2_MF2,
14509 0 : 667 => Opcode::PseudoVAESDM_VS_MF2_MF4,
14510 0 : 668 => Opcode::PseudoVAESDM_VS_MF2_MF8,
14511 0 : 669 => Opcode::PseudoVAESDM_VV_M1,
14512 0 : 670 => Opcode::PseudoVAESDM_VV_M2,
14513 0 : 671 => Opcode::PseudoVAESDM_VV_M4,
14514 0 : 672 => Opcode::PseudoVAESDM_VV_M8,
14515 0 : 673 => Opcode::PseudoVAESDM_VV_MF2,
14516 0 : 674 => Opcode::PseudoVAESEF_VS_M1_M1,
14517 0 : 675 => Opcode::PseudoVAESEF_VS_M1_MF2,
14518 0 : 676 => Opcode::PseudoVAESEF_VS_M1_MF4,
14519 0 : 677 => Opcode::PseudoVAESEF_VS_M1_MF8,
14520 0 : 678 => Opcode::PseudoVAESEF_VS_M2_M1,
14521 0 : 679 => Opcode::PseudoVAESEF_VS_M2_M2,
14522 0 : 680 => Opcode::PseudoVAESEF_VS_M2_MF2,
14523 0 : 681 => Opcode::PseudoVAESEF_VS_M2_MF4,
14524 0 : 682 => Opcode::PseudoVAESEF_VS_M2_MF8,
14525 0 : 683 => Opcode::PseudoVAESEF_VS_M4_M1,
14526 0 : 684 => Opcode::PseudoVAESEF_VS_M4_M2,
14527 0 : 685 => Opcode::PseudoVAESEF_VS_M4_M4,
14528 0 : 686 => Opcode::PseudoVAESEF_VS_M4_MF2,
14529 0 : 687 => Opcode::PseudoVAESEF_VS_M4_MF4,
14530 0 : 688 => Opcode::PseudoVAESEF_VS_M4_MF8,
14531 0 : 689 => Opcode::PseudoVAESEF_VS_M8_M1,
14532 0 : 690 => Opcode::PseudoVAESEF_VS_M8_M2,
14533 0 : 691 => Opcode::PseudoVAESEF_VS_M8_M4,
14534 0 : 692 => Opcode::PseudoVAESEF_VS_M8_MF2,
14535 0 : 693 => Opcode::PseudoVAESEF_VS_M8_MF4,
14536 0 : 694 => Opcode::PseudoVAESEF_VS_M8_MF8,
14537 0 : 695 => Opcode::PseudoVAESEF_VS_MF2_MF2,
14538 0 : 696 => Opcode::PseudoVAESEF_VS_MF2_MF4,
14539 0 : 697 => Opcode::PseudoVAESEF_VS_MF2_MF8,
14540 0 : 698 => Opcode::PseudoVAESEF_VV_M1,
14541 0 : 699 => Opcode::PseudoVAESEF_VV_M2,
14542 0 : 700 => Opcode::PseudoVAESEF_VV_M4,
14543 0 : 701 => Opcode::PseudoVAESEF_VV_M8,
14544 0 : 702 => Opcode::PseudoVAESEF_VV_MF2,
14545 0 : 703 => Opcode::PseudoVAESEM_VS_M1_M1,
14546 0 : 704 => Opcode::PseudoVAESEM_VS_M1_MF2,
14547 0 : 705 => Opcode::PseudoVAESEM_VS_M1_MF4,
14548 0 : 706 => Opcode::PseudoVAESEM_VS_M1_MF8,
14549 0 : 707 => Opcode::PseudoVAESEM_VS_M2_M1,
14550 0 : 708 => Opcode::PseudoVAESEM_VS_M2_M2,
14551 0 : 709 => Opcode::PseudoVAESEM_VS_M2_MF2,
14552 0 : 710 => Opcode::PseudoVAESEM_VS_M2_MF4,
14553 0 : 711 => Opcode::PseudoVAESEM_VS_M2_MF8,
14554 0 : 712 => Opcode::PseudoVAESEM_VS_M4_M1,
14555 0 : 713 => Opcode::PseudoVAESEM_VS_M4_M2,
14556 0 : 714 => Opcode::PseudoVAESEM_VS_M4_M4,
14557 0 : 715 => Opcode::PseudoVAESEM_VS_M4_MF2,
14558 0 : 716 => Opcode::PseudoVAESEM_VS_M4_MF4,
14559 0 : 717 => Opcode::PseudoVAESEM_VS_M4_MF8,
14560 0 : 718 => Opcode::PseudoVAESEM_VS_M8_M1,
14561 0 : 719 => Opcode::PseudoVAESEM_VS_M8_M2,
14562 0 : 720 => Opcode::PseudoVAESEM_VS_M8_M4,
14563 0 : 721 => Opcode::PseudoVAESEM_VS_M8_MF2,
14564 0 : 722 => Opcode::PseudoVAESEM_VS_M8_MF4,
14565 0 : 723 => Opcode::PseudoVAESEM_VS_M8_MF8,
14566 0 : 724 => Opcode::PseudoVAESEM_VS_MF2_MF2,
14567 0 : 725 => Opcode::PseudoVAESEM_VS_MF2_MF4,
14568 0 : 726 => Opcode::PseudoVAESEM_VS_MF2_MF8,
14569 0 : 727 => Opcode::PseudoVAESEM_VV_M1,
14570 0 : 728 => Opcode::PseudoVAESEM_VV_M2,
14571 0 : 729 => Opcode::PseudoVAESEM_VV_M4,
14572 0 : 730 => Opcode::PseudoVAESEM_VV_M8,
14573 0 : 731 => Opcode::PseudoVAESEM_VV_MF2,
14574 0 : 732 => Opcode::PseudoVAESKF1_VI_M1,
14575 0 : 733 => Opcode::PseudoVAESKF1_VI_M2,
14576 0 : 734 => Opcode::PseudoVAESKF1_VI_M4,
14577 0 : 735 => Opcode::PseudoVAESKF1_VI_M8,
14578 0 : 736 => Opcode::PseudoVAESKF1_VI_MF2,
14579 0 : 737 => Opcode::PseudoVAESKF2_VI_M1,
14580 0 : 738 => Opcode::PseudoVAESKF2_VI_M2,
14581 0 : 739 => Opcode::PseudoVAESKF2_VI_M4,
14582 0 : 740 => Opcode::PseudoVAESKF2_VI_M8,
14583 0 : 741 => Opcode::PseudoVAESKF2_VI_MF2,
14584 0 : 742 => Opcode::PseudoVAESZ_VS_M1_M1,
14585 0 : 743 => Opcode::PseudoVAESZ_VS_M1_MF2,
14586 0 : 744 => Opcode::PseudoVAESZ_VS_M1_MF4,
14587 0 : 745 => Opcode::PseudoVAESZ_VS_M1_MF8,
14588 0 : 746 => Opcode::PseudoVAESZ_VS_M2_M1,
14589 0 : 747 => Opcode::PseudoVAESZ_VS_M2_M2,
14590 0 : 748 => Opcode::PseudoVAESZ_VS_M2_MF2,
14591 0 : 749 => Opcode::PseudoVAESZ_VS_M2_MF4,
14592 0 : 750 => Opcode::PseudoVAESZ_VS_M2_MF8,
14593 0 : 751 => Opcode::PseudoVAESZ_VS_M4_M1,
14594 0 : 752 => Opcode::PseudoVAESZ_VS_M4_M2,
14595 0 : 753 => Opcode::PseudoVAESZ_VS_M4_M4,
14596 0 : 754 => Opcode::PseudoVAESZ_VS_M4_MF2,
14597 0 : 755 => Opcode::PseudoVAESZ_VS_M4_MF4,
14598 0 : 756 => Opcode::PseudoVAESZ_VS_M4_MF8,
14599 0 : 757 => Opcode::PseudoVAESZ_VS_M8_M1,
14600 0 : 758 => Opcode::PseudoVAESZ_VS_M8_M2,
14601 0 : 759 => Opcode::PseudoVAESZ_VS_M8_M4,
14602 0 : 760 => Opcode::PseudoVAESZ_VS_M8_MF2,
14603 0 : 761 => Opcode::PseudoVAESZ_VS_M8_MF4,
14604 0 : 762 => Opcode::PseudoVAESZ_VS_M8_MF8,
14605 0 : 763 => Opcode::PseudoVAESZ_VS_MF2_MF2,
14606 0 : 764 => Opcode::PseudoVAESZ_VS_MF2_MF4,
14607 0 : 765 => Opcode::PseudoVAESZ_VS_MF2_MF8,
14608 0 : 766 => Opcode::PseudoVANDN_VV_M1,
14609 0 : 767 => Opcode::PseudoVANDN_VV_M1_MASK,
14610 0 : 768 => Opcode::PseudoVANDN_VV_M2,
14611 0 : 769 => Opcode::PseudoVANDN_VV_M2_MASK,
14612 0 : 770 => Opcode::PseudoVANDN_VV_M4,
14613 0 : 771 => Opcode::PseudoVANDN_VV_M4_MASK,
14614 0 : 772 => Opcode::PseudoVANDN_VV_M8,
14615 0 : 773 => Opcode::PseudoVANDN_VV_M8_MASK,
14616 0 : 774 => Opcode::PseudoVANDN_VV_MF2,
14617 0 : 775 => Opcode::PseudoVANDN_VV_MF2_MASK,
14618 0 : 776 => Opcode::PseudoVANDN_VV_MF4,
14619 0 : 777 => Opcode::PseudoVANDN_VV_MF4_MASK,
14620 0 : 778 => Opcode::PseudoVANDN_VV_MF8,
14621 0 : 779 => Opcode::PseudoVANDN_VV_MF8_MASK,
14622 0 : 780 => Opcode::PseudoVANDN_VX_M1,
14623 0 : 781 => Opcode::PseudoVANDN_VX_M1_MASK,
14624 0 : 782 => Opcode::PseudoVANDN_VX_M2,
14625 0 : 783 => Opcode::PseudoVANDN_VX_M2_MASK,
14626 0 : 784 => Opcode::PseudoVANDN_VX_M4,
14627 0 : 785 => Opcode::PseudoVANDN_VX_M4_MASK,
14628 0 : 786 => Opcode::PseudoVANDN_VX_M8,
14629 0 : 787 => Opcode::PseudoVANDN_VX_M8_MASK,
14630 0 : 788 => Opcode::PseudoVANDN_VX_MF2,
14631 0 : 789 => Opcode::PseudoVANDN_VX_MF2_MASK,
14632 0 : 790 => Opcode::PseudoVANDN_VX_MF4,
14633 0 : 791 => Opcode::PseudoVANDN_VX_MF4_MASK,
14634 0 : 792 => Opcode::PseudoVANDN_VX_MF8,
14635 0 : 793 => Opcode::PseudoVANDN_VX_MF8_MASK,
14636 0 : 794 => Opcode::PseudoVAND_VI_M1,
14637 0 : 795 => Opcode::PseudoVAND_VI_M1_MASK,
14638 0 : 796 => Opcode::PseudoVAND_VI_M2,
14639 0 : 797 => Opcode::PseudoVAND_VI_M2_MASK,
14640 0 : 798 => Opcode::PseudoVAND_VI_M4,
14641 0 : 799 => Opcode::PseudoVAND_VI_M4_MASK,
14642 0 : 800 => Opcode::PseudoVAND_VI_M8,
14643 0 : 801 => Opcode::PseudoVAND_VI_M8_MASK,
14644 0 : 802 => Opcode::PseudoVAND_VI_MF2,
14645 0 : 803 => Opcode::PseudoVAND_VI_MF2_MASK,
14646 0 : 804 => Opcode::PseudoVAND_VI_MF4,
14647 0 : 805 => Opcode::PseudoVAND_VI_MF4_MASK,
14648 0 : 806 => Opcode::PseudoVAND_VI_MF8,
14649 0 : 807 => Opcode::PseudoVAND_VI_MF8_MASK,
14650 0 : 808 => Opcode::PseudoVAND_VV_M1,
14651 0 : 809 => Opcode::PseudoVAND_VV_M1_MASK,
14652 0 : 810 => Opcode::PseudoVAND_VV_M2,
14653 0 : 811 => Opcode::PseudoVAND_VV_M2_MASK,
14654 0 : 812 => Opcode::PseudoVAND_VV_M4,
14655 0 : 813 => Opcode::PseudoVAND_VV_M4_MASK,
14656 0 : 814 => Opcode::PseudoVAND_VV_M8,
14657 0 : 815 => Opcode::PseudoVAND_VV_M8_MASK,
14658 0 : 816 => Opcode::PseudoVAND_VV_MF2,
14659 0 : 817 => Opcode::PseudoVAND_VV_MF2_MASK,
14660 0 : 818 => Opcode::PseudoVAND_VV_MF4,
14661 0 : 819 => Opcode::PseudoVAND_VV_MF4_MASK,
14662 0 : 820 => Opcode::PseudoVAND_VV_MF8,
14663 0 : 821 => Opcode::PseudoVAND_VV_MF8_MASK,
14664 0 : 822 => Opcode::PseudoVAND_VX_M1,
14665 0 : 823 => Opcode::PseudoVAND_VX_M1_MASK,
14666 0 : 824 => Opcode::PseudoVAND_VX_M2,
14667 0 : 825 => Opcode::PseudoVAND_VX_M2_MASK,
14668 0 : 826 => Opcode::PseudoVAND_VX_M4,
14669 0 : 827 => Opcode::PseudoVAND_VX_M4_MASK,
14670 0 : 828 => Opcode::PseudoVAND_VX_M8,
14671 0 : 829 => Opcode::PseudoVAND_VX_M8_MASK,
14672 0 : 830 => Opcode::PseudoVAND_VX_MF2,
14673 0 : 831 => Opcode::PseudoVAND_VX_MF2_MASK,
14674 0 : 832 => Opcode::PseudoVAND_VX_MF4,
14675 0 : 833 => Opcode::PseudoVAND_VX_MF4_MASK,
14676 0 : 834 => Opcode::PseudoVAND_VX_MF8,
14677 0 : 835 => Opcode::PseudoVAND_VX_MF8_MASK,
14678 0 : 836 => Opcode::PseudoVASUBU_VV_M1,
14679 0 : 837 => Opcode::PseudoVASUBU_VV_M1_MASK,
14680 0 : 838 => Opcode::PseudoVASUBU_VV_M2,
14681 0 : 839 => Opcode::PseudoVASUBU_VV_M2_MASK,
14682 0 : 840 => Opcode::PseudoVASUBU_VV_M4,
14683 0 : 841 => Opcode::PseudoVASUBU_VV_M4_MASK,
14684 0 : 842 => Opcode::PseudoVASUBU_VV_M8,
14685 0 : 843 => Opcode::PseudoVASUBU_VV_M8_MASK,
14686 0 : 844 => Opcode::PseudoVASUBU_VV_MF2,
14687 0 : 845 => Opcode::PseudoVASUBU_VV_MF2_MASK,
14688 0 : 846 => Opcode::PseudoVASUBU_VV_MF4,
14689 0 : 847 => Opcode::PseudoVASUBU_VV_MF4_MASK,
14690 0 : 848 => Opcode::PseudoVASUBU_VV_MF8,
14691 0 : 849 => Opcode::PseudoVASUBU_VV_MF8_MASK,
14692 0 : 850 => Opcode::PseudoVASUBU_VX_M1,
14693 0 : 851 => Opcode::PseudoVASUBU_VX_M1_MASK,
14694 0 : 852 => Opcode::PseudoVASUBU_VX_M2,
14695 0 : 853 => Opcode::PseudoVASUBU_VX_M2_MASK,
14696 0 : 854 => Opcode::PseudoVASUBU_VX_M4,
14697 0 : 855 => Opcode::PseudoVASUBU_VX_M4_MASK,
14698 0 : 856 => Opcode::PseudoVASUBU_VX_M8,
14699 0 : 857 => Opcode::PseudoVASUBU_VX_M8_MASK,
14700 0 : 858 => Opcode::PseudoVASUBU_VX_MF2,
14701 0 : 859 => Opcode::PseudoVASUBU_VX_MF2_MASK,
14702 0 : 860 => Opcode::PseudoVASUBU_VX_MF4,
14703 0 : 861 => Opcode::PseudoVASUBU_VX_MF4_MASK,
14704 0 : 862 => Opcode::PseudoVASUBU_VX_MF8,
14705 0 : 863 => Opcode::PseudoVASUBU_VX_MF8_MASK,
14706 0 : 864 => Opcode::PseudoVASUB_VV_M1,
14707 0 : 865 => Opcode::PseudoVASUB_VV_M1_MASK,
14708 0 : 866 => Opcode::PseudoVASUB_VV_M2,
14709 0 : 867 => Opcode::PseudoVASUB_VV_M2_MASK,
14710 0 : 868 => Opcode::PseudoVASUB_VV_M4,
14711 0 : 869 => Opcode::PseudoVASUB_VV_M4_MASK,
14712 0 : 870 => Opcode::PseudoVASUB_VV_M8,
14713 0 : 871 => Opcode::PseudoVASUB_VV_M8_MASK,
14714 0 : 872 => Opcode::PseudoVASUB_VV_MF2,
14715 0 : 873 => Opcode::PseudoVASUB_VV_MF2_MASK,
14716 0 : 874 => Opcode::PseudoVASUB_VV_MF4,
14717 0 : 875 => Opcode::PseudoVASUB_VV_MF4_MASK,
14718 0 : 876 => Opcode::PseudoVASUB_VV_MF8,
14719 0 : 877 => Opcode::PseudoVASUB_VV_MF8_MASK,
14720 0 : 878 => Opcode::PseudoVASUB_VX_M1,
14721 0 : 879 => Opcode::PseudoVASUB_VX_M1_MASK,
14722 0 : 880 => Opcode::PseudoVASUB_VX_M2,
14723 0 : 881 => Opcode::PseudoVASUB_VX_M2_MASK,
14724 0 : 882 => Opcode::PseudoVASUB_VX_M4,
14725 0 : 883 => Opcode::PseudoVASUB_VX_M4_MASK,
14726 0 : 884 => Opcode::PseudoVASUB_VX_M8,
14727 0 : 885 => Opcode::PseudoVASUB_VX_M8_MASK,
14728 0 : 886 => Opcode::PseudoVASUB_VX_MF2,
14729 0 : 887 => Opcode::PseudoVASUB_VX_MF2_MASK,
14730 0 : 888 => Opcode::PseudoVASUB_VX_MF4,
14731 0 : 889 => Opcode::PseudoVASUB_VX_MF4_MASK,
14732 0 : 890 => Opcode::PseudoVASUB_VX_MF8,
14733 0 : 891 => Opcode::PseudoVASUB_VX_MF8_MASK,
14734 0 : 892 => Opcode::PseudoVBREV8_V_M1,
14735 0 : 893 => Opcode::PseudoVBREV8_V_M1_MASK,
14736 0 : 894 => Opcode::PseudoVBREV8_V_M2,
14737 0 : 895 => Opcode::PseudoVBREV8_V_M2_MASK,
14738 0 : 896 => Opcode::PseudoVBREV8_V_M4,
14739 0 : 897 => Opcode::PseudoVBREV8_V_M4_MASK,
14740 0 : 898 => Opcode::PseudoVBREV8_V_M8,
14741 0 : 899 => Opcode::PseudoVBREV8_V_M8_MASK,
14742 0 : 900 => Opcode::PseudoVBREV8_V_MF2,
14743 0 : 901 => Opcode::PseudoVBREV8_V_MF2_MASK,
14744 0 : 902 => Opcode::PseudoVBREV8_V_MF4,
14745 0 : 903 => Opcode::PseudoVBREV8_V_MF4_MASK,
14746 0 : 904 => Opcode::PseudoVBREV8_V_MF8,
14747 0 : 905 => Opcode::PseudoVBREV8_V_MF8_MASK,
14748 0 : 906 => Opcode::PseudoVBREV_V_M1,
14749 0 : 907 => Opcode::PseudoVBREV_V_M1_MASK,
14750 0 : 908 => Opcode::PseudoVBREV_V_M2,
14751 0 : 909 => Opcode::PseudoVBREV_V_M2_MASK,
14752 0 : 910 => Opcode::PseudoVBREV_V_M4,
14753 0 : 911 => Opcode::PseudoVBREV_V_M4_MASK,
14754 0 : 912 => Opcode::PseudoVBREV_V_M8,
14755 0 : 913 => Opcode::PseudoVBREV_V_M8_MASK,
14756 0 : 914 => Opcode::PseudoVBREV_V_MF2,
14757 0 : 915 => Opcode::PseudoVBREV_V_MF2_MASK,
14758 0 : 916 => Opcode::PseudoVBREV_V_MF4,
14759 0 : 917 => Opcode::PseudoVBREV_V_MF4_MASK,
14760 0 : 918 => Opcode::PseudoVBREV_V_MF8,
14761 0 : 919 => Opcode::PseudoVBREV_V_MF8_MASK,
14762 0 : 920 => Opcode::PseudoVCLMULH_VV_M1,
14763 0 : 921 => Opcode::PseudoVCLMULH_VV_M1_MASK,
14764 0 : 922 => Opcode::PseudoVCLMULH_VV_M2,
14765 0 : 923 => Opcode::PseudoVCLMULH_VV_M2_MASK,
14766 0 : 924 => Opcode::PseudoVCLMULH_VV_M4,
14767 0 : 925 => Opcode::PseudoVCLMULH_VV_M4_MASK,
14768 0 : 926 => Opcode::PseudoVCLMULH_VV_M8,
14769 0 : 927 => Opcode::PseudoVCLMULH_VV_M8_MASK,
14770 0 : 928 => Opcode::PseudoVCLMULH_VV_MF2,
14771 0 : 929 => Opcode::PseudoVCLMULH_VV_MF2_MASK,
14772 0 : 930 => Opcode::PseudoVCLMULH_VV_MF4,
14773 0 : 931 => Opcode::PseudoVCLMULH_VV_MF4_MASK,
14774 0 : 932 => Opcode::PseudoVCLMULH_VV_MF8,
14775 0 : 933 => Opcode::PseudoVCLMULH_VV_MF8_MASK,
14776 0 : 934 => Opcode::PseudoVCLMULH_VX_M1,
14777 0 : 935 => Opcode::PseudoVCLMULH_VX_M1_MASK,
14778 0 : 936 => Opcode::PseudoVCLMULH_VX_M2,
14779 0 : 937 => Opcode::PseudoVCLMULH_VX_M2_MASK,
14780 0 : 938 => Opcode::PseudoVCLMULH_VX_M4,
14781 0 : 939 => Opcode::PseudoVCLMULH_VX_M4_MASK,
14782 0 : 940 => Opcode::PseudoVCLMULH_VX_M8,
14783 0 : 941 => Opcode::PseudoVCLMULH_VX_M8_MASK,
14784 0 : 942 => Opcode::PseudoVCLMULH_VX_MF2,
14785 0 : 943 => Opcode::PseudoVCLMULH_VX_MF2_MASK,
14786 0 : 944 => Opcode::PseudoVCLMULH_VX_MF4,
14787 0 : 945 => Opcode::PseudoVCLMULH_VX_MF4_MASK,
14788 0 : 946 => Opcode::PseudoVCLMULH_VX_MF8,
14789 0 : 947 => Opcode::PseudoVCLMULH_VX_MF8_MASK,
14790 0 : 948 => Opcode::PseudoVCLMUL_VV_M1,
14791 0 : 949 => Opcode::PseudoVCLMUL_VV_M1_MASK,
14792 0 : 950 => Opcode::PseudoVCLMUL_VV_M2,
14793 0 : 951 => Opcode::PseudoVCLMUL_VV_M2_MASK,
14794 0 : 952 => Opcode::PseudoVCLMUL_VV_M4,
14795 0 : 953 => Opcode::PseudoVCLMUL_VV_M4_MASK,
14796 0 : 954 => Opcode::PseudoVCLMUL_VV_M8,
14797 0 : 955 => Opcode::PseudoVCLMUL_VV_M8_MASK,
14798 0 : 956 => Opcode::PseudoVCLMUL_VV_MF2,
14799 0 : 957 => Opcode::PseudoVCLMUL_VV_MF2_MASK,
14800 0 : 958 => Opcode::PseudoVCLMUL_VV_MF4,
14801 0 : 959 => Opcode::PseudoVCLMUL_VV_MF4_MASK,
14802 0 : 960 => Opcode::PseudoVCLMUL_VV_MF8,
14803 0 : 961 => Opcode::PseudoVCLMUL_VV_MF8_MASK,
14804 0 : 962 => Opcode::PseudoVCLMUL_VX_M1,
14805 0 : 963 => Opcode::PseudoVCLMUL_VX_M1_MASK,
14806 0 : 964 => Opcode::PseudoVCLMUL_VX_M2,
14807 0 : 965 => Opcode::PseudoVCLMUL_VX_M2_MASK,
14808 0 : 966 => Opcode::PseudoVCLMUL_VX_M4,
14809 0 : 967 => Opcode::PseudoVCLMUL_VX_M4_MASK,
14810 0 : 968 => Opcode::PseudoVCLMUL_VX_M8,
14811 0 : 969 => Opcode::PseudoVCLMUL_VX_M8_MASK,
14812 0 : 970 => Opcode::PseudoVCLMUL_VX_MF2,
14813 0 : 971 => Opcode::PseudoVCLMUL_VX_MF2_MASK,
14814 0 : 972 => Opcode::PseudoVCLMUL_VX_MF4,
14815 0 : 973 => Opcode::PseudoVCLMUL_VX_MF4_MASK,
14816 0 : 974 => Opcode::PseudoVCLMUL_VX_MF8,
14817 0 : 975 => Opcode::PseudoVCLMUL_VX_MF8_MASK,
14818 0 : 976 => Opcode::PseudoVCLZ_V_M1,
14819 0 : 977 => Opcode::PseudoVCLZ_V_M1_MASK,
14820 0 : 978 => Opcode::PseudoVCLZ_V_M2,
14821 0 : 979 => Opcode::PseudoVCLZ_V_M2_MASK,
14822 0 : 980 => Opcode::PseudoVCLZ_V_M4,
14823 0 : 981 => Opcode::PseudoVCLZ_V_M4_MASK,
14824 0 : 982 => Opcode::PseudoVCLZ_V_M8,
14825 0 : 983 => Opcode::PseudoVCLZ_V_M8_MASK,
14826 0 : 984 => Opcode::PseudoVCLZ_V_MF2,
14827 0 : 985 => Opcode::PseudoVCLZ_V_MF2_MASK,
14828 0 : 986 => Opcode::PseudoVCLZ_V_MF4,
14829 0 : 987 => Opcode::PseudoVCLZ_V_MF4_MASK,
14830 0 : 988 => Opcode::PseudoVCLZ_V_MF8,
14831 0 : 989 => Opcode::PseudoVCLZ_V_MF8_MASK,
14832 0 : 990 => Opcode::PseudoVCOMPRESS_VM_M1_E16,
14833 0 : 991 => Opcode::PseudoVCOMPRESS_VM_M1_E32,
14834 0 : 992 => Opcode::PseudoVCOMPRESS_VM_M1_E64,
14835 0 : 993 => Opcode::PseudoVCOMPRESS_VM_M1_E8,
14836 0 : 994 => Opcode::PseudoVCOMPRESS_VM_M2_E16,
14837 0 : 995 => Opcode::PseudoVCOMPRESS_VM_M2_E32,
14838 0 : 996 => Opcode::PseudoVCOMPRESS_VM_M2_E64,
14839 0 : 997 => Opcode::PseudoVCOMPRESS_VM_M2_E8,
14840 0 : 998 => Opcode::PseudoVCOMPRESS_VM_M4_E16,
14841 0 : 999 => Opcode::PseudoVCOMPRESS_VM_M4_E32,
14842 0 : 1000 => Opcode::PseudoVCOMPRESS_VM_M4_E64,
14843 0 : 1001 => Opcode::PseudoVCOMPRESS_VM_M4_E8,
14844 0 : 1002 => Opcode::PseudoVCOMPRESS_VM_M8_E16,
14845 0 : 1003 => Opcode::PseudoVCOMPRESS_VM_M8_E32,
14846 0 : 1004 => Opcode::PseudoVCOMPRESS_VM_M8_E64,
14847 0 : 1005 => Opcode::PseudoVCOMPRESS_VM_M8_E8,
14848 0 : 1006 => Opcode::PseudoVCOMPRESS_VM_MF2_E16,
14849 0 : 1007 => Opcode::PseudoVCOMPRESS_VM_MF2_E32,
14850 0 : 1008 => Opcode::PseudoVCOMPRESS_VM_MF2_E8,
14851 0 : 1009 => Opcode::PseudoVCOMPRESS_VM_MF4_E16,
14852 0 : 1010 => Opcode::PseudoVCOMPRESS_VM_MF4_E8,
14853 0 : 1011 => Opcode::PseudoVCOMPRESS_VM_MF8_E8,
14854 0 : 1012 => Opcode::PseudoVCPOP_M_B1,
14855 0 : 1013 => Opcode::PseudoVCPOP_M_B16,
14856 0 : 1014 => Opcode::PseudoVCPOP_M_B16_MASK,
14857 0 : 1015 => Opcode::PseudoVCPOP_M_B1_MASK,
14858 0 : 1016 => Opcode::PseudoVCPOP_M_B2,
14859 0 : 1017 => Opcode::PseudoVCPOP_M_B2_MASK,
14860 0 : 1018 => Opcode::PseudoVCPOP_M_B32,
14861 0 : 1019 => Opcode::PseudoVCPOP_M_B32_MASK,
14862 0 : 1020 => Opcode::PseudoVCPOP_M_B4,
14863 0 : 1021 => Opcode::PseudoVCPOP_M_B4_MASK,
14864 0 : 1022 => Opcode::PseudoVCPOP_M_B64,
14865 0 : 1023 => Opcode::PseudoVCPOP_M_B64_MASK,
14866 0 : 1024 => Opcode::PseudoVCPOP_M_B8,
14867 0 : 1025 => Opcode::PseudoVCPOP_M_B8_MASK,
14868 0 : 1026 => Opcode::PseudoVCPOP_V_M1,
14869 0 : 1027 => Opcode::PseudoVCPOP_V_M1_MASK,
14870 0 : 1028 => Opcode::PseudoVCPOP_V_M2,
14871 0 : 1029 => Opcode::PseudoVCPOP_V_M2_MASK,
14872 0 : 1030 => Opcode::PseudoVCPOP_V_M4,
14873 0 : 1031 => Opcode::PseudoVCPOP_V_M4_MASK,
14874 0 : 1032 => Opcode::PseudoVCPOP_V_M8,
14875 0 : 1033 => Opcode::PseudoVCPOP_V_M8_MASK,
14876 0 : 1034 => Opcode::PseudoVCPOP_V_MF2,
14877 0 : 1035 => Opcode::PseudoVCPOP_V_MF2_MASK,
14878 0 : 1036 => Opcode::PseudoVCPOP_V_MF4,
14879 0 : 1037 => Opcode::PseudoVCPOP_V_MF4_MASK,
14880 0 : 1038 => Opcode::PseudoVCPOP_V_MF8,
14881 0 : 1039 => Opcode::PseudoVCPOP_V_MF8_MASK,
14882 0 : 1040 => Opcode::PseudoVCTZ_V_M1,
14883 0 : 1041 => Opcode::PseudoVCTZ_V_M1_MASK,
14884 0 : 1042 => Opcode::PseudoVCTZ_V_M2,
14885 0 : 1043 => Opcode::PseudoVCTZ_V_M2_MASK,
14886 0 : 1044 => Opcode::PseudoVCTZ_V_M4,
14887 0 : 1045 => Opcode::PseudoVCTZ_V_M4_MASK,
14888 0 : 1046 => Opcode::PseudoVCTZ_V_M8,
14889 0 : 1047 => Opcode::PseudoVCTZ_V_M8_MASK,
14890 0 : 1048 => Opcode::PseudoVCTZ_V_MF2,
14891 0 : 1049 => Opcode::PseudoVCTZ_V_MF2_MASK,
14892 0 : 1050 => Opcode::PseudoVCTZ_V_MF4,
14893 0 : 1051 => Opcode::PseudoVCTZ_V_MF4_MASK,
14894 0 : 1052 => Opcode::PseudoVCTZ_V_MF8,
14895 0 : 1053 => Opcode::PseudoVCTZ_V_MF8_MASK,
14896 0 : 1054 => Opcode::PseudoVC_FPR16VV_SE_M1,
14897 0 : 1055 => Opcode::PseudoVC_FPR16VV_SE_M2,
14898 0 : 1056 => Opcode::PseudoVC_FPR16VV_SE_M4,
14899 0 : 1057 => Opcode::PseudoVC_FPR16VV_SE_M8,
14900 0 : 1058 => Opcode::PseudoVC_FPR16VV_SE_MF2,
14901 0 : 1059 => Opcode::PseudoVC_FPR16VV_SE_MF4,
14902 0 : 1060 => Opcode::PseudoVC_FPR16VW_SE_M1,
14903 0 : 1061 => Opcode::PseudoVC_FPR16VW_SE_M2,
14904 0 : 1062 => Opcode::PseudoVC_FPR16VW_SE_M4,
14905 0 : 1063 => Opcode::PseudoVC_FPR16VW_SE_M8,
14906 0 : 1064 => Opcode::PseudoVC_FPR16VW_SE_MF2,
14907 0 : 1065 => Opcode::PseudoVC_FPR16VW_SE_MF4,
14908 0 : 1066 => Opcode::PseudoVC_FPR16V_SE_M1,
14909 0 : 1067 => Opcode::PseudoVC_FPR16V_SE_M2,
14910 0 : 1068 => Opcode::PseudoVC_FPR16V_SE_M4,
14911 0 : 1069 => Opcode::PseudoVC_FPR16V_SE_M8,
14912 0 : 1070 => Opcode::PseudoVC_FPR16V_SE_MF2,
14913 0 : 1071 => Opcode::PseudoVC_FPR16V_SE_MF4,
14914 0 : 1072 => Opcode::PseudoVC_FPR32VV_SE_M1,
14915 0 : 1073 => Opcode::PseudoVC_FPR32VV_SE_M2,
14916 0 : 1074 => Opcode::PseudoVC_FPR32VV_SE_M4,
14917 0 : 1075 => Opcode::PseudoVC_FPR32VV_SE_M8,
14918 0 : 1076 => Opcode::PseudoVC_FPR32VV_SE_MF2,
14919 0 : 1077 => Opcode::PseudoVC_FPR32VW_SE_M1,
14920 0 : 1078 => Opcode::PseudoVC_FPR32VW_SE_M2,
14921 0 : 1079 => Opcode::PseudoVC_FPR32VW_SE_M4,
14922 0 : 1080 => Opcode::PseudoVC_FPR32VW_SE_M8,
14923 0 : 1081 => Opcode::PseudoVC_FPR32VW_SE_MF2,
14924 0 : 1082 => Opcode::PseudoVC_FPR32V_SE_M1,
14925 0 : 1083 => Opcode::PseudoVC_FPR32V_SE_M2,
14926 0 : 1084 => Opcode::PseudoVC_FPR32V_SE_M4,
14927 0 : 1085 => Opcode::PseudoVC_FPR32V_SE_M8,
14928 0 : 1086 => Opcode::PseudoVC_FPR32V_SE_MF2,
14929 0 : 1087 => Opcode::PseudoVC_FPR64VV_SE_M1,
14930 0 : 1088 => Opcode::PseudoVC_FPR64VV_SE_M2,
14931 0 : 1089 => Opcode::PseudoVC_FPR64VV_SE_M4,
14932 0 : 1090 => Opcode::PseudoVC_FPR64VV_SE_M8,
14933 0 : 1091 => Opcode::PseudoVC_FPR64V_SE_M1,
14934 0 : 1092 => Opcode::PseudoVC_FPR64V_SE_M2,
14935 0 : 1093 => Opcode::PseudoVC_FPR64V_SE_M4,
14936 0 : 1094 => Opcode::PseudoVC_FPR64V_SE_M8,
14937 0 : 1095 => Opcode::PseudoVC_IVV_SE_M1,
14938 0 : 1096 => Opcode::PseudoVC_IVV_SE_M2,
14939 0 : 1097 => Opcode::PseudoVC_IVV_SE_M4,
14940 0 : 1098 => Opcode::PseudoVC_IVV_SE_M8,
14941 0 : 1099 => Opcode::PseudoVC_IVV_SE_MF2,
14942 0 : 1100 => Opcode::PseudoVC_IVV_SE_MF4,
14943 0 : 1101 => Opcode::PseudoVC_IVV_SE_MF8,
14944 0 : 1102 => Opcode::PseudoVC_IVW_SE_M1,
14945 0 : 1103 => Opcode::PseudoVC_IVW_SE_M2,
14946 0 : 1104 => Opcode::PseudoVC_IVW_SE_M4,
14947 0 : 1105 => Opcode::PseudoVC_IVW_SE_MF2,
14948 0 : 1106 => Opcode::PseudoVC_IVW_SE_MF4,
14949 0 : 1107 => Opcode::PseudoVC_IVW_SE_MF8,
14950 0 : 1108 => Opcode::PseudoVC_IV_SE_M1,
14951 0 : 1109 => Opcode::PseudoVC_IV_SE_M2,
14952 0 : 1110 => Opcode::PseudoVC_IV_SE_M4,
14953 0 : 1111 => Opcode::PseudoVC_IV_SE_M8,
14954 0 : 1112 => Opcode::PseudoVC_IV_SE_MF2,
14955 0 : 1113 => Opcode::PseudoVC_IV_SE_MF4,
14956 0 : 1114 => Opcode::PseudoVC_IV_SE_MF8,
14957 0 : 1115 => Opcode::PseudoVC_I_SE_M1,
14958 0 : 1116 => Opcode::PseudoVC_I_SE_M2,
14959 0 : 1117 => Opcode::PseudoVC_I_SE_M4,
14960 0 : 1118 => Opcode::PseudoVC_I_SE_M8,
14961 0 : 1119 => Opcode::PseudoVC_I_SE_MF2,
14962 0 : 1120 => Opcode::PseudoVC_I_SE_MF4,
14963 0 : 1121 => Opcode::PseudoVC_I_SE_MF8,
14964 0 : 1122 => Opcode::PseudoVC_VVV_SE_M1,
14965 0 : 1123 => Opcode::PseudoVC_VVV_SE_M2,
14966 0 : 1124 => Opcode::PseudoVC_VVV_SE_M4,
14967 0 : 1125 => Opcode::PseudoVC_VVV_SE_M8,
14968 0 : 1126 => Opcode::PseudoVC_VVV_SE_MF2,
14969 0 : 1127 => Opcode::PseudoVC_VVV_SE_MF4,
14970 0 : 1128 => Opcode::PseudoVC_VVV_SE_MF8,
14971 0 : 1129 => Opcode::PseudoVC_VVW_SE_M1,
14972 0 : 1130 => Opcode::PseudoVC_VVW_SE_M2,
14973 0 : 1131 => Opcode::PseudoVC_VVW_SE_M4,
14974 0 : 1132 => Opcode::PseudoVC_VVW_SE_MF2,
14975 0 : 1133 => Opcode::PseudoVC_VVW_SE_MF4,
14976 0 : 1134 => Opcode::PseudoVC_VVW_SE_MF8,
14977 0 : 1135 => Opcode::PseudoVC_VV_SE_M1,
14978 0 : 1136 => Opcode::PseudoVC_VV_SE_M2,
14979 0 : 1137 => Opcode::PseudoVC_VV_SE_M4,
14980 0 : 1138 => Opcode::PseudoVC_VV_SE_M8,
14981 0 : 1139 => Opcode::PseudoVC_VV_SE_MF2,
14982 0 : 1140 => Opcode::PseudoVC_VV_SE_MF4,
14983 0 : 1141 => Opcode::PseudoVC_VV_SE_MF8,
14984 0 : 1142 => Opcode::PseudoVC_V_FPR16VV_M1,
14985 0 : 1143 => Opcode::PseudoVC_V_FPR16VV_M2,
14986 0 : 1144 => Opcode::PseudoVC_V_FPR16VV_M4,
14987 0 : 1145 => Opcode::PseudoVC_V_FPR16VV_M8,
14988 0 : 1146 => Opcode::PseudoVC_V_FPR16VV_MF2,
14989 0 : 1147 => Opcode::PseudoVC_V_FPR16VV_MF4,
14990 0 : 1148 => Opcode::PseudoVC_V_FPR16VV_SE_M1,
14991 0 : 1149 => Opcode::PseudoVC_V_FPR16VV_SE_M2,
14992 0 : 1150 => Opcode::PseudoVC_V_FPR16VV_SE_M4,
14993 0 : 1151 => Opcode::PseudoVC_V_FPR16VV_SE_M8,
14994 0 : 1152 => Opcode::PseudoVC_V_FPR16VV_SE_MF2,
14995 0 : 1153 => Opcode::PseudoVC_V_FPR16VV_SE_MF4,
14996 0 : 1154 => Opcode::PseudoVC_V_FPR16VW_M1,
14997 0 : 1155 => Opcode::PseudoVC_V_FPR16VW_M2,
14998 0 : 1156 => Opcode::PseudoVC_V_FPR16VW_M4,
14999 0 : 1157 => Opcode::PseudoVC_V_FPR16VW_M8,
15000 0 : 1158 => Opcode::PseudoVC_V_FPR16VW_MF2,
15001 0 : 1159 => Opcode::PseudoVC_V_FPR16VW_MF4,
15002 0 : 1160 => Opcode::PseudoVC_V_FPR16VW_SE_M1,
15003 0 : 1161 => Opcode::PseudoVC_V_FPR16VW_SE_M2,
15004 0 : 1162 => Opcode::PseudoVC_V_FPR16VW_SE_M4,
15005 0 : 1163 => Opcode::PseudoVC_V_FPR16VW_SE_M8,
15006 0 : 1164 => Opcode::PseudoVC_V_FPR16VW_SE_MF2,
15007 0 : 1165 => Opcode::PseudoVC_V_FPR16VW_SE_MF4,
15008 0 : 1166 => Opcode::PseudoVC_V_FPR16V_M1,
15009 0 : 1167 => Opcode::PseudoVC_V_FPR16V_M2,
15010 0 : 1168 => Opcode::PseudoVC_V_FPR16V_M4,
15011 0 : 1169 => Opcode::PseudoVC_V_FPR16V_M8,
15012 0 : 1170 => Opcode::PseudoVC_V_FPR16V_MF2,
15013 0 : 1171 => Opcode::PseudoVC_V_FPR16V_MF4,
15014 0 : 1172 => Opcode::PseudoVC_V_FPR16V_SE_M1,
15015 0 : 1173 => Opcode::PseudoVC_V_FPR16V_SE_M2,
15016 0 : 1174 => Opcode::PseudoVC_V_FPR16V_SE_M4,
15017 0 : 1175 => Opcode::PseudoVC_V_FPR16V_SE_M8,
15018 0 : 1176 => Opcode::PseudoVC_V_FPR16V_SE_MF2,
15019 0 : 1177 => Opcode::PseudoVC_V_FPR16V_SE_MF4,
15020 0 : 1178 => Opcode::PseudoVC_V_FPR32VV_M1,
15021 0 : 1179 => Opcode::PseudoVC_V_FPR32VV_M2,
15022 0 : 1180 => Opcode::PseudoVC_V_FPR32VV_M4,
15023 0 : 1181 => Opcode::PseudoVC_V_FPR32VV_M8,
15024 0 : 1182 => Opcode::PseudoVC_V_FPR32VV_MF2,
15025 0 : 1183 => Opcode::PseudoVC_V_FPR32VV_SE_M1,
15026 0 : 1184 => Opcode::PseudoVC_V_FPR32VV_SE_M2,
15027 0 : 1185 => Opcode::PseudoVC_V_FPR32VV_SE_M4,
15028 0 : 1186 => Opcode::PseudoVC_V_FPR32VV_SE_M8,
15029 0 : 1187 => Opcode::PseudoVC_V_FPR32VV_SE_MF2,
15030 0 : 1188 => Opcode::PseudoVC_V_FPR32VW_M1,
15031 0 : 1189 => Opcode::PseudoVC_V_FPR32VW_M2,
15032 0 : 1190 => Opcode::PseudoVC_V_FPR32VW_M4,
15033 0 : 1191 => Opcode::PseudoVC_V_FPR32VW_M8,
15034 0 : 1192 => Opcode::PseudoVC_V_FPR32VW_MF2,
15035 0 : 1193 => Opcode::PseudoVC_V_FPR32VW_SE_M1,
15036 0 : 1194 => Opcode::PseudoVC_V_FPR32VW_SE_M2,
15037 0 : 1195 => Opcode::PseudoVC_V_FPR32VW_SE_M4,
15038 0 : 1196 => Opcode::PseudoVC_V_FPR32VW_SE_M8,
15039 0 : 1197 => Opcode::PseudoVC_V_FPR32VW_SE_MF2,
15040 0 : 1198 => Opcode::PseudoVC_V_FPR32V_M1,
15041 0 : 1199 => Opcode::PseudoVC_V_FPR32V_M2,
15042 0 : 1200 => Opcode::PseudoVC_V_FPR32V_M4,
15043 0 : 1201 => Opcode::PseudoVC_V_FPR32V_M8,
15044 0 : 1202 => Opcode::PseudoVC_V_FPR32V_MF2,
15045 0 : 1203 => Opcode::PseudoVC_V_FPR32V_SE_M1,
15046 0 : 1204 => Opcode::PseudoVC_V_FPR32V_SE_M2,
15047 0 : 1205 => Opcode::PseudoVC_V_FPR32V_SE_M4,
15048 0 : 1206 => Opcode::PseudoVC_V_FPR32V_SE_M8,
15049 0 : 1207 => Opcode::PseudoVC_V_FPR32V_SE_MF2,
15050 0 : 1208 => Opcode::PseudoVC_V_FPR64VV_M1,
15051 0 : 1209 => Opcode::PseudoVC_V_FPR64VV_M2,
15052 0 : 1210 => Opcode::PseudoVC_V_FPR64VV_M4,
15053 0 : 1211 => Opcode::PseudoVC_V_FPR64VV_M8,
15054 0 : 1212 => Opcode::PseudoVC_V_FPR64VV_SE_M1,
15055 0 : 1213 => Opcode::PseudoVC_V_FPR64VV_SE_M2,
15056 0 : 1214 => Opcode::PseudoVC_V_FPR64VV_SE_M4,
15057 0 : 1215 => Opcode::PseudoVC_V_FPR64VV_SE_M8,
15058 0 : 1216 => Opcode::PseudoVC_V_FPR64V_M1,
15059 0 : 1217 => Opcode::PseudoVC_V_FPR64V_M2,
15060 0 : 1218 => Opcode::PseudoVC_V_FPR64V_M4,
15061 0 : 1219 => Opcode::PseudoVC_V_FPR64V_M8,
15062 0 : 1220 => Opcode::PseudoVC_V_FPR64V_SE_M1,
15063 0 : 1221 => Opcode::PseudoVC_V_FPR64V_SE_M2,
15064 0 : 1222 => Opcode::PseudoVC_V_FPR64V_SE_M4,
15065 0 : 1223 => Opcode::PseudoVC_V_FPR64V_SE_M8,
15066 0 : 1224 => Opcode::PseudoVC_V_IVV_M1,
15067 0 : 1225 => Opcode::PseudoVC_V_IVV_M2,
15068 0 : 1226 => Opcode::PseudoVC_V_IVV_M4,
15069 0 : 1227 => Opcode::PseudoVC_V_IVV_M8,
15070 0 : 1228 => Opcode::PseudoVC_V_IVV_MF2,
15071 0 : 1229 => Opcode::PseudoVC_V_IVV_MF4,
15072 0 : 1230 => Opcode::PseudoVC_V_IVV_MF8,
15073 0 : 1231 => Opcode::PseudoVC_V_IVV_SE_M1,
15074 0 : 1232 => Opcode::PseudoVC_V_IVV_SE_M2,
15075 0 : 1233 => Opcode::PseudoVC_V_IVV_SE_M4,
15076 0 : 1234 => Opcode::PseudoVC_V_IVV_SE_M8,
15077 0 : 1235 => Opcode::PseudoVC_V_IVV_SE_MF2,
15078 0 : 1236 => Opcode::PseudoVC_V_IVV_SE_MF4,
15079 0 : 1237 => Opcode::PseudoVC_V_IVV_SE_MF8,
15080 0 : 1238 => Opcode::PseudoVC_V_IVW_M1,
15081 0 : 1239 => Opcode::PseudoVC_V_IVW_M2,
15082 0 : 1240 => Opcode::PseudoVC_V_IVW_M4,
15083 0 : 1241 => Opcode::PseudoVC_V_IVW_MF2,
15084 0 : 1242 => Opcode::PseudoVC_V_IVW_MF4,
15085 0 : 1243 => Opcode::PseudoVC_V_IVW_MF8,
15086 0 : 1244 => Opcode::PseudoVC_V_IVW_SE_M1,
15087 0 : 1245 => Opcode::PseudoVC_V_IVW_SE_M2,
15088 0 : 1246 => Opcode::PseudoVC_V_IVW_SE_M4,
15089 0 : 1247 => Opcode::PseudoVC_V_IVW_SE_MF2,
15090 0 : 1248 => Opcode::PseudoVC_V_IVW_SE_MF4,
15091 0 : 1249 => Opcode::PseudoVC_V_IVW_SE_MF8,
15092 0 : 1250 => Opcode::PseudoVC_V_IV_M1,
15093 0 : 1251 => Opcode::PseudoVC_V_IV_M2,
15094 0 : 1252 => Opcode::PseudoVC_V_IV_M4,
15095 0 : 1253 => Opcode::PseudoVC_V_IV_M8,
15096 0 : 1254 => Opcode::PseudoVC_V_IV_MF2,
15097 0 : 1255 => Opcode::PseudoVC_V_IV_MF4,
15098 0 : 1256 => Opcode::PseudoVC_V_IV_MF8,
15099 0 : 1257 => Opcode::PseudoVC_V_IV_SE_M1,
15100 0 : 1258 => Opcode::PseudoVC_V_IV_SE_M2,
15101 0 : 1259 => Opcode::PseudoVC_V_IV_SE_M4,
15102 0 : 1260 => Opcode::PseudoVC_V_IV_SE_M8,
15103 0 : 1261 => Opcode::PseudoVC_V_IV_SE_MF2,
15104 0 : 1262 => Opcode::PseudoVC_V_IV_SE_MF4,
15105 0 : 1263 => Opcode::PseudoVC_V_IV_SE_MF8,
15106 0 : 1264 => Opcode::PseudoVC_V_I_M1,
15107 0 : 1265 => Opcode::PseudoVC_V_I_M2,
15108 0 : 1266 => Opcode::PseudoVC_V_I_M4,
15109 0 : 1267 => Opcode::PseudoVC_V_I_M8,
15110 0 : 1268 => Opcode::PseudoVC_V_I_MF2,
15111 0 : 1269 => Opcode::PseudoVC_V_I_MF4,
15112 0 : 1270 => Opcode::PseudoVC_V_I_MF8,
15113 0 : 1271 => Opcode::PseudoVC_V_I_SE_M1,
15114 0 : 1272 => Opcode::PseudoVC_V_I_SE_M2,
15115 0 : 1273 => Opcode::PseudoVC_V_I_SE_M4,
15116 0 : 1274 => Opcode::PseudoVC_V_I_SE_M8,
15117 0 : 1275 => Opcode::PseudoVC_V_I_SE_MF2,
15118 0 : 1276 => Opcode::PseudoVC_V_I_SE_MF4,
15119 0 : 1277 => Opcode::PseudoVC_V_I_SE_MF8,
15120 0 : 1278 => Opcode::PseudoVC_V_VVV_M1,
15121 0 : 1279 => Opcode::PseudoVC_V_VVV_M2,
15122 0 : 1280 => Opcode::PseudoVC_V_VVV_M4,
15123 0 : 1281 => Opcode::PseudoVC_V_VVV_M8,
15124 0 : 1282 => Opcode::PseudoVC_V_VVV_MF2,
15125 0 : 1283 => Opcode::PseudoVC_V_VVV_MF4,
15126 0 : 1284 => Opcode::PseudoVC_V_VVV_MF8,
15127 0 : 1285 => Opcode::PseudoVC_V_VVV_SE_M1,
15128 0 : 1286 => Opcode::PseudoVC_V_VVV_SE_M2,
15129 0 : 1287 => Opcode::PseudoVC_V_VVV_SE_M4,
15130 0 : 1288 => Opcode::PseudoVC_V_VVV_SE_M8,
15131 0 : 1289 => Opcode::PseudoVC_V_VVV_SE_MF2,
15132 0 : 1290 => Opcode::PseudoVC_V_VVV_SE_MF4,
15133 0 : 1291 => Opcode::PseudoVC_V_VVV_SE_MF8,
15134 0 : 1292 => Opcode::PseudoVC_V_VVW_M1,
15135 0 : 1293 => Opcode::PseudoVC_V_VVW_M2,
15136 0 : 1294 => Opcode::PseudoVC_V_VVW_M4,
15137 0 : 1295 => Opcode::PseudoVC_V_VVW_MF2,
15138 0 : 1296 => Opcode::PseudoVC_V_VVW_MF4,
15139 0 : 1297 => Opcode::PseudoVC_V_VVW_MF8,
15140 0 : 1298 => Opcode::PseudoVC_V_VVW_SE_M1,
15141 0 : 1299 => Opcode::PseudoVC_V_VVW_SE_M2,
15142 0 : 1300 => Opcode::PseudoVC_V_VVW_SE_M4,
15143 0 : 1301 => Opcode::PseudoVC_V_VVW_SE_MF2,
15144 0 : 1302 => Opcode::PseudoVC_V_VVW_SE_MF4,
15145 0 : 1303 => Opcode::PseudoVC_V_VVW_SE_MF8,
15146 0 : 1304 => Opcode::PseudoVC_V_VV_M1,
15147 0 : 1305 => Opcode::PseudoVC_V_VV_M2,
15148 0 : 1306 => Opcode::PseudoVC_V_VV_M4,
15149 0 : 1307 => Opcode::PseudoVC_V_VV_M8,
15150 0 : 1308 => Opcode::PseudoVC_V_VV_MF2,
15151 0 : 1309 => Opcode::PseudoVC_V_VV_MF4,
15152 0 : 1310 => Opcode::PseudoVC_V_VV_MF8,
15153 0 : 1311 => Opcode::PseudoVC_V_VV_SE_M1,
15154 0 : 1312 => Opcode::PseudoVC_V_VV_SE_M2,
15155 0 : 1313 => Opcode::PseudoVC_V_VV_SE_M4,
15156 0 : 1314 => Opcode::PseudoVC_V_VV_SE_M8,
15157 0 : 1315 => Opcode::PseudoVC_V_VV_SE_MF2,
15158 0 : 1316 => Opcode::PseudoVC_V_VV_SE_MF4,
15159 0 : 1317 => Opcode::PseudoVC_V_VV_SE_MF8,
15160 0 : 1318 => Opcode::PseudoVC_V_XVV_M1,
15161 0 : 1319 => Opcode::PseudoVC_V_XVV_M2,
15162 0 : 1320 => Opcode::PseudoVC_V_XVV_M4,
15163 0 : 1321 => Opcode::PseudoVC_V_XVV_M8,
15164 0 : 1322 => Opcode::PseudoVC_V_XVV_MF2,
15165 0 : 1323 => Opcode::PseudoVC_V_XVV_MF4,
15166 0 : 1324 => Opcode::PseudoVC_V_XVV_MF8,
15167 0 : 1325 => Opcode::PseudoVC_V_XVV_SE_M1,
15168 0 : 1326 => Opcode::PseudoVC_V_XVV_SE_M2,
15169 0 : 1327 => Opcode::PseudoVC_V_XVV_SE_M4,
15170 0 : 1328 => Opcode::PseudoVC_V_XVV_SE_M8,
15171 0 : 1329 => Opcode::PseudoVC_V_XVV_SE_MF2,
15172 0 : 1330 => Opcode::PseudoVC_V_XVV_SE_MF4,
15173 0 : 1331 => Opcode::PseudoVC_V_XVV_SE_MF8,
15174 0 : 1332 => Opcode::PseudoVC_V_XVW_M1,
15175 0 : 1333 => Opcode::PseudoVC_V_XVW_M2,
15176 0 : 1334 => Opcode::PseudoVC_V_XVW_M4,
15177 0 : 1335 => Opcode::PseudoVC_V_XVW_MF2,
15178 0 : 1336 => Opcode::PseudoVC_V_XVW_MF4,
15179 0 : 1337 => Opcode::PseudoVC_V_XVW_MF8,
15180 0 : 1338 => Opcode::PseudoVC_V_XVW_SE_M1,
15181 0 : 1339 => Opcode::PseudoVC_V_XVW_SE_M2,
15182 0 : 1340 => Opcode::PseudoVC_V_XVW_SE_M4,
15183 0 : 1341 => Opcode::PseudoVC_V_XVW_SE_MF2,
15184 0 : 1342 => Opcode::PseudoVC_V_XVW_SE_MF4,
15185 0 : 1343 => Opcode::PseudoVC_V_XVW_SE_MF8,
15186 0 : 1344 => Opcode::PseudoVC_V_XV_M1,
15187 0 : 1345 => Opcode::PseudoVC_V_XV_M2,
15188 0 : 1346 => Opcode::PseudoVC_V_XV_M4,
15189 0 : 1347 => Opcode::PseudoVC_V_XV_M8,
15190 0 : 1348 => Opcode::PseudoVC_V_XV_MF2,
15191 0 : 1349 => Opcode::PseudoVC_V_XV_MF4,
15192 0 : 1350 => Opcode::PseudoVC_V_XV_MF8,
15193 0 : 1351 => Opcode::PseudoVC_V_XV_SE_M1,
15194 0 : 1352 => Opcode::PseudoVC_V_XV_SE_M2,
15195 0 : 1353 => Opcode::PseudoVC_V_XV_SE_M4,
15196 0 : 1354 => Opcode::PseudoVC_V_XV_SE_M8,
15197 0 : 1355 => Opcode::PseudoVC_V_XV_SE_MF2,
15198 0 : 1356 => Opcode::PseudoVC_V_XV_SE_MF4,
15199 0 : 1357 => Opcode::PseudoVC_V_XV_SE_MF8,
15200 0 : 1358 => Opcode::PseudoVC_V_X_M1,
15201 0 : 1359 => Opcode::PseudoVC_V_X_M2,
15202 0 : 1360 => Opcode::PseudoVC_V_X_M4,
15203 0 : 1361 => Opcode::PseudoVC_V_X_M8,
15204 0 : 1362 => Opcode::PseudoVC_V_X_MF2,
15205 0 : 1363 => Opcode::PseudoVC_V_X_MF4,
15206 0 : 1364 => Opcode::PseudoVC_V_X_MF8,
15207 0 : 1365 => Opcode::PseudoVC_V_X_SE_M1,
15208 0 : 1366 => Opcode::PseudoVC_V_X_SE_M2,
15209 0 : 1367 => Opcode::PseudoVC_V_X_SE_M4,
15210 0 : 1368 => Opcode::PseudoVC_V_X_SE_M8,
15211 0 : 1369 => Opcode::PseudoVC_V_X_SE_MF2,
15212 0 : 1370 => Opcode::PseudoVC_V_X_SE_MF4,
15213 0 : 1371 => Opcode::PseudoVC_V_X_SE_MF8,
15214 0 : 1372 => Opcode::PseudoVC_XVV_SE_M1,
15215 0 : 1373 => Opcode::PseudoVC_XVV_SE_M2,
15216 0 : 1374 => Opcode::PseudoVC_XVV_SE_M4,
15217 0 : 1375 => Opcode::PseudoVC_XVV_SE_M8,
15218 0 : 1376 => Opcode::PseudoVC_XVV_SE_MF2,
15219 0 : 1377 => Opcode::PseudoVC_XVV_SE_MF4,
15220 0 : 1378 => Opcode::PseudoVC_XVV_SE_MF8,
15221 0 : 1379 => Opcode::PseudoVC_XVW_SE_M1,
15222 0 : 1380 => Opcode::PseudoVC_XVW_SE_M2,
15223 0 : 1381 => Opcode::PseudoVC_XVW_SE_M4,
15224 0 : 1382 => Opcode::PseudoVC_XVW_SE_MF2,
15225 0 : 1383 => Opcode::PseudoVC_XVW_SE_MF4,
15226 0 : 1384 => Opcode::PseudoVC_XVW_SE_MF8,
15227 0 : 1385 => Opcode::PseudoVC_XV_SE_M1,
15228 0 : 1386 => Opcode::PseudoVC_XV_SE_M2,
15229 0 : 1387 => Opcode::PseudoVC_XV_SE_M4,
15230 0 : 1388 => Opcode::PseudoVC_XV_SE_M8,
15231 0 : 1389 => Opcode::PseudoVC_XV_SE_MF2,
15232 0 : 1390 => Opcode::PseudoVC_XV_SE_MF4,
15233 0 : 1391 => Opcode::PseudoVC_XV_SE_MF8,
15234 0 : 1392 => Opcode::PseudoVC_X_SE_M1,
15235 0 : 1393 => Opcode::PseudoVC_X_SE_M2,
15236 0 : 1394 => Opcode::PseudoVC_X_SE_M4,
15237 0 : 1395 => Opcode::PseudoVC_X_SE_M8,
15238 0 : 1396 => Opcode::PseudoVC_X_SE_MF2,
15239 0 : 1397 => Opcode::PseudoVC_X_SE_MF4,
15240 0 : 1398 => Opcode::PseudoVC_X_SE_MF8,
15241 0 : 1399 => Opcode::PseudoVDIVU_VV_M1_E16,
15242 0 : 1400 => Opcode::PseudoVDIVU_VV_M1_E16_MASK,
15243 0 : 1401 => Opcode::PseudoVDIVU_VV_M1_E32,
15244 0 : 1402 => Opcode::PseudoVDIVU_VV_M1_E32_MASK,
15245 0 : 1403 => Opcode::PseudoVDIVU_VV_M1_E64,
15246 0 : 1404 => Opcode::PseudoVDIVU_VV_M1_E64_MASK,
15247 0 : 1405 => Opcode::PseudoVDIVU_VV_M1_E8,
15248 0 : 1406 => Opcode::PseudoVDIVU_VV_M1_E8_MASK,
15249 0 : 1407 => Opcode::PseudoVDIVU_VV_M2_E16,
15250 0 : 1408 => Opcode::PseudoVDIVU_VV_M2_E16_MASK,
15251 0 : 1409 => Opcode::PseudoVDIVU_VV_M2_E32,
15252 0 : 1410 => Opcode::PseudoVDIVU_VV_M2_E32_MASK,
15253 0 : 1411 => Opcode::PseudoVDIVU_VV_M2_E64,
15254 0 : 1412 => Opcode::PseudoVDIVU_VV_M2_E64_MASK,
15255 0 : 1413 => Opcode::PseudoVDIVU_VV_M2_E8,
15256 0 : 1414 => Opcode::PseudoVDIVU_VV_M2_E8_MASK,
15257 0 : 1415 => Opcode::PseudoVDIVU_VV_M4_E16,
15258 0 : 1416 => Opcode::PseudoVDIVU_VV_M4_E16_MASK,
15259 0 : 1417 => Opcode::PseudoVDIVU_VV_M4_E32,
15260 0 : 1418 => Opcode::PseudoVDIVU_VV_M4_E32_MASK,
15261 0 : 1419 => Opcode::PseudoVDIVU_VV_M4_E64,
15262 0 : 1420 => Opcode::PseudoVDIVU_VV_M4_E64_MASK,
15263 0 : 1421 => Opcode::PseudoVDIVU_VV_M4_E8,
15264 0 : 1422 => Opcode::PseudoVDIVU_VV_M4_E8_MASK,
15265 0 : 1423 => Opcode::PseudoVDIVU_VV_M8_E16,
15266 0 : 1424 => Opcode::PseudoVDIVU_VV_M8_E16_MASK,
15267 0 : 1425 => Opcode::PseudoVDIVU_VV_M8_E32,
15268 0 : 1426 => Opcode::PseudoVDIVU_VV_M8_E32_MASK,
15269 0 : 1427 => Opcode::PseudoVDIVU_VV_M8_E64,
15270 0 : 1428 => Opcode::PseudoVDIVU_VV_M8_E64_MASK,
15271 0 : 1429 => Opcode::PseudoVDIVU_VV_M8_E8,
15272 0 : 1430 => Opcode::PseudoVDIVU_VV_M8_E8_MASK,
15273 0 : 1431 => Opcode::PseudoVDIVU_VV_MF2_E16,
15274 0 : 1432 => Opcode::PseudoVDIVU_VV_MF2_E16_MASK,
15275 0 : 1433 => Opcode::PseudoVDIVU_VV_MF2_E32,
15276 0 : 1434 => Opcode::PseudoVDIVU_VV_MF2_E32_MASK,
15277 0 : 1435 => Opcode::PseudoVDIVU_VV_MF2_E8,
15278 0 : 1436 => Opcode::PseudoVDIVU_VV_MF2_E8_MASK,
15279 0 : 1437 => Opcode::PseudoVDIVU_VV_MF4_E16,
15280 0 : 1438 => Opcode::PseudoVDIVU_VV_MF4_E16_MASK,
15281 0 : 1439 => Opcode::PseudoVDIVU_VV_MF4_E8,
15282 0 : 1440 => Opcode::PseudoVDIVU_VV_MF4_E8_MASK,
15283 0 : 1441 => Opcode::PseudoVDIVU_VV_MF8_E8,
15284 0 : 1442 => Opcode::PseudoVDIVU_VV_MF8_E8_MASK,
15285 0 : 1443 => Opcode::PseudoVDIVU_VX_M1_E16,
15286 0 : 1444 => Opcode::PseudoVDIVU_VX_M1_E16_MASK,
15287 0 : 1445 => Opcode::PseudoVDIVU_VX_M1_E32,
15288 0 : 1446 => Opcode::PseudoVDIVU_VX_M1_E32_MASK,
15289 0 : 1447 => Opcode::PseudoVDIVU_VX_M1_E64,
15290 0 : 1448 => Opcode::PseudoVDIVU_VX_M1_E64_MASK,
15291 0 : 1449 => Opcode::PseudoVDIVU_VX_M1_E8,
15292 0 : 1450 => Opcode::PseudoVDIVU_VX_M1_E8_MASK,
15293 0 : 1451 => Opcode::PseudoVDIVU_VX_M2_E16,
15294 0 : 1452 => Opcode::PseudoVDIVU_VX_M2_E16_MASK,
15295 0 : 1453 => Opcode::PseudoVDIVU_VX_M2_E32,
15296 0 : 1454 => Opcode::PseudoVDIVU_VX_M2_E32_MASK,
15297 0 : 1455 => Opcode::PseudoVDIVU_VX_M2_E64,
15298 0 : 1456 => Opcode::PseudoVDIVU_VX_M2_E64_MASK,
15299 0 : 1457 => Opcode::PseudoVDIVU_VX_M2_E8,
15300 0 : 1458 => Opcode::PseudoVDIVU_VX_M2_E8_MASK,
15301 0 : 1459 => Opcode::PseudoVDIVU_VX_M4_E16,
15302 0 : 1460 => Opcode::PseudoVDIVU_VX_M4_E16_MASK,
15303 0 : 1461 => Opcode::PseudoVDIVU_VX_M4_E32,
15304 0 : 1462 => Opcode::PseudoVDIVU_VX_M4_E32_MASK,
15305 0 : 1463 => Opcode::PseudoVDIVU_VX_M4_E64,
15306 0 : 1464 => Opcode::PseudoVDIVU_VX_M4_E64_MASK,
15307 0 : 1465 => Opcode::PseudoVDIVU_VX_M4_E8,
15308 0 : 1466 => Opcode::PseudoVDIVU_VX_M4_E8_MASK,
15309 0 : 1467 => Opcode::PseudoVDIVU_VX_M8_E16,
15310 0 : 1468 => Opcode::PseudoVDIVU_VX_M8_E16_MASK,
15311 0 : 1469 => Opcode::PseudoVDIVU_VX_M8_E32,
15312 0 : 1470 => Opcode::PseudoVDIVU_VX_M8_E32_MASK,
15313 0 : 1471 => Opcode::PseudoVDIVU_VX_M8_E64,
15314 0 : 1472 => Opcode::PseudoVDIVU_VX_M8_E64_MASK,
15315 0 : 1473 => Opcode::PseudoVDIVU_VX_M8_E8,
15316 0 : 1474 => Opcode::PseudoVDIVU_VX_M8_E8_MASK,
15317 0 : 1475 => Opcode::PseudoVDIVU_VX_MF2_E16,
15318 0 : 1476 => Opcode::PseudoVDIVU_VX_MF2_E16_MASK,
15319 0 : 1477 => Opcode::PseudoVDIVU_VX_MF2_E32,
15320 0 : 1478 => Opcode::PseudoVDIVU_VX_MF2_E32_MASK,
15321 0 : 1479 => Opcode::PseudoVDIVU_VX_MF2_E8,
15322 0 : 1480 => Opcode::PseudoVDIVU_VX_MF2_E8_MASK,
15323 0 : 1481 => Opcode::PseudoVDIVU_VX_MF4_E16,
15324 0 : 1482 => Opcode::PseudoVDIVU_VX_MF4_E16_MASK,
15325 0 : 1483 => Opcode::PseudoVDIVU_VX_MF4_E8,
15326 0 : 1484 => Opcode::PseudoVDIVU_VX_MF4_E8_MASK,
15327 0 : 1485 => Opcode::PseudoVDIVU_VX_MF8_E8,
15328 0 : 1486 => Opcode::PseudoVDIVU_VX_MF8_E8_MASK,
15329 0 : 1487 => Opcode::PseudoVDIV_VV_M1_E16,
15330 0 : 1488 => Opcode::PseudoVDIV_VV_M1_E16_MASK,
15331 0 : 1489 => Opcode::PseudoVDIV_VV_M1_E32,
15332 0 : 1490 => Opcode::PseudoVDIV_VV_M1_E32_MASK,
15333 0 : 1491 => Opcode::PseudoVDIV_VV_M1_E64,
15334 0 : 1492 => Opcode::PseudoVDIV_VV_M1_E64_MASK,
15335 0 : 1493 => Opcode::PseudoVDIV_VV_M1_E8,
15336 0 : 1494 => Opcode::PseudoVDIV_VV_M1_E8_MASK,
15337 0 : 1495 => Opcode::PseudoVDIV_VV_M2_E16,
15338 0 : 1496 => Opcode::PseudoVDIV_VV_M2_E16_MASK,
15339 0 : 1497 => Opcode::PseudoVDIV_VV_M2_E32,
15340 0 : 1498 => Opcode::PseudoVDIV_VV_M2_E32_MASK,
15341 0 : 1499 => Opcode::PseudoVDIV_VV_M2_E64,
15342 0 : 1500 => Opcode::PseudoVDIV_VV_M2_E64_MASK,
15343 0 : 1501 => Opcode::PseudoVDIV_VV_M2_E8,
15344 0 : 1502 => Opcode::PseudoVDIV_VV_M2_E8_MASK,
15345 0 : 1503 => Opcode::PseudoVDIV_VV_M4_E16,
15346 0 : 1504 => Opcode::PseudoVDIV_VV_M4_E16_MASK,
15347 0 : 1505 => Opcode::PseudoVDIV_VV_M4_E32,
15348 0 : 1506 => Opcode::PseudoVDIV_VV_M4_E32_MASK,
15349 0 : 1507 => Opcode::PseudoVDIV_VV_M4_E64,
15350 0 : 1508 => Opcode::PseudoVDIV_VV_M4_E64_MASK,
15351 0 : 1509 => Opcode::PseudoVDIV_VV_M4_E8,
15352 0 : 1510 => Opcode::PseudoVDIV_VV_M4_E8_MASK,
15353 0 : 1511 => Opcode::PseudoVDIV_VV_M8_E16,
15354 0 : 1512 => Opcode::PseudoVDIV_VV_M8_E16_MASK,
15355 0 : 1513 => Opcode::PseudoVDIV_VV_M8_E32,
15356 0 : 1514 => Opcode::PseudoVDIV_VV_M8_E32_MASK,
15357 0 : 1515 => Opcode::PseudoVDIV_VV_M8_E64,
15358 0 : 1516 => Opcode::PseudoVDIV_VV_M8_E64_MASK,
15359 0 : 1517 => Opcode::PseudoVDIV_VV_M8_E8,
15360 0 : 1518 => Opcode::PseudoVDIV_VV_M8_E8_MASK,
15361 0 : 1519 => Opcode::PseudoVDIV_VV_MF2_E16,
15362 0 : 1520 => Opcode::PseudoVDIV_VV_MF2_E16_MASK,
15363 0 : 1521 => Opcode::PseudoVDIV_VV_MF2_E32,
15364 0 : 1522 => Opcode::PseudoVDIV_VV_MF2_E32_MASK,
15365 0 : 1523 => Opcode::PseudoVDIV_VV_MF2_E8,
15366 0 : 1524 => Opcode::PseudoVDIV_VV_MF2_E8_MASK,
15367 0 : 1525 => Opcode::PseudoVDIV_VV_MF4_E16,
15368 0 : 1526 => Opcode::PseudoVDIV_VV_MF4_E16_MASK,
15369 0 : 1527 => Opcode::PseudoVDIV_VV_MF4_E8,
15370 0 : 1528 => Opcode::PseudoVDIV_VV_MF4_E8_MASK,
15371 0 : 1529 => Opcode::PseudoVDIV_VV_MF8_E8,
15372 0 : 1530 => Opcode::PseudoVDIV_VV_MF8_E8_MASK,
15373 0 : 1531 => Opcode::PseudoVDIV_VX_M1_E16,
15374 0 : 1532 => Opcode::PseudoVDIV_VX_M1_E16_MASK,
15375 0 : 1533 => Opcode::PseudoVDIV_VX_M1_E32,
15376 0 : 1534 => Opcode::PseudoVDIV_VX_M1_E32_MASK,
15377 0 : 1535 => Opcode::PseudoVDIV_VX_M1_E64,
15378 0 : 1536 => Opcode::PseudoVDIV_VX_M1_E64_MASK,
15379 0 : 1537 => Opcode::PseudoVDIV_VX_M1_E8,
15380 0 : 1538 => Opcode::PseudoVDIV_VX_M1_E8_MASK,
15381 0 : 1539 => Opcode::PseudoVDIV_VX_M2_E16,
15382 0 : 1540 => Opcode::PseudoVDIV_VX_M2_E16_MASK,
15383 0 : 1541 => Opcode::PseudoVDIV_VX_M2_E32,
15384 0 : 1542 => Opcode::PseudoVDIV_VX_M2_E32_MASK,
15385 0 : 1543 => Opcode::PseudoVDIV_VX_M2_E64,
15386 0 : 1544 => Opcode::PseudoVDIV_VX_M2_E64_MASK,
15387 0 : 1545 => Opcode::PseudoVDIV_VX_M2_E8,
15388 0 : 1546 => Opcode::PseudoVDIV_VX_M2_E8_MASK,
15389 0 : 1547 => Opcode::PseudoVDIV_VX_M4_E16,
15390 0 : 1548 => Opcode::PseudoVDIV_VX_M4_E16_MASK,
15391 0 : 1549 => Opcode::PseudoVDIV_VX_M4_E32,
15392 0 : 1550 => Opcode::PseudoVDIV_VX_M4_E32_MASK,
15393 0 : 1551 => Opcode::PseudoVDIV_VX_M4_E64,
15394 0 : 1552 => Opcode::PseudoVDIV_VX_M4_E64_MASK,
15395 0 : 1553 => Opcode::PseudoVDIV_VX_M4_E8,
15396 0 : 1554 => Opcode::PseudoVDIV_VX_M4_E8_MASK,
15397 0 : 1555 => Opcode::PseudoVDIV_VX_M8_E16,
15398 0 : 1556 => Opcode::PseudoVDIV_VX_M8_E16_MASK,
15399 0 : 1557 => Opcode::PseudoVDIV_VX_M8_E32,
15400 0 : 1558 => Opcode::PseudoVDIV_VX_M8_E32_MASK,
15401 0 : 1559 => Opcode::PseudoVDIV_VX_M8_E64,
15402 0 : 1560 => Opcode::PseudoVDIV_VX_M8_E64_MASK,
15403 0 : 1561 => Opcode::PseudoVDIV_VX_M8_E8,
15404 0 : 1562 => Opcode::PseudoVDIV_VX_M8_E8_MASK,
15405 0 : 1563 => Opcode::PseudoVDIV_VX_MF2_E16,
15406 0 : 1564 => Opcode::PseudoVDIV_VX_MF2_E16_MASK,
15407 0 : 1565 => Opcode::PseudoVDIV_VX_MF2_E32,
15408 0 : 1566 => Opcode::PseudoVDIV_VX_MF2_E32_MASK,
15409 0 : 1567 => Opcode::PseudoVDIV_VX_MF2_E8,
15410 0 : 1568 => Opcode::PseudoVDIV_VX_MF2_E8_MASK,
15411 0 : 1569 => Opcode::PseudoVDIV_VX_MF4_E16,
15412 0 : 1570 => Opcode::PseudoVDIV_VX_MF4_E16_MASK,
15413 0 : 1571 => Opcode::PseudoVDIV_VX_MF4_E8,
15414 0 : 1572 => Opcode::PseudoVDIV_VX_MF4_E8_MASK,
15415 0 : 1573 => Opcode::PseudoVDIV_VX_MF8_E8,
15416 0 : 1574 => Opcode::PseudoVDIV_VX_MF8_E8_MASK,
15417 0 : 1575 => Opcode::PseudoVFADD_VFPR16_M1_E16,
15418 0 : 1576 => Opcode::PseudoVFADD_VFPR16_M1_E16_MASK,
15419 0 : 1577 => Opcode::PseudoVFADD_VFPR16_M2_E16,
15420 0 : 1578 => Opcode::PseudoVFADD_VFPR16_M2_E16_MASK,
15421 0 : 1579 => Opcode::PseudoVFADD_VFPR16_M4_E16,
15422 0 : 1580 => Opcode::PseudoVFADD_VFPR16_M4_E16_MASK,
15423 0 : 1581 => Opcode::PseudoVFADD_VFPR16_M8_E16,
15424 0 : 1582 => Opcode::PseudoVFADD_VFPR16_M8_E16_MASK,
15425 0 : 1583 => Opcode::PseudoVFADD_VFPR16_MF2_E16,
15426 0 : 1584 => Opcode::PseudoVFADD_VFPR16_MF2_E16_MASK,
15427 0 : 1585 => Opcode::PseudoVFADD_VFPR16_MF4_E16,
15428 0 : 1586 => Opcode::PseudoVFADD_VFPR16_MF4_E16_MASK,
15429 0 : 1587 => Opcode::PseudoVFADD_VFPR32_M1_E32,
15430 0 : 1588 => Opcode::PseudoVFADD_VFPR32_M1_E32_MASK,
15431 0 : 1589 => Opcode::PseudoVFADD_VFPR32_M2_E32,
15432 0 : 1590 => Opcode::PseudoVFADD_VFPR32_M2_E32_MASK,
15433 0 : 1591 => Opcode::PseudoVFADD_VFPR32_M4_E32,
15434 0 : 1592 => Opcode::PseudoVFADD_VFPR32_M4_E32_MASK,
15435 0 : 1593 => Opcode::PseudoVFADD_VFPR32_M8_E32,
15436 0 : 1594 => Opcode::PseudoVFADD_VFPR32_M8_E32_MASK,
15437 0 : 1595 => Opcode::PseudoVFADD_VFPR32_MF2_E32,
15438 0 : 1596 => Opcode::PseudoVFADD_VFPR32_MF2_E32_MASK,
15439 0 : 1597 => Opcode::PseudoVFADD_VFPR64_M1_E64,
15440 0 : 1598 => Opcode::PseudoVFADD_VFPR64_M1_E64_MASK,
15441 0 : 1599 => Opcode::PseudoVFADD_VFPR64_M2_E64,
15442 0 : 1600 => Opcode::PseudoVFADD_VFPR64_M2_E64_MASK,
15443 0 : 1601 => Opcode::PseudoVFADD_VFPR64_M4_E64,
15444 0 : 1602 => Opcode::PseudoVFADD_VFPR64_M4_E64_MASK,
15445 0 : 1603 => Opcode::PseudoVFADD_VFPR64_M8_E64,
15446 0 : 1604 => Opcode::PseudoVFADD_VFPR64_M8_E64_MASK,
15447 0 : 1605 => Opcode::PseudoVFADD_VV_M1_E16,
15448 0 : 1606 => Opcode::PseudoVFADD_VV_M1_E16_MASK,
15449 0 : 1607 => Opcode::PseudoVFADD_VV_M1_E32,
15450 0 : 1608 => Opcode::PseudoVFADD_VV_M1_E32_MASK,
15451 0 : 1609 => Opcode::PseudoVFADD_VV_M1_E64,
15452 0 : 1610 => Opcode::PseudoVFADD_VV_M1_E64_MASK,
15453 0 : 1611 => Opcode::PseudoVFADD_VV_M2_E16,
15454 0 : 1612 => Opcode::PseudoVFADD_VV_M2_E16_MASK,
15455 0 : 1613 => Opcode::PseudoVFADD_VV_M2_E32,
15456 0 : 1614 => Opcode::PseudoVFADD_VV_M2_E32_MASK,
15457 0 : 1615 => Opcode::PseudoVFADD_VV_M2_E64,
15458 0 : 1616 => Opcode::PseudoVFADD_VV_M2_E64_MASK,
15459 0 : 1617 => Opcode::PseudoVFADD_VV_M4_E16,
15460 0 : 1618 => Opcode::PseudoVFADD_VV_M4_E16_MASK,
15461 0 : 1619 => Opcode::PseudoVFADD_VV_M4_E32,
15462 0 : 1620 => Opcode::PseudoVFADD_VV_M4_E32_MASK,
15463 0 : 1621 => Opcode::PseudoVFADD_VV_M4_E64,
15464 0 : 1622 => Opcode::PseudoVFADD_VV_M4_E64_MASK,
15465 0 : 1623 => Opcode::PseudoVFADD_VV_M8_E16,
15466 0 : 1624 => Opcode::PseudoVFADD_VV_M8_E16_MASK,
15467 0 : 1625 => Opcode::PseudoVFADD_VV_M8_E32,
15468 0 : 1626 => Opcode::PseudoVFADD_VV_M8_E32_MASK,
15469 0 : 1627 => Opcode::PseudoVFADD_VV_M8_E64,
15470 0 : 1628 => Opcode::PseudoVFADD_VV_M8_E64_MASK,
15471 0 : 1629 => Opcode::PseudoVFADD_VV_MF2_E16,
15472 0 : 1630 => Opcode::PseudoVFADD_VV_MF2_E16_MASK,
15473 0 : 1631 => Opcode::PseudoVFADD_VV_MF2_E32,
15474 0 : 1632 => Opcode::PseudoVFADD_VV_MF2_E32_MASK,
15475 0 : 1633 => Opcode::PseudoVFADD_VV_MF4_E16,
15476 0 : 1634 => Opcode::PseudoVFADD_VV_MF4_E16_MASK,
15477 0 : 1635 => Opcode::PseudoVFCLASS_V_M1,
15478 0 : 1636 => Opcode::PseudoVFCLASS_V_M1_MASK,
15479 0 : 1637 => Opcode::PseudoVFCLASS_V_M2,
15480 0 : 1638 => Opcode::PseudoVFCLASS_V_M2_MASK,
15481 0 : 1639 => Opcode::PseudoVFCLASS_V_M4,
15482 0 : 1640 => Opcode::PseudoVFCLASS_V_M4_MASK,
15483 0 : 1641 => Opcode::PseudoVFCLASS_V_M8,
15484 0 : 1642 => Opcode::PseudoVFCLASS_V_M8_MASK,
15485 0 : 1643 => Opcode::PseudoVFCLASS_V_MF2,
15486 0 : 1644 => Opcode::PseudoVFCLASS_V_MF2_MASK,
15487 0 : 1645 => Opcode::PseudoVFCLASS_V_MF4,
15488 0 : 1646 => Opcode::PseudoVFCLASS_V_MF4_MASK,
15489 0 : 1647 => Opcode::PseudoVFCVT_F_XU_V_M1_E16,
15490 0 : 1648 => Opcode::PseudoVFCVT_F_XU_V_M1_E16_MASK,
15491 0 : 1649 => Opcode::PseudoVFCVT_F_XU_V_M1_E32,
15492 0 : 1650 => Opcode::PseudoVFCVT_F_XU_V_M1_E32_MASK,
15493 0 : 1651 => Opcode::PseudoVFCVT_F_XU_V_M1_E64,
15494 0 : 1652 => Opcode::PseudoVFCVT_F_XU_V_M1_E64_MASK,
15495 0 : 1653 => Opcode::PseudoVFCVT_F_XU_V_M2_E16,
15496 0 : 1654 => Opcode::PseudoVFCVT_F_XU_V_M2_E16_MASK,
15497 0 : 1655 => Opcode::PseudoVFCVT_F_XU_V_M2_E32,
15498 0 : 1656 => Opcode::PseudoVFCVT_F_XU_V_M2_E32_MASK,
15499 0 : 1657 => Opcode::PseudoVFCVT_F_XU_V_M2_E64,
15500 0 : 1658 => Opcode::PseudoVFCVT_F_XU_V_M2_E64_MASK,
15501 0 : 1659 => Opcode::PseudoVFCVT_F_XU_V_M4_E16,
15502 0 : 1660 => Opcode::PseudoVFCVT_F_XU_V_M4_E16_MASK,
15503 0 : 1661 => Opcode::PseudoVFCVT_F_XU_V_M4_E32,
15504 0 : 1662 => Opcode::PseudoVFCVT_F_XU_V_M4_E32_MASK,
15505 0 : 1663 => Opcode::PseudoVFCVT_F_XU_V_M4_E64,
15506 0 : 1664 => Opcode::PseudoVFCVT_F_XU_V_M4_E64_MASK,
15507 0 : 1665 => Opcode::PseudoVFCVT_F_XU_V_M8_E16,
15508 0 : 1666 => Opcode::PseudoVFCVT_F_XU_V_M8_E16_MASK,
15509 0 : 1667 => Opcode::PseudoVFCVT_F_XU_V_M8_E32,
15510 0 : 1668 => Opcode::PseudoVFCVT_F_XU_V_M8_E32_MASK,
15511 0 : 1669 => Opcode::PseudoVFCVT_F_XU_V_M8_E64,
15512 0 : 1670 => Opcode::PseudoVFCVT_F_XU_V_M8_E64_MASK,
15513 0 : 1671 => Opcode::PseudoVFCVT_F_XU_V_MF2_E16,
15514 0 : 1672 => Opcode::PseudoVFCVT_F_XU_V_MF2_E16_MASK,
15515 0 : 1673 => Opcode::PseudoVFCVT_F_XU_V_MF2_E32,
15516 0 : 1674 => Opcode::PseudoVFCVT_F_XU_V_MF2_E32_MASK,
15517 0 : 1675 => Opcode::PseudoVFCVT_F_XU_V_MF4_E16,
15518 0 : 1676 => Opcode::PseudoVFCVT_F_XU_V_MF4_E16_MASK,
15519 0 : 1677 => Opcode::PseudoVFCVT_F_X_V_M1_E16,
15520 0 : 1678 => Opcode::PseudoVFCVT_F_X_V_M1_E16_MASK,
15521 0 : 1679 => Opcode::PseudoVFCVT_F_X_V_M1_E32,
15522 0 : 1680 => Opcode::PseudoVFCVT_F_X_V_M1_E32_MASK,
15523 0 : 1681 => Opcode::PseudoVFCVT_F_X_V_M1_E64,
15524 0 : 1682 => Opcode::PseudoVFCVT_F_X_V_M1_E64_MASK,
15525 0 : 1683 => Opcode::PseudoVFCVT_F_X_V_M2_E16,
15526 0 : 1684 => Opcode::PseudoVFCVT_F_X_V_M2_E16_MASK,
15527 0 : 1685 => Opcode::PseudoVFCVT_F_X_V_M2_E32,
15528 0 : 1686 => Opcode::PseudoVFCVT_F_X_V_M2_E32_MASK,
15529 0 : 1687 => Opcode::PseudoVFCVT_F_X_V_M2_E64,
15530 0 : 1688 => Opcode::PseudoVFCVT_F_X_V_M2_E64_MASK,
15531 0 : 1689 => Opcode::PseudoVFCVT_F_X_V_M4_E16,
15532 0 : 1690 => Opcode::PseudoVFCVT_F_X_V_M4_E16_MASK,
15533 0 : 1691 => Opcode::PseudoVFCVT_F_X_V_M4_E32,
15534 0 : 1692 => Opcode::PseudoVFCVT_F_X_V_M4_E32_MASK,
15535 0 : 1693 => Opcode::PseudoVFCVT_F_X_V_M4_E64,
15536 0 : 1694 => Opcode::PseudoVFCVT_F_X_V_M4_E64_MASK,
15537 0 : 1695 => Opcode::PseudoVFCVT_F_X_V_M8_E16,
15538 0 : 1696 => Opcode::PseudoVFCVT_F_X_V_M8_E16_MASK,
15539 0 : 1697 => Opcode::PseudoVFCVT_F_X_V_M8_E32,
15540 0 : 1698 => Opcode::PseudoVFCVT_F_X_V_M8_E32_MASK,
15541 0 : 1699 => Opcode::PseudoVFCVT_F_X_V_M8_E64,
15542 0 : 1700 => Opcode::PseudoVFCVT_F_X_V_M8_E64_MASK,
15543 0 : 1701 => Opcode::PseudoVFCVT_F_X_V_MF2_E16,
15544 0 : 1702 => Opcode::PseudoVFCVT_F_X_V_MF2_E16_MASK,
15545 0 : 1703 => Opcode::PseudoVFCVT_F_X_V_MF2_E32,
15546 0 : 1704 => Opcode::PseudoVFCVT_F_X_V_MF2_E32_MASK,
15547 0 : 1705 => Opcode::PseudoVFCVT_F_X_V_MF4_E16,
15548 0 : 1706 => Opcode::PseudoVFCVT_F_X_V_MF4_E16_MASK,
15549 0 : 1707 => Opcode::PseudoVFCVT_RM_F_XU_V_M1_E16,
15550 0 : 1708 => Opcode::PseudoVFCVT_RM_F_XU_V_M1_E16_MASK,
15551 0 : 1709 => Opcode::PseudoVFCVT_RM_F_XU_V_M1_E32,
15552 0 : 1710 => Opcode::PseudoVFCVT_RM_F_XU_V_M1_E32_MASK,
15553 0 : 1711 => Opcode::PseudoVFCVT_RM_F_XU_V_M1_E64,
15554 0 : 1712 => Opcode::PseudoVFCVT_RM_F_XU_V_M1_E64_MASK,
15555 0 : 1713 => Opcode::PseudoVFCVT_RM_F_XU_V_M2_E16,
15556 0 : 1714 => Opcode::PseudoVFCVT_RM_F_XU_V_M2_E16_MASK,
15557 0 : 1715 => Opcode::PseudoVFCVT_RM_F_XU_V_M2_E32,
15558 0 : 1716 => Opcode::PseudoVFCVT_RM_F_XU_V_M2_E32_MASK,
15559 0 : 1717 => Opcode::PseudoVFCVT_RM_F_XU_V_M2_E64,
15560 0 : 1718 => Opcode::PseudoVFCVT_RM_F_XU_V_M2_E64_MASK,
15561 0 : 1719 => Opcode::PseudoVFCVT_RM_F_XU_V_M4_E16,
15562 0 : 1720 => Opcode::PseudoVFCVT_RM_F_XU_V_M4_E16_MASK,
15563 0 : 1721 => Opcode::PseudoVFCVT_RM_F_XU_V_M4_E32,
15564 0 : 1722 => Opcode::PseudoVFCVT_RM_F_XU_V_M4_E32_MASK,
15565 0 : 1723 => Opcode::PseudoVFCVT_RM_F_XU_V_M4_E64,
15566 0 : 1724 => Opcode::PseudoVFCVT_RM_F_XU_V_M4_E64_MASK,
15567 0 : 1725 => Opcode::PseudoVFCVT_RM_F_XU_V_M8_E16,
15568 0 : 1726 => Opcode::PseudoVFCVT_RM_F_XU_V_M8_E16_MASK,
15569 0 : 1727 => Opcode::PseudoVFCVT_RM_F_XU_V_M8_E32,
15570 0 : 1728 => Opcode::PseudoVFCVT_RM_F_XU_V_M8_E32_MASK,
15571 0 : 1729 => Opcode::PseudoVFCVT_RM_F_XU_V_M8_E64,
15572 0 : 1730 => Opcode::PseudoVFCVT_RM_F_XU_V_M8_E64_MASK,
15573 0 : 1731 => Opcode::PseudoVFCVT_RM_F_XU_V_MF2_E16,
15574 0 : 1732 => Opcode::PseudoVFCVT_RM_F_XU_V_MF2_E16_MASK,
15575 0 : 1733 => Opcode::PseudoVFCVT_RM_F_XU_V_MF2_E32,
15576 0 : 1734 => Opcode::PseudoVFCVT_RM_F_XU_V_MF2_E32_MASK,
15577 0 : 1735 => Opcode::PseudoVFCVT_RM_F_XU_V_MF4_E16,
15578 0 : 1736 => Opcode::PseudoVFCVT_RM_F_XU_V_MF4_E16_MASK,
15579 0 : 1737 => Opcode::PseudoVFCVT_RM_F_X_V_M1_E16,
15580 0 : 1738 => Opcode::PseudoVFCVT_RM_F_X_V_M1_E16_MASK,
15581 0 : 1739 => Opcode::PseudoVFCVT_RM_F_X_V_M1_E32,
15582 0 : 1740 => Opcode::PseudoVFCVT_RM_F_X_V_M1_E32_MASK,
15583 0 : 1741 => Opcode::PseudoVFCVT_RM_F_X_V_M1_E64,
15584 0 : 1742 => Opcode::PseudoVFCVT_RM_F_X_V_M1_E64_MASK,
15585 0 : 1743 => Opcode::PseudoVFCVT_RM_F_X_V_M2_E16,
15586 0 : 1744 => Opcode::PseudoVFCVT_RM_F_X_V_M2_E16_MASK,
15587 0 : 1745 => Opcode::PseudoVFCVT_RM_F_X_V_M2_E32,
15588 0 : 1746 => Opcode::PseudoVFCVT_RM_F_X_V_M2_E32_MASK,
15589 0 : 1747 => Opcode::PseudoVFCVT_RM_F_X_V_M2_E64,
15590 0 : 1748 => Opcode::PseudoVFCVT_RM_F_X_V_M2_E64_MASK,
15591 0 : 1749 => Opcode::PseudoVFCVT_RM_F_X_V_M4_E16,
15592 0 : 1750 => Opcode::PseudoVFCVT_RM_F_X_V_M4_E16_MASK,
15593 0 : 1751 => Opcode::PseudoVFCVT_RM_F_X_V_M4_E32,
15594 0 : 1752 => Opcode::PseudoVFCVT_RM_F_X_V_M4_E32_MASK,
15595 0 : 1753 => Opcode::PseudoVFCVT_RM_F_X_V_M4_E64,
15596 0 : 1754 => Opcode::PseudoVFCVT_RM_F_X_V_M4_E64_MASK,
15597 0 : 1755 => Opcode::PseudoVFCVT_RM_F_X_V_M8_E16,
15598 0 : 1756 => Opcode::PseudoVFCVT_RM_F_X_V_M8_E16_MASK,
15599 0 : 1757 => Opcode::PseudoVFCVT_RM_F_X_V_M8_E32,
15600 0 : 1758 => Opcode::PseudoVFCVT_RM_F_X_V_M8_E32_MASK,
15601 0 : 1759 => Opcode::PseudoVFCVT_RM_F_X_V_M8_E64,
15602 0 : 1760 => Opcode::PseudoVFCVT_RM_F_X_V_M8_E64_MASK,
15603 0 : 1761 => Opcode::PseudoVFCVT_RM_F_X_V_MF2_E16,
15604 0 : 1762 => Opcode::PseudoVFCVT_RM_F_X_V_MF2_E16_MASK,
15605 0 : 1763 => Opcode::PseudoVFCVT_RM_F_X_V_MF2_E32,
15606 0 : 1764 => Opcode::PseudoVFCVT_RM_F_X_V_MF2_E32_MASK,
15607 0 : 1765 => Opcode::PseudoVFCVT_RM_F_X_V_MF4_E16,
15608 0 : 1766 => Opcode::PseudoVFCVT_RM_F_X_V_MF4_E16_MASK,
15609 0 : 1767 => Opcode::PseudoVFCVT_RM_XU_F_V_M1,
15610 0 : 1768 => Opcode::PseudoVFCVT_RM_XU_F_V_M1_MASK,
15611 0 : 1769 => Opcode::PseudoVFCVT_RM_XU_F_V_M2,
15612 0 : 1770 => Opcode::PseudoVFCVT_RM_XU_F_V_M2_MASK,
15613 0 : 1771 => Opcode::PseudoVFCVT_RM_XU_F_V_M4,
15614 0 : 1772 => Opcode::PseudoVFCVT_RM_XU_F_V_M4_MASK,
15615 0 : 1773 => Opcode::PseudoVFCVT_RM_XU_F_V_M8,
15616 0 : 1774 => Opcode::PseudoVFCVT_RM_XU_F_V_M8_MASK,
15617 0 : 1775 => Opcode::PseudoVFCVT_RM_XU_F_V_MF2,
15618 0 : 1776 => Opcode::PseudoVFCVT_RM_XU_F_V_MF2_MASK,
15619 0 : 1777 => Opcode::PseudoVFCVT_RM_XU_F_V_MF4,
15620 0 : 1778 => Opcode::PseudoVFCVT_RM_XU_F_V_MF4_MASK,
15621 0 : 1779 => Opcode::PseudoVFCVT_RM_X_F_V_M1,
15622 0 : 1780 => Opcode::PseudoVFCVT_RM_X_F_V_M1_MASK,
15623 0 : 1781 => Opcode::PseudoVFCVT_RM_X_F_V_M2,
15624 0 : 1782 => Opcode::PseudoVFCVT_RM_X_F_V_M2_MASK,
15625 0 : 1783 => Opcode::PseudoVFCVT_RM_X_F_V_M4,
15626 0 : 1784 => Opcode::PseudoVFCVT_RM_X_F_V_M4_MASK,
15627 0 : 1785 => Opcode::PseudoVFCVT_RM_X_F_V_M8,
15628 0 : 1786 => Opcode::PseudoVFCVT_RM_X_F_V_M8_MASK,
15629 0 : 1787 => Opcode::PseudoVFCVT_RM_X_F_V_MF2,
15630 0 : 1788 => Opcode::PseudoVFCVT_RM_X_F_V_MF2_MASK,
15631 0 : 1789 => Opcode::PseudoVFCVT_RM_X_F_V_MF4,
15632 0 : 1790 => Opcode::PseudoVFCVT_RM_X_F_V_MF4_MASK,
15633 0 : 1791 => Opcode::PseudoVFCVT_RTZ_XU_F_V_M1,
15634 0 : 1792 => Opcode::PseudoVFCVT_RTZ_XU_F_V_M1_MASK,
15635 0 : 1793 => Opcode::PseudoVFCVT_RTZ_XU_F_V_M2,
15636 0 : 1794 => Opcode::PseudoVFCVT_RTZ_XU_F_V_M2_MASK,
15637 0 : 1795 => Opcode::PseudoVFCVT_RTZ_XU_F_V_M4,
15638 0 : 1796 => Opcode::PseudoVFCVT_RTZ_XU_F_V_M4_MASK,
15639 0 : 1797 => Opcode::PseudoVFCVT_RTZ_XU_F_V_M8,
15640 0 : 1798 => Opcode::PseudoVFCVT_RTZ_XU_F_V_M8_MASK,
15641 0 : 1799 => Opcode::PseudoVFCVT_RTZ_XU_F_V_MF2,
15642 0 : 1800 => Opcode::PseudoVFCVT_RTZ_XU_F_V_MF2_MASK,
15643 0 : 1801 => Opcode::PseudoVFCVT_RTZ_XU_F_V_MF4,
15644 0 : 1802 => Opcode::PseudoVFCVT_RTZ_XU_F_V_MF4_MASK,
15645 0 : 1803 => Opcode::PseudoVFCVT_RTZ_X_F_V_M1,
15646 0 : 1804 => Opcode::PseudoVFCVT_RTZ_X_F_V_M1_MASK,
15647 0 : 1805 => Opcode::PseudoVFCVT_RTZ_X_F_V_M2,
15648 0 : 1806 => Opcode::PseudoVFCVT_RTZ_X_F_V_M2_MASK,
15649 0 : 1807 => Opcode::PseudoVFCVT_RTZ_X_F_V_M4,
15650 0 : 1808 => Opcode::PseudoVFCVT_RTZ_X_F_V_M4_MASK,
15651 0 : 1809 => Opcode::PseudoVFCVT_RTZ_X_F_V_M8,
15652 0 : 1810 => Opcode::PseudoVFCVT_RTZ_X_F_V_M8_MASK,
15653 0 : 1811 => Opcode::PseudoVFCVT_RTZ_X_F_V_MF2,
15654 0 : 1812 => Opcode::PseudoVFCVT_RTZ_X_F_V_MF2_MASK,
15655 0 : 1813 => Opcode::PseudoVFCVT_RTZ_X_F_V_MF4,
15656 0 : 1814 => Opcode::PseudoVFCVT_RTZ_X_F_V_MF4_MASK,
15657 0 : 1815 => Opcode::PseudoVFCVT_XU_F_V_M1,
15658 0 : 1816 => Opcode::PseudoVFCVT_XU_F_V_M1_MASK,
15659 0 : 1817 => Opcode::PseudoVFCVT_XU_F_V_M2,
15660 0 : 1818 => Opcode::PseudoVFCVT_XU_F_V_M2_MASK,
15661 0 : 1819 => Opcode::PseudoVFCVT_XU_F_V_M4,
15662 0 : 1820 => Opcode::PseudoVFCVT_XU_F_V_M4_MASK,
15663 0 : 1821 => Opcode::PseudoVFCVT_XU_F_V_M8,
15664 0 : 1822 => Opcode::PseudoVFCVT_XU_F_V_M8_MASK,
15665 0 : 1823 => Opcode::PseudoVFCVT_XU_F_V_MF2,
15666 0 : 1824 => Opcode::PseudoVFCVT_XU_F_V_MF2_MASK,
15667 0 : 1825 => Opcode::PseudoVFCVT_XU_F_V_MF4,
15668 0 : 1826 => Opcode::PseudoVFCVT_XU_F_V_MF4_MASK,
15669 0 : 1827 => Opcode::PseudoVFCVT_X_F_V_M1,
15670 0 : 1828 => Opcode::PseudoVFCVT_X_F_V_M1_MASK,
15671 0 : 1829 => Opcode::PseudoVFCVT_X_F_V_M2,
15672 0 : 1830 => Opcode::PseudoVFCVT_X_F_V_M2_MASK,
15673 0 : 1831 => Opcode::PseudoVFCVT_X_F_V_M4,
15674 0 : 1832 => Opcode::PseudoVFCVT_X_F_V_M4_MASK,
15675 0 : 1833 => Opcode::PseudoVFCVT_X_F_V_M8,
15676 0 : 1834 => Opcode::PseudoVFCVT_X_F_V_M8_MASK,
15677 0 : 1835 => Opcode::PseudoVFCVT_X_F_V_MF2,
15678 0 : 1836 => Opcode::PseudoVFCVT_X_F_V_MF2_MASK,
15679 0 : 1837 => Opcode::PseudoVFCVT_X_F_V_MF4,
15680 0 : 1838 => Opcode::PseudoVFCVT_X_F_V_MF4_MASK,
15681 0 : 1839 => Opcode::PseudoVFDIV_VFPR16_M1_E16,
15682 0 : 1840 => Opcode::PseudoVFDIV_VFPR16_M1_E16_MASK,
15683 0 : 1841 => Opcode::PseudoVFDIV_VFPR16_M2_E16,
15684 0 : 1842 => Opcode::PseudoVFDIV_VFPR16_M2_E16_MASK,
15685 0 : 1843 => Opcode::PseudoVFDIV_VFPR16_M4_E16,
15686 0 : 1844 => Opcode::PseudoVFDIV_VFPR16_M4_E16_MASK,
15687 0 : 1845 => Opcode::PseudoVFDIV_VFPR16_M8_E16,
15688 0 : 1846 => Opcode::PseudoVFDIV_VFPR16_M8_E16_MASK,
15689 0 : 1847 => Opcode::PseudoVFDIV_VFPR16_MF2_E16,
15690 0 : 1848 => Opcode::PseudoVFDIV_VFPR16_MF2_E16_MASK,
15691 0 : 1849 => Opcode::PseudoVFDIV_VFPR16_MF4_E16,
15692 0 : 1850 => Opcode::PseudoVFDIV_VFPR16_MF4_E16_MASK,
15693 0 : 1851 => Opcode::PseudoVFDIV_VFPR32_M1_E32,
15694 0 : 1852 => Opcode::PseudoVFDIV_VFPR32_M1_E32_MASK,
15695 0 : 1853 => Opcode::PseudoVFDIV_VFPR32_M2_E32,
15696 0 : 1854 => Opcode::PseudoVFDIV_VFPR32_M2_E32_MASK,
15697 0 : 1855 => Opcode::PseudoVFDIV_VFPR32_M4_E32,
15698 0 : 1856 => Opcode::PseudoVFDIV_VFPR32_M4_E32_MASK,
15699 0 : 1857 => Opcode::PseudoVFDIV_VFPR32_M8_E32,
15700 0 : 1858 => Opcode::PseudoVFDIV_VFPR32_M8_E32_MASK,
15701 0 : 1859 => Opcode::PseudoVFDIV_VFPR32_MF2_E32,
15702 0 : 1860 => Opcode::PseudoVFDIV_VFPR32_MF2_E32_MASK,
15703 0 : 1861 => Opcode::PseudoVFDIV_VFPR64_M1_E64,
15704 0 : 1862 => Opcode::PseudoVFDIV_VFPR64_M1_E64_MASK,
15705 0 : 1863 => Opcode::PseudoVFDIV_VFPR64_M2_E64,
15706 0 : 1864 => Opcode::PseudoVFDIV_VFPR64_M2_E64_MASK,
15707 0 : 1865 => Opcode::PseudoVFDIV_VFPR64_M4_E64,
15708 0 : 1866 => Opcode::PseudoVFDIV_VFPR64_M4_E64_MASK,
15709 0 : 1867 => Opcode::PseudoVFDIV_VFPR64_M8_E64,
15710 0 : 1868 => Opcode::PseudoVFDIV_VFPR64_M8_E64_MASK,
15711 0 : 1869 => Opcode::PseudoVFDIV_VV_M1_E16,
15712 0 : 1870 => Opcode::PseudoVFDIV_VV_M1_E16_MASK,
15713 0 : 1871 => Opcode::PseudoVFDIV_VV_M1_E32,
15714 0 : 1872 => Opcode::PseudoVFDIV_VV_M1_E32_MASK,
15715 0 : 1873 => Opcode::PseudoVFDIV_VV_M1_E64,
15716 0 : 1874 => Opcode::PseudoVFDIV_VV_M1_E64_MASK,
15717 0 : 1875 => Opcode::PseudoVFDIV_VV_M2_E16,
15718 0 : 1876 => Opcode::PseudoVFDIV_VV_M2_E16_MASK,
15719 0 : 1877 => Opcode::PseudoVFDIV_VV_M2_E32,
15720 0 : 1878 => Opcode::PseudoVFDIV_VV_M2_E32_MASK,
15721 0 : 1879 => Opcode::PseudoVFDIV_VV_M2_E64,
15722 0 : 1880 => Opcode::PseudoVFDIV_VV_M2_E64_MASK,
15723 0 : 1881 => Opcode::PseudoVFDIV_VV_M4_E16,
15724 0 : 1882 => Opcode::PseudoVFDIV_VV_M4_E16_MASK,
15725 0 : 1883 => Opcode::PseudoVFDIV_VV_M4_E32,
15726 0 : 1884 => Opcode::PseudoVFDIV_VV_M4_E32_MASK,
15727 0 : 1885 => Opcode::PseudoVFDIV_VV_M4_E64,
15728 0 : 1886 => Opcode::PseudoVFDIV_VV_M4_E64_MASK,
15729 0 : 1887 => Opcode::PseudoVFDIV_VV_M8_E16,
15730 0 : 1888 => Opcode::PseudoVFDIV_VV_M8_E16_MASK,
15731 0 : 1889 => Opcode::PseudoVFDIV_VV_M8_E32,
15732 0 : 1890 => Opcode::PseudoVFDIV_VV_M8_E32_MASK,
15733 0 : 1891 => Opcode::PseudoVFDIV_VV_M8_E64,
15734 0 : 1892 => Opcode::PseudoVFDIV_VV_M8_E64_MASK,
15735 0 : 1893 => Opcode::PseudoVFDIV_VV_MF2_E16,
15736 0 : 1894 => Opcode::PseudoVFDIV_VV_MF2_E16_MASK,
15737 0 : 1895 => Opcode::PseudoVFDIV_VV_MF2_E32,
15738 0 : 1896 => Opcode::PseudoVFDIV_VV_MF2_E32_MASK,
15739 0 : 1897 => Opcode::PseudoVFDIV_VV_MF4_E16,
15740 0 : 1898 => Opcode::PseudoVFDIV_VV_MF4_E16_MASK,
15741 0 : 1899 => Opcode::PseudoVFIRST_M_B1,
15742 0 : 1900 => Opcode::PseudoVFIRST_M_B16,
15743 0 : 1901 => Opcode::PseudoVFIRST_M_B16_MASK,
15744 0 : 1902 => Opcode::PseudoVFIRST_M_B1_MASK,
15745 0 : 1903 => Opcode::PseudoVFIRST_M_B2,
15746 0 : 1904 => Opcode::PseudoVFIRST_M_B2_MASK,
15747 0 : 1905 => Opcode::PseudoVFIRST_M_B32,
15748 0 : 1906 => Opcode::PseudoVFIRST_M_B32_MASK,
15749 0 : 1907 => Opcode::PseudoVFIRST_M_B4,
15750 0 : 1908 => Opcode::PseudoVFIRST_M_B4_MASK,
15751 0 : 1909 => Opcode::PseudoVFIRST_M_B64,
15752 0 : 1910 => Opcode::PseudoVFIRST_M_B64_MASK,
15753 0 : 1911 => Opcode::PseudoVFIRST_M_B8,
15754 0 : 1912 => Opcode::PseudoVFIRST_M_B8_MASK,
15755 0 : 1913 => Opcode::PseudoVFMACC_VFPR16_M1_E16,
15756 0 : 1914 => Opcode::PseudoVFMACC_VFPR16_M1_E16_MASK,
15757 0 : 1915 => Opcode::PseudoVFMACC_VFPR16_M2_E16,
15758 0 : 1916 => Opcode::PseudoVFMACC_VFPR16_M2_E16_MASK,
15759 0 : 1917 => Opcode::PseudoVFMACC_VFPR16_M4_E16,
15760 0 : 1918 => Opcode::PseudoVFMACC_VFPR16_M4_E16_MASK,
15761 0 : 1919 => Opcode::PseudoVFMACC_VFPR16_M8_E16,
15762 0 : 1920 => Opcode::PseudoVFMACC_VFPR16_M8_E16_MASK,
15763 0 : 1921 => Opcode::PseudoVFMACC_VFPR16_MF2_E16,
15764 0 : 1922 => Opcode::PseudoVFMACC_VFPR16_MF2_E16_MASK,
15765 0 : 1923 => Opcode::PseudoVFMACC_VFPR16_MF4_E16,
15766 0 : 1924 => Opcode::PseudoVFMACC_VFPR16_MF4_E16_MASK,
15767 0 : 1925 => Opcode::PseudoVFMACC_VFPR32_M1_E32,
15768 0 : 1926 => Opcode::PseudoVFMACC_VFPR32_M1_E32_MASK,
15769 0 : 1927 => Opcode::PseudoVFMACC_VFPR32_M2_E32,
15770 0 : 1928 => Opcode::PseudoVFMACC_VFPR32_M2_E32_MASK,
15771 0 : 1929 => Opcode::PseudoVFMACC_VFPR32_M4_E32,
15772 0 : 1930 => Opcode::PseudoVFMACC_VFPR32_M4_E32_MASK,
15773 0 : 1931 => Opcode::PseudoVFMACC_VFPR32_M8_E32,
15774 0 : 1932 => Opcode::PseudoVFMACC_VFPR32_M8_E32_MASK,
15775 0 : 1933 => Opcode::PseudoVFMACC_VFPR32_MF2_E32,
15776 0 : 1934 => Opcode::PseudoVFMACC_VFPR32_MF2_E32_MASK,
15777 0 : 1935 => Opcode::PseudoVFMACC_VFPR64_M1_E64,
15778 0 : 1936 => Opcode::PseudoVFMACC_VFPR64_M1_E64_MASK,
15779 0 : 1937 => Opcode::PseudoVFMACC_VFPR64_M2_E64,
15780 0 : 1938 => Opcode::PseudoVFMACC_VFPR64_M2_E64_MASK,
15781 0 : 1939 => Opcode::PseudoVFMACC_VFPR64_M4_E64,
15782 0 : 1940 => Opcode::PseudoVFMACC_VFPR64_M4_E64_MASK,
15783 0 : 1941 => Opcode::PseudoVFMACC_VFPR64_M8_E64,
15784 0 : 1942 => Opcode::PseudoVFMACC_VFPR64_M8_E64_MASK,
15785 0 : 1943 => Opcode::PseudoVFMACC_VV_M1_E16,
15786 0 : 1944 => Opcode::PseudoVFMACC_VV_M1_E16_MASK,
15787 0 : 1945 => Opcode::PseudoVFMACC_VV_M1_E32,
15788 0 : 1946 => Opcode::PseudoVFMACC_VV_M1_E32_MASK,
15789 0 : 1947 => Opcode::PseudoVFMACC_VV_M1_E64,
15790 0 : 1948 => Opcode::PseudoVFMACC_VV_M1_E64_MASK,
15791 0 : 1949 => Opcode::PseudoVFMACC_VV_M2_E16,
15792 0 : 1950 => Opcode::PseudoVFMACC_VV_M2_E16_MASK,
15793 0 : 1951 => Opcode::PseudoVFMACC_VV_M2_E32,
15794 0 : 1952 => Opcode::PseudoVFMACC_VV_M2_E32_MASK,
15795 0 : 1953 => Opcode::PseudoVFMACC_VV_M2_E64,
15796 0 : 1954 => Opcode::PseudoVFMACC_VV_M2_E64_MASK,
15797 0 : 1955 => Opcode::PseudoVFMACC_VV_M4_E16,
15798 0 : 1956 => Opcode::PseudoVFMACC_VV_M4_E16_MASK,
15799 0 : 1957 => Opcode::PseudoVFMACC_VV_M4_E32,
15800 0 : 1958 => Opcode::PseudoVFMACC_VV_M4_E32_MASK,
15801 0 : 1959 => Opcode::PseudoVFMACC_VV_M4_E64,
15802 0 : 1960 => Opcode::PseudoVFMACC_VV_M4_E64_MASK,
15803 0 : 1961 => Opcode::PseudoVFMACC_VV_M8_E16,
15804 0 : 1962 => Opcode::PseudoVFMACC_VV_M8_E16_MASK,
15805 0 : 1963 => Opcode::PseudoVFMACC_VV_M8_E32,
15806 0 : 1964 => Opcode::PseudoVFMACC_VV_M8_E32_MASK,
15807 0 : 1965 => Opcode::PseudoVFMACC_VV_M8_E64,
15808 0 : 1966 => Opcode::PseudoVFMACC_VV_M8_E64_MASK,
15809 0 : 1967 => Opcode::PseudoVFMACC_VV_MF2_E16,
15810 0 : 1968 => Opcode::PseudoVFMACC_VV_MF2_E16_MASK,
15811 0 : 1969 => Opcode::PseudoVFMACC_VV_MF2_E32,
15812 0 : 1970 => Opcode::PseudoVFMACC_VV_MF2_E32_MASK,
15813 0 : 1971 => Opcode::PseudoVFMACC_VV_MF4_E16,
15814 0 : 1972 => Opcode::PseudoVFMACC_VV_MF4_E16_MASK,
15815 0 : 1973 => Opcode::PseudoVFMADD_VFPR16_M1_E16,
15816 0 : 1974 => Opcode::PseudoVFMADD_VFPR16_M1_E16_MASK,
15817 0 : 1975 => Opcode::PseudoVFMADD_VFPR16_M2_E16,
15818 0 : 1976 => Opcode::PseudoVFMADD_VFPR16_M2_E16_MASK,
15819 0 : 1977 => Opcode::PseudoVFMADD_VFPR16_M4_E16,
15820 0 : 1978 => Opcode::PseudoVFMADD_VFPR16_M4_E16_MASK,
15821 0 : 1979 => Opcode::PseudoVFMADD_VFPR16_M8_E16,
15822 0 : 1980 => Opcode::PseudoVFMADD_VFPR16_M8_E16_MASK,
15823 0 : 1981 => Opcode::PseudoVFMADD_VFPR16_MF2_E16,
15824 0 : 1982 => Opcode::PseudoVFMADD_VFPR16_MF2_E16_MASK,
15825 0 : 1983 => Opcode::PseudoVFMADD_VFPR16_MF4_E16,
15826 0 : 1984 => Opcode::PseudoVFMADD_VFPR16_MF4_E16_MASK,
15827 0 : 1985 => Opcode::PseudoVFMADD_VFPR32_M1_E32,
15828 0 : 1986 => Opcode::PseudoVFMADD_VFPR32_M1_E32_MASK,
15829 0 : 1987 => Opcode::PseudoVFMADD_VFPR32_M2_E32,
15830 0 : 1988 => Opcode::PseudoVFMADD_VFPR32_M2_E32_MASK,
15831 0 : 1989 => Opcode::PseudoVFMADD_VFPR32_M4_E32,
15832 0 : 1990 => Opcode::PseudoVFMADD_VFPR32_M4_E32_MASK,
15833 0 : 1991 => Opcode::PseudoVFMADD_VFPR32_M8_E32,
15834 0 : 1992 => Opcode::PseudoVFMADD_VFPR32_M8_E32_MASK,
15835 0 : 1993 => Opcode::PseudoVFMADD_VFPR32_MF2_E32,
15836 0 : 1994 => Opcode::PseudoVFMADD_VFPR32_MF2_E32_MASK,
15837 0 : 1995 => Opcode::PseudoVFMADD_VFPR64_M1_E64,
15838 0 : 1996 => Opcode::PseudoVFMADD_VFPR64_M1_E64_MASK,
15839 0 : 1997 => Opcode::PseudoVFMADD_VFPR64_M2_E64,
15840 0 : 1998 => Opcode::PseudoVFMADD_VFPR64_M2_E64_MASK,
15841 0 : 1999 => Opcode::PseudoVFMADD_VFPR64_M4_E64,
15842 0 : 2000 => Opcode::PseudoVFMADD_VFPR64_M4_E64_MASK,
15843 0 : 2001 => Opcode::PseudoVFMADD_VFPR64_M8_E64,
15844 0 : 2002 => Opcode::PseudoVFMADD_VFPR64_M8_E64_MASK,
15845 0 : 2003 => Opcode::PseudoVFMADD_VV_M1_E16,
15846 0 : 2004 => Opcode::PseudoVFMADD_VV_M1_E16_MASK,
15847 0 : 2005 => Opcode::PseudoVFMADD_VV_M1_E32,
15848 0 : 2006 => Opcode::PseudoVFMADD_VV_M1_E32_MASK,
15849 0 : 2007 => Opcode::PseudoVFMADD_VV_M1_E64,
15850 0 : 2008 => Opcode::PseudoVFMADD_VV_M1_E64_MASK,
15851 0 : 2009 => Opcode::PseudoVFMADD_VV_M2_E16,
15852 0 : 2010 => Opcode::PseudoVFMADD_VV_M2_E16_MASK,
15853 0 : 2011 => Opcode::PseudoVFMADD_VV_M2_E32,
15854 0 : 2012 => Opcode::PseudoVFMADD_VV_M2_E32_MASK,
15855 0 : 2013 => Opcode::PseudoVFMADD_VV_M2_E64,
15856 0 : 2014 => Opcode::PseudoVFMADD_VV_M2_E64_MASK,
15857 0 : 2015 => Opcode::PseudoVFMADD_VV_M4_E16,
15858 0 : 2016 => Opcode::PseudoVFMADD_VV_M4_E16_MASK,
15859 0 : 2017 => Opcode::PseudoVFMADD_VV_M4_E32,
15860 0 : 2018 => Opcode::PseudoVFMADD_VV_M4_E32_MASK,
15861 0 : 2019 => Opcode::PseudoVFMADD_VV_M4_E64,
15862 0 : 2020 => Opcode::PseudoVFMADD_VV_M4_E64_MASK,
15863 0 : 2021 => Opcode::PseudoVFMADD_VV_M8_E16,
15864 0 : 2022 => Opcode::PseudoVFMADD_VV_M8_E16_MASK,
15865 0 : 2023 => Opcode::PseudoVFMADD_VV_M8_E32,
15866 0 : 2024 => Opcode::PseudoVFMADD_VV_M8_E32_MASK,
15867 0 : 2025 => Opcode::PseudoVFMADD_VV_M8_E64,
15868 0 : 2026 => Opcode::PseudoVFMADD_VV_M8_E64_MASK,
15869 0 : 2027 => Opcode::PseudoVFMADD_VV_MF2_E16,
15870 0 : 2028 => Opcode::PseudoVFMADD_VV_MF2_E16_MASK,
15871 0 : 2029 => Opcode::PseudoVFMADD_VV_MF2_E32,
15872 0 : 2030 => Opcode::PseudoVFMADD_VV_MF2_E32_MASK,
15873 0 : 2031 => Opcode::PseudoVFMADD_VV_MF4_E16,
15874 0 : 2032 => Opcode::PseudoVFMADD_VV_MF4_E16_MASK,
15875 0 : 2033 => Opcode::PseudoVFMAX_VFPR16_M1_E16,
15876 0 : 2034 => Opcode::PseudoVFMAX_VFPR16_M1_E16_MASK,
15877 0 : 2035 => Opcode::PseudoVFMAX_VFPR16_M2_E16,
15878 0 : 2036 => Opcode::PseudoVFMAX_VFPR16_M2_E16_MASK,
15879 0 : 2037 => Opcode::PseudoVFMAX_VFPR16_M4_E16,
15880 0 : 2038 => Opcode::PseudoVFMAX_VFPR16_M4_E16_MASK,
15881 0 : 2039 => Opcode::PseudoVFMAX_VFPR16_M8_E16,
15882 0 : 2040 => Opcode::PseudoVFMAX_VFPR16_M8_E16_MASK,
15883 0 : 2041 => Opcode::PseudoVFMAX_VFPR16_MF2_E16,
15884 0 : 2042 => Opcode::PseudoVFMAX_VFPR16_MF2_E16_MASK,
15885 0 : 2043 => Opcode::PseudoVFMAX_VFPR16_MF4_E16,
15886 0 : 2044 => Opcode::PseudoVFMAX_VFPR16_MF4_E16_MASK,
15887 0 : 2045 => Opcode::PseudoVFMAX_VFPR32_M1_E32,
15888 0 : 2046 => Opcode::PseudoVFMAX_VFPR32_M1_E32_MASK,
15889 0 : 2047 => Opcode::PseudoVFMAX_VFPR32_M2_E32,
15890 0 : 2048 => Opcode::PseudoVFMAX_VFPR32_M2_E32_MASK,
15891 0 : 2049 => Opcode::PseudoVFMAX_VFPR32_M4_E32,
15892 0 : 2050 => Opcode::PseudoVFMAX_VFPR32_M4_E32_MASK,
15893 0 : 2051 => Opcode::PseudoVFMAX_VFPR32_M8_E32,
15894 0 : 2052 => Opcode::PseudoVFMAX_VFPR32_M8_E32_MASK,
15895 0 : 2053 => Opcode::PseudoVFMAX_VFPR32_MF2_E32,
15896 0 : 2054 => Opcode::PseudoVFMAX_VFPR32_MF2_E32_MASK,
15897 0 : 2055 => Opcode::PseudoVFMAX_VFPR64_M1_E64,
15898 0 : 2056 => Opcode::PseudoVFMAX_VFPR64_M1_E64_MASK,
15899 0 : 2057 => Opcode::PseudoVFMAX_VFPR64_M2_E64,
15900 0 : 2058 => Opcode::PseudoVFMAX_VFPR64_M2_E64_MASK,
15901 0 : 2059 => Opcode::PseudoVFMAX_VFPR64_M4_E64,
15902 0 : 2060 => Opcode::PseudoVFMAX_VFPR64_M4_E64_MASK,
15903 0 : 2061 => Opcode::PseudoVFMAX_VFPR64_M8_E64,
15904 0 : 2062 => Opcode::PseudoVFMAX_VFPR64_M8_E64_MASK,
15905 0 : 2063 => Opcode::PseudoVFMAX_VV_M1_E16,
15906 0 : 2064 => Opcode::PseudoVFMAX_VV_M1_E16_MASK,
15907 0 : 2065 => Opcode::PseudoVFMAX_VV_M1_E32,
15908 0 : 2066 => Opcode::PseudoVFMAX_VV_M1_E32_MASK,
15909 0 : 2067 => Opcode::PseudoVFMAX_VV_M1_E64,
15910 0 : 2068 => Opcode::PseudoVFMAX_VV_M1_E64_MASK,
15911 0 : 2069 => Opcode::PseudoVFMAX_VV_M2_E16,
15912 0 : 2070 => Opcode::PseudoVFMAX_VV_M2_E16_MASK,
15913 0 : 2071 => Opcode::PseudoVFMAX_VV_M2_E32,
15914 0 : 2072 => Opcode::PseudoVFMAX_VV_M2_E32_MASK,
15915 0 : 2073 => Opcode::PseudoVFMAX_VV_M2_E64,
15916 0 : 2074 => Opcode::PseudoVFMAX_VV_M2_E64_MASK,
15917 0 : 2075 => Opcode::PseudoVFMAX_VV_M4_E16,
15918 0 : 2076 => Opcode::PseudoVFMAX_VV_M4_E16_MASK,
15919 0 : 2077 => Opcode::PseudoVFMAX_VV_M4_E32,
15920 0 : 2078 => Opcode::PseudoVFMAX_VV_M4_E32_MASK,
15921 0 : 2079 => Opcode::PseudoVFMAX_VV_M4_E64,
15922 0 : 2080 => Opcode::PseudoVFMAX_VV_M4_E64_MASK,
15923 0 : 2081 => Opcode::PseudoVFMAX_VV_M8_E16,
15924 0 : 2082 => Opcode::PseudoVFMAX_VV_M8_E16_MASK,
15925 0 : 2083 => Opcode::PseudoVFMAX_VV_M8_E32,
15926 0 : 2084 => Opcode::PseudoVFMAX_VV_M8_E32_MASK,
15927 0 : 2085 => Opcode::PseudoVFMAX_VV_M8_E64,
15928 0 : 2086 => Opcode::PseudoVFMAX_VV_M8_E64_MASK,
15929 0 : 2087 => Opcode::PseudoVFMAX_VV_MF2_E16,
15930 0 : 2088 => Opcode::PseudoVFMAX_VV_MF2_E16_MASK,
15931 0 : 2089 => Opcode::PseudoVFMAX_VV_MF2_E32,
15932 0 : 2090 => Opcode::PseudoVFMAX_VV_MF2_E32_MASK,
15933 0 : 2091 => Opcode::PseudoVFMAX_VV_MF4_E16,
15934 0 : 2092 => Opcode::PseudoVFMAX_VV_MF4_E16_MASK,
15935 0 : 2093 => Opcode::PseudoVFMERGE_VFPR16M_M1,
15936 0 : 2094 => Opcode::PseudoVFMERGE_VFPR16M_M2,
15937 0 : 2095 => Opcode::PseudoVFMERGE_VFPR16M_M4,
15938 0 : 2096 => Opcode::PseudoVFMERGE_VFPR16M_M8,
15939 0 : 2097 => Opcode::PseudoVFMERGE_VFPR16M_MF2,
15940 0 : 2098 => Opcode::PseudoVFMERGE_VFPR16M_MF4,
15941 0 : 2099 => Opcode::PseudoVFMERGE_VFPR32M_M1,
15942 0 : 2100 => Opcode::PseudoVFMERGE_VFPR32M_M2,
15943 0 : 2101 => Opcode::PseudoVFMERGE_VFPR32M_M4,
15944 0 : 2102 => Opcode::PseudoVFMERGE_VFPR32M_M8,
15945 0 : 2103 => Opcode::PseudoVFMERGE_VFPR32M_MF2,
15946 0 : 2104 => Opcode::PseudoVFMERGE_VFPR64M_M1,
15947 0 : 2105 => Opcode::PseudoVFMERGE_VFPR64M_M2,
15948 0 : 2106 => Opcode::PseudoVFMERGE_VFPR64M_M4,
15949 0 : 2107 => Opcode::PseudoVFMERGE_VFPR64M_M8,
15950 0 : 2108 => Opcode::PseudoVFMIN_VFPR16_M1_E16,
15951 0 : 2109 => Opcode::PseudoVFMIN_VFPR16_M1_E16_MASK,
15952 0 : 2110 => Opcode::PseudoVFMIN_VFPR16_M2_E16,
15953 0 : 2111 => Opcode::PseudoVFMIN_VFPR16_M2_E16_MASK,
15954 0 : 2112 => Opcode::PseudoVFMIN_VFPR16_M4_E16,
15955 0 : 2113 => Opcode::PseudoVFMIN_VFPR16_M4_E16_MASK,
15956 0 : 2114 => Opcode::PseudoVFMIN_VFPR16_M8_E16,
15957 0 : 2115 => Opcode::PseudoVFMIN_VFPR16_M8_E16_MASK,
15958 0 : 2116 => Opcode::PseudoVFMIN_VFPR16_MF2_E16,
15959 0 : 2117 => Opcode::PseudoVFMIN_VFPR16_MF2_E16_MASK,
15960 0 : 2118 => Opcode::PseudoVFMIN_VFPR16_MF4_E16,
15961 0 : 2119 => Opcode::PseudoVFMIN_VFPR16_MF4_E16_MASK,
15962 0 : 2120 => Opcode::PseudoVFMIN_VFPR32_M1_E32,
15963 0 : 2121 => Opcode::PseudoVFMIN_VFPR32_M1_E32_MASK,
15964 0 : 2122 => Opcode::PseudoVFMIN_VFPR32_M2_E32,
15965 0 : 2123 => Opcode::PseudoVFMIN_VFPR32_M2_E32_MASK,
15966 0 : 2124 => Opcode::PseudoVFMIN_VFPR32_M4_E32,
15967 0 : 2125 => Opcode::PseudoVFMIN_VFPR32_M4_E32_MASK,
15968 0 : 2126 => Opcode::PseudoVFMIN_VFPR32_M8_E32,
15969 0 : 2127 => Opcode::PseudoVFMIN_VFPR32_M8_E32_MASK,
15970 0 : 2128 => Opcode::PseudoVFMIN_VFPR32_MF2_E32,
15971 0 : 2129 => Opcode::PseudoVFMIN_VFPR32_MF2_E32_MASK,
15972 0 : 2130 => Opcode::PseudoVFMIN_VFPR64_M1_E64,
15973 0 : 2131 => Opcode::PseudoVFMIN_VFPR64_M1_E64_MASK,
15974 0 : 2132 => Opcode::PseudoVFMIN_VFPR64_M2_E64,
15975 0 : 2133 => Opcode::PseudoVFMIN_VFPR64_M2_E64_MASK,
15976 0 : 2134 => Opcode::PseudoVFMIN_VFPR64_M4_E64,
15977 0 : 2135 => Opcode::PseudoVFMIN_VFPR64_M4_E64_MASK,
15978 0 : 2136 => Opcode::PseudoVFMIN_VFPR64_M8_E64,
15979 0 : 2137 => Opcode::PseudoVFMIN_VFPR64_M8_E64_MASK,
15980 0 : 2138 => Opcode::PseudoVFMIN_VV_M1_E16,
15981 0 : 2139 => Opcode::PseudoVFMIN_VV_M1_E16_MASK,
15982 0 : 2140 => Opcode::PseudoVFMIN_VV_M1_E32,
15983 0 : 2141 => Opcode::PseudoVFMIN_VV_M1_E32_MASK,
15984 0 : 2142 => Opcode::PseudoVFMIN_VV_M1_E64,
15985 0 : 2143 => Opcode::PseudoVFMIN_VV_M1_E64_MASK,
15986 0 : 2144 => Opcode::PseudoVFMIN_VV_M2_E16,
15987 0 : 2145 => Opcode::PseudoVFMIN_VV_M2_E16_MASK,
15988 0 : 2146 => Opcode::PseudoVFMIN_VV_M2_E32,
15989 0 : 2147 => Opcode::PseudoVFMIN_VV_M2_E32_MASK,
15990 0 : 2148 => Opcode::PseudoVFMIN_VV_M2_E64,
15991 0 : 2149 => Opcode::PseudoVFMIN_VV_M2_E64_MASK,
15992 0 : 2150 => Opcode::PseudoVFMIN_VV_M4_E16,
15993 0 : 2151 => Opcode::PseudoVFMIN_VV_M4_E16_MASK,
15994 0 : 2152 => Opcode::PseudoVFMIN_VV_M4_E32,
15995 0 : 2153 => Opcode::PseudoVFMIN_VV_M4_E32_MASK,
15996 0 : 2154 => Opcode::PseudoVFMIN_VV_M4_E64,
15997 0 : 2155 => Opcode::PseudoVFMIN_VV_M4_E64_MASK,
15998 0 : 2156 => Opcode::PseudoVFMIN_VV_M8_E16,
15999 0 : 2157 => Opcode::PseudoVFMIN_VV_M8_E16_MASK,
16000 0 : 2158 => Opcode::PseudoVFMIN_VV_M8_E32,
16001 0 : 2159 => Opcode::PseudoVFMIN_VV_M8_E32_MASK,
16002 0 : 2160 => Opcode::PseudoVFMIN_VV_M8_E64,
16003 0 : 2161 => Opcode::PseudoVFMIN_VV_M8_E64_MASK,
16004 0 : 2162 => Opcode::PseudoVFMIN_VV_MF2_E16,
16005 0 : 2163 => Opcode::PseudoVFMIN_VV_MF2_E16_MASK,
16006 0 : 2164 => Opcode::PseudoVFMIN_VV_MF2_E32,
16007 0 : 2165 => Opcode::PseudoVFMIN_VV_MF2_E32_MASK,
16008 0 : 2166 => Opcode::PseudoVFMIN_VV_MF4_E16,
16009 0 : 2167 => Opcode::PseudoVFMIN_VV_MF4_E16_MASK,
16010 0 : 2168 => Opcode::PseudoVFMSAC_VFPR16_M1_E16,
16011 0 : 2169 => Opcode::PseudoVFMSAC_VFPR16_M1_E16_MASK,
16012 0 : 2170 => Opcode::PseudoVFMSAC_VFPR16_M2_E16,
16013 0 : 2171 => Opcode::PseudoVFMSAC_VFPR16_M2_E16_MASK,
16014 0 : 2172 => Opcode::PseudoVFMSAC_VFPR16_M4_E16,
16015 0 : 2173 => Opcode::PseudoVFMSAC_VFPR16_M4_E16_MASK,
16016 0 : 2174 => Opcode::PseudoVFMSAC_VFPR16_M8_E16,
16017 0 : 2175 => Opcode::PseudoVFMSAC_VFPR16_M8_E16_MASK,
16018 0 : 2176 => Opcode::PseudoVFMSAC_VFPR16_MF2_E16,
16019 0 : 2177 => Opcode::PseudoVFMSAC_VFPR16_MF2_E16_MASK,
16020 0 : 2178 => Opcode::PseudoVFMSAC_VFPR16_MF4_E16,
16021 0 : 2179 => Opcode::PseudoVFMSAC_VFPR16_MF4_E16_MASK,
16022 0 : 2180 => Opcode::PseudoVFMSAC_VFPR32_M1_E32,
16023 0 : 2181 => Opcode::PseudoVFMSAC_VFPR32_M1_E32_MASK,
16024 0 : 2182 => Opcode::PseudoVFMSAC_VFPR32_M2_E32,
16025 0 : 2183 => Opcode::PseudoVFMSAC_VFPR32_M2_E32_MASK,
16026 0 : 2184 => Opcode::PseudoVFMSAC_VFPR32_M4_E32,
16027 0 : 2185 => Opcode::PseudoVFMSAC_VFPR32_M4_E32_MASK,
16028 0 : 2186 => Opcode::PseudoVFMSAC_VFPR32_M8_E32,
16029 0 : 2187 => Opcode::PseudoVFMSAC_VFPR32_M8_E32_MASK,
16030 0 : 2188 => Opcode::PseudoVFMSAC_VFPR32_MF2_E32,
16031 0 : 2189 => Opcode::PseudoVFMSAC_VFPR32_MF2_E32_MASK,
16032 0 : 2190 => Opcode::PseudoVFMSAC_VFPR64_M1_E64,
16033 0 : 2191 => Opcode::PseudoVFMSAC_VFPR64_M1_E64_MASK,
16034 0 : 2192 => Opcode::PseudoVFMSAC_VFPR64_M2_E64,
16035 0 : 2193 => Opcode::PseudoVFMSAC_VFPR64_M2_E64_MASK,
16036 0 : 2194 => Opcode::PseudoVFMSAC_VFPR64_M4_E64,
16037 0 : 2195 => Opcode::PseudoVFMSAC_VFPR64_M4_E64_MASK,
16038 0 : 2196 => Opcode::PseudoVFMSAC_VFPR64_M8_E64,
16039 0 : 2197 => Opcode::PseudoVFMSAC_VFPR64_M8_E64_MASK,
16040 0 : 2198 => Opcode::PseudoVFMSAC_VV_M1_E16,
16041 0 : 2199 => Opcode::PseudoVFMSAC_VV_M1_E16_MASK,
16042 0 : 2200 => Opcode::PseudoVFMSAC_VV_M1_E32,
16043 0 : 2201 => Opcode::PseudoVFMSAC_VV_M1_E32_MASK,
16044 0 : 2202 => Opcode::PseudoVFMSAC_VV_M1_E64,
16045 0 : 2203 => Opcode::PseudoVFMSAC_VV_M1_E64_MASK,
16046 0 : 2204 => Opcode::PseudoVFMSAC_VV_M2_E16,
16047 0 : 2205 => Opcode::PseudoVFMSAC_VV_M2_E16_MASK,
16048 0 : 2206 => Opcode::PseudoVFMSAC_VV_M2_E32,
16049 0 : 2207 => Opcode::PseudoVFMSAC_VV_M2_E32_MASK,
16050 0 : 2208 => Opcode::PseudoVFMSAC_VV_M2_E64,
16051 0 : 2209 => Opcode::PseudoVFMSAC_VV_M2_E64_MASK,
16052 0 : 2210 => Opcode::PseudoVFMSAC_VV_M4_E16,
16053 0 : 2211 => Opcode::PseudoVFMSAC_VV_M4_E16_MASK,
16054 0 : 2212 => Opcode::PseudoVFMSAC_VV_M4_E32,
16055 0 : 2213 => Opcode::PseudoVFMSAC_VV_M4_E32_MASK,
16056 0 : 2214 => Opcode::PseudoVFMSAC_VV_M4_E64,
16057 0 : 2215 => Opcode::PseudoVFMSAC_VV_M4_E64_MASK,
16058 0 : 2216 => Opcode::PseudoVFMSAC_VV_M8_E16,
16059 0 : 2217 => Opcode::PseudoVFMSAC_VV_M8_E16_MASK,
16060 0 : 2218 => Opcode::PseudoVFMSAC_VV_M8_E32,
16061 0 : 2219 => Opcode::PseudoVFMSAC_VV_M8_E32_MASK,
16062 0 : 2220 => Opcode::PseudoVFMSAC_VV_M8_E64,
16063 0 : 2221 => Opcode::PseudoVFMSAC_VV_M8_E64_MASK,
16064 0 : 2222 => Opcode::PseudoVFMSAC_VV_MF2_E16,
16065 0 : 2223 => Opcode::PseudoVFMSAC_VV_MF2_E16_MASK,
16066 0 : 2224 => Opcode::PseudoVFMSAC_VV_MF2_E32,
16067 0 : 2225 => Opcode::PseudoVFMSAC_VV_MF2_E32_MASK,
16068 0 : 2226 => Opcode::PseudoVFMSAC_VV_MF4_E16,
16069 0 : 2227 => Opcode::PseudoVFMSAC_VV_MF4_E16_MASK,
16070 0 : 2228 => Opcode::PseudoVFMSUB_VFPR16_M1_E16,
16071 0 : 2229 => Opcode::PseudoVFMSUB_VFPR16_M1_E16_MASK,
16072 0 : 2230 => Opcode::PseudoVFMSUB_VFPR16_M2_E16,
16073 0 : 2231 => Opcode::PseudoVFMSUB_VFPR16_M2_E16_MASK,
16074 0 : 2232 => Opcode::PseudoVFMSUB_VFPR16_M4_E16,
16075 0 : 2233 => Opcode::PseudoVFMSUB_VFPR16_M4_E16_MASK,
16076 0 : 2234 => Opcode::PseudoVFMSUB_VFPR16_M8_E16,
16077 0 : 2235 => Opcode::PseudoVFMSUB_VFPR16_M8_E16_MASK,
16078 0 : 2236 => Opcode::PseudoVFMSUB_VFPR16_MF2_E16,
16079 0 : 2237 => Opcode::PseudoVFMSUB_VFPR16_MF2_E16_MASK,
16080 0 : 2238 => Opcode::PseudoVFMSUB_VFPR16_MF4_E16,
16081 0 : 2239 => Opcode::PseudoVFMSUB_VFPR16_MF4_E16_MASK,
16082 0 : 2240 => Opcode::PseudoVFMSUB_VFPR32_M1_E32,
16083 0 : 2241 => Opcode::PseudoVFMSUB_VFPR32_M1_E32_MASK,
16084 0 : 2242 => Opcode::PseudoVFMSUB_VFPR32_M2_E32,
16085 0 : 2243 => Opcode::PseudoVFMSUB_VFPR32_M2_E32_MASK,
16086 0 : 2244 => Opcode::PseudoVFMSUB_VFPR32_M4_E32,
16087 0 : 2245 => Opcode::PseudoVFMSUB_VFPR32_M4_E32_MASK,
16088 0 : 2246 => Opcode::PseudoVFMSUB_VFPR32_M8_E32,
16089 0 : 2247 => Opcode::PseudoVFMSUB_VFPR32_M8_E32_MASK,
16090 0 : 2248 => Opcode::PseudoVFMSUB_VFPR32_MF2_E32,
16091 0 : 2249 => Opcode::PseudoVFMSUB_VFPR32_MF2_E32_MASK,
16092 0 : 2250 => Opcode::PseudoVFMSUB_VFPR64_M1_E64,
16093 0 : 2251 => Opcode::PseudoVFMSUB_VFPR64_M1_E64_MASK,
16094 0 : 2252 => Opcode::PseudoVFMSUB_VFPR64_M2_E64,
16095 0 : 2253 => Opcode::PseudoVFMSUB_VFPR64_M2_E64_MASK,
16096 0 : 2254 => Opcode::PseudoVFMSUB_VFPR64_M4_E64,
16097 0 : 2255 => Opcode::PseudoVFMSUB_VFPR64_M4_E64_MASK,
16098 0 : 2256 => Opcode::PseudoVFMSUB_VFPR64_M8_E64,
16099 0 : 2257 => Opcode::PseudoVFMSUB_VFPR64_M8_E64_MASK,
16100 0 : 2258 => Opcode::PseudoVFMSUB_VV_M1_E16,
16101 0 : 2259 => Opcode::PseudoVFMSUB_VV_M1_E16_MASK,
16102 0 : 2260 => Opcode::PseudoVFMSUB_VV_M1_E32,
16103 0 : 2261 => Opcode::PseudoVFMSUB_VV_M1_E32_MASK,
16104 0 : 2262 => Opcode::PseudoVFMSUB_VV_M1_E64,
16105 0 : 2263 => Opcode::PseudoVFMSUB_VV_M1_E64_MASK,
16106 0 : 2264 => Opcode::PseudoVFMSUB_VV_M2_E16,
16107 0 : 2265 => Opcode::PseudoVFMSUB_VV_M2_E16_MASK,
16108 0 : 2266 => Opcode::PseudoVFMSUB_VV_M2_E32,
16109 0 : 2267 => Opcode::PseudoVFMSUB_VV_M2_E32_MASK,
16110 0 : 2268 => Opcode::PseudoVFMSUB_VV_M2_E64,
16111 0 : 2269 => Opcode::PseudoVFMSUB_VV_M2_E64_MASK,
16112 0 : 2270 => Opcode::PseudoVFMSUB_VV_M4_E16,
16113 0 : 2271 => Opcode::PseudoVFMSUB_VV_M4_E16_MASK,
16114 0 : 2272 => Opcode::PseudoVFMSUB_VV_M4_E32,
16115 0 : 2273 => Opcode::PseudoVFMSUB_VV_M4_E32_MASK,
16116 0 : 2274 => Opcode::PseudoVFMSUB_VV_M4_E64,
16117 0 : 2275 => Opcode::PseudoVFMSUB_VV_M4_E64_MASK,
16118 0 : 2276 => Opcode::PseudoVFMSUB_VV_M8_E16,
16119 0 : 2277 => Opcode::PseudoVFMSUB_VV_M8_E16_MASK,
16120 0 : 2278 => Opcode::PseudoVFMSUB_VV_M8_E32,
16121 0 : 2279 => Opcode::PseudoVFMSUB_VV_M8_E32_MASK,
16122 0 : 2280 => Opcode::PseudoVFMSUB_VV_M8_E64,
16123 0 : 2281 => Opcode::PseudoVFMSUB_VV_M8_E64_MASK,
16124 0 : 2282 => Opcode::PseudoVFMSUB_VV_MF2_E16,
16125 0 : 2283 => Opcode::PseudoVFMSUB_VV_MF2_E16_MASK,
16126 0 : 2284 => Opcode::PseudoVFMSUB_VV_MF2_E32,
16127 0 : 2285 => Opcode::PseudoVFMSUB_VV_MF2_E32_MASK,
16128 0 : 2286 => Opcode::PseudoVFMSUB_VV_MF4_E16,
16129 0 : 2287 => Opcode::PseudoVFMSUB_VV_MF4_E16_MASK,
16130 0 : 2288 => Opcode::PseudoVFMUL_VFPR16_M1_E16,
16131 0 : 2289 => Opcode::PseudoVFMUL_VFPR16_M1_E16_MASK,
16132 0 : 2290 => Opcode::PseudoVFMUL_VFPR16_M2_E16,
16133 0 : 2291 => Opcode::PseudoVFMUL_VFPR16_M2_E16_MASK,
16134 0 : 2292 => Opcode::PseudoVFMUL_VFPR16_M4_E16,
16135 0 : 2293 => Opcode::PseudoVFMUL_VFPR16_M4_E16_MASK,
16136 0 : 2294 => Opcode::PseudoVFMUL_VFPR16_M8_E16,
16137 0 : 2295 => Opcode::PseudoVFMUL_VFPR16_M8_E16_MASK,
16138 0 : 2296 => Opcode::PseudoVFMUL_VFPR16_MF2_E16,
16139 0 : 2297 => Opcode::PseudoVFMUL_VFPR16_MF2_E16_MASK,
16140 0 : 2298 => Opcode::PseudoVFMUL_VFPR16_MF4_E16,
16141 0 : 2299 => Opcode::PseudoVFMUL_VFPR16_MF4_E16_MASK,
16142 0 : 2300 => Opcode::PseudoVFMUL_VFPR32_M1_E32,
16143 0 : 2301 => Opcode::PseudoVFMUL_VFPR32_M1_E32_MASK,
16144 0 : 2302 => Opcode::PseudoVFMUL_VFPR32_M2_E32,
16145 0 : 2303 => Opcode::PseudoVFMUL_VFPR32_M2_E32_MASK,
16146 0 : 2304 => Opcode::PseudoVFMUL_VFPR32_M4_E32,
16147 0 : 2305 => Opcode::PseudoVFMUL_VFPR32_M4_E32_MASK,
16148 0 : 2306 => Opcode::PseudoVFMUL_VFPR32_M8_E32,
16149 0 : 2307 => Opcode::PseudoVFMUL_VFPR32_M8_E32_MASK,
16150 0 : 2308 => Opcode::PseudoVFMUL_VFPR32_MF2_E32,
16151 0 : 2309 => Opcode::PseudoVFMUL_VFPR32_MF2_E32_MASK,
16152 0 : 2310 => Opcode::PseudoVFMUL_VFPR64_M1_E64,
16153 0 : 2311 => Opcode::PseudoVFMUL_VFPR64_M1_E64_MASK,
16154 0 : 2312 => Opcode::PseudoVFMUL_VFPR64_M2_E64,
16155 0 : 2313 => Opcode::PseudoVFMUL_VFPR64_M2_E64_MASK,
16156 0 : 2314 => Opcode::PseudoVFMUL_VFPR64_M4_E64,
16157 0 : 2315 => Opcode::PseudoVFMUL_VFPR64_M4_E64_MASK,
16158 0 : 2316 => Opcode::PseudoVFMUL_VFPR64_M8_E64,
16159 0 : 2317 => Opcode::PseudoVFMUL_VFPR64_M8_E64_MASK,
16160 0 : 2318 => Opcode::PseudoVFMUL_VV_M1_E16,
16161 0 : 2319 => Opcode::PseudoVFMUL_VV_M1_E16_MASK,
16162 0 : 2320 => Opcode::PseudoVFMUL_VV_M1_E32,
16163 0 : 2321 => Opcode::PseudoVFMUL_VV_M1_E32_MASK,
16164 0 : 2322 => Opcode::PseudoVFMUL_VV_M1_E64,
16165 0 : 2323 => Opcode::PseudoVFMUL_VV_M1_E64_MASK,
16166 0 : 2324 => Opcode::PseudoVFMUL_VV_M2_E16,
16167 0 : 2325 => Opcode::PseudoVFMUL_VV_M2_E16_MASK,
16168 0 : 2326 => Opcode::PseudoVFMUL_VV_M2_E32,
16169 0 : 2327 => Opcode::PseudoVFMUL_VV_M2_E32_MASK,
16170 0 : 2328 => Opcode::PseudoVFMUL_VV_M2_E64,
16171 0 : 2329 => Opcode::PseudoVFMUL_VV_M2_E64_MASK,
16172 0 : 2330 => Opcode::PseudoVFMUL_VV_M4_E16,
16173 0 : 2331 => Opcode::PseudoVFMUL_VV_M4_E16_MASK,
16174 0 : 2332 => Opcode::PseudoVFMUL_VV_M4_E32,
16175 0 : 2333 => Opcode::PseudoVFMUL_VV_M4_E32_MASK,
16176 0 : 2334 => Opcode::PseudoVFMUL_VV_M4_E64,
16177 0 : 2335 => Opcode::PseudoVFMUL_VV_M4_E64_MASK,
16178 0 : 2336 => Opcode::PseudoVFMUL_VV_M8_E16,
16179 0 : 2337 => Opcode::PseudoVFMUL_VV_M8_E16_MASK,
16180 0 : 2338 => Opcode::PseudoVFMUL_VV_M8_E32,
16181 0 : 2339 => Opcode::PseudoVFMUL_VV_M8_E32_MASK,
16182 0 : 2340 => Opcode::PseudoVFMUL_VV_M8_E64,
16183 0 : 2341 => Opcode::PseudoVFMUL_VV_M8_E64_MASK,
16184 0 : 2342 => Opcode::PseudoVFMUL_VV_MF2_E16,
16185 0 : 2343 => Opcode::PseudoVFMUL_VV_MF2_E16_MASK,
16186 0 : 2344 => Opcode::PseudoVFMUL_VV_MF2_E32,
16187 0 : 2345 => Opcode::PseudoVFMUL_VV_MF2_E32_MASK,
16188 0 : 2346 => Opcode::PseudoVFMUL_VV_MF4_E16,
16189 0 : 2347 => Opcode::PseudoVFMUL_VV_MF4_E16_MASK,
16190 0 : 2348 => Opcode::PseudoVFMV_FPR16_S_M1,
16191 0 : 2349 => Opcode::PseudoVFMV_FPR16_S_M2,
16192 0 : 2350 => Opcode::PseudoVFMV_FPR16_S_M4,
16193 0 : 2351 => Opcode::PseudoVFMV_FPR16_S_M8,
16194 0 : 2352 => Opcode::PseudoVFMV_FPR16_S_MF2,
16195 0 : 2353 => Opcode::PseudoVFMV_FPR16_S_MF4,
16196 0 : 2354 => Opcode::PseudoVFMV_FPR32_S_M1,
16197 0 : 2355 => Opcode::PseudoVFMV_FPR32_S_M2,
16198 0 : 2356 => Opcode::PseudoVFMV_FPR32_S_M4,
16199 0 : 2357 => Opcode::PseudoVFMV_FPR32_S_M8,
16200 0 : 2358 => Opcode::PseudoVFMV_FPR32_S_MF2,
16201 0 : 2359 => Opcode::PseudoVFMV_FPR64_S_M1,
16202 0 : 2360 => Opcode::PseudoVFMV_FPR64_S_M2,
16203 0 : 2361 => Opcode::PseudoVFMV_FPR64_S_M4,
16204 0 : 2362 => Opcode::PseudoVFMV_FPR64_S_M8,
16205 0 : 2363 => Opcode::PseudoVFMV_S_FPR16_M1,
16206 0 : 2364 => Opcode::PseudoVFMV_S_FPR16_M2,
16207 0 : 2365 => Opcode::PseudoVFMV_S_FPR16_M4,
16208 0 : 2366 => Opcode::PseudoVFMV_S_FPR16_M8,
16209 0 : 2367 => Opcode::PseudoVFMV_S_FPR16_MF2,
16210 0 : 2368 => Opcode::PseudoVFMV_S_FPR16_MF4,
16211 0 : 2369 => Opcode::PseudoVFMV_S_FPR32_M1,
16212 0 : 2370 => Opcode::PseudoVFMV_S_FPR32_M2,
16213 0 : 2371 => Opcode::PseudoVFMV_S_FPR32_M4,
16214 0 : 2372 => Opcode::PseudoVFMV_S_FPR32_M8,
16215 0 : 2373 => Opcode::PseudoVFMV_S_FPR32_MF2,
16216 0 : 2374 => Opcode::PseudoVFMV_S_FPR64_M1,
16217 0 : 2375 => Opcode::PseudoVFMV_S_FPR64_M2,
16218 0 : 2376 => Opcode::PseudoVFMV_S_FPR64_M4,
16219 0 : 2377 => Opcode::PseudoVFMV_S_FPR64_M8,
16220 0 : 2378 => Opcode::PseudoVFMV_V_FPR16_M1,
16221 0 : 2379 => Opcode::PseudoVFMV_V_FPR16_M2,
16222 0 : 2380 => Opcode::PseudoVFMV_V_FPR16_M4,
16223 0 : 2381 => Opcode::PseudoVFMV_V_FPR16_M8,
16224 0 : 2382 => Opcode::PseudoVFMV_V_FPR16_MF2,
16225 0 : 2383 => Opcode::PseudoVFMV_V_FPR16_MF4,
16226 0 : 2384 => Opcode::PseudoVFMV_V_FPR32_M1,
16227 0 : 2385 => Opcode::PseudoVFMV_V_FPR32_M2,
16228 0 : 2386 => Opcode::PseudoVFMV_V_FPR32_M4,
16229 0 : 2387 => Opcode::PseudoVFMV_V_FPR32_M8,
16230 0 : 2388 => Opcode::PseudoVFMV_V_FPR32_MF2,
16231 0 : 2389 => Opcode::PseudoVFMV_V_FPR64_M1,
16232 0 : 2390 => Opcode::PseudoVFMV_V_FPR64_M2,
16233 0 : 2391 => Opcode::PseudoVFMV_V_FPR64_M4,
16234 0 : 2392 => Opcode::PseudoVFMV_V_FPR64_M8,
16235 0 : 2393 => Opcode::PseudoVFNCVTBF16_F_F_W_M1_E16,
16236 0 : 2394 => Opcode::PseudoVFNCVTBF16_F_F_W_M1_E16_MASK,
16237 0 : 2395 => Opcode::PseudoVFNCVTBF16_F_F_W_M1_E32,
16238 0 : 2396 => Opcode::PseudoVFNCVTBF16_F_F_W_M1_E32_MASK,
16239 0 : 2397 => Opcode::PseudoVFNCVTBF16_F_F_W_M2_E16,
16240 0 : 2398 => Opcode::PseudoVFNCVTBF16_F_F_W_M2_E16_MASK,
16241 0 : 2399 => Opcode::PseudoVFNCVTBF16_F_F_W_M2_E32,
16242 0 : 2400 => Opcode::PseudoVFNCVTBF16_F_F_W_M2_E32_MASK,
16243 0 : 2401 => Opcode::PseudoVFNCVTBF16_F_F_W_M4_E16,
16244 0 : 2402 => Opcode::PseudoVFNCVTBF16_F_F_W_M4_E16_MASK,
16245 0 : 2403 => Opcode::PseudoVFNCVTBF16_F_F_W_M4_E32,
16246 0 : 2404 => Opcode::PseudoVFNCVTBF16_F_F_W_M4_E32_MASK,
16247 0 : 2405 => Opcode::PseudoVFNCVTBF16_F_F_W_MF2_E16,
16248 0 : 2406 => Opcode::PseudoVFNCVTBF16_F_F_W_MF2_E16_MASK,
16249 0 : 2407 => Opcode::PseudoVFNCVTBF16_F_F_W_MF2_E32,
16250 0 : 2408 => Opcode::PseudoVFNCVTBF16_F_F_W_MF2_E32_MASK,
16251 0 : 2409 => Opcode::PseudoVFNCVTBF16_F_F_W_MF4_E16,
16252 0 : 2410 => Opcode::PseudoVFNCVTBF16_F_F_W_MF4_E16_MASK,
16253 0 : 2411 => Opcode::PseudoVFNCVT_F_F_W_M1_E16,
16254 0 : 2412 => Opcode::PseudoVFNCVT_F_F_W_M1_E16_MASK,
16255 0 : 2413 => Opcode::PseudoVFNCVT_F_F_W_M1_E32,
16256 0 : 2414 => Opcode::PseudoVFNCVT_F_F_W_M1_E32_MASK,
16257 0 : 2415 => Opcode::PseudoVFNCVT_F_F_W_M2_E16,
16258 0 : 2416 => Opcode::PseudoVFNCVT_F_F_W_M2_E16_MASK,
16259 0 : 2417 => Opcode::PseudoVFNCVT_F_F_W_M2_E32,
16260 0 : 2418 => Opcode::PseudoVFNCVT_F_F_W_M2_E32_MASK,
16261 0 : 2419 => Opcode::PseudoVFNCVT_F_F_W_M4_E16,
16262 0 : 2420 => Opcode::PseudoVFNCVT_F_F_W_M4_E16_MASK,
16263 0 : 2421 => Opcode::PseudoVFNCVT_F_F_W_M4_E32,
16264 0 : 2422 => Opcode::PseudoVFNCVT_F_F_W_M4_E32_MASK,
16265 0 : 2423 => Opcode::PseudoVFNCVT_F_F_W_MF2_E16,
16266 0 : 2424 => Opcode::PseudoVFNCVT_F_F_W_MF2_E16_MASK,
16267 0 : 2425 => Opcode::PseudoVFNCVT_F_F_W_MF2_E32,
16268 0 : 2426 => Opcode::PseudoVFNCVT_F_F_W_MF2_E32_MASK,
16269 0 : 2427 => Opcode::PseudoVFNCVT_F_F_W_MF4_E16,
16270 0 : 2428 => Opcode::PseudoVFNCVT_F_F_W_MF4_E16_MASK,
16271 0 : 2429 => Opcode::PseudoVFNCVT_F_XU_W_M1_E16,
16272 0 : 2430 => Opcode::PseudoVFNCVT_F_XU_W_M1_E16_MASK,
16273 0 : 2431 => Opcode::PseudoVFNCVT_F_XU_W_M1_E32,
16274 0 : 2432 => Opcode::PseudoVFNCVT_F_XU_W_M1_E32_MASK,
16275 0 : 2433 => Opcode::PseudoVFNCVT_F_XU_W_M2_E16,
16276 0 : 2434 => Opcode::PseudoVFNCVT_F_XU_W_M2_E16_MASK,
16277 0 : 2435 => Opcode::PseudoVFNCVT_F_XU_W_M2_E32,
16278 0 : 2436 => Opcode::PseudoVFNCVT_F_XU_W_M2_E32_MASK,
16279 0 : 2437 => Opcode::PseudoVFNCVT_F_XU_W_M4_E16,
16280 0 : 2438 => Opcode::PseudoVFNCVT_F_XU_W_M4_E16_MASK,
16281 0 : 2439 => Opcode::PseudoVFNCVT_F_XU_W_M4_E32,
16282 0 : 2440 => Opcode::PseudoVFNCVT_F_XU_W_M4_E32_MASK,
16283 0 : 2441 => Opcode::PseudoVFNCVT_F_XU_W_MF2_E16,
16284 0 : 2442 => Opcode::PseudoVFNCVT_F_XU_W_MF2_E16_MASK,
16285 0 : 2443 => Opcode::PseudoVFNCVT_F_XU_W_MF2_E32,
16286 0 : 2444 => Opcode::PseudoVFNCVT_F_XU_W_MF2_E32_MASK,
16287 0 : 2445 => Opcode::PseudoVFNCVT_F_XU_W_MF4_E16,
16288 0 : 2446 => Opcode::PseudoVFNCVT_F_XU_W_MF4_E16_MASK,
16289 0 : 2447 => Opcode::PseudoVFNCVT_F_X_W_M1_E16,
16290 0 : 2448 => Opcode::PseudoVFNCVT_F_X_W_M1_E16_MASK,
16291 0 : 2449 => Opcode::PseudoVFNCVT_F_X_W_M1_E32,
16292 0 : 2450 => Opcode::PseudoVFNCVT_F_X_W_M1_E32_MASK,
16293 0 : 2451 => Opcode::PseudoVFNCVT_F_X_W_M2_E16,
16294 0 : 2452 => Opcode::PseudoVFNCVT_F_X_W_M2_E16_MASK,
16295 0 : 2453 => Opcode::PseudoVFNCVT_F_X_W_M2_E32,
16296 0 : 2454 => Opcode::PseudoVFNCVT_F_X_W_M2_E32_MASK,
16297 0 : 2455 => Opcode::PseudoVFNCVT_F_X_W_M4_E16,
16298 0 : 2456 => Opcode::PseudoVFNCVT_F_X_W_M4_E16_MASK,
16299 0 : 2457 => Opcode::PseudoVFNCVT_F_X_W_M4_E32,
16300 0 : 2458 => Opcode::PseudoVFNCVT_F_X_W_M4_E32_MASK,
16301 0 : 2459 => Opcode::PseudoVFNCVT_F_X_W_MF2_E16,
16302 0 : 2460 => Opcode::PseudoVFNCVT_F_X_W_MF2_E16_MASK,
16303 0 : 2461 => Opcode::PseudoVFNCVT_F_X_W_MF2_E32,
16304 0 : 2462 => Opcode::PseudoVFNCVT_F_X_W_MF2_E32_MASK,
16305 0 : 2463 => Opcode::PseudoVFNCVT_F_X_W_MF4_E16,
16306 0 : 2464 => Opcode::PseudoVFNCVT_F_X_W_MF4_E16_MASK,
16307 0 : 2465 => Opcode::PseudoVFNCVT_RM_F_XU_W_M1_E16,
16308 0 : 2466 => Opcode::PseudoVFNCVT_RM_F_XU_W_M1_E16_MASK,
16309 0 : 2467 => Opcode::PseudoVFNCVT_RM_F_XU_W_M1_E32,
16310 0 : 2468 => Opcode::PseudoVFNCVT_RM_F_XU_W_M1_E32_MASK,
16311 0 : 2469 => Opcode::PseudoVFNCVT_RM_F_XU_W_M2_E16,
16312 0 : 2470 => Opcode::PseudoVFNCVT_RM_F_XU_W_M2_E16_MASK,
16313 0 : 2471 => Opcode::PseudoVFNCVT_RM_F_XU_W_M2_E32,
16314 0 : 2472 => Opcode::PseudoVFNCVT_RM_F_XU_W_M2_E32_MASK,
16315 0 : 2473 => Opcode::PseudoVFNCVT_RM_F_XU_W_M4_E16,
16316 0 : 2474 => Opcode::PseudoVFNCVT_RM_F_XU_W_M4_E16_MASK,
16317 0 : 2475 => Opcode::PseudoVFNCVT_RM_F_XU_W_M4_E32,
16318 0 : 2476 => Opcode::PseudoVFNCVT_RM_F_XU_W_M4_E32_MASK,
16319 0 : 2477 => Opcode::PseudoVFNCVT_RM_F_XU_W_MF2_E16,
16320 0 : 2478 => Opcode::PseudoVFNCVT_RM_F_XU_W_MF2_E16_MASK,
16321 0 : 2479 => Opcode::PseudoVFNCVT_RM_F_XU_W_MF2_E32,
16322 0 : 2480 => Opcode::PseudoVFNCVT_RM_F_XU_W_MF2_E32_MASK,
16323 0 : 2481 => Opcode::PseudoVFNCVT_RM_F_XU_W_MF4_E16,
16324 0 : 2482 => Opcode::PseudoVFNCVT_RM_F_XU_W_MF4_E16_MASK,
16325 0 : 2483 => Opcode::PseudoVFNCVT_RM_F_X_W_M1_E16,
16326 0 : 2484 => Opcode::PseudoVFNCVT_RM_F_X_W_M1_E16_MASK,
16327 0 : 2485 => Opcode::PseudoVFNCVT_RM_F_X_W_M1_E32,
16328 0 : 2486 => Opcode::PseudoVFNCVT_RM_F_X_W_M1_E32_MASK,
16329 0 : 2487 => Opcode::PseudoVFNCVT_RM_F_X_W_M2_E16,
16330 0 : 2488 => Opcode::PseudoVFNCVT_RM_F_X_W_M2_E16_MASK,
16331 0 : 2489 => Opcode::PseudoVFNCVT_RM_F_X_W_M2_E32,
16332 0 : 2490 => Opcode::PseudoVFNCVT_RM_F_X_W_M2_E32_MASK,
16333 0 : 2491 => Opcode::PseudoVFNCVT_RM_F_X_W_M4_E16,
16334 0 : 2492 => Opcode::PseudoVFNCVT_RM_F_X_W_M4_E16_MASK,
16335 0 : 2493 => Opcode::PseudoVFNCVT_RM_F_X_W_M4_E32,
16336 0 : 2494 => Opcode::PseudoVFNCVT_RM_F_X_W_M4_E32_MASK,
16337 0 : 2495 => Opcode::PseudoVFNCVT_RM_F_X_W_MF2_E16,
16338 0 : 2496 => Opcode::PseudoVFNCVT_RM_F_X_W_MF2_E16_MASK,
16339 0 : 2497 => Opcode::PseudoVFNCVT_RM_F_X_W_MF2_E32,
16340 0 : 2498 => Opcode::PseudoVFNCVT_RM_F_X_W_MF2_E32_MASK,
16341 0 : 2499 => Opcode::PseudoVFNCVT_RM_F_X_W_MF4_E16,
16342 0 : 2500 => Opcode::PseudoVFNCVT_RM_F_X_W_MF4_E16_MASK,
16343 0 : 2501 => Opcode::PseudoVFNCVT_RM_XU_F_W_M1,
16344 0 : 2502 => Opcode::PseudoVFNCVT_RM_XU_F_W_M1_MASK,
16345 0 : 2503 => Opcode::PseudoVFNCVT_RM_XU_F_W_M2,
16346 0 : 2504 => Opcode::PseudoVFNCVT_RM_XU_F_W_M2_MASK,
16347 0 : 2505 => Opcode::PseudoVFNCVT_RM_XU_F_W_M4,
16348 0 : 2506 => Opcode::PseudoVFNCVT_RM_XU_F_W_M4_MASK,
16349 0 : 2507 => Opcode::PseudoVFNCVT_RM_XU_F_W_MF2,
16350 0 : 2508 => Opcode::PseudoVFNCVT_RM_XU_F_W_MF2_MASK,
16351 0 : 2509 => Opcode::PseudoVFNCVT_RM_XU_F_W_MF4,
16352 0 : 2510 => Opcode::PseudoVFNCVT_RM_XU_F_W_MF4_MASK,
16353 0 : 2511 => Opcode::PseudoVFNCVT_RM_XU_F_W_MF8,
16354 0 : 2512 => Opcode::PseudoVFNCVT_RM_XU_F_W_MF8_MASK,
16355 0 : 2513 => Opcode::PseudoVFNCVT_RM_X_F_W_M1,
16356 0 : 2514 => Opcode::PseudoVFNCVT_RM_X_F_W_M1_MASK,
16357 0 : 2515 => Opcode::PseudoVFNCVT_RM_X_F_W_M2,
16358 0 : 2516 => Opcode::PseudoVFNCVT_RM_X_F_W_M2_MASK,
16359 0 : 2517 => Opcode::PseudoVFNCVT_RM_X_F_W_M4,
16360 0 : 2518 => Opcode::PseudoVFNCVT_RM_X_F_W_M4_MASK,
16361 0 : 2519 => Opcode::PseudoVFNCVT_RM_X_F_W_MF2,
16362 0 : 2520 => Opcode::PseudoVFNCVT_RM_X_F_W_MF2_MASK,
16363 0 : 2521 => Opcode::PseudoVFNCVT_RM_X_F_W_MF4,
16364 0 : 2522 => Opcode::PseudoVFNCVT_RM_X_F_W_MF4_MASK,
16365 0 : 2523 => Opcode::PseudoVFNCVT_RM_X_F_W_MF8,
16366 0 : 2524 => Opcode::PseudoVFNCVT_RM_X_F_W_MF8_MASK,
16367 0 : 2525 => Opcode::PseudoVFNCVT_ROD_F_F_W_M1_E16,
16368 0 : 2526 => Opcode::PseudoVFNCVT_ROD_F_F_W_M1_E16_MASK,
16369 0 : 2527 => Opcode::PseudoVFNCVT_ROD_F_F_W_M1_E32,
16370 0 : 2528 => Opcode::PseudoVFNCVT_ROD_F_F_W_M1_E32_MASK,
16371 0 : 2529 => Opcode::PseudoVFNCVT_ROD_F_F_W_M2_E16,
16372 0 : 2530 => Opcode::PseudoVFNCVT_ROD_F_F_W_M2_E16_MASK,
16373 0 : 2531 => Opcode::PseudoVFNCVT_ROD_F_F_W_M2_E32,
16374 0 : 2532 => Opcode::PseudoVFNCVT_ROD_F_F_W_M2_E32_MASK,
16375 0 : 2533 => Opcode::PseudoVFNCVT_ROD_F_F_W_M4_E16,
16376 0 : 2534 => Opcode::PseudoVFNCVT_ROD_F_F_W_M4_E16_MASK,
16377 0 : 2535 => Opcode::PseudoVFNCVT_ROD_F_F_W_M4_E32,
16378 0 : 2536 => Opcode::PseudoVFNCVT_ROD_F_F_W_M4_E32_MASK,
16379 0 : 2537 => Opcode::PseudoVFNCVT_ROD_F_F_W_MF2_E16,
16380 0 : 2538 => Opcode::PseudoVFNCVT_ROD_F_F_W_MF2_E16_MASK,
16381 0 : 2539 => Opcode::PseudoVFNCVT_ROD_F_F_W_MF2_E32,
16382 0 : 2540 => Opcode::PseudoVFNCVT_ROD_F_F_W_MF2_E32_MASK,
16383 0 : 2541 => Opcode::PseudoVFNCVT_ROD_F_F_W_MF4_E16,
16384 0 : 2542 => Opcode::PseudoVFNCVT_ROD_F_F_W_MF4_E16_MASK,
16385 0 : 2543 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_M1,
16386 0 : 2544 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_M1_MASK,
16387 0 : 2545 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_M2,
16388 0 : 2546 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_M2_MASK,
16389 0 : 2547 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_M4,
16390 0 : 2548 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_M4_MASK,
16391 0 : 2549 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_MF2,
16392 0 : 2550 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK,
16393 0 : 2551 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_MF4,
16394 0 : 2552 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK,
16395 0 : 2553 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_MF8,
16396 0 : 2554 => Opcode::PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK,
16397 0 : 2555 => Opcode::PseudoVFNCVT_RTZ_X_F_W_M1,
16398 0 : 2556 => Opcode::PseudoVFNCVT_RTZ_X_F_W_M1_MASK,
16399 0 : 2557 => Opcode::PseudoVFNCVT_RTZ_X_F_W_M2,
16400 0 : 2558 => Opcode::PseudoVFNCVT_RTZ_X_F_W_M2_MASK,
16401 0 : 2559 => Opcode::PseudoVFNCVT_RTZ_X_F_W_M4,
16402 0 : 2560 => Opcode::PseudoVFNCVT_RTZ_X_F_W_M4_MASK,
16403 0 : 2561 => Opcode::PseudoVFNCVT_RTZ_X_F_W_MF2,
16404 0 : 2562 => Opcode::PseudoVFNCVT_RTZ_X_F_W_MF2_MASK,
16405 0 : 2563 => Opcode::PseudoVFNCVT_RTZ_X_F_W_MF4,
16406 0 : 2564 => Opcode::PseudoVFNCVT_RTZ_X_F_W_MF4_MASK,
16407 0 : 2565 => Opcode::PseudoVFNCVT_RTZ_X_F_W_MF8,
16408 0 : 2566 => Opcode::PseudoVFNCVT_RTZ_X_F_W_MF8_MASK,
16409 0 : 2567 => Opcode::PseudoVFNCVT_XU_F_W_M1,
16410 0 : 2568 => Opcode::PseudoVFNCVT_XU_F_W_M1_MASK,
16411 0 : 2569 => Opcode::PseudoVFNCVT_XU_F_W_M2,
16412 0 : 2570 => Opcode::PseudoVFNCVT_XU_F_W_M2_MASK,
16413 0 : 2571 => Opcode::PseudoVFNCVT_XU_F_W_M4,
16414 0 : 2572 => Opcode::PseudoVFNCVT_XU_F_W_M4_MASK,
16415 0 : 2573 => Opcode::PseudoVFNCVT_XU_F_W_MF2,
16416 0 : 2574 => Opcode::PseudoVFNCVT_XU_F_W_MF2_MASK,
16417 0 : 2575 => Opcode::PseudoVFNCVT_XU_F_W_MF4,
16418 0 : 2576 => Opcode::PseudoVFNCVT_XU_F_W_MF4_MASK,
16419 0 : 2577 => Opcode::PseudoVFNCVT_XU_F_W_MF8,
16420 0 : 2578 => Opcode::PseudoVFNCVT_XU_F_W_MF8_MASK,
16421 0 : 2579 => Opcode::PseudoVFNCVT_X_F_W_M1,
16422 0 : 2580 => Opcode::PseudoVFNCVT_X_F_W_M1_MASK,
16423 0 : 2581 => Opcode::PseudoVFNCVT_X_F_W_M2,
16424 0 : 2582 => Opcode::PseudoVFNCVT_X_F_W_M2_MASK,
16425 0 : 2583 => Opcode::PseudoVFNCVT_X_F_W_M4,
16426 0 : 2584 => Opcode::PseudoVFNCVT_X_F_W_M4_MASK,
16427 0 : 2585 => Opcode::PseudoVFNCVT_X_F_W_MF2,
16428 0 : 2586 => Opcode::PseudoVFNCVT_X_F_W_MF2_MASK,
16429 0 : 2587 => Opcode::PseudoVFNCVT_X_F_W_MF4,
16430 0 : 2588 => Opcode::PseudoVFNCVT_X_F_W_MF4_MASK,
16431 0 : 2589 => Opcode::PseudoVFNCVT_X_F_W_MF8,
16432 0 : 2590 => Opcode::PseudoVFNCVT_X_F_W_MF8_MASK,
16433 0 : 2591 => Opcode::PseudoVFNMACC_VFPR16_M1_E16,
16434 0 : 2592 => Opcode::PseudoVFNMACC_VFPR16_M1_E16_MASK,
16435 0 : 2593 => Opcode::PseudoVFNMACC_VFPR16_M2_E16,
16436 0 : 2594 => Opcode::PseudoVFNMACC_VFPR16_M2_E16_MASK,
16437 0 : 2595 => Opcode::PseudoVFNMACC_VFPR16_M4_E16,
16438 0 : 2596 => Opcode::PseudoVFNMACC_VFPR16_M4_E16_MASK,
16439 0 : 2597 => Opcode::PseudoVFNMACC_VFPR16_M8_E16,
16440 0 : 2598 => Opcode::PseudoVFNMACC_VFPR16_M8_E16_MASK,
16441 0 : 2599 => Opcode::PseudoVFNMACC_VFPR16_MF2_E16,
16442 0 : 2600 => Opcode::PseudoVFNMACC_VFPR16_MF2_E16_MASK,
16443 0 : 2601 => Opcode::PseudoVFNMACC_VFPR16_MF4_E16,
16444 0 : 2602 => Opcode::PseudoVFNMACC_VFPR16_MF4_E16_MASK,
16445 0 : 2603 => Opcode::PseudoVFNMACC_VFPR32_M1_E32,
16446 0 : 2604 => Opcode::PseudoVFNMACC_VFPR32_M1_E32_MASK,
16447 0 : 2605 => Opcode::PseudoVFNMACC_VFPR32_M2_E32,
16448 0 : 2606 => Opcode::PseudoVFNMACC_VFPR32_M2_E32_MASK,
16449 0 : 2607 => Opcode::PseudoVFNMACC_VFPR32_M4_E32,
16450 0 : 2608 => Opcode::PseudoVFNMACC_VFPR32_M4_E32_MASK,
16451 0 : 2609 => Opcode::PseudoVFNMACC_VFPR32_M8_E32,
16452 0 : 2610 => Opcode::PseudoVFNMACC_VFPR32_M8_E32_MASK,
16453 0 : 2611 => Opcode::PseudoVFNMACC_VFPR32_MF2_E32,
16454 0 : 2612 => Opcode::PseudoVFNMACC_VFPR32_MF2_E32_MASK,
16455 0 : 2613 => Opcode::PseudoVFNMACC_VFPR64_M1_E64,
16456 0 : 2614 => Opcode::PseudoVFNMACC_VFPR64_M1_E64_MASK,
16457 0 : 2615 => Opcode::PseudoVFNMACC_VFPR64_M2_E64,
16458 0 : 2616 => Opcode::PseudoVFNMACC_VFPR64_M2_E64_MASK,
16459 0 : 2617 => Opcode::PseudoVFNMACC_VFPR64_M4_E64,
16460 0 : 2618 => Opcode::PseudoVFNMACC_VFPR64_M4_E64_MASK,
16461 0 : 2619 => Opcode::PseudoVFNMACC_VFPR64_M8_E64,
16462 0 : 2620 => Opcode::PseudoVFNMACC_VFPR64_M8_E64_MASK,
16463 0 : 2621 => Opcode::PseudoVFNMACC_VV_M1_E16,
16464 0 : 2622 => Opcode::PseudoVFNMACC_VV_M1_E16_MASK,
16465 0 : 2623 => Opcode::PseudoVFNMACC_VV_M1_E32,
16466 0 : 2624 => Opcode::PseudoVFNMACC_VV_M1_E32_MASK,
16467 0 : 2625 => Opcode::PseudoVFNMACC_VV_M1_E64,
16468 0 : 2626 => Opcode::PseudoVFNMACC_VV_M1_E64_MASK,
16469 0 : 2627 => Opcode::PseudoVFNMACC_VV_M2_E16,
16470 0 : 2628 => Opcode::PseudoVFNMACC_VV_M2_E16_MASK,
16471 0 : 2629 => Opcode::PseudoVFNMACC_VV_M2_E32,
16472 0 : 2630 => Opcode::PseudoVFNMACC_VV_M2_E32_MASK,
16473 0 : 2631 => Opcode::PseudoVFNMACC_VV_M2_E64,
16474 0 : 2632 => Opcode::PseudoVFNMACC_VV_M2_E64_MASK,
16475 0 : 2633 => Opcode::PseudoVFNMACC_VV_M4_E16,
16476 0 : 2634 => Opcode::PseudoVFNMACC_VV_M4_E16_MASK,
16477 0 : 2635 => Opcode::PseudoVFNMACC_VV_M4_E32,
16478 0 : 2636 => Opcode::PseudoVFNMACC_VV_M4_E32_MASK,
16479 0 : 2637 => Opcode::PseudoVFNMACC_VV_M4_E64,
16480 0 : 2638 => Opcode::PseudoVFNMACC_VV_M4_E64_MASK,
16481 0 : 2639 => Opcode::PseudoVFNMACC_VV_M8_E16,
16482 0 : 2640 => Opcode::PseudoVFNMACC_VV_M8_E16_MASK,
16483 0 : 2641 => Opcode::PseudoVFNMACC_VV_M8_E32,
16484 0 : 2642 => Opcode::PseudoVFNMACC_VV_M8_E32_MASK,
16485 0 : 2643 => Opcode::PseudoVFNMACC_VV_M8_E64,
16486 0 : 2644 => Opcode::PseudoVFNMACC_VV_M8_E64_MASK,
16487 0 : 2645 => Opcode::PseudoVFNMACC_VV_MF2_E16,
16488 0 : 2646 => Opcode::PseudoVFNMACC_VV_MF2_E16_MASK,
16489 0 : 2647 => Opcode::PseudoVFNMACC_VV_MF2_E32,
16490 0 : 2648 => Opcode::PseudoVFNMACC_VV_MF2_E32_MASK,
16491 0 : 2649 => Opcode::PseudoVFNMACC_VV_MF4_E16,
16492 0 : 2650 => Opcode::PseudoVFNMACC_VV_MF4_E16_MASK,
16493 0 : 2651 => Opcode::PseudoVFNMADD_VFPR16_M1_E16,
16494 0 : 2652 => Opcode::PseudoVFNMADD_VFPR16_M1_E16_MASK,
16495 0 : 2653 => Opcode::PseudoVFNMADD_VFPR16_M2_E16,
16496 0 : 2654 => Opcode::PseudoVFNMADD_VFPR16_M2_E16_MASK,
16497 0 : 2655 => Opcode::PseudoVFNMADD_VFPR16_M4_E16,
16498 0 : 2656 => Opcode::PseudoVFNMADD_VFPR16_M4_E16_MASK,
16499 0 : 2657 => Opcode::PseudoVFNMADD_VFPR16_M8_E16,
16500 0 : 2658 => Opcode::PseudoVFNMADD_VFPR16_M8_E16_MASK,
16501 0 : 2659 => Opcode::PseudoVFNMADD_VFPR16_MF2_E16,
16502 0 : 2660 => Opcode::PseudoVFNMADD_VFPR16_MF2_E16_MASK,
16503 0 : 2661 => Opcode::PseudoVFNMADD_VFPR16_MF4_E16,
16504 0 : 2662 => Opcode::PseudoVFNMADD_VFPR16_MF4_E16_MASK,
16505 0 : 2663 => Opcode::PseudoVFNMADD_VFPR32_M1_E32,
16506 0 : 2664 => Opcode::PseudoVFNMADD_VFPR32_M1_E32_MASK,
16507 0 : 2665 => Opcode::PseudoVFNMADD_VFPR32_M2_E32,
16508 0 : 2666 => Opcode::PseudoVFNMADD_VFPR32_M2_E32_MASK,
16509 0 : 2667 => Opcode::PseudoVFNMADD_VFPR32_M4_E32,
16510 0 : 2668 => Opcode::PseudoVFNMADD_VFPR32_M4_E32_MASK,
16511 0 : 2669 => Opcode::PseudoVFNMADD_VFPR32_M8_E32,
16512 0 : 2670 => Opcode::PseudoVFNMADD_VFPR32_M8_E32_MASK,
16513 0 : 2671 => Opcode::PseudoVFNMADD_VFPR32_MF2_E32,
16514 0 : 2672 => Opcode::PseudoVFNMADD_VFPR32_MF2_E32_MASK,
16515 0 : 2673 => Opcode::PseudoVFNMADD_VFPR64_M1_E64,
16516 0 : 2674 => Opcode::PseudoVFNMADD_VFPR64_M1_E64_MASK,
16517 0 : 2675 => Opcode::PseudoVFNMADD_VFPR64_M2_E64,
16518 0 : 2676 => Opcode::PseudoVFNMADD_VFPR64_M2_E64_MASK,
16519 0 : 2677 => Opcode::PseudoVFNMADD_VFPR64_M4_E64,
16520 0 : 2678 => Opcode::PseudoVFNMADD_VFPR64_M4_E64_MASK,
16521 0 : 2679 => Opcode::PseudoVFNMADD_VFPR64_M8_E64,
16522 0 : 2680 => Opcode::PseudoVFNMADD_VFPR64_M8_E64_MASK,
16523 0 : 2681 => Opcode::PseudoVFNMADD_VV_M1_E16,
16524 0 : 2682 => Opcode::PseudoVFNMADD_VV_M1_E16_MASK,
16525 0 : 2683 => Opcode::PseudoVFNMADD_VV_M1_E32,
16526 0 : 2684 => Opcode::PseudoVFNMADD_VV_M1_E32_MASK,
16527 0 : 2685 => Opcode::PseudoVFNMADD_VV_M1_E64,
16528 0 : 2686 => Opcode::PseudoVFNMADD_VV_M1_E64_MASK,
16529 0 : 2687 => Opcode::PseudoVFNMADD_VV_M2_E16,
16530 0 : 2688 => Opcode::PseudoVFNMADD_VV_M2_E16_MASK,
16531 0 : 2689 => Opcode::PseudoVFNMADD_VV_M2_E32,
16532 0 : 2690 => Opcode::PseudoVFNMADD_VV_M2_E32_MASK,
16533 0 : 2691 => Opcode::PseudoVFNMADD_VV_M2_E64,
16534 0 : 2692 => Opcode::PseudoVFNMADD_VV_M2_E64_MASK,
16535 0 : 2693 => Opcode::PseudoVFNMADD_VV_M4_E16,
16536 0 : 2694 => Opcode::PseudoVFNMADD_VV_M4_E16_MASK,
16537 0 : 2695 => Opcode::PseudoVFNMADD_VV_M4_E32,
16538 0 : 2696 => Opcode::PseudoVFNMADD_VV_M4_E32_MASK,
16539 0 : 2697 => Opcode::PseudoVFNMADD_VV_M4_E64,
16540 0 : 2698 => Opcode::PseudoVFNMADD_VV_M4_E64_MASK,
16541 0 : 2699 => Opcode::PseudoVFNMADD_VV_M8_E16,
16542 0 : 2700 => Opcode::PseudoVFNMADD_VV_M8_E16_MASK,
16543 0 : 2701 => Opcode::PseudoVFNMADD_VV_M8_E32,
16544 0 : 2702 => Opcode::PseudoVFNMADD_VV_M8_E32_MASK,
16545 0 : 2703 => Opcode::PseudoVFNMADD_VV_M8_E64,
16546 0 : 2704 => Opcode::PseudoVFNMADD_VV_M8_E64_MASK,
16547 0 : 2705 => Opcode::PseudoVFNMADD_VV_MF2_E16,
16548 0 : 2706 => Opcode::PseudoVFNMADD_VV_MF2_E16_MASK,
16549 0 : 2707 => Opcode::PseudoVFNMADD_VV_MF2_E32,
16550 0 : 2708 => Opcode::PseudoVFNMADD_VV_MF2_E32_MASK,
16551 0 : 2709 => Opcode::PseudoVFNMADD_VV_MF4_E16,
16552 0 : 2710 => Opcode::PseudoVFNMADD_VV_MF4_E16_MASK,
16553 0 : 2711 => Opcode::PseudoVFNMSAC_VFPR16_M1_E16,
16554 0 : 2712 => Opcode::PseudoVFNMSAC_VFPR16_M1_E16_MASK,
16555 0 : 2713 => Opcode::PseudoVFNMSAC_VFPR16_M2_E16,
16556 0 : 2714 => Opcode::PseudoVFNMSAC_VFPR16_M2_E16_MASK,
16557 0 : 2715 => Opcode::PseudoVFNMSAC_VFPR16_M4_E16,
16558 0 : 2716 => Opcode::PseudoVFNMSAC_VFPR16_M4_E16_MASK,
16559 0 : 2717 => Opcode::PseudoVFNMSAC_VFPR16_M8_E16,
16560 0 : 2718 => Opcode::PseudoVFNMSAC_VFPR16_M8_E16_MASK,
16561 0 : 2719 => Opcode::PseudoVFNMSAC_VFPR16_MF2_E16,
16562 0 : 2720 => Opcode::PseudoVFNMSAC_VFPR16_MF2_E16_MASK,
16563 0 : 2721 => Opcode::PseudoVFNMSAC_VFPR16_MF4_E16,
16564 0 : 2722 => Opcode::PseudoVFNMSAC_VFPR16_MF4_E16_MASK,
16565 0 : 2723 => Opcode::PseudoVFNMSAC_VFPR32_M1_E32,
16566 0 : 2724 => Opcode::PseudoVFNMSAC_VFPR32_M1_E32_MASK,
16567 0 : 2725 => Opcode::PseudoVFNMSAC_VFPR32_M2_E32,
16568 0 : 2726 => Opcode::PseudoVFNMSAC_VFPR32_M2_E32_MASK,
16569 0 : 2727 => Opcode::PseudoVFNMSAC_VFPR32_M4_E32,
16570 0 : 2728 => Opcode::PseudoVFNMSAC_VFPR32_M4_E32_MASK,
16571 0 : 2729 => Opcode::PseudoVFNMSAC_VFPR32_M8_E32,
16572 0 : 2730 => Opcode::PseudoVFNMSAC_VFPR32_M8_E32_MASK,
16573 0 : 2731 => Opcode::PseudoVFNMSAC_VFPR32_MF2_E32,
16574 0 : 2732 => Opcode::PseudoVFNMSAC_VFPR32_MF2_E32_MASK,
16575 0 : 2733 => Opcode::PseudoVFNMSAC_VFPR64_M1_E64,
16576 0 : 2734 => Opcode::PseudoVFNMSAC_VFPR64_M1_E64_MASK,
16577 0 : 2735 => Opcode::PseudoVFNMSAC_VFPR64_M2_E64,
16578 0 : 2736 => Opcode::PseudoVFNMSAC_VFPR64_M2_E64_MASK,
16579 0 : 2737 => Opcode::PseudoVFNMSAC_VFPR64_M4_E64,
16580 0 : 2738 => Opcode::PseudoVFNMSAC_VFPR64_M4_E64_MASK,
16581 0 : 2739 => Opcode::PseudoVFNMSAC_VFPR64_M8_E64,
16582 0 : 2740 => Opcode::PseudoVFNMSAC_VFPR64_M8_E64_MASK,
16583 0 : 2741 => Opcode::PseudoVFNMSAC_VV_M1_E16,
16584 0 : 2742 => Opcode::PseudoVFNMSAC_VV_M1_E16_MASK,
16585 0 : 2743 => Opcode::PseudoVFNMSAC_VV_M1_E32,
16586 0 : 2744 => Opcode::PseudoVFNMSAC_VV_M1_E32_MASK,
16587 0 : 2745 => Opcode::PseudoVFNMSAC_VV_M1_E64,
16588 0 : 2746 => Opcode::PseudoVFNMSAC_VV_M1_E64_MASK,
16589 0 : 2747 => Opcode::PseudoVFNMSAC_VV_M2_E16,
16590 0 : 2748 => Opcode::PseudoVFNMSAC_VV_M2_E16_MASK,
16591 0 : 2749 => Opcode::PseudoVFNMSAC_VV_M2_E32,
16592 0 : 2750 => Opcode::PseudoVFNMSAC_VV_M2_E32_MASK,
16593 0 : 2751 => Opcode::PseudoVFNMSAC_VV_M2_E64,
16594 0 : 2752 => Opcode::PseudoVFNMSAC_VV_M2_E64_MASK,
16595 0 : 2753 => Opcode::PseudoVFNMSAC_VV_M4_E16,
16596 0 : 2754 => Opcode::PseudoVFNMSAC_VV_M4_E16_MASK,
16597 0 : 2755 => Opcode::PseudoVFNMSAC_VV_M4_E32,
16598 0 : 2756 => Opcode::PseudoVFNMSAC_VV_M4_E32_MASK,
16599 0 : 2757 => Opcode::PseudoVFNMSAC_VV_M4_E64,
16600 0 : 2758 => Opcode::PseudoVFNMSAC_VV_M4_E64_MASK,
16601 0 : 2759 => Opcode::PseudoVFNMSAC_VV_M8_E16,
16602 0 : 2760 => Opcode::PseudoVFNMSAC_VV_M8_E16_MASK,
16603 0 : 2761 => Opcode::PseudoVFNMSAC_VV_M8_E32,
16604 0 : 2762 => Opcode::PseudoVFNMSAC_VV_M8_E32_MASK,
16605 0 : 2763 => Opcode::PseudoVFNMSAC_VV_M8_E64,
16606 0 : 2764 => Opcode::PseudoVFNMSAC_VV_M8_E64_MASK,
16607 0 : 2765 => Opcode::PseudoVFNMSAC_VV_MF2_E16,
16608 0 : 2766 => Opcode::PseudoVFNMSAC_VV_MF2_E16_MASK,
16609 0 : 2767 => Opcode::PseudoVFNMSAC_VV_MF2_E32,
16610 0 : 2768 => Opcode::PseudoVFNMSAC_VV_MF2_E32_MASK,
16611 0 : 2769 => Opcode::PseudoVFNMSAC_VV_MF4_E16,
16612 0 : 2770 => Opcode::PseudoVFNMSAC_VV_MF4_E16_MASK,
16613 0 : 2771 => Opcode::PseudoVFNMSUB_VFPR16_M1_E16,
16614 0 : 2772 => Opcode::PseudoVFNMSUB_VFPR16_M1_E16_MASK,
16615 0 : 2773 => Opcode::PseudoVFNMSUB_VFPR16_M2_E16,
16616 0 : 2774 => Opcode::PseudoVFNMSUB_VFPR16_M2_E16_MASK,
16617 0 : 2775 => Opcode::PseudoVFNMSUB_VFPR16_M4_E16,
16618 0 : 2776 => Opcode::PseudoVFNMSUB_VFPR16_M4_E16_MASK,
16619 0 : 2777 => Opcode::PseudoVFNMSUB_VFPR16_M8_E16,
16620 0 : 2778 => Opcode::PseudoVFNMSUB_VFPR16_M8_E16_MASK,
16621 0 : 2779 => Opcode::PseudoVFNMSUB_VFPR16_MF2_E16,
16622 0 : 2780 => Opcode::PseudoVFNMSUB_VFPR16_MF2_E16_MASK,
16623 0 : 2781 => Opcode::PseudoVFNMSUB_VFPR16_MF4_E16,
16624 0 : 2782 => Opcode::PseudoVFNMSUB_VFPR16_MF4_E16_MASK,
16625 0 : 2783 => Opcode::PseudoVFNMSUB_VFPR32_M1_E32,
16626 0 : 2784 => Opcode::PseudoVFNMSUB_VFPR32_M1_E32_MASK,
16627 0 : 2785 => Opcode::PseudoVFNMSUB_VFPR32_M2_E32,
16628 0 : 2786 => Opcode::PseudoVFNMSUB_VFPR32_M2_E32_MASK,
16629 0 : 2787 => Opcode::PseudoVFNMSUB_VFPR32_M4_E32,
16630 0 : 2788 => Opcode::PseudoVFNMSUB_VFPR32_M4_E32_MASK,
16631 0 : 2789 => Opcode::PseudoVFNMSUB_VFPR32_M8_E32,
16632 0 : 2790 => Opcode::PseudoVFNMSUB_VFPR32_M8_E32_MASK,
16633 0 : 2791 => Opcode::PseudoVFNMSUB_VFPR32_MF2_E32,
16634 0 : 2792 => Opcode::PseudoVFNMSUB_VFPR32_MF2_E32_MASK,
16635 0 : 2793 => Opcode::PseudoVFNMSUB_VFPR64_M1_E64,
16636 0 : 2794 => Opcode::PseudoVFNMSUB_VFPR64_M1_E64_MASK,
16637 0 : 2795 => Opcode::PseudoVFNMSUB_VFPR64_M2_E64,
16638 0 : 2796 => Opcode::PseudoVFNMSUB_VFPR64_M2_E64_MASK,
16639 0 : 2797 => Opcode::PseudoVFNMSUB_VFPR64_M4_E64,
16640 0 : 2798 => Opcode::PseudoVFNMSUB_VFPR64_M4_E64_MASK,
16641 0 : 2799 => Opcode::PseudoVFNMSUB_VFPR64_M8_E64,
16642 0 : 2800 => Opcode::PseudoVFNMSUB_VFPR64_M8_E64_MASK,
16643 0 : 2801 => Opcode::PseudoVFNMSUB_VV_M1_E16,
16644 0 : 2802 => Opcode::PseudoVFNMSUB_VV_M1_E16_MASK,
16645 0 : 2803 => Opcode::PseudoVFNMSUB_VV_M1_E32,
16646 0 : 2804 => Opcode::PseudoVFNMSUB_VV_M1_E32_MASK,
16647 0 : 2805 => Opcode::PseudoVFNMSUB_VV_M1_E64,
16648 0 : 2806 => Opcode::PseudoVFNMSUB_VV_M1_E64_MASK,
16649 0 : 2807 => Opcode::PseudoVFNMSUB_VV_M2_E16,
16650 0 : 2808 => Opcode::PseudoVFNMSUB_VV_M2_E16_MASK,
16651 0 : 2809 => Opcode::PseudoVFNMSUB_VV_M2_E32,
16652 0 : 2810 => Opcode::PseudoVFNMSUB_VV_M2_E32_MASK,
16653 0 : 2811 => Opcode::PseudoVFNMSUB_VV_M2_E64,
16654 0 : 2812 => Opcode::PseudoVFNMSUB_VV_M2_E64_MASK,
16655 0 : 2813 => Opcode::PseudoVFNMSUB_VV_M4_E16,
16656 0 : 2814 => Opcode::PseudoVFNMSUB_VV_M4_E16_MASK,
16657 0 : 2815 => Opcode::PseudoVFNMSUB_VV_M4_E32,
16658 0 : 2816 => Opcode::PseudoVFNMSUB_VV_M4_E32_MASK,
16659 0 : 2817 => Opcode::PseudoVFNMSUB_VV_M4_E64,
16660 0 : 2818 => Opcode::PseudoVFNMSUB_VV_M4_E64_MASK,
16661 0 : 2819 => Opcode::PseudoVFNMSUB_VV_M8_E16,
16662 0 : 2820 => Opcode::PseudoVFNMSUB_VV_M8_E16_MASK,
16663 0 : 2821 => Opcode::PseudoVFNMSUB_VV_M8_E32,
16664 0 : 2822 => Opcode::PseudoVFNMSUB_VV_M8_E32_MASK,
16665 0 : 2823 => Opcode::PseudoVFNMSUB_VV_M8_E64,
16666 0 : 2824 => Opcode::PseudoVFNMSUB_VV_M8_E64_MASK,
16667 0 : 2825 => Opcode::PseudoVFNMSUB_VV_MF2_E16,
16668 0 : 2826 => Opcode::PseudoVFNMSUB_VV_MF2_E16_MASK,
16669 0 : 2827 => Opcode::PseudoVFNMSUB_VV_MF2_E32,
16670 0 : 2828 => Opcode::PseudoVFNMSUB_VV_MF2_E32_MASK,
16671 0 : 2829 => Opcode::PseudoVFNMSUB_VV_MF4_E16,
16672 0 : 2830 => Opcode::PseudoVFNMSUB_VV_MF4_E16_MASK,
16673 0 : 2831 => Opcode::PseudoVFNRCLIP_XU_F_QF_M1,
16674 0 : 2832 => Opcode::PseudoVFNRCLIP_XU_F_QF_M1_MASK,
16675 0 : 2833 => Opcode::PseudoVFNRCLIP_XU_F_QF_M2,
16676 0 : 2834 => Opcode::PseudoVFNRCLIP_XU_F_QF_M2_MASK,
16677 0 : 2835 => Opcode::PseudoVFNRCLIP_XU_F_QF_MF2,
16678 0 : 2836 => Opcode::PseudoVFNRCLIP_XU_F_QF_MF2_MASK,
16679 0 : 2837 => Opcode::PseudoVFNRCLIP_XU_F_QF_MF4,
16680 0 : 2838 => Opcode::PseudoVFNRCLIP_XU_F_QF_MF4_MASK,
16681 0 : 2839 => Opcode::PseudoVFNRCLIP_XU_F_QF_MF8,
16682 0 : 2840 => Opcode::PseudoVFNRCLIP_XU_F_QF_MF8_MASK,
16683 0 : 2841 => Opcode::PseudoVFNRCLIP_X_F_QF_M1,
16684 0 : 2842 => Opcode::PseudoVFNRCLIP_X_F_QF_M1_MASK,
16685 0 : 2843 => Opcode::PseudoVFNRCLIP_X_F_QF_M2,
16686 0 : 2844 => Opcode::PseudoVFNRCLIP_X_F_QF_M2_MASK,
16687 0 : 2845 => Opcode::PseudoVFNRCLIP_X_F_QF_MF2,
16688 0 : 2846 => Opcode::PseudoVFNRCLIP_X_F_QF_MF2_MASK,
16689 0 : 2847 => Opcode::PseudoVFNRCLIP_X_F_QF_MF4,
16690 0 : 2848 => Opcode::PseudoVFNRCLIP_X_F_QF_MF4_MASK,
16691 0 : 2849 => Opcode::PseudoVFNRCLIP_X_F_QF_MF8,
16692 0 : 2850 => Opcode::PseudoVFNRCLIP_X_F_QF_MF8_MASK,
16693 0 : 2851 => Opcode::PseudoVFRDIV_VFPR16_M1_E16,
16694 0 : 2852 => Opcode::PseudoVFRDIV_VFPR16_M1_E16_MASK,
16695 0 : 2853 => Opcode::PseudoVFRDIV_VFPR16_M2_E16,
16696 0 : 2854 => Opcode::PseudoVFRDIV_VFPR16_M2_E16_MASK,
16697 0 : 2855 => Opcode::PseudoVFRDIV_VFPR16_M4_E16,
16698 0 : 2856 => Opcode::PseudoVFRDIV_VFPR16_M4_E16_MASK,
16699 0 : 2857 => Opcode::PseudoVFRDIV_VFPR16_M8_E16,
16700 0 : 2858 => Opcode::PseudoVFRDIV_VFPR16_M8_E16_MASK,
16701 0 : 2859 => Opcode::PseudoVFRDIV_VFPR16_MF2_E16,
16702 0 : 2860 => Opcode::PseudoVFRDIV_VFPR16_MF2_E16_MASK,
16703 0 : 2861 => Opcode::PseudoVFRDIV_VFPR16_MF4_E16,
16704 0 : 2862 => Opcode::PseudoVFRDIV_VFPR16_MF4_E16_MASK,
16705 0 : 2863 => Opcode::PseudoVFRDIV_VFPR32_M1_E32,
16706 0 : 2864 => Opcode::PseudoVFRDIV_VFPR32_M1_E32_MASK,
16707 0 : 2865 => Opcode::PseudoVFRDIV_VFPR32_M2_E32,
16708 0 : 2866 => Opcode::PseudoVFRDIV_VFPR32_M2_E32_MASK,
16709 0 : 2867 => Opcode::PseudoVFRDIV_VFPR32_M4_E32,
16710 0 : 2868 => Opcode::PseudoVFRDIV_VFPR32_M4_E32_MASK,
16711 0 : 2869 => Opcode::PseudoVFRDIV_VFPR32_M8_E32,
16712 0 : 2870 => Opcode::PseudoVFRDIV_VFPR32_M8_E32_MASK,
16713 0 : 2871 => Opcode::PseudoVFRDIV_VFPR32_MF2_E32,
16714 0 : 2872 => Opcode::PseudoVFRDIV_VFPR32_MF2_E32_MASK,
16715 0 : 2873 => Opcode::PseudoVFRDIV_VFPR64_M1_E64,
16716 0 : 2874 => Opcode::PseudoVFRDIV_VFPR64_M1_E64_MASK,
16717 0 : 2875 => Opcode::PseudoVFRDIV_VFPR64_M2_E64,
16718 0 : 2876 => Opcode::PseudoVFRDIV_VFPR64_M2_E64_MASK,
16719 0 : 2877 => Opcode::PseudoVFRDIV_VFPR64_M4_E64,
16720 0 : 2878 => Opcode::PseudoVFRDIV_VFPR64_M4_E64_MASK,
16721 0 : 2879 => Opcode::PseudoVFRDIV_VFPR64_M8_E64,
16722 0 : 2880 => Opcode::PseudoVFRDIV_VFPR64_M8_E64_MASK,
16723 0 : 2881 => Opcode::PseudoVFREC7_V_M1_E16,
16724 0 : 2882 => Opcode::PseudoVFREC7_V_M1_E16_MASK,
16725 0 : 2883 => Opcode::PseudoVFREC7_V_M1_E32,
16726 0 : 2884 => Opcode::PseudoVFREC7_V_M1_E32_MASK,
16727 0 : 2885 => Opcode::PseudoVFREC7_V_M1_E64,
16728 0 : 2886 => Opcode::PseudoVFREC7_V_M1_E64_MASK,
16729 0 : 2887 => Opcode::PseudoVFREC7_V_M2_E16,
16730 0 : 2888 => Opcode::PseudoVFREC7_V_M2_E16_MASK,
16731 0 : 2889 => Opcode::PseudoVFREC7_V_M2_E32,
16732 0 : 2890 => Opcode::PseudoVFREC7_V_M2_E32_MASK,
16733 0 : 2891 => Opcode::PseudoVFREC7_V_M2_E64,
16734 0 : 2892 => Opcode::PseudoVFREC7_V_M2_E64_MASK,
16735 0 : 2893 => Opcode::PseudoVFREC7_V_M4_E16,
16736 0 : 2894 => Opcode::PseudoVFREC7_V_M4_E16_MASK,
16737 0 : 2895 => Opcode::PseudoVFREC7_V_M4_E32,
16738 0 : 2896 => Opcode::PseudoVFREC7_V_M4_E32_MASK,
16739 0 : 2897 => Opcode::PseudoVFREC7_V_M4_E64,
16740 0 : 2898 => Opcode::PseudoVFREC7_V_M4_E64_MASK,
16741 0 : 2899 => Opcode::PseudoVFREC7_V_M8_E16,
16742 0 : 2900 => Opcode::PseudoVFREC7_V_M8_E16_MASK,
16743 0 : 2901 => Opcode::PseudoVFREC7_V_M8_E32,
16744 0 : 2902 => Opcode::PseudoVFREC7_V_M8_E32_MASK,
16745 0 : 2903 => Opcode::PseudoVFREC7_V_M8_E64,
16746 0 : 2904 => Opcode::PseudoVFREC7_V_M8_E64_MASK,
16747 0 : 2905 => Opcode::PseudoVFREC7_V_MF2_E16,
16748 0 : 2906 => Opcode::PseudoVFREC7_V_MF2_E16_MASK,
16749 0 : 2907 => Opcode::PseudoVFREC7_V_MF2_E32,
16750 0 : 2908 => Opcode::PseudoVFREC7_V_MF2_E32_MASK,
16751 0 : 2909 => Opcode::PseudoVFREC7_V_MF4_E16,
16752 0 : 2910 => Opcode::PseudoVFREC7_V_MF4_E16_MASK,
16753 0 : 2911 => Opcode::PseudoVFREDMAX_VS_M1_E16,
16754 0 : 2912 => Opcode::PseudoVFREDMAX_VS_M1_E16_MASK,
16755 0 : 2913 => Opcode::PseudoVFREDMAX_VS_M1_E32,
16756 0 : 2914 => Opcode::PseudoVFREDMAX_VS_M1_E32_MASK,
16757 0 : 2915 => Opcode::PseudoVFREDMAX_VS_M1_E64,
16758 0 : 2916 => Opcode::PseudoVFREDMAX_VS_M1_E64_MASK,
16759 0 : 2917 => Opcode::PseudoVFREDMAX_VS_M2_E16,
16760 0 : 2918 => Opcode::PseudoVFREDMAX_VS_M2_E16_MASK,
16761 0 : 2919 => Opcode::PseudoVFREDMAX_VS_M2_E32,
16762 0 : 2920 => Opcode::PseudoVFREDMAX_VS_M2_E32_MASK,
16763 0 : 2921 => Opcode::PseudoVFREDMAX_VS_M2_E64,
16764 0 : 2922 => Opcode::PseudoVFREDMAX_VS_M2_E64_MASK,
16765 0 : 2923 => Opcode::PseudoVFREDMAX_VS_M4_E16,
16766 0 : 2924 => Opcode::PseudoVFREDMAX_VS_M4_E16_MASK,
16767 0 : 2925 => Opcode::PseudoVFREDMAX_VS_M4_E32,
16768 0 : 2926 => Opcode::PseudoVFREDMAX_VS_M4_E32_MASK,
16769 0 : 2927 => Opcode::PseudoVFREDMAX_VS_M4_E64,
16770 0 : 2928 => Opcode::PseudoVFREDMAX_VS_M4_E64_MASK,
16771 0 : 2929 => Opcode::PseudoVFREDMAX_VS_M8_E16,
16772 0 : 2930 => Opcode::PseudoVFREDMAX_VS_M8_E16_MASK,
16773 0 : 2931 => Opcode::PseudoVFREDMAX_VS_M8_E32,
16774 0 : 2932 => Opcode::PseudoVFREDMAX_VS_M8_E32_MASK,
16775 0 : 2933 => Opcode::PseudoVFREDMAX_VS_M8_E64,
16776 0 : 2934 => Opcode::PseudoVFREDMAX_VS_M8_E64_MASK,
16777 0 : 2935 => Opcode::PseudoVFREDMAX_VS_MF2_E16,
16778 0 : 2936 => Opcode::PseudoVFREDMAX_VS_MF2_E16_MASK,
16779 0 : 2937 => Opcode::PseudoVFREDMAX_VS_MF2_E32,
16780 0 : 2938 => Opcode::PseudoVFREDMAX_VS_MF2_E32_MASK,
16781 0 : 2939 => Opcode::PseudoVFREDMAX_VS_MF4_E16,
16782 0 : 2940 => Opcode::PseudoVFREDMAX_VS_MF4_E16_MASK,
16783 0 : 2941 => Opcode::PseudoVFREDMIN_VS_M1_E16,
16784 0 : 2942 => Opcode::PseudoVFREDMIN_VS_M1_E16_MASK,
16785 0 : 2943 => Opcode::PseudoVFREDMIN_VS_M1_E32,
16786 0 : 2944 => Opcode::PseudoVFREDMIN_VS_M1_E32_MASK,
16787 0 : 2945 => Opcode::PseudoVFREDMIN_VS_M1_E64,
16788 0 : 2946 => Opcode::PseudoVFREDMIN_VS_M1_E64_MASK,
16789 0 : 2947 => Opcode::PseudoVFREDMIN_VS_M2_E16,
16790 0 : 2948 => Opcode::PseudoVFREDMIN_VS_M2_E16_MASK,
16791 0 : 2949 => Opcode::PseudoVFREDMIN_VS_M2_E32,
16792 0 : 2950 => Opcode::PseudoVFREDMIN_VS_M2_E32_MASK,
16793 0 : 2951 => Opcode::PseudoVFREDMIN_VS_M2_E64,
16794 0 : 2952 => Opcode::PseudoVFREDMIN_VS_M2_E64_MASK,
16795 0 : 2953 => Opcode::PseudoVFREDMIN_VS_M4_E16,
16796 0 : 2954 => Opcode::PseudoVFREDMIN_VS_M4_E16_MASK,
16797 0 : 2955 => Opcode::PseudoVFREDMIN_VS_M4_E32,
16798 0 : 2956 => Opcode::PseudoVFREDMIN_VS_M4_E32_MASK,
16799 0 : 2957 => Opcode::PseudoVFREDMIN_VS_M4_E64,
16800 0 : 2958 => Opcode::PseudoVFREDMIN_VS_M4_E64_MASK,
16801 0 : 2959 => Opcode::PseudoVFREDMIN_VS_M8_E16,
16802 0 : 2960 => Opcode::PseudoVFREDMIN_VS_M8_E16_MASK,
16803 0 : 2961 => Opcode::PseudoVFREDMIN_VS_M8_E32,
16804 0 : 2962 => Opcode::PseudoVFREDMIN_VS_M8_E32_MASK,
16805 0 : 2963 => Opcode::PseudoVFREDMIN_VS_M8_E64,
16806 0 : 2964 => Opcode::PseudoVFREDMIN_VS_M8_E64_MASK,
16807 0 : 2965 => Opcode::PseudoVFREDMIN_VS_MF2_E16,
16808 0 : 2966 => Opcode::PseudoVFREDMIN_VS_MF2_E16_MASK,
16809 0 : 2967 => Opcode::PseudoVFREDMIN_VS_MF2_E32,
16810 0 : 2968 => Opcode::PseudoVFREDMIN_VS_MF2_E32_MASK,
16811 0 : 2969 => Opcode::PseudoVFREDMIN_VS_MF4_E16,
16812 0 : 2970 => Opcode::PseudoVFREDMIN_VS_MF4_E16_MASK,
16813 0 : 2971 => Opcode::PseudoVFREDOSUM_VS_M1_E16,
16814 0 : 2972 => Opcode::PseudoVFREDOSUM_VS_M1_E16_MASK,
16815 0 : 2973 => Opcode::PseudoVFREDOSUM_VS_M1_E32,
16816 0 : 2974 => Opcode::PseudoVFREDOSUM_VS_M1_E32_MASK,
16817 0 : 2975 => Opcode::PseudoVFREDOSUM_VS_M1_E64,
16818 0 : 2976 => Opcode::PseudoVFREDOSUM_VS_M1_E64_MASK,
16819 0 : 2977 => Opcode::PseudoVFREDOSUM_VS_M2_E16,
16820 0 : 2978 => Opcode::PseudoVFREDOSUM_VS_M2_E16_MASK,
16821 0 : 2979 => Opcode::PseudoVFREDOSUM_VS_M2_E32,
16822 0 : 2980 => Opcode::PseudoVFREDOSUM_VS_M2_E32_MASK,
16823 0 : 2981 => Opcode::PseudoVFREDOSUM_VS_M2_E64,
16824 0 : 2982 => Opcode::PseudoVFREDOSUM_VS_M2_E64_MASK,
16825 0 : 2983 => Opcode::PseudoVFREDOSUM_VS_M4_E16,
16826 0 : 2984 => Opcode::PseudoVFREDOSUM_VS_M4_E16_MASK,
16827 0 : 2985 => Opcode::PseudoVFREDOSUM_VS_M4_E32,
16828 0 : 2986 => Opcode::PseudoVFREDOSUM_VS_M4_E32_MASK,
16829 0 : 2987 => Opcode::PseudoVFREDOSUM_VS_M4_E64,
16830 0 : 2988 => Opcode::PseudoVFREDOSUM_VS_M4_E64_MASK,
16831 0 : 2989 => Opcode::PseudoVFREDOSUM_VS_M8_E16,
16832 0 : 2990 => Opcode::PseudoVFREDOSUM_VS_M8_E16_MASK,
16833 0 : 2991 => Opcode::PseudoVFREDOSUM_VS_M8_E32,
16834 0 : 2992 => Opcode::PseudoVFREDOSUM_VS_M8_E32_MASK,
16835 0 : 2993 => Opcode::PseudoVFREDOSUM_VS_M8_E64,
16836 0 : 2994 => Opcode::PseudoVFREDOSUM_VS_M8_E64_MASK,
16837 0 : 2995 => Opcode::PseudoVFREDOSUM_VS_MF2_E16,
16838 0 : 2996 => Opcode::PseudoVFREDOSUM_VS_MF2_E16_MASK,
16839 0 : 2997 => Opcode::PseudoVFREDOSUM_VS_MF2_E32,
16840 0 : 2998 => Opcode::PseudoVFREDOSUM_VS_MF2_E32_MASK,
16841 0 : 2999 => Opcode::PseudoVFREDOSUM_VS_MF4_E16,
16842 0 : 3000 => Opcode::PseudoVFREDOSUM_VS_MF4_E16_MASK,
16843 0 : 3001 => Opcode::PseudoVFREDUSUM_VS_M1_E16,
16844 0 : 3002 => Opcode::PseudoVFREDUSUM_VS_M1_E16_MASK,
16845 0 : 3003 => Opcode::PseudoVFREDUSUM_VS_M1_E32,
16846 0 : 3004 => Opcode::PseudoVFREDUSUM_VS_M1_E32_MASK,
16847 0 : 3005 => Opcode::PseudoVFREDUSUM_VS_M1_E64,
16848 0 : 3006 => Opcode::PseudoVFREDUSUM_VS_M1_E64_MASK,
16849 0 : 3007 => Opcode::PseudoVFREDUSUM_VS_M2_E16,
16850 0 : 3008 => Opcode::PseudoVFREDUSUM_VS_M2_E16_MASK,
16851 0 : 3009 => Opcode::PseudoVFREDUSUM_VS_M2_E32,
16852 0 : 3010 => Opcode::PseudoVFREDUSUM_VS_M2_E32_MASK,
16853 0 : 3011 => Opcode::PseudoVFREDUSUM_VS_M2_E64,
16854 0 : 3012 => Opcode::PseudoVFREDUSUM_VS_M2_E64_MASK,
16855 0 : 3013 => Opcode::PseudoVFREDUSUM_VS_M4_E16,
16856 0 : 3014 => Opcode::PseudoVFREDUSUM_VS_M4_E16_MASK,
16857 0 : 3015 => Opcode::PseudoVFREDUSUM_VS_M4_E32,
16858 0 : 3016 => Opcode::PseudoVFREDUSUM_VS_M4_E32_MASK,
16859 0 : 3017 => Opcode::PseudoVFREDUSUM_VS_M4_E64,
16860 0 : 3018 => Opcode::PseudoVFREDUSUM_VS_M4_E64_MASK,
16861 0 : 3019 => Opcode::PseudoVFREDUSUM_VS_M8_E16,
16862 0 : 3020 => Opcode::PseudoVFREDUSUM_VS_M8_E16_MASK,
16863 0 : 3021 => Opcode::PseudoVFREDUSUM_VS_M8_E32,
16864 0 : 3022 => Opcode::PseudoVFREDUSUM_VS_M8_E32_MASK,
16865 0 : 3023 => Opcode::PseudoVFREDUSUM_VS_M8_E64,
16866 0 : 3024 => Opcode::PseudoVFREDUSUM_VS_M8_E64_MASK,
16867 0 : 3025 => Opcode::PseudoVFREDUSUM_VS_MF2_E16,
16868 0 : 3026 => Opcode::PseudoVFREDUSUM_VS_MF2_E16_MASK,
16869 0 : 3027 => Opcode::PseudoVFREDUSUM_VS_MF2_E32,
16870 0 : 3028 => Opcode::PseudoVFREDUSUM_VS_MF2_E32_MASK,
16871 0 : 3029 => Opcode::PseudoVFREDUSUM_VS_MF4_E16,
16872 0 : 3030 => Opcode::PseudoVFREDUSUM_VS_MF4_E16_MASK,
16873 0 : 3031 => Opcode::PseudoVFROUND_NOEXCEPT_V_M1_MASK,
16874 0 : 3032 => Opcode::PseudoVFROUND_NOEXCEPT_V_M2_MASK,
16875 0 : 3033 => Opcode::PseudoVFROUND_NOEXCEPT_V_M4_MASK,
16876 0 : 3034 => Opcode::PseudoVFROUND_NOEXCEPT_V_M8_MASK,
16877 0 : 3035 => Opcode::PseudoVFROUND_NOEXCEPT_V_MF2_MASK,
16878 0 : 3036 => Opcode::PseudoVFROUND_NOEXCEPT_V_MF4_MASK,
16879 0 : 3037 => Opcode::PseudoVFRSQRT7_V_M1_E16,
16880 0 : 3038 => Opcode::PseudoVFRSQRT7_V_M1_E16_MASK,
16881 0 : 3039 => Opcode::PseudoVFRSQRT7_V_M1_E32,
16882 0 : 3040 => Opcode::PseudoVFRSQRT7_V_M1_E32_MASK,
16883 0 : 3041 => Opcode::PseudoVFRSQRT7_V_M1_E64,
16884 0 : 3042 => Opcode::PseudoVFRSQRT7_V_M1_E64_MASK,
16885 0 : 3043 => Opcode::PseudoVFRSQRT7_V_M2_E16,
16886 0 : 3044 => Opcode::PseudoVFRSQRT7_V_M2_E16_MASK,
16887 0 : 3045 => Opcode::PseudoVFRSQRT7_V_M2_E32,
16888 0 : 3046 => Opcode::PseudoVFRSQRT7_V_M2_E32_MASK,
16889 0 : 3047 => Opcode::PseudoVFRSQRT7_V_M2_E64,
16890 0 : 3048 => Opcode::PseudoVFRSQRT7_V_M2_E64_MASK,
16891 0 : 3049 => Opcode::PseudoVFRSQRT7_V_M4_E16,
16892 0 : 3050 => Opcode::PseudoVFRSQRT7_V_M4_E16_MASK,
16893 0 : 3051 => Opcode::PseudoVFRSQRT7_V_M4_E32,
16894 0 : 3052 => Opcode::PseudoVFRSQRT7_V_M4_E32_MASK,
16895 0 : 3053 => Opcode::PseudoVFRSQRT7_V_M4_E64,
16896 0 : 3054 => Opcode::PseudoVFRSQRT7_V_M4_E64_MASK,
16897 0 : 3055 => Opcode::PseudoVFRSQRT7_V_M8_E16,
16898 0 : 3056 => Opcode::PseudoVFRSQRT7_V_M8_E16_MASK,
16899 0 : 3057 => Opcode::PseudoVFRSQRT7_V_M8_E32,
16900 0 : 3058 => Opcode::PseudoVFRSQRT7_V_M8_E32_MASK,
16901 0 : 3059 => Opcode::PseudoVFRSQRT7_V_M8_E64,
16902 0 : 3060 => Opcode::PseudoVFRSQRT7_V_M8_E64_MASK,
16903 0 : 3061 => Opcode::PseudoVFRSQRT7_V_MF2_E16,
16904 0 : 3062 => Opcode::PseudoVFRSQRT7_V_MF2_E16_MASK,
16905 0 : 3063 => Opcode::PseudoVFRSQRT7_V_MF2_E32,
16906 0 : 3064 => Opcode::PseudoVFRSQRT7_V_MF2_E32_MASK,
16907 0 : 3065 => Opcode::PseudoVFRSQRT7_V_MF4_E16,
16908 0 : 3066 => Opcode::PseudoVFRSQRT7_V_MF4_E16_MASK,
16909 0 : 3067 => Opcode::PseudoVFRSUB_VFPR16_M1_E16,
16910 0 : 3068 => Opcode::PseudoVFRSUB_VFPR16_M1_E16_MASK,
16911 0 : 3069 => Opcode::PseudoVFRSUB_VFPR16_M2_E16,
16912 0 : 3070 => Opcode::PseudoVFRSUB_VFPR16_M2_E16_MASK,
16913 0 : 3071 => Opcode::PseudoVFRSUB_VFPR16_M4_E16,
16914 0 : 3072 => Opcode::PseudoVFRSUB_VFPR16_M4_E16_MASK,
16915 0 : 3073 => Opcode::PseudoVFRSUB_VFPR16_M8_E16,
16916 0 : 3074 => Opcode::PseudoVFRSUB_VFPR16_M8_E16_MASK,
16917 0 : 3075 => Opcode::PseudoVFRSUB_VFPR16_MF2_E16,
16918 0 : 3076 => Opcode::PseudoVFRSUB_VFPR16_MF2_E16_MASK,
16919 0 : 3077 => Opcode::PseudoVFRSUB_VFPR16_MF4_E16,
16920 0 : 3078 => Opcode::PseudoVFRSUB_VFPR16_MF4_E16_MASK,
16921 0 : 3079 => Opcode::PseudoVFRSUB_VFPR32_M1_E32,
16922 0 : 3080 => Opcode::PseudoVFRSUB_VFPR32_M1_E32_MASK,
16923 0 : 3081 => Opcode::PseudoVFRSUB_VFPR32_M2_E32,
16924 0 : 3082 => Opcode::PseudoVFRSUB_VFPR32_M2_E32_MASK,
16925 0 : 3083 => Opcode::PseudoVFRSUB_VFPR32_M4_E32,
16926 0 : 3084 => Opcode::PseudoVFRSUB_VFPR32_M4_E32_MASK,
16927 0 : 3085 => Opcode::PseudoVFRSUB_VFPR32_M8_E32,
16928 0 : 3086 => Opcode::PseudoVFRSUB_VFPR32_M8_E32_MASK,
16929 0 : 3087 => Opcode::PseudoVFRSUB_VFPR32_MF2_E32,
16930 0 : 3088 => Opcode::PseudoVFRSUB_VFPR32_MF2_E32_MASK,
16931 0 : 3089 => Opcode::PseudoVFRSUB_VFPR64_M1_E64,
16932 0 : 3090 => Opcode::PseudoVFRSUB_VFPR64_M1_E64_MASK,
16933 0 : 3091 => Opcode::PseudoVFRSUB_VFPR64_M2_E64,
16934 0 : 3092 => Opcode::PseudoVFRSUB_VFPR64_M2_E64_MASK,
16935 0 : 3093 => Opcode::PseudoVFRSUB_VFPR64_M4_E64,
16936 0 : 3094 => Opcode::PseudoVFRSUB_VFPR64_M4_E64_MASK,
16937 0 : 3095 => Opcode::PseudoVFRSUB_VFPR64_M8_E64,
16938 0 : 3096 => Opcode::PseudoVFRSUB_VFPR64_M8_E64_MASK,
16939 0 : 3097 => Opcode::PseudoVFSGNJN_VFPR16_M1_E16,
16940 0 : 3098 => Opcode::PseudoVFSGNJN_VFPR16_M1_E16_MASK,
16941 0 : 3099 => Opcode::PseudoVFSGNJN_VFPR16_M2_E16,
16942 0 : 3100 => Opcode::PseudoVFSGNJN_VFPR16_M2_E16_MASK,
16943 0 : 3101 => Opcode::PseudoVFSGNJN_VFPR16_M4_E16,
16944 0 : 3102 => Opcode::PseudoVFSGNJN_VFPR16_M4_E16_MASK,
16945 0 : 3103 => Opcode::PseudoVFSGNJN_VFPR16_M8_E16,
16946 0 : 3104 => Opcode::PseudoVFSGNJN_VFPR16_M8_E16_MASK,
16947 0 : 3105 => Opcode::PseudoVFSGNJN_VFPR16_MF2_E16,
16948 0 : 3106 => Opcode::PseudoVFSGNJN_VFPR16_MF2_E16_MASK,
16949 0 : 3107 => Opcode::PseudoVFSGNJN_VFPR16_MF4_E16,
16950 0 : 3108 => Opcode::PseudoVFSGNJN_VFPR16_MF4_E16_MASK,
16951 0 : 3109 => Opcode::PseudoVFSGNJN_VFPR32_M1_E32,
16952 0 : 3110 => Opcode::PseudoVFSGNJN_VFPR32_M1_E32_MASK,
16953 0 : 3111 => Opcode::PseudoVFSGNJN_VFPR32_M2_E32,
16954 0 : 3112 => Opcode::PseudoVFSGNJN_VFPR32_M2_E32_MASK,
16955 0 : 3113 => Opcode::PseudoVFSGNJN_VFPR32_M4_E32,
16956 0 : 3114 => Opcode::PseudoVFSGNJN_VFPR32_M4_E32_MASK,
16957 0 : 3115 => Opcode::PseudoVFSGNJN_VFPR32_M8_E32,
16958 0 : 3116 => Opcode::PseudoVFSGNJN_VFPR32_M8_E32_MASK,
16959 0 : 3117 => Opcode::PseudoVFSGNJN_VFPR32_MF2_E32,
16960 0 : 3118 => Opcode::PseudoVFSGNJN_VFPR32_MF2_E32_MASK,
16961 0 : 3119 => Opcode::PseudoVFSGNJN_VFPR64_M1_E64,
16962 0 : 3120 => Opcode::PseudoVFSGNJN_VFPR64_M1_E64_MASK,
16963 0 : 3121 => Opcode::PseudoVFSGNJN_VFPR64_M2_E64,
16964 0 : 3122 => Opcode::PseudoVFSGNJN_VFPR64_M2_E64_MASK,
16965 0 : 3123 => Opcode::PseudoVFSGNJN_VFPR64_M4_E64,
16966 0 : 3124 => Opcode::PseudoVFSGNJN_VFPR64_M4_E64_MASK,
16967 0 : 3125 => Opcode::PseudoVFSGNJN_VFPR64_M8_E64,
16968 0 : 3126 => Opcode::PseudoVFSGNJN_VFPR64_M8_E64_MASK,
16969 0 : 3127 => Opcode::PseudoVFSGNJN_VV_M1_E16,
16970 0 : 3128 => Opcode::PseudoVFSGNJN_VV_M1_E16_MASK,
16971 0 : 3129 => Opcode::PseudoVFSGNJN_VV_M1_E32,
16972 0 : 3130 => Opcode::PseudoVFSGNJN_VV_M1_E32_MASK,
16973 0 : 3131 => Opcode::PseudoVFSGNJN_VV_M1_E64,
16974 0 : 3132 => Opcode::PseudoVFSGNJN_VV_M1_E64_MASK,
16975 0 : 3133 => Opcode::PseudoVFSGNJN_VV_M2_E16,
16976 0 : 3134 => Opcode::PseudoVFSGNJN_VV_M2_E16_MASK,
16977 0 : 3135 => Opcode::PseudoVFSGNJN_VV_M2_E32,
16978 0 : 3136 => Opcode::PseudoVFSGNJN_VV_M2_E32_MASK,
16979 0 : 3137 => Opcode::PseudoVFSGNJN_VV_M2_E64,
16980 0 : 3138 => Opcode::PseudoVFSGNJN_VV_M2_E64_MASK,
16981 0 : 3139 => Opcode::PseudoVFSGNJN_VV_M4_E16,
16982 0 : 3140 => Opcode::PseudoVFSGNJN_VV_M4_E16_MASK,
16983 0 : 3141 => Opcode::PseudoVFSGNJN_VV_M4_E32,
16984 0 : 3142 => Opcode::PseudoVFSGNJN_VV_M4_E32_MASK,
16985 0 : 3143 => Opcode::PseudoVFSGNJN_VV_M4_E64,
16986 0 : 3144 => Opcode::PseudoVFSGNJN_VV_M4_E64_MASK,
16987 0 : 3145 => Opcode::PseudoVFSGNJN_VV_M8_E16,
16988 0 : 3146 => Opcode::PseudoVFSGNJN_VV_M8_E16_MASK,
16989 0 : 3147 => Opcode::PseudoVFSGNJN_VV_M8_E32,
16990 0 : 3148 => Opcode::PseudoVFSGNJN_VV_M8_E32_MASK,
16991 0 : 3149 => Opcode::PseudoVFSGNJN_VV_M8_E64,
16992 0 : 3150 => Opcode::PseudoVFSGNJN_VV_M8_E64_MASK,
16993 0 : 3151 => Opcode::PseudoVFSGNJN_VV_MF2_E16,
16994 0 : 3152 => Opcode::PseudoVFSGNJN_VV_MF2_E16_MASK,
16995 0 : 3153 => Opcode::PseudoVFSGNJN_VV_MF2_E32,
16996 0 : 3154 => Opcode::PseudoVFSGNJN_VV_MF2_E32_MASK,
16997 0 : 3155 => Opcode::PseudoVFSGNJN_VV_MF4_E16,
16998 0 : 3156 => Opcode::PseudoVFSGNJN_VV_MF4_E16_MASK,
16999 0 : 3157 => Opcode::PseudoVFSGNJX_VFPR16_M1_E16,
17000 0 : 3158 => Opcode::PseudoVFSGNJX_VFPR16_M1_E16_MASK,
17001 0 : 3159 => Opcode::PseudoVFSGNJX_VFPR16_M2_E16,
17002 0 : 3160 => Opcode::PseudoVFSGNJX_VFPR16_M2_E16_MASK,
17003 0 : 3161 => Opcode::PseudoVFSGNJX_VFPR16_M4_E16,
17004 0 : 3162 => Opcode::PseudoVFSGNJX_VFPR16_M4_E16_MASK,
17005 0 : 3163 => Opcode::PseudoVFSGNJX_VFPR16_M8_E16,
17006 0 : 3164 => Opcode::PseudoVFSGNJX_VFPR16_M8_E16_MASK,
17007 0 : 3165 => Opcode::PseudoVFSGNJX_VFPR16_MF2_E16,
17008 0 : 3166 => Opcode::PseudoVFSGNJX_VFPR16_MF2_E16_MASK,
17009 0 : 3167 => Opcode::PseudoVFSGNJX_VFPR16_MF4_E16,
17010 0 : 3168 => Opcode::PseudoVFSGNJX_VFPR16_MF4_E16_MASK,
17011 0 : 3169 => Opcode::PseudoVFSGNJX_VFPR32_M1_E32,
17012 0 : 3170 => Opcode::PseudoVFSGNJX_VFPR32_M1_E32_MASK,
17013 0 : 3171 => Opcode::PseudoVFSGNJX_VFPR32_M2_E32,
17014 0 : 3172 => Opcode::PseudoVFSGNJX_VFPR32_M2_E32_MASK,
17015 0 : 3173 => Opcode::PseudoVFSGNJX_VFPR32_M4_E32,
17016 0 : 3174 => Opcode::PseudoVFSGNJX_VFPR32_M4_E32_MASK,
17017 0 : 3175 => Opcode::PseudoVFSGNJX_VFPR32_M8_E32,
17018 0 : 3176 => Opcode::PseudoVFSGNJX_VFPR32_M8_E32_MASK,
17019 0 : 3177 => Opcode::PseudoVFSGNJX_VFPR32_MF2_E32,
17020 0 : 3178 => Opcode::PseudoVFSGNJX_VFPR32_MF2_E32_MASK,
17021 0 : 3179 => Opcode::PseudoVFSGNJX_VFPR64_M1_E64,
17022 0 : 3180 => Opcode::PseudoVFSGNJX_VFPR64_M1_E64_MASK,
17023 0 : 3181 => Opcode::PseudoVFSGNJX_VFPR64_M2_E64,
17024 0 : 3182 => Opcode::PseudoVFSGNJX_VFPR64_M2_E64_MASK,
17025 0 : 3183 => Opcode::PseudoVFSGNJX_VFPR64_M4_E64,
17026 0 : 3184 => Opcode::PseudoVFSGNJX_VFPR64_M4_E64_MASK,
17027 0 : 3185 => Opcode::PseudoVFSGNJX_VFPR64_M8_E64,
17028 0 : 3186 => Opcode::PseudoVFSGNJX_VFPR64_M8_E64_MASK,
17029 0 : 3187 => Opcode::PseudoVFSGNJX_VV_M1_E16,
17030 0 : 3188 => Opcode::PseudoVFSGNJX_VV_M1_E16_MASK,
17031 0 : 3189 => Opcode::PseudoVFSGNJX_VV_M1_E32,
17032 0 : 3190 => Opcode::PseudoVFSGNJX_VV_M1_E32_MASK,
17033 0 : 3191 => Opcode::PseudoVFSGNJX_VV_M1_E64,
17034 0 : 3192 => Opcode::PseudoVFSGNJX_VV_M1_E64_MASK,
17035 0 : 3193 => Opcode::PseudoVFSGNJX_VV_M2_E16,
17036 0 : 3194 => Opcode::PseudoVFSGNJX_VV_M2_E16_MASK,
17037 0 : 3195 => Opcode::PseudoVFSGNJX_VV_M2_E32,
17038 0 : 3196 => Opcode::PseudoVFSGNJX_VV_M2_E32_MASK,
17039 0 : 3197 => Opcode::PseudoVFSGNJX_VV_M2_E64,
17040 0 : 3198 => Opcode::PseudoVFSGNJX_VV_M2_E64_MASK,
17041 0 : 3199 => Opcode::PseudoVFSGNJX_VV_M4_E16,
17042 0 : 3200 => Opcode::PseudoVFSGNJX_VV_M4_E16_MASK,
17043 0 : 3201 => Opcode::PseudoVFSGNJX_VV_M4_E32,
17044 0 : 3202 => Opcode::PseudoVFSGNJX_VV_M4_E32_MASK,
17045 0 : 3203 => Opcode::PseudoVFSGNJX_VV_M4_E64,
17046 0 : 3204 => Opcode::PseudoVFSGNJX_VV_M4_E64_MASK,
17047 0 : 3205 => Opcode::PseudoVFSGNJX_VV_M8_E16,
17048 0 : 3206 => Opcode::PseudoVFSGNJX_VV_M8_E16_MASK,
17049 0 : 3207 => Opcode::PseudoVFSGNJX_VV_M8_E32,
17050 0 : 3208 => Opcode::PseudoVFSGNJX_VV_M8_E32_MASK,
17051 0 : 3209 => Opcode::PseudoVFSGNJX_VV_M8_E64,
17052 0 : 3210 => Opcode::PseudoVFSGNJX_VV_M8_E64_MASK,
17053 0 : 3211 => Opcode::PseudoVFSGNJX_VV_MF2_E16,
17054 0 : 3212 => Opcode::PseudoVFSGNJX_VV_MF2_E16_MASK,
17055 0 : 3213 => Opcode::PseudoVFSGNJX_VV_MF2_E32,
17056 0 : 3214 => Opcode::PseudoVFSGNJX_VV_MF2_E32_MASK,
17057 0 : 3215 => Opcode::PseudoVFSGNJX_VV_MF4_E16,
17058 0 : 3216 => Opcode::PseudoVFSGNJX_VV_MF4_E16_MASK,
17059 0 : 3217 => Opcode::PseudoVFSGNJ_VFPR16_M1_E16,
17060 0 : 3218 => Opcode::PseudoVFSGNJ_VFPR16_M1_E16_MASK,
17061 0 : 3219 => Opcode::PseudoVFSGNJ_VFPR16_M2_E16,
17062 0 : 3220 => Opcode::PseudoVFSGNJ_VFPR16_M2_E16_MASK,
17063 0 : 3221 => Opcode::PseudoVFSGNJ_VFPR16_M4_E16,
17064 0 : 3222 => Opcode::PseudoVFSGNJ_VFPR16_M4_E16_MASK,
17065 0 : 3223 => Opcode::PseudoVFSGNJ_VFPR16_M8_E16,
17066 0 : 3224 => Opcode::PseudoVFSGNJ_VFPR16_M8_E16_MASK,
17067 0 : 3225 => Opcode::PseudoVFSGNJ_VFPR16_MF2_E16,
17068 0 : 3226 => Opcode::PseudoVFSGNJ_VFPR16_MF2_E16_MASK,
17069 0 : 3227 => Opcode::PseudoVFSGNJ_VFPR16_MF4_E16,
17070 0 : 3228 => Opcode::PseudoVFSGNJ_VFPR16_MF4_E16_MASK,
17071 0 : 3229 => Opcode::PseudoVFSGNJ_VFPR32_M1_E32,
17072 0 : 3230 => Opcode::PseudoVFSGNJ_VFPR32_M1_E32_MASK,
17073 0 : 3231 => Opcode::PseudoVFSGNJ_VFPR32_M2_E32,
17074 0 : 3232 => Opcode::PseudoVFSGNJ_VFPR32_M2_E32_MASK,
17075 0 : 3233 => Opcode::PseudoVFSGNJ_VFPR32_M4_E32,
17076 0 : 3234 => Opcode::PseudoVFSGNJ_VFPR32_M4_E32_MASK,
17077 0 : 3235 => Opcode::PseudoVFSGNJ_VFPR32_M8_E32,
17078 0 : 3236 => Opcode::PseudoVFSGNJ_VFPR32_M8_E32_MASK,
17079 0 : 3237 => Opcode::PseudoVFSGNJ_VFPR32_MF2_E32,
17080 0 : 3238 => Opcode::PseudoVFSGNJ_VFPR32_MF2_E32_MASK,
17081 0 : 3239 => Opcode::PseudoVFSGNJ_VFPR64_M1_E64,
17082 0 : 3240 => Opcode::PseudoVFSGNJ_VFPR64_M1_E64_MASK,
17083 0 : 3241 => Opcode::PseudoVFSGNJ_VFPR64_M2_E64,
17084 0 : 3242 => Opcode::PseudoVFSGNJ_VFPR64_M2_E64_MASK,
17085 0 : 3243 => Opcode::PseudoVFSGNJ_VFPR64_M4_E64,
17086 0 : 3244 => Opcode::PseudoVFSGNJ_VFPR64_M4_E64_MASK,
17087 0 : 3245 => Opcode::PseudoVFSGNJ_VFPR64_M8_E64,
17088 0 : 3246 => Opcode::PseudoVFSGNJ_VFPR64_M8_E64_MASK,
17089 0 : 3247 => Opcode::PseudoVFSGNJ_VV_M1_E16,
17090 0 : 3248 => Opcode::PseudoVFSGNJ_VV_M1_E16_MASK,
17091 0 : 3249 => Opcode::PseudoVFSGNJ_VV_M1_E32,
17092 0 : 3250 => Opcode::PseudoVFSGNJ_VV_M1_E32_MASK,
17093 0 : 3251 => Opcode::PseudoVFSGNJ_VV_M1_E64,
17094 0 : 3252 => Opcode::PseudoVFSGNJ_VV_M1_E64_MASK,
17095 0 : 3253 => Opcode::PseudoVFSGNJ_VV_M2_E16,
17096 0 : 3254 => Opcode::PseudoVFSGNJ_VV_M2_E16_MASK,
17097 0 : 3255 => Opcode::PseudoVFSGNJ_VV_M2_E32,
17098 0 : 3256 => Opcode::PseudoVFSGNJ_VV_M2_E32_MASK,
17099 0 : 3257 => Opcode::PseudoVFSGNJ_VV_M2_E64,
17100 0 : 3258 => Opcode::PseudoVFSGNJ_VV_M2_E64_MASK,
17101 0 : 3259 => Opcode::PseudoVFSGNJ_VV_M4_E16,
17102 0 : 3260 => Opcode::PseudoVFSGNJ_VV_M4_E16_MASK,
17103 0 : 3261 => Opcode::PseudoVFSGNJ_VV_M4_E32,
17104 0 : 3262 => Opcode::PseudoVFSGNJ_VV_M4_E32_MASK,
17105 0 : 3263 => Opcode::PseudoVFSGNJ_VV_M4_E64,
17106 0 : 3264 => Opcode::PseudoVFSGNJ_VV_M4_E64_MASK,
17107 0 : 3265 => Opcode::PseudoVFSGNJ_VV_M8_E16,
17108 0 : 3266 => Opcode::PseudoVFSGNJ_VV_M8_E16_MASK,
17109 0 : 3267 => Opcode::PseudoVFSGNJ_VV_M8_E32,
17110 0 : 3268 => Opcode::PseudoVFSGNJ_VV_M8_E32_MASK,
17111 0 : 3269 => Opcode::PseudoVFSGNJ_VV_M8_E64,
17112 0 : 3270 => Opcode::PseudoVFSGNJ_VV_M8_E64_MASK,
17113 0 : 3271 => Opcode::PseudoVFSGNJ_VV_MF2_E16,
17114 0 : 3272 => Opcode::PseudoVFSGNJ_VV_MF2_E16_MASK,
17115 0 : 3273 => Opcode::PseudoVFSGNJ_VV_MF2_E32,
17116 0 : 3274 => Opcode::PseudoVFSGNJ_VV_MF2_E32_MASK,
17117 0 : 3275 => Opcode::PseudoVFSGNJ_VV_MF4_E16,
17118 0 : 3276 => Opcode::PseudoVFSGNJ_VV_MF4_E16_MASK,
17119 0 : 3277 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_M1,
17120 0 : 3278 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_M1_MASK,
17121 0 : 3279 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_M2,
17122 0 : 3280 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_M2_MASK,
17123 0 : 3281 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_M4,
17124 0 : 3282 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_M4_MASK,
17125 0 : 3283 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_M8,
17126 0 : 3284 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_M8_MASK,
17127 0 : 3285 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_MF2,
17128 0 : 3286 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK,
17129 0 : 3287 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_MF4,
17130 0 : 3288 => Opcode::PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK,
17131 0 : 3289 => Opcode::PseudoVFSLIDE1DOWN_VFPR32_M1,
17132 0 : 3290 => Opcode::PseudoVFSLIDE1DOWN_VFPR32_M1_MASK,
17133 0 : 3291 => Opcode::PseudoVFSLIDE1DOWN_VFPR32_M2,
17134 0 : 3292 => Opcode::PseudoVFSLIDE1DOWN_VFPR32_M2_MASK,
17135 0 : 3293 => Opcode::PseudoVFSLIDE1DOWN_VFPR32_M4,
17136 0 : 3294 => Opcode::PseudoVFSLIDE1DOWN_VFPR32_M4_MASK,
17137 0 : 3295 => Opcode::PseudoVFSLIDE1DOWN_VFPR32_M8,
17138 0 : 3296 => Opcode::PseudoVFSLIDE1DOWN_VFPR32_M8_MASK,
17139 0 : 3297 => Opcode::PseudoVFSLIDE1DOWN_VFPR32_MF2,
17140 0 : 3298 => Opcode::PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK,
17141 0 : 3299 => Opcode::PseudoVFSLIDE1DOWN_VFPR64_M1,
17142 0 : 3300 => Opcode::PseudoVFSLIDE1DOWN_VFPR64_M1_MASK,
17143 0 : 3301 => Opcode::PseudoVFSLIDE1DOWN_VFPR64_M2,
17144 0 : 3302 => Opcode::PseudoVFSLIDE1DOWN_VFPR64_M2_MASK,
17145 0 : 3303 => Opcode::PseudoVFSLIDE1DOWN_VFPR64_M4,
17146 0 : 3304 => Opcode::PseudoVFSLIDE1DOWN_VFPR64_M4_MASK,
17147 0 : 3305 => Opcode::PseudoVFSLIDE1DOWN_VFPR64_M8,
17148 0 : 3306 => Opcode::PseudoVFSLIDE1DOWN_VFPR64_M8_MASK,
17149 0 : 3307 => Opcode::PseudoVFSLIDE1UP_VFPR16_M1,
17150 0 : 3308 => Opcode::PseudoVFSLIDE1UP_VFPR16_M1_MASK,
17151 0 : 3309 => Opcode::PseudoVFSLIDE1UP_VFPR16_M2,
17152 0 : 3310 => Opcode::PseudoVFSLIDE1UP_VFPR16_M2_MASK,
17153 0 : 3311 => Opcode::PseudoVFSLIDE1UP_VFPR16_M4,
17154 0 : 3312 => Opcode::PseudoVFSLIDE1UP_VFPR16_M4_MASK,
17155 0 : 3313 => Opcode::PseudoVFSLIDE1UP_VFPR16_M8,
17156 0 : 3314 => Opcode::PseudoVFSLIDE1UP_VFPR16_M8_MASK,
17157 0 : 3315 => Opcode::PseudoVFSLIDE1UP_VFPR16_MF2,
17158 0 : 3316 => Opcode::PseudoVFSLIDE1UP_VFPR16_MF2_MASK,
17159 0 : 3317 => Opcode::PseudoVFSLIDE1UP_VFPR16_MF4,
17160 0 : 3318 => Opcode::PseudoVFSLIDE1UP_VFPR16_MF4_MASK,
17161 0 : 3319 => Opcode::PseudoVFSLIDE1UP_VFPR32_M1,
17162 0 : 3320 => Opcode::PseudoVFSLIDE1UP_VFPR32_M1_MASK,
17163 0 : 3321 => Opcode::PseudoVFSLIDE1UP_VFPR32_M2,
17164 0 : 3322 => Opcode::PseudoVFSLIDE1UP_VFPR32_M2_MASK,
17165 0 : 3323 => Opcode::PseudoVFSLIDE1UP_VFPR32_M4,
17166 0 : 3324 => Opcode::PseudoVFSLIDE1UP_VFPR32_M4_MASK,
17167 0 : 3325 => Opcode::PseudoVFSLIDE1UP_VFPR32_M8,
17168 0 : 3326 => Opcode::PseudoVFSLIDE1UP_VFPR32_M8_MASK,
17169 0 : 3327 => Opcode::PseudoVFSLIDE1UP_VFPR32_MF2,
17170 0 : 3328 => Opcode::PseudoVFSLIDE1UP_VFPR32_MF2_MASK,
17171 0 : 3329 => Opcode::PseudoVFSLIDE1UP_VFPR64_M1,
17172 0 : 3330 => Opcode::PseudoVFSLIDE1UP_VFPR64_M1_MASK,
17173 0 : 3331 => Opcode::PseudoVFSLIDE1UP_VFPR64_M2,
17174 0 : 3332 => Opcode::PseudoVFSLIDE1UP_VFPR64_M2_MASK,
17175 0 : 3333 => Opcode::PseudoVFSLIDE1UP_VFPR64_M4,
17176 0 : 3334 => Opcode::PseudoVFSLIDE1UP_VFPR64_M4_MASK,
17177 0 : 3335 => Opcode::PseudoVFSLIDE1UP_VFPR64_M8,
17178 0 : 3336 => Opcode::PseudoVFSLIDE1UP_VFPR64_M8_MASK,
17179 0 : 3337 => Opcode::PseudoVFSQRT_V_M1_E16,
17180 0 : 3338 => Opcode::PseudoVFSQRT_V_M1_E16_MASK,
17181 0 : 3339 => Opcode::PseudoVFSQRT_V_M1_E32,
17182 0 : 3340 => Opcode::PseudoVFSQRT_V_M1_E32_MASK,
17183 0 : 3341 => Opcode::PseudoVFSQRT_V_M1_E64,
17184 0 : 3342 => Opcode::PseudoVFSQRT_V_M1_E64_MASK,
17185 0 : 3343 => Opcode::PseudoVFSQRT_V_M2_E16,
17186 0 : 3344 => Opcode::PseudoVFSQRT_V_M2_E16_MASK,
17187 0 : 3345 => Opcode::PseudoVFSQRT_V_M2_E32,
17188 0 : 3346 => Opcode::PseudoVFSQRT_V_M2_E32_MASK,
17189 0 : 3347 => Opcode::PseudoVFSQRT_V_M2_E64,
17190 0 : 3348 => Opcode::PseudoVFSQRT_V_M2_E64_MASK,
17191 0 : 3349 => Opcode::PseudoVFSQRT_V_M4_E16,
17192 0 : 3350 => Opcode::PseudoVFSQRT_V_M4_E16_MASK,
17193 0 : 3351 => Opcode::PseudoVFSQRT_V_M4_E32,
17194 0 : 3352 => Opcode::PseudoVFSQRT_V_M4_E32_MASK,
17195 0 : 3353 => Opcode::PseudoVFSQRT_V_M4_E64,
17196 0 : 3354 => Opcode::PseudoVFSQRT_V_M4_E64_MASK,
17197 0 : 3355 => Opcode::PseudoVFSQRT_V_M8_E16,
17198 0 : 3356 => Opcode::PseudoVFSQRT_V_M8_E16_MASK,
17199 0 : 3357 => Opcode::PseudoVFSQRT_V_M8_E32,
17200 0 : 3358 => Opcode::PseudoVFSQRT_V_M8_E32_MASK,
17201 0 : 3359 => Opcode::PseudoVFSQRT_V_M8_E64,
17202 0 : 3360 => Opcode::PseudoVFSQRT_V_M8_E64_MASK,
17203 0 : 3361 => Opcode::PseudoVFSQRT_V_MF2_E16,
17204 0 : 3362 => Opcode::PseudoVFSQRT_V_MF2_E16_MASK,
17205 0 : 3363 => Opcode::PseudoVFSQRT_V_MF2_E32,
17206 0 : 3364 => Opcode::PseudoVFSQRT_V_MF2_E32_MASK,
17207 0 : 3365 => Opcode::PseudoVFSQRT_V_MF4_E16,
17208 0 : 3366 => Opcode::PseudoVFSQRT_V_MF4_E16_MASK,
17209 0 : 3367 => Opcode::PseudoVFSUB_VFPR16_M1_E16,
17210 0 : 3368 => Opcode::PseudoVFSUB_VFPR16_M1_E16_MASK,
17211 0 : 3369 => Opcode::PseudoVFSUB_VFPR16_M2_E16,
17212 0 : 3370 => Opcode::PseudoVFSUB_VFPR16_M2_E16_MASK,
17213 0 : 3371 => Opcode::PseudoVFSUB_VFPR16_M4_E16,
17214 0 : 3372 => Opcode::PseudoVFSUB_VFPR16_M4_E16_MASK,
17215 0 : 3373 => Opcode::PseudoVFSUB_VFPR16_M8_E16,
17216 0 : 3374 => Opcode::PseudoVFSUB_VFPR16_M8_E16_MASK,
17217 0 : 3375 => Opcode::PseudoVFSUB_VFPR16_MF2_E16,
17218 0 : 3376 => Opcode::PseudoVFSUB_VFPR16_MF2_E16_MASK,
17219 0 : 3377 => Opcode::PseudoVFSUB_VFPR16_MF4_E16,
17220 0 : 3378 => Opcode::PseudoVFSUB_VFPR16_MF4_E16_MASK,
17221 0 : 3379 => Opcode::PseudoVFSUB_VFPR32_M1_E32,
17222 0 : 3380 => Opcode::PseudoVFSUB_VFPR32_M1_E32_MASK,
17223 0 : 3381 => Opcode::PseudoVFSUB_VFPR32_M2_E32,
17224 0 : 3382 => Opcode::PseudoVFSUB_VFPR32_M2_E32_MASK,
17225 0 : 3383 => Opcode::PseudoVFSUB_VFPR32_M4_E32,
17226 0 : 3384 => Opcode::PseudoVFSUB_VFPR32_M4_E32_MASK,
17227 0 : 3385 => Opcode::PseudoVFSUB_VFPR32_M8_E32,
17228 0 : 3386 => Opcode::PseudoVFSUB_VFPR32_M8_E32_MASK,
17229 0 : 3387 => Opcode::PseudoVFSUB_VFPR32_MF2_E32,
17230 0 : 3388 => Opcode::PseudoVFSUB_VFPR32_MF2_E32_MASK,
17231 0 : 3389 => Opcode::PseudoVFSUB_VFPR64_M1_E64,
17232 0 : 3390 => Opcode::PseudoVFSUB_VFPR64_M1_E64_MASK,
17233 0 : 3391 => Opcode::PseudoVFSUB_VFPR64_M2_E64,
17234 0 : 3392 => Opcode::PseudoVFSUB_VFPR64_M2_E64_MASK,
17235 0 : 3393 => Opcode::PseudoVFSUB_VFPR64_M4_E64,
17236 0 : 3394 => Opcode::PseudoVFSUB_VFPR64_M4_E64_MASK,
17237 0 : 3395 => Opcode::PseudoVFSUB_VFPR64_M8_E64,
17238 0 : 3396 => Opcode::PseudoVFSUB_VFPR64_M8_E64_MASK,
17239 0 : 3397 => Opcode::PseudoVFSUB_VV_M1_E16,
17240 0 : 3398 => Opcode::PseudoVFSUB_VV_M1_E16_MASK,
17241 0 : 3399 => Opcode::PseudoVFSUB_VV_M1_E32,
17242 0 : 3400 => Opcode::PseudoVFSUB_VV_M1_E32_MASK,
17243 0 : 3401 => Opcode::PseudoVFSUB_VV_M1_E64,
17244 0 : 3402 => Opcode::PseudoVFSUB_VV_M1_E64_MASK,
17245 0 : 3403 => Opcode::PseudoVFSUB_VV_M2_E16,
17246 0 : 3404 => Opcode::PseudoVFSUB_VV_M2_E16_MASK,
17247 0 : 3405 => Opcode::PseudoVFSUB_VV_M2_E32,
17248 0 : 3406 => Opcode::PseudoVFSUB_VV_M2_E32_MASK,
17249 0 : 3407 => Opcode::PseudoVFSUB_VV_M2_E64,
17250 0 : 3408 => Opcode::PseudoVFSUB_VV_M2_E64_MASK,
17251 0 : 3409 => Opcode::PseudoVFSUB_VV_M4_E16,
17252 0 : 3410 => Opcode::PseudoVFSUB_VV_M4_E16_MASK,
17253 0 : 3411 => Opcode::PseudoVFSUB_VV_M4_E32,
17254 0 : 3412 => Opcode::PseudoVFSUB_VV_M4_E32_MASK,
17255 0 : 3413 => Opcode::PseudoVFSUB_VV_M4_E64,
17256 0 : 3414 => Opcode::PseudoVFSUB_VV_M4_E64_MASK,
17257 0 : 3415 => Opcode::PseudoVFSUB_VV_M8_E16,
17258 0 : 3416 => Opcode::PseudoVFSUB_VV_M8_E16_MASK,
17259 0 : 3417 => Opcode::PseudoVFSUB_VV_M8_E32,
17260 0 : 3418 => Opcode::PseudoVFSUB_VV_M8_E32_MASK,
17261 0 : 3419 => Opcode::PseudoVFSUB_VV_M8_E64,
17262 0 : 3420 => Opcode::PseudoVFSUB_VV_M8_E64_MASK,
17263 0 : 3421 => Opcode::PseudoVFSUB_VV_MF2_E16,
17264 0 : 3422 => Opcode::PseudoVFSUB_VV_MF2_E16_MASK,
17265 0 : 3423 => Opcode::PseudoVFSUB_VV_MF2_E32,
17266 0 : 3424 => Opcode::PseudoVFSUB_VV_MF2_E32_MASK,
17267 0 : 3425 => Opcode::PseudoVFSUB_VV_MF4_E16,
17268 0 : 3426 => Opcode::PseudoVFSUB_VV_MF4_E16_MASK,
17269 0 : 3427 => Opcode::PseudoVFWADD_VFPR16_M1_E16,
17270 0 : 3428 => Opcode::PseudoVFWADD_VFPR16_M1_E16_MASK,
17271 0 : 3429 => Opcode::PseudoVFWADD_VFPR16_M2_E16,
17272 0 : 3430 => Opcode::PseudoVFWADD_VFPR16_M2_E16_MASK,
17273 0 : 3431 => Opcode::PseudoVFWADD_VFPR16_M4_E16,
17274 0 : 3432 => Opcode::PseudoVFWADD_VFPR16_M4_E16_MASK,
17275 0 : 3433 => Opcode::PseudoVFWADD_VFPR16_MF2_E16,
17276 0 : 3434 => Opcode::PseudoVFWADD_VFPR16_MF2_E16_MASK,
17277 0 : 3435 => Opcode::PseudoVFWADD_VFPR16_MF4_E16,
17278 0 : 3436 => Opcode::PseudoVFWADD_VFPR16_MF4_E16_MASK,
17279 0 : 3437 => Opcode::PseudoVFWADD_VFPR32_M1_E32,
17280 0 : 3438 => Opcode::PseudoVFWADD_VFPR32_M1_E32_MASK,
17281 0 : 3439 => Opcode::PseudoVFWADD_VFPR32_M2_E32,
17282 0 : 3440 => Opcode::PseudoVFWADD_VFPR32_M2_E32_MASK,
17283 0 : 3441 => Opcode::PseudoVFWADD_VFPR32_M4_E32,
17284 0 : 3442 => Opcode::PseudoVFWADD_VFPR32_M4_E32_MASK,
17285 0 : 3443 => Opcode::PseudoVFWADD_VFPR32_MF2_E32,
17286 0 : 3444 => Opcode::PseudoVFWADD_VFPR32_MF2_E32_MASK,
17287 0 : 3445 => Opcode::PseudoVFWADD_VV_M1_E16,
17288 0 : 3446 => Opcode::PseudoVFWADD_VV_M1_E16_MASK,
17289 0 : 3447 => Opcode::PseudoVFWADD_VV_M1_E32,
17290 0 : 3448 => Opcode::PseudoVFWADD_VV_M1_E32_MASK,
17291 0 : 3449 => Opcode::PseudoVFWADD_VV_M2_E16,
17292 0 : 3450 => Opcode::PseudoVFWADD_VV_M2_E16_MASK,
17293 0 : 3451 => Opcode::PseudoVFWADD_VV_M2_E32,
17294 0 : 3452 => Opcode::PseudoVFWADD_VV_M2_E32_MASK,
17295 0 : 3453 => Opcode::PseudoVFWADD_VV_M4_E16,
17296 0 : 3454 => Opcode::PseudoVFWADD_VV_M4_E16_MASK,
17297 0 : 3455 => Opcode::PseudoVFWADD_VV_M4_E32,
17298 0 : 3456 => Opcode::PseudoVFWADD_VV_M4_E32_MASK,
17299 0 : 3457 => Opcode::PseudoVFWADD_VV_MF2_E16,
17300 0 : 3458 => Opcode::PseudoVFWADD_VV_MF2_E16_MASK,
17301 0 : 3459 => Opcode::PseudoVFWADD_VV_MF2_E32,
17302 0 : 3460 => Opcode::PseudoVFWADD_VV_MF2_E32_MASK,
17303 0 : 3461 => Opcode::PseudoVFWADD_VV_MF4_E16,
17304 0 : 3462 => Opcode::PseudoVFWADD_VV_MF4_E16_MASK,
17305 0 : 3463 => Opcode::PseudoVFWADD_WFPR16_M1_E16,
17306 0 : 3464 => Opcode::PseudoVFWADD_WFPR16_M1_E16_MASK,
17307 0 : 3465 => Opcode::PseudoVFWADD_WFPR16_M2_E16,
17308 0 : 3466 => Opcode::PseudoVFWADD_WFPR16_M2_E16_MASK,
17309 0 : 3467 => Opcode::PseudoVFWADD_WFPR16_M4_E16,
17310 0 : 3468 => Opcode::PseudoVFWADD_WFPR16_M4_E16_MASK,
17311 0 : 3469 => Opcode::PseudoVFWADD_WFPR16_MF2_E16,
17312 0 : 3470 => Opcode::PseudoVFWADD_WFPR16_MF2_E16_MASK,
17313 0 : 3471 => Opcode::PseudoVFWADD_WFPR16_MF4_E16,
17314 0 : 3472 => Opcode::PseudoVFWADD_WFPR16_MF4_E16_MASK,
17315 0 : 3473 => Opcode::PseudoVFWADD_WFPR32_M1_E32,
17316 0 : 3474 => Opcode::PseudoVFWADD_WFPR32_M1_E32_MASK,
17317 0 : 3475 => Opcode::PseudoVFWADD_WFPR32_M2_E32,
17318 0 : 3476 => Opcode::PseudoVFWADD_WFPR32_M2_E32_MASK,
17319 0 : 3477 => Opcode::PseudoVFWADD_WFPR32_M4_E32,
17320 0 : 3478 => Opcode::PseudoVFWADD_WFPR32_M4_E32_MASK,
17321 0 : 3479 => Opcode::PseudoVFWADD_WFPR32_MF2_E32,
17322 0 : 3480 => Opcode::PseudoVFWADD_WFPR32_MF2_E32_MASK,
17323 0 : 3481 => Opcode::PseudoVFWADD_WV_M1_E16,
17324 0 : 3482 => Opcode::PseudoVFWADD_WV_M1_E16_MASK,
17325 0 : 3483 => Opcode::PseudoVFWADD_WV_M1_E16_MASK_TIED,
17326 0 : 3484 => Opcode::PseudoVFWADD_WV_M1_E16_TIED,
17327 0 : 3485 => Opcode::PseudoVFWADD_WV_M1_E32,
17328 0 : 3486 => Opcode::PseudoVFWADD_WV_M1_E32_MASK,
17329 0 : 3487 => Opcode::PseudoVFWADD_WV_M1_E32_MASK_TIED,
17330 0 : 3488 => Opcode::PseudoVFWADD_WV_M1_E32_TIED,
17331 0 : 3489 => Opcode::PseudoVFWADD_WV_M2_E16,
17332 0 : 3490 => Opcode::PseudoVFWADD_WV_M2_E16_MASK,
17333 0 : 3491 => Opcode::PseudoVFWADD_WV_M2_E16_MASK_TIED,
17334 0 : 3492 => Opcode::PseudoVFWADD_WV_M2_E16_TIED,
17335 0 : 3493 => Opcode::PseudoVFWADD_WV_M2_E32,
17336 0 : 3494 => Opcode::PseudoVFWADD_WV_M2_E32_MASK,
17337 0 : 3495 => Opcode::PseudoVFWADD_WV_M2_E32_MASK_TIED,
17338 0 : 3496 => Opcode::PseudoVFWADD_WV_M2_E32_TIED,
17339 0 : 3497 => Opcode::PseudoVFWADD_WV_M4_E16,
17340 0 : 3498 => Opcode::PseudoVFWADD_WV_M4_E16_MASK,
17341 0 : 3499 => Opcode::PseudoVFWADD_WV_M4_E16_MASK_TIED,
17342 0 : 3500 => Opcode::PseudoVFWADD_WV_M4_E16_TIED,
17343 0 : 3501 => Opcode::PseudoVFWADD_WV_M4_E32,
17344 0 : 3502 => Opcode::PseudoVFWADD_WV_M4_E32_MASK,
17345 0 : 3503 => Opcode::PseudoVFWADD_WV_M4_E32_MASK_TIED,
17346 0 : 3504 => Opcode::PseudoVFWADD_WV_M4_E32_TIED,
17347 0 : 3505 => Opcode::PseudoVFWADD_WV_MF2_E16,
17348 0 : 3506 => Opcode::PseudoVFWADD_WV_MF2_E16_MASK,
17349 0 : 3507 => Opcode::PseudoVFWADD_WV_MF2_E16_MASK_TIED,
17350 0 : 3508 => Opcode::PseudoVFWADD_WV_MF2_E16_TIED,
17351 0 : 3509 => Opcode::PseudoVFWADD_WV_MF2_E32,
17352 0 : 3510 => Opcode::PseudoVFWADD_WV_MF2_E32_MASK,
17353 0 : 3511 => Opcode::PseudoVFWADD_WV_MF2_E32_MASK_TIED,
17354 0 : 3512 => Opcode::PseudoVFWADD_WV_MF2_E32_TIED,
17355 0 : 3513 => Opcode::PseudoVFWADD_WV_MF4_E16,
17356 0 : 3514 => Opcode::PseudoVFWADD_WV_MF4_E16_MASK,
17357 0 : 3515 => Opcode::PseudoVFWADD_WV_MF4_E16_MASK_TIED,
17358 0 : 3516 => Opcode::PseudoVFWADD_WV_MF4_E16_TIED,
17359 0 : 3517 => Opcode::PseudoVFWCVTBF16_F_F_V_M1_E16,
17360 0 : 3518 => Opcode::PseudoVFWCVTBF16_F_F_V_M1_E16_MASK,
17361 0 : 3519 => Opcode::PseudoVFWCVTBF16_F_F_V_M1_E32,
17362 0 : 3520 => Opcode::PseudoVFWCVTBF16_F_F_V_M1_E32_MASK,
17363 0 : 3521 => Opcode::PseudoVFWCVTBF16_F_F_V_M2_E16,
17364 0 : 3522 => Opcode::PseudoVFWCVTBF16_F_F_V_M2_E16_MASK,
17365 0 : 3523 => Opcode::PseudoVFWCVTBF16_F_F_V_M2_E32,
17366 0 : 3524 => Opcode::PseudoVFWCVTBF16_F_F_V_M2_E32_MASK,
17367 0 : 3525 => Opcode::PseudoVFWCVTBF16_F_F_V_M4_E16,
17368 0 : 3526 => Opcode::PseudoVFWCVTBF16_F_F_V_M4_E16_MASK,
17369 0 : 3527 => Opcode::PseudoVFWCVTBF16_F_F_V_M4_E32,
17370 0 : 3528 => Opcode::PseudoVFWCVTBF16_F_F_V_M4_E32_MASK,
17371 0 : 3529 => Opcode::PseudoVFWCVTBF16_F_F_V_MF2_E16,
17372 0 : 3530 => Opcode::PseudoVFWCVTBF16_F_F_V_MF2_E16_MASK,
17373 0 : 3531 => Opcode::PseudoVFWCVTBF16_F_F_V_MF2_E32,
17374 0 : 3532 => Opcode::PseudoVFWCVTBF16_F_F_V_MF2_E32_MASK,
17375 0 : 3533 => Opcode::PseudoVFWCVTBF16_F_F_V_MF4_E16,
17376 0 : 3534 => Opcode::PseudoVFWCVTBF16_F_F_V_MF4_E16_MASK,
17377 0 : 3535 => Opcode::PseudoVFWCVT_F_F_V_M1_E16,
17378 0 : 3536 => Opcode::PseudoVFWCVT_F_F_V_M1_E16_MASK,
17379 0 : 3537 => Opcode::PseudoVFWCVT_F_F_V_M1_E32,
17380 0 : 3538 => Opcode::PseudoVFWCVT_F_F_V_M1_E32_MASK,
17381 0 : 3539 => Opcode::PseudoVFWCVT_F_F_V_M2_E16,
17382 0 : 3540 => Opcode::PseudoVFWCVT_F_F_V_M2_E16_MASK,
17383 0 : 3541 => Opcode::PseudoVFWCVT_F_F_V_M2_E32,
17384 0 : 3542 => Opcode::PseudoVFWCVT_F_F_V_M2_E32_MASK,
17385 0 : 3543 => Opcode::PseudoVFWCVT_F_F_V_M4_E16,
17386 0 : 3544 => Opcode::PseudoVFWCVT_F_F_V_M4_E16_MASK,
17387 0 : 3545 => Opcode::PseudoVFWCVT_F_F_V_M4_E32,
17388 0 : 3546 => Opcode::PseudoVFWCVT_F_F_V_M4_E32_MASK,
17389 0 : 3547 => Opcode::PseudoVFWCVT_F_F_V_MF2_E16,
17390 0 : 3548 => Opcode::PseudoVFWCVT_F_F_V_MF2_E16_MASK,
17391 0 : 3549 => Opcode::PseudoVFWCVT_F_F_V_MF2_E32,
17392 0 : 3550 => Opcode::PseudoVFWCVT_F_F_V_MF2_E32_MASK,
17393 0 : 3551 => Opcode::PseudoVFWCVT_F_F_V_MF4_E16,
17394 0 : 3552 => Opcode::PseudoVFWCVT_F_F_V_MF4_E16_MASK,
17395 0 : 3553 => Opcode::PseudoVFWCVT_F_XU_V_M1_E16,
17396 0 : 3554 => Opcode::PseudoVFWCVT_F_XU_V_M1_E16_MASK,
17397 0 : 3555 => Opcode::PseudoVFWCVT_F_XU_V_M1_E32,
17398 0 : 3556 => Opcode::PseudoVFWCVT_F_XU_V_M1_E32_MASK,
17399 0 : 3557 => Opcode::PseudoVFWCVT_F_XU_V_M1_E8,
17400 0 : 3558 => Opcode::PseudoVFWCVT_F_XU_V_M1_E8_MASK,
17401 0 : 3559 => Opcode::PseudoVFWCVT_F_XU_V_M2_E16,
17402 0 : 3560 => Opcode::PseudoVFWCVT_F_XU_V_M2_E16_MASK,
17403 0 : 3561 => Opcode::PseudoVFWCVT_F_XU_V_M2_E32,
17404 0 : 3562 => Opcode::PseudoVFWCVT_F_XU_V_M2_E32_MASK,
17405 0 : 3563 => Opcode::PseudoVFWCVT_F_XU_V_M2_E8,
17406 0 : 3564 => Opcode::PseudoVFWCVT_F_XU_V_M2_E8_MASK,
17407 0 : 3565 => Opcode::PseudoVFWCVT_F_XU_V_M4_E16,
17408 0 : 3566 => Opcode::PseudoVFWCVT_F_XU_V_M4_E16_MASK,
17409 0 : 3567 => Opcode::PseudoVFWCVT_F_XU_V_M4_E32,
17410 0 : 3568 => Opcode::PseudoVFWCVT_F_XU_V_M4_E32_MASK,
17411 0 : 3569 => Opcode::PseudoVFWCVT_F_XU_V_M4_E8,
17412 0 : 3570 => Opcode::PseudoVFWCVT_F_XU_V_M4_E8_MASK,
17413 0 : 3571 => Opcode::PseudoVFWCVT_F_XU_V_MF2_E16,
17414 0 : 3572 => Opcode::PseudoVFWCVT_F_XU_V_MF2_E16_MASK,
17415 0 : 3573 => Opcode::PseudoVFWCVT_F_XU_V_MF2_E32,
17416 0 : 3574 => Opcode::PseudoVFWCVT_F_XU_V_MF2_E32_MASK,
17417 0 : 3575 => Opcode::PseudoVFWCVT_F_XU_V_MF2_E8,
17418 0 : 3576 => Opcode::PseudoVFWCVT_F_XU_V_MF2_E8_MASK,
17419 0 : 3577 => Opcode::PseudoVFWCVT_F_XU_V_MF4_E16,
17420 0 : 3578 => Opcode::PseudoVFWCVT_F_XU_V_MF4_E16_MASK,
17421 0 : 3579 => Opcode::PseudoVFWCVT_F_XU_V_MF4_E8,
17422 0 : 3580 => Opcode::PseudoVFWCVT_F_XU_V_MF4_E8_MASK,
17423 0 : 3581 => Opcode::PseudoVFWCVT_F_XU_V_MF8_E8,
17424 0 : 3582 => Opcode::PseudoVFWCVT_F_XU_V_MF8_E8_MASK,
17425 0 : 3583 => Opcode::PseudoVFWCVT_F_X_V_M1_E16,
17426 0 : 3584 => Opcode::PseudoVFWCVT_F_X_V_M1_E16_MASK,
17427 0 : 3585 => Opcode::PseudoVFWCVT_F_X_V_M1_E32,
17428 0 : 3586 => Opcode::PseudoVFWCVT_F_X_V_M1_E32_MASK,
17429 0 : 3587 => Opcode::PseudoVFWCVT_F_X_V_M1_E8,
17430 0 : 3588 => Opcode::PseudoVFWCVT_F_X_V_M1_E8_MASK,
17431 0 : 3589 => Opcode::PseudoVFWCVT_F_X_V_M2_E16,
17432 0 : 3590 => Opcode::PseudoVFWCVT_F_X_V_M2_E16_MASK,
17433 0 : 3591 => Opcode::PseudoVFWCVT_F_X_V_M2_E32,
17434 0 : 3592 => Opcode::PseudoVFWCVT_F_X_V_M2_E32_MASK,
17435 0 : 3593 => Opcode::PseudoVFWCVT_F_X_V_M2_E8,
17436 0 : 3594 => Opcode::PseudoVFWCVT_F_X_V_M2_E8_MASK,
17437 0 : 3595 => Opcode::PseudoVFWCVT_F_X_V_M4_E16,
17438 0 : 3596 => Opcode::PseudoVFWCVT_F_X_V_M4_E16_MASK,
17439 0 : 3597 => Opcode::PseudoVFWCVT_F_X_V_M4_E32,
17440 0 : 3598 => Opcode::PseudoVFWCVT_F_X_V_M4_E32_MASK,
17441 0 : 3599 => Opcode::PseudoVFWCVT_F_X_V_M4_E8,
17442 0 : 3600 => Opcode::PseudoVFWCVT_F_X_V_M4_E8_MASK,
17443 0 : 3601 => Opcode::PseudoVFWCVT_F_X_V_MF2_E16,
17444 0 : 3602 => Opcode::PseudoVFWCVT_F_X_V_MF2_E16_MASK,
17445 0 : 3603 => Opcode::PseudoVFWCVT_F_X_V_MF2_E32,
17446 0 : 3604 => Opcode::PseudoVFWCVT_F_X_V_MF2_E32_MASK,
17447 0 : 3605 => Opcode::PseudoVFWCVT_F_X_V_MF2_E8,
17448 0 : 3606 => Opcode::PseudoVFWCVT_F_X_V_MF2_E8_MASK,
17449 0 : 3607 => Opcode::PseudoVFWCVT_F_X_V_MF4_E16,
17450 0 : 3608 => Opcode::PseudoVFWCVT_F_X_V_MF4_E16_MASK,
17451 0 : 3609 => Opcode::PseudoVFWCVT_F_X_V_MF4_E8,
17452 0 : 3610 => Opcode::PseudoVFWCVT_F_X_V_MF4_E8_MASK,
17453 0 : 3611 => Opcode::PseudoVFWCVT_F_X_V_MF8_E8,
17454 0 : 3612 => Opcode::PseudoVFWCVT_F_X_V_MF8_E8_MASK,
17455 0 : 3613 => Opcode::PseudoVFWCVT_RM_XU_F_V_M1,
17456 0 : 3614 => Opcode::PseudoVFWCVT_RM_XU_F_V_M1_MASK,
17457 0 : 3615 => Opcode::PseudoVFWCVT_RM_XU_F_V_M2,
17458 0 : 3616 => Opcode::PseudoVFWCVT_RM_XU_F_V_M2_MASK,
17459 0 : 3617 => Opcode::PseudoVFWCVT_RM_XU_F_V_M4,
17460 0 : 3618 => Opcode::PseudoVFWCVT_RM_XU_F_V_M4_MASK,
17461 0 : 3619 => Opcode::PseudoVFWCVT_RM_XU_F_V_MF2,
17462 0 : 3620 => Opcode::PseudoVFWCVT_RM_XU_F_V_MF2_MASK,
17463 0 : 3621 => Opcode::PseudoVFWCVT_RM_XU_F_V_MF4,
17464 0 : 3622 => Opcode::PseudoVFWCVT_RM_XU_F_V_MF4_MASK,
17465 0 : 3623 => Opcode::PseudoVFWCVT_RM_X_F_V_M1,
17466 0 : 3624 => Opcode::PseudoVFWCVT_RM_X_F_V_M1_MASK,
17467 0 : 3625 => Opcode::PseudoVFWCVT_RM_X_F_V_M2,
17468 0 : 3626 => Opcode::PseudoVFWCVT_RM_X_F_V_M2_MASK,
17469 0 : 3627 => Opcode::PseudoVFWCVT_RM_X_F_V_M4,
17470 0 : 3628 => Opcode::PseudoVFWCVT_RM_X_F_V_M4_MASK,
17471 0 : 3629 => Opcode::PseudoVFWCVT_RM_X_F_V_MF2,
17472 0 : 3630 => Opcode::PseudoVFWCVT_RM_X_F_V_MF2_MASK,
17473 0 : 3631 => Opcode::PseudoVFWCVT_RM_X_F_V_MF4,
17474 0 : 3632 => Opcode::PseudoVFWCVT_RM_X_F_V_MF4_MASK,
17475 0 : 3633 => Opcode::PseudoVFWCVT_RTZ_XU_F_V_M1,
17476 0 : 3634 => Opcode::PseudoVFWCVT_RTZ_XU_F_V_M1_MASK,
17477 0 : 3635 => Opcode::PseudoVFWCVT_RTZ_XU_F_V_M2,
17478 0 : 3636 => Opcode::PseudoVFWCVT_RTZ_XU_F_V_M2_MASK,
17479 0 : 3637 => Opcode::PseudoVFWCVT_RTZ_XU_F_V_M4,
17480 0 : 3638 => Opcode::PseudoVFWCVT_RTZ_XU_F_V_M4_MASK,
17481 0 : 3639 => Opcode::PseudoVFWCVT_RTZ_XU_F_V_MF2,
17482 0 : 3640 => Opcode::PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK,
17483 0 : 3641 => Opcode::PseudoVFWCVT_RTZ_XU_F_V_MF4,
17484 0 : 3642 => Opcode::PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK,
17485 0 : 3643 => Opcode::PseudoVFWCVT_RTZ_X_F_V_M1,
17486 0 : 3644 => Opcode::PseudoVFWCVT_RTZ_X_F_V_M1_MASK,
17487 0 : 3645 => Opcode::PseudoVFWCVT_RTZ_X_F_V_M2,
17488 0 : 3646 => Opcode::PseudoVFWCVT_RTZ_X_F_V_M2_MASK,
17489 0 : 3647 => Opcode::PseudoVFWCVT_RTZ_X_F_V_M4,
17490 0 : 3648 => Opcode::PseudoVFWCVT_RTZ_X_F_V_M4_MASK,
17491 0 : 3649 => Opcode::PseudoVFWCVT_RTZ_X_F_V_MF2,
17492 0 : 3650 => Opcode::PseudoVFWCVT_RTZ_X_F_V_MF2_MASK,
17493 0 : 3651 => Opcode::PseudoVFWCVT_RTZ_X_F_V_MF4,
17494 0 : 3652 => Opcode::PseudoVFWCVT_RTZ_X_F_V_MF4_MASK,
17495 0 : 3653 => Opcode::PseudoVFWCVT_XU_F_V_M1,
17496 0 : 3654 => Opcode::PseudoVFWCVT_XU_F_V_M1_MASK,
17497 0 : 3655 => Opcode::PseudoVFWCVT_XU_F_V_M2,
17498 0 : 3656 => Opcode::PseudoVFWCVT_XU_F_V_M2_MASK,
17499 0 : 3657 => Opcode::PseudoVFWCVT_XU_F_V_M4,
17500 0 : 3658 => Opcode::PseudoVFWCVT_XU_F_V_M4_MASK,
17501 0 : 3659 => Opcode::PseudoVFWCVT_XU_F_V_MF2,
17502 0 : 3660 => Opcode::PseudoVFWCVT_XU_F_V_MF2_MASK,
17503 0 : 3661 => Opcode::PseudoVFWCVT_XU_F_V_MF4,
17504 0 : 3662 => Opcode::PseudoVFWCVT_XU_F_V_MF4_MASK,
17505 0 : 3663 => Opcode::PseudoVFWCVT_X_F_V_M1,
17506 0 : 3664 => Opcode::PseudoVFWCVT_X_F_V_M1_MASK,
17507 0 : 3665 => Opcode::PseudoVFWCVT_X_F_V_M2,
17508 0 : 3666 => Opcode::PseudoVFWCVT_X_F_V_M2_MASK,
17509 0 : 3667 => Opcode::PseudoVFWCVT_X_F_V_M4,
17510 0 : 3668 => Opcode::PseudoVFWCVT_X_F_V_M4_MASK,
17511 0 : 3669 => Opcode::PseudoVFWCVT_X_F_V_MF2,
17512 0 : 3670 => Opcode::PseudoVFWCVT_X_F_V_MF2_MASK,
17513 0 : 3671 => Opcode::PseudoVFWCVT_X_F_V_MF4,
17514 0 : 3672 => Opcode::PseudoVFWCVT_X_F_V_MF4_MASK,
17515 0 : 3673 => Opcode::PseudoVFWMACCBF16_VFPR16_M1_E16,
17516 0 : 3674 => Opcode::PseudoVFWMACCBF16_VFPR16_M1_E16_MASK,
17517 0 : 3675 => Opcode::PseudoVFWMACCBF16_VFPR16_M2_E16,
17518 0 : 3676 => Opcode::PseudoVFWMACCBF16_VFPR16_M2_E16_MASK,
17519 0 : 3677 => Opcode::PseudoVFWMACCBF16_VFPR16_M4_E16,
17520 0 : 3678 => Opcode::PseudoVFWMACCBF16_VFPR16_M4_E16_MASK,
17521 0 : 3679 => Opcode::PseudoVFWMACCBF16_VFPR16_MF2_E16,
17522 0 : 3680 => Opcode::PseudoVFWMACCBF16_VFPR16_MF2_E16_MASK,
17523 0 : 3681 => Opcode::PseudoVFWMACCBF16_VFPR16_MF4_E16,
17524 0 : 3682 => Opcode::PseudoVFWMACCBF16_VFPR16_MF4_E16_MASK,
17525 0 : 3683 => Opcode::PseudoVFWMACCBF16_VV_M1_E16,
17526 0 : 3684 => Opcode::PseudoVFWMACCBF16_VV_M1_E16_MASK,
17527 0 : 3685 => Opcode::PseudoVFWMACCBF16_VV_M1_E32,
17528 0 : 3686 => Opcode::PseudoVFWMACCBF16_VV_M1_E32_MASK,
17529 0 : 3687 => Opcode::PseudoVFWMACCBF16_VV_M2_E16,
17530 0 : 3688 => Opcode::PseudoVFWMACCBF16_VV_M2_E16_MASK,
17531 0 : 3689 => Opcode::PseudoVFWMACCBF16_VV_M2_E32,
17532 0 : 3690 => Opcode::PseudoVFWMACCBF16_VV_M2_E32_MASK,
17533 0 : 3691 => Opcode::PseudoVFWMACCBF16_VV_M4_E16,
17534 0 : 3692 => Opcode::PseudoVFWMACCBF16_VV_M4_E16_MASK,
17535 0 : 3693 => Opcode::PseudoVFWMACCBF16_VV_M4_E32,
17536 0 : 3694 => Opcode::PseudoVFWMACCBF16_VV_M4_E32_MASK,
17537 0 : 3695 => Opcode::PseudoVFWMACCBF16_VV_MF2_E16,
17538 0 : 3696 => Opcode::PseudoVFWMACCBF16_VV_MF2_E16_MASK,
17539 0 : 3697 => Opcode::PseudoVFWMACCBF16_VV_MF2_E32,
17540 0 : 3698 => Opcode::PseudoVFWMACCBF16_VV_MF2_E32_MASK,
17541 0 : 3699 => Opcode::PseudoVFWMACCBF16_VV_MF4_E16,
17542 0 : 3700 => Opcode::PseudoVFWMACCBF16_VV_MF4_E16_MASK,
17543 0 : 3701 => Opcode::PseudoVFWMACC_4x4x4_M1,
17544 0 : 3702 => Opcode::PseudoVFWMACC_4x4x4_M2,
17545 0 : 3703 => Opcode::PseudoVFWMACC_4x4x4_M4,
17546 0 : 3704 => Opcode::PseudoVFWMACC_4x4x4_M8,
17547 0 : 3705 => Opcode::PseudoVFWMACC_4x4x4_MF2,
17548 0 : 3706 => Opcode::PseudoVFWMACC_4x4x4_MF4,
17549 0 : 3707 => Opcode::PseudoVFWMACC_VFPR16_M1_E16,
17550 0 : 3708 => Opcode::PseudoVFWMACC_VFPR16_M1_E16_MASK,
17551 0 : 3709 => Opcode::PseudoVFWMACC_VFPR16_M2_E16,
17552 0 : 3710 => Opcode::PseudoVFWMACC_VFPR16_M2_E16_MASK,
17553 0 : 3711 => Opcode::PseudoVFWMACC_VFPR16_M4_E16,
17554 0 : 3712 => Opcode::PseudoVFWMACC_VFPR16_M4_E16_MASK,
17555 0 : 3713 => Opcode::PseudoVFWMACC_VFPR16_MF2_E16,
17556 0 : 3714 => Opcode::PseudoVFWMACC_VFPR16_MF2_E16_MASK,
17557 0 : 3715 => Opcode::PseudoVFWMACC_VFPR16_MF4_E16,
17558 0 : 3716 => Opcode::PseudoVFWMACC_VFPR16_MF4_E16_MASK,
17559 0 : 3717 => Opcode::PseudoVFWMACC_VFPR32_M1_E32,
17560 0 : 3718 => Opcode::PseudoVFWMACC_VFPR32_M1_E32_MASK,
17561 0 : 3719 => Opcode::PseudoVFWMACC_VFPR32_M2_E32,
17562 0 : 3720 => Opcode::PseudoVFWMACC_VFPR32_M2_E32_MASK,
17563 0 : 3721 => Opcode::PseudoVFWMACC_VFPR32_M4_E32,
17564 0 : 3722 => Opcode::PseudoVFWMACC_VFPR32_M4_E32_MASK,
17565 0 : 3723 => Opcode::PseudoVFWMACC_VFPR32_MF2_E32,
17566 0 : 3724 => Opcode::PseudoVFWMACC_VFPR32_MF2_E32_MASK,
17567 0 : 3725 => Opcode::PseudoVFWMACC_VV_M1_E16,
17568 0 : 3726 => Opcode::PseudoVFWMACC_VV_M1_E16_MASK,
17569 0 : 3727 => Opcode::PseudoVFWMACC_VV_M1_E32,
17570 0 : 3728 => Opcode::PseudoVFWMACC_VV_M1_E32_MASK,
17571 0 : 3729 => Opcode::PseudoVFWMACC_VV_M2_E16,
17572 0 : 3730 => Opcode::PseudoVFWMACC_VV_M2_E16_MASK,
17573 0 : 3731 => Opcode::PseudoVFWMACC_VV_M2_E32,
17574 0 : 3732 => Opcode::PseudoVFWMACC_VV_M2_E32_MASK,
17575 0 : 3733 => Opcode::PseudoVFWMACC_VV_M4_E16,
17576 0 : 3734 => Opcode::PseudoVFWMACC_VV_M4_E16_MASK,
17577 0 : 3735 => Opcode::PseudoVFWMACC_VV_M4_E32,
17578 0 : 3736 => Opcode::PseudoVFWMACC_VV_M4_E32_MASK,
17579 0 : 3737 => Opcode::PseudoVFWMACC_VV_MF2_E16,
17580 0 : 3738 => Opcode::PseudoVFWMACC_VV_MF2_E16_MASK,
17581 0 : 3739 => Opcode::PseudoVFWMACC_VV_MF2_E32,
17582 0 : 3740 => Opcode::PseudoVFWMACC_VV_MF2_E32_MASK,
17583 0 : 3741 => Opcode::PseudoVFWMACC_VV_MF4_E16,
17584 0 : 3742 => Opcode::PseudoVFWMACC_VV_MF4_E16_MASK,
17585 0 : 3743 => Opcode::PseudoVFWMSAC_VFPR16_M1_E16,
17586 0 : 3744 => Opcode::PseudoVFWMSAC_VFPR16_M1_E16_MASK,
17587 0 : 3745 => Opcode::PseudoVFWMSAC_VFPR16_M2_E16,
17588 0 : 3746 => Opcode::PseudoVFWMSAC_VFPR16_M2_E16_MASK,
17589 0 : 3747 => Opcode::PseudoVFWMSAC_VFPR16_M4_E16,
17590 0 : 3748 => Opcode::PseudoVFWMSAC_VFPR16_M4_E16_MASK,
17591 0 : 3749 => Opcode::PseudoVFWMSAC_VFPR16_MF2_E16,
17592 0 : 3750 => Opcode::PseudoVFWMSAC_VFPR16_MF2_E16_MASK,
17593 0 : 3751 => Opcode::PseudoVFWMSAC_VFPR16_MF4_E16,
17594 0 : 3752 => Opcode::PseudoVFWMSAC_VFPR16_MF4_E16_MASK,
17595 0 : 3753 => Opcode::PseudoVFWMSAC_VFPR32_M1_E32,
17596 0 : 3754 => Opcode::PseudoVFWMSAC_VFPR32_M1_E32_MASK,
17597 0 : 3755 => Opcode::PseudoVFWMSAC_VFPR32_M2_E32,
17598 0 : 3756 => Opcode::PseudoVFWMSAC_VFPR32_M2_E32_MASK,
17599 0 : 3757 => Opcode::PseudoVFWMSAC_VFPR32_M4_E32,
17600 0 : 3758 => Opcode::PseudoVFWMSAC_VFPR32_M4_E32_MASK,
17601 0 : 3759 => Opcode::PseudoVFWMSAC_VFPR32_MF2_E32,
17602 0 : 3760 => Opcode::PseudoVFWMSAC_VFPR32_MF2_E32_MASK,
17603 0 : 3761 => Opcode::PseudoVFWMSAC_VV_M1_E16,
17604 0 : 3762 => Opcode::PseudoVFWMSAC_VV_M1_E16_MASK,
17605 0 : 3763 => Opcode::PseudoVFWMSAC_VV_M1_E32,
17606 0 : 3764 => Opcode::PseudoVFWMSAC_VV_M1_E32_MASK,
17607 0 : 3765 => Opcode::PseudoVFWMSAC_VV_M2_E16,
17608 0 : 3766 => Opcode::PseudoVFWMSAC_VV_M2_E16_MASK,
17609 0 : 3767 => Opcode::PseudoVFWMSAC_VV_M2_E32,
17610 0 : 3768 => Opcode::PseudoVFWMSAC_VV_M2_E32_MASK,
17611 0 : 3769 => Opcode::PseudoVFWMSAC_VV_M4_E16,
17612 0 : 3770 => Opcode::PseudoVFWMSAC_VV_M4_E16_MASK,
17613 0 : 3771 => Opcode::PseudoVFWMSAC_VV_M4_E32,
17614 0 : 3772 => Opcode::PseudoVFWMSAC_VV_M4_E32_MASK,
17615 0 : 3773 => Opcode::PseudoVFWMSAC_VV_MF2_E16,
17616 0 : 3774 => Opcode::PseudoVFWMSAC_VV_MF2_E16_MASK,
17617 0 : 3775 => Opcode::PseudoVFWMSAC_VV_MF2_E32,
17618 0 : 3776 => Opcode::PseudoVFWMSAC_VV_MF2_E32_MASK,
17619 0 : 3777 => Opcode::PseudoVFWMSAC_VV_MF4_E16,
17620 0 : 3778 => Opcode::PseudoVFWMSAC_VV_MF4_E16_MASK,
17621 0 : 3779 => Opcode::PseudoVFWMUL_VFPR16_M1_E16,
17622 0 : 3780 => Opcode::PseudoVFWMUL_VFPR16_M1_E16_MASK,
17623 0 : 3781 => Opcode::PseudoVFWMUL_VFPR16_M2_E16,
17624 0 : 3782 => Opcode::PseudoVFWMUL_VFPR16_M2_E16_MASK,
17625 0 : 3783 => Opcode::PseudoVFWMUL_VFPR16_M4_E16,
17626 0 : 3784 => Opcode::PseudoVFWMUL_VFPR16_M4_E16_MASK,
17627 0 : 3785 => Opcode::PseudoVFWMUL_VFPR16_MF2_E16,
17628 0 : 3786 => Opcode::PseudoVFWMUL_VFPR16_MF2_E16_MASK,
17629 0 : 3787 => Opcode::PseudoVFWMUL_VFPR16_MF4_E16,
17630 0 : 3788 => Opcode::PseudoVFWMUL_VFPR16_MF4_E16_MASK,
17631 0 : 3789 => Opcode::PseudoVFWMUL_VFPR32_M1_E32,
17632 0 : 3790 => Opcode::PseudoVFWMUL_VFPR32_M1_E32_MASK,
17633 0 : 3791 => Opcode::PseudoVFWMUL_VFPR32_M2_E32,
17634 0 : 3792 => Opcode::PseudoVFWMUL_VFPR32_M2_E32_MASK,
17635 0 : 3793 => Opcode::PseudoVFWMUL_VFPR32_M4_E32,
17636 0 : 3794 => Opcode::PseudoVFWMUL_VFPR32_M4_E32_MASK,
17637 0 : 3795 => Opcode::PseudoVFWMUL_VFPR32_MF2_E32,
17638 0 : 3796 => Opcode::PseudoVFWMUL_VFPR32_MF2_E32_MASK,
17639 0 : 3797 => Opcode::PseudoVFWMUL_VV_M1_E16,
17640 0 : 3798 => Opcode::PseudoVFWMUL_VV_M1_E16_MASK,
17641 0 : 3799 => Opcode::PseudoVFWMUL_VV_M1_E32,
17642 0 : 3800 => Opcode::PseudoVFWMUL_VV_M1_E32_MASK,
17643 0 : 3801 => Opcode::PseudoVFWMUL_VV_M2_E16,
17644 0 : 3802 => Opcode::PseudoVFWMUL_VV_M2_E16_MASK,
17645 0 : 3803 => Opcode::PseudoVFWMUL_VV_M2_E32,
17646 0 : 3804 => Opcode::PseudoVFWMUL_VV_M2_E32_MASK,
17647 0 : 3805 => Opcode::PseudoVFWMUL_VV_M4_E16,
17648 0 : 3806 => Opcode::PseudoVFWMUL_VV_M4_E16_MASK,
17649 0 : 3807 => Opcode::PseudoVFWMUL_VV_M4_E32,
17650 0 : 3808 => Opcode::PseudoVFWMUL_VV_M4_E32_MASK,
17651 0 : 3809 => Opcode::PseudoVFWMUL_VV_MF2_E16,
17652 0 : 3810 => Opcode::PseudoVFWMUL_VV_MF2_E16_MASK,
17653 0 : 3811 => Opcode::PseudoVFWMUL_VV_MF2_E32,
17654 0 : 3812 => Opcode::PseudoVFWMUL_VV_MF2_E32_MASK,
17655 0 : 3813 => Opcode::PseudoVFWMUL_VV_MF4_E16,
17656 0 : 3814 => Opcode::PseudoVFWMUL_VV_MF4_E16_MASK,
17657 0 : 3815 => Opcode::PseudoVFWNMACC_VFPR16_M1_E16,
17658 0 : 3816 => Opcode::PseudoVFWNMACC_VFPR16_M1_E16_MASK,
17659 0 : 3817 => Opcode::PseudoVFWNMACC_VFPR16_M2_E16,
17660 0 : 3818 => Opcode::PseudoVFWNMACC_VFPR16_M2_E16_MASK,
17661 0 : 3819 => Opcode::PseudoVFWNMACC_VFPR16_M4_E16,
17662 0 : 3820 => Opcode::PseudoVFWNMACC_VFPR16_M4_E16_MASK,
17663 0 : 3821 => Opcode::PseudoVFWNMACC_VFPR16_MF2_E16,
17664 0 : 3822 => Opcode::PseudoVFWNMACC_VFPR16_MF2_E16_MASK,
17665 0 : 3823 => Opcode::PseudoVFWNMACC_VFPR16_MF4_E16,
17666 0 : 3824 => Opcode::PseudoVFWNMACC_VFPR16_MF4_E16_MASK,
17667 0 : 3825 => Opcode::PseudoVFWNMACC_VFPR32_M1_E32,
17668 0 : 3826 => Opcode::PseudoVFWNMACC_VFPR32_M1_E32_MASK,
17669 0 : 3827 => Opcode::PseudoVFWNMACC_VFPR32_M2_E32,
17670 0 : 3828 => Opcode::PseudoVFWNMACC_VFPR32_M2_E32_MASK,
17671 0 : 3829 => Opcode::PseudoVFWNMACC_VFPR32_M4_E32,
17672 0 : 3830 => Opcode::PseudoVFWNMACC_VFPR32_M4_E32_MASK,
17673 0 : 3831 => Opcode::PseudoVFWNMACC_VFPR32_MF2_E32,
17674 0 : 3832 => Opcode::PseudoVFWNMACC_VFPR32_MF2_E32_MASK,
17675 0 : 3833 => Opcode::PseudoVFWNMACC_VV_M1_E16,
17676 0 : 3834 => Opcode::PseudoVFWNMACC_VV_M1_E16_MASK,
17677 0 : 3835 => Opcode::PseudoVFWNMACC_VV_M1_E32,
17678 0 : 3836 => Opcode::PseudoVFWNMACC_VV_M1_E32_MASK,
17679 0 : 3837 => Opcode::PseudoVFWNMACC_VV_M2_E16,
17680 0 : 3838 => Opcode::PseudoVFWNMACC_VV_M2_E16_MASK,
17681 0 : 3839 => Opcode::PseudoVFWNMACC_VV_M2_E32,
17682 0 : 3840 => Opcode::PseudoVFWNMACC_VV_M2_E32_MASK,
17683 0 : 3841 => Opcode::PseudoVFWNMACC_VV_M4_E16,
17684 0 : 3842 => Opcode::PseudoVFWNMACC_VV_M4_E16_MASK,
17685 0 : 3843 => Opcode::PseudoVFWNMACC_VV_M4_E32,
17686 0 : 3844 => Opcode::PseudoVFWNMACC_VV_M4_E32_MASK,
17687 0 : 3845 => Opcode::PseudoVFWNMACC_VV_MF2_E16,
17688 0 : 3846 => Opcode::PseudoVFWNMACC_VV_MF2_E16_MASK,
17689 0 : 3847 => Opcode::PseudoVFWNMACC_VV_MF2_E32,
17690 0 : 3848 => Opcode::PseudoVFWNMACC_VV_MF2_E32_MASK,
17691 0 : 3849 => Opcode::PseudoVFWNMACC_VV_MF4_E16,
17692 0 : 3850 => Opcode::PseudoVFWNMACC_VV_MF4_E16_MASK,
17693 0 : 3851 => Opcode::PseudoVFWNMSAC_VFPR16_M1_E16,
17694 0 : 3852 => Opcode::PseudoVFWNMSAC_VFPR16_M1_E16_MASK,
17695 0 : 3853 => Opcode::PseudoVFWNMSAC_VFPR16_M2_E16,
17696 0 : 3854 => Opcode::PseudoVFWNMSAC_VFPR16_M2_E16_MASK,
17697 0 : 3855 => Opcode::PseudoVFWNMSAC_VFPR16_M4_E16,
17698 0 : 3856 => Opcode::PseudoVFWNMSAC_VFPR16_M4_E16_MASK,
17699 0 : 3857 => Opcode::PseudoVFWNMSAC_VFPR16_MF2_E16,
17700 0 : 3858 => Opcode::PseudoVFWNMSAC_VFPR16_MF2_E16_MASK,
17701 0 : 3859 => Opcode::PseudoVFWNMSAC_VFPR16_MF4_E16,
17702 0 : 3860 => Opcode::PseudoVFWNMSAC_VFPR16_MF4_E16_MASK,
17703 0 : 3861 => Opcode::PseudoVFWNMSAC_VFPR32_M1_E32,
17704 0 : 3862 => Opcode::PseudoVFWNMSAC_VFPR32_M1_E32_MASK,
17705 0 : 3863 => Opcode::PseudoVFWNMSAC_VFPR32_M2_E32,
17706 0 : 3864 => Opcode::PseudoVFWNMSAC_VFPR32_M2_E32_MASK,
17707 0 : 3865 => Opcode::PseudoVFWNMSAC_VFPR32_M4_E32,
17708 0 : 3866 => Opcode::PseudoVFWNMSAC_VFPR32_M4_E32_MASK,
17709 0 : 3867 => Opcode::PseudoVFWNMSAC_VFPR32_MF2_E32,
17710 0 : 3868 => Opcode::PseudoVFWNMSAC_VFPR32_MF2_E32_MASK,
17711 0 : 3869 => Opcode::PseudoVFWNMSAC_VV_M1_E16,
17712 0 : 3870 => Opcode::PseudoVFWNMSAC_VV_M1_E16_MASK,
17713 0 : 3871 => Opcode::PseudoVFWNMSAC_VV_M1_E32,
17714 0 : 3872 => Opcode::PseudoVFWNMSAC_VV_M1_E32_MASK,
17715 0 : 3873 => Opcode::PseudoVFWNMSAC_VV_M2_E16,
17716 0 : 3874 => Opcode::PseudoVFWNMSAC_VV_M2_E16_MASK,
17717 0 : 3875 => Opcode::PseudoVFWNMSAC_VV_M2_E32,
17718 0 : 3876 => Opcode::PseudoVFWNMSAC_VV_M2_E32_MASK,
17719 0 : 3877 => Opcode::PseudoVFWNMSAC_VV_M4_E16,
17720 0 : 3878 => Opcode::PseudoVFWNMSAC_VV_M4_E16_MASK,
17721 0 : 3879 => Opcode::PseudoVFWNMSAC_VV_M4_E32,
17722 0 : 3880 => Opcode::PseudoVFWNMSAC_VV_M4_E32_MASK,
17723 0 : 3881 => Opcode::PseudoVFWNMSAC_VV_MF2_E16,
17724 0 : 3882 => Opcode::PseudoVFWNMSAC_VV_MF2_E16_MASK,
17725 0 : 3883 => Opcode::PseudoVFWNMSAC_VV_MF2_E32,
17726 0 : 3884 => Opcode::PseudoVFWNMSAC_VV_MF2_E32_MASK,
17727 0 : 3885 => Opcode::PseudoVFWNMSAC_VV_MF4_E16,
17728 0 : 3886 => Opcode::PseudoVFWNMSAC_VV_MF4_E16_MASK,
17729 0 : 3887 => Opcode::PseudoVFWREDOSUM_VS_M1_E16,
17730 0 : 3888 => Opcode::PseudoVFWREDOSUM_VS_M1_E16_MASK,
17731 0 : 3889 => Opcode::PseudoVFWREDOSUM_VS_M1_E32,
17732 0 : 3890 => Opcode::PseudoVFWREDOSUM_VS_M1_E32_MASK,
17733 0 : 3891 => Opcode::PseudoVFWREDOSUM_VS_M2_E16,
17734 0 : 3892 => Opcode::PseudoVFWREDOSUM_VS_M2_E16_MASK,
17735 0 : 3893 => Opcode::PseudoVFWREDOSUM_VS_M2_E32,
17736 0 : 3894 => Opcode::PseudoVFWREDOSUM_VS_M2_E32_MASK,
17737 0 : 3895 => Opcode::PseudoVFWREDOSUM_VS_M4_E16,
17738 0 : 3896 => Opcode::PseudoVFWREDOSUM_VS_M4_E16_MASK,
17739 0 : 3897 => Opcode::PseudoVFWREDOSUM_VS_M4_E32,
17740 0 : 3898 => Opcode::PseudoVFWREDOSUM_VS_M4_E32_MASK,
17741 0 : 3899 => Opcode::PseudoVFWREDOSUM_VS_M8_E16,
17742 0 : 3900 => Opcode::PseudoVFWREDOSUM_VS_M8_E16_MASK,
17743 0 : 3901 => Opcode::PseudoVFWREDOSUM_VS_M8_E32,
17744 0 : 3902 => Opcode::PseudoVFWREDOSUM_VS_M8_E32_MASK,
17745 0 : 3903 => Opcode::PseudoVFWREDOSUM_VS_MF2_E16,
17746 0 : 3904 => Opcode::PseudoVFWREDOSUM_VS_MF2_E16_MASK,
17747 0 : 3905 => Opcode::PseudoVFWREDOSUM_VS_MF2_E32,
17748 0 : 3906 => Opcode::PseudoVFWREDOSUM_VS_MF2_E32_MASK,
17749 0 : 3907 => Opcode::PseudoVFWREDOSUM_VS_MF4_E16,
17750 0 : 3908 => Opcode::PseudoVFWREDOSUM_VS_MF4_E16_MASK,
17751 0 : 3909 => Opcode::PseudoVFWREDUSUM_VS_M1_E16,
17752 0 : 3910 => Opcode::PseudoVFWREDUSUM_VS_M1_E16_MASK,
17753 0 : 3911 => Opcode::PseudoVFWREDUSUM_VS_M1_E32,
17754 0 : 3912 => Opcode::PseudoVFWREDUSUM_VS_M1_E32_MASK,
17755 0 : 3913 => Opcode::PseudoVFWREDUSUM_VS_M2_E16,
17756 0 : 3914 => Opcode::PseudoVFWREDUSUM_VS_M2_E16_MASK,
17757 0 : 3915 => Opcode::PseudoVFWREDUSUM_VS_M2_E32,
17758 0 : 3916 => Opcode::PseudoVFWREDUSUM_VS_M2_E32_MASK,
17759 0 : 3917 => Opcode::PseudoVFWREDUSUM_VS_M4_E16,
17760 0 : 3918 => Opcode::PseudoVFWREDUSUM_VS_M4_E16_MASK,
17761 0 : 3919 => Opcode::PseudoVFWREDUSUM_VS_M4_E32,
17762 0 : 3920 => Opcode::PseudoVFWREDUSUM_VS_M4_E32_MASK,
17763 0 : 3921 => Opcode::PseudoVFWREDUSUM_VS_M8_E16,
17764 0 : 3922 => Opcode::PseudoVFWREDUSUM_VS_M8_E16_MASK,
17765 0 : 3923 => Opcode::PseudoVFWREDUSUM_VS_M8_E32,
17766 0 : 3924 => Opcode::PseudoVFWREDUSUM_VS_M8_E32_MASK,
17767 0 : 3925 => Opcode::PseudoVFWREDUSUM_VS_MF2_E16,
17768 0 : 3926 => Opcode::PseudoVFWREDUSUM_VS_MF2_E16_MASK,
17769 0 : 3927 => Opcode::PseudoVFWREDUSUM_VS_MF2_E32,
17770 0 : 3928 => Opcode::PseudoVFWREDUSUM_VS_MF2_E32_MASK,
17771 0 : 3929 => Opcode::PseudoVFWREDUSUM_VS_MF4_E16,
17772 0 : 3930 => Opcode::PseudoVFWREDUSUM_VS_MF4_E16_MASK,
17773 0 : 3931 => Opcode::PseudoVFWSUB_VFPR16_M1_E16,
17774 0 : 3932 => Opcode::PseudoVFWSUB_VFPR16_M1_E16_MASK,
17775 0 : 3933 => Opcode::PseudoVFWSUB_VFPR16_M2_E16,
17776 0 : 3934 => Opcode::PseudoVFWSUB_VFPR16_M2_E16_MASK,
17777 0 : 3935 => Opcode::PseudoVFWSUB_VFPR16_M4_E16,
17778 0 : 3936 => Opcode::PseudoVFWSUB_VFPR16_M4_E16_MASK,
17779 0 : 3937 => Opcode::PseudoVFWSUB_VFPR16_MF2_E16,
17780 0 : 3938 => Opcode::PseudoVFWSUB_VFPR16_MF2_E16_MASK,
17781 0 : 3939 => Opcode::PseudoVFWSUB_VFPR16_MF4_E16,
17782 0 : 3940 => Opcode::PseudoVFWSUB_VFPR16_MF4_E16_MASK,
17783 0 : 3941 => Opcode::PseudoVFWSUB_VFPR32_M1_E32,
17784 0 : 3942 => Opcode::PseudoVFWSUB_VFPR32_M1_E32_MASK,
17785 0 : 3943 => Opcode::PseudoVFWSUB_VFPR32_M2_E32,
17786 0 : 3944 => Opcode::PseudoVFWSUB_VFPR32_M2_E32_MASK,
17787 0 : 3945 => Opcode::PseudoVFWSUB_VFPR32_M4_E32,
17788 0 : 3946 => Opcode::PseudoVFWSUB_VFPR32_M4_E32_MASK,
17789 0 : 3947 => Opcode::PseudoVFWSUB_VFPR32_MF2_E32,
17790 0 : 3948 => Opcode::PseudoVFWSUB_VFPR32_MF2_E32_MASK,
17791 0 : 3949 => Opcode::PseudoVFWSUB_VV_M1_E16,
17792 0 : 3950 => Opcode::PseudoVFWSUB_VV_M1_E16_MASK,
17793 0 : 3951 => Opcode::PseudoVFWSUB_VV_M1_E32,
17794 0 : 3952 => Opcode::PseudoVFWSUB_VV_M1_E32_MASK,
17795 0 : 3953 => Opcode::PseudoVFWSUB_VV_M2_E16,
17796 0 : 3954 => Opcode::PseudoVFWSUB_VV_M2_E16_MASK,
17797 0 : 3955 => Opcode::PseudoVFWSUB_VV_M2_E32,
17798 0 : 3956 => Opcode::PseudoVFWSUB_VV_M2_E32_MASK,
17799 0 : 3957 => Opcode::PseudoVFWSUB_VV_M4_E16,
17800 0 : 3958 => Opcode::PseudoVFWSUB_VV_M4_E16_MASK,
17801 0 : 3959 => Opcode::PseudoVFWSUB_VV_M4_E32,
17802 0 : 3960 => Opcode::PseudoVFWSUB_VV_M4_E32_MASK,
17803 0 : 3961 => Opcode::PseudoVFWSUB_VV_MF2_E16,
17804 0 : 3962 => Opcode::PseudoVFWSUB_VV_MF2_E16_MASK,
17805 0 : 3963 => Opcode::PseudoVFWSUB_VV_MF2_E32,
17806 0 : 3964 => Opcode::PseudoVFWSUB_VV_MF2_E32_MASK,
17807 0 : 3965 => Opcode::PseudoVFWSUB_VV_MF4_E16,
17808 0 : 3966 => Opcode::PseudoVFWSUB_VV_MF4_E16_MASK,
17809 0 : 3967 => Opcode::PseudoVFWSUB_WFPR16_M1_E16,
17810 0 : 3968 => Opcode::PseudoVFWSUB_WFPR16_M1_E16_MASK,
17811 0 : 3969 => Opcode::PseudoVFWSUB_WFPR16_M2_E16,
17812 0 : 3970 => Opcode::PseudoVFWSUB_WFPR16_M2_E16_MASK,
17813 0 : 3971 => Opcode::PseudoVFWSUB_WFPR16_M4_E16,
17814 0 : 3972 => Opcode::PseudoVFWSUB_WFPR16_M4_E16_MASK,
17815 0 : 3973 => Opcode::PseudoVFWSUB_WFPR16_MF2_E16,
17816 0 : 3974 => Opcode::PseudoVFWSUB_WFPR16_MF2_E16_MASK,
17817 0 : 3975 => Opcode::PseudoVFWSUB_WFPR16_MF4_E16,
17818 0 : 3976 => Opcode::PseudoVFWSUB_WFPR16_MF4_E16_MASK,
17819 0 : 3977 => Opcode::PseudoVFWSUB_WFPR32_M1_E32,
17820 0 : 3978 => Opcode::PseudoVFWSUB_WFPR32_M1_E32_MASK,
17821 0 : 3979 => Opcode::PseudoVFWSUB_WFPR32_M2_E32,
17822 0 : 3980 => Opcode::PseudoVFWSUB_WFPR32_M2_E32_MASK,
17823 0 : 3981 => Opcode::PseudoVFWSUB_WFPR32_M4_E32,
17824 0 : 3982 => Opcode::PseudoVFWSUB_WFPR32_M4_E32_MASK,
17825 0 : 3983 => Opcode::PseudoVFWSUB_WFPR32_MF2_E32,
17826 0 : 3984 => Opcode::PseudoVFWSUB_WFPR32_MF2_E32_MASK,
17827 0 : 3985 => Opcode::PseudoVFWSUB_WV_M1_E16,
17828 0 : 3986 => Opcode::PseudoVFWSUB_WV_M1_E16_MASK,
17829 0 : 3987 => Opcode::PseudoVFWSUB_WV_M1_E16_MASK_TIED,
17830 0 : 3988 => Opcode::PseudoVFWSUB_WV_M1_E16_TIED,
17831 0 : 3989 => Opcode::PseudoVFWSUB_WV_M1_E32,
17832 0 : 3990 => Opcode::PseudoVFWSUB_WV_M1_E32_MASK,
17833 0 : 3991 => Opcode::PseudoVFWSUB_WV_M1_E32_MASK_TIED,
17834 0 : 3992 => Opcode::PseudoVFWSUB_WV_M1_E32_TIED,
17835 0 : 3993 => Opcode::PseudoVFWSUB_WV_M2_E16,
17836 0 : 3994 => Opcode::PseudoVFWSUB_WV_M2_E16_MASK,
17837 0 : 3995 => Opcode::PseudoVFWSUB_WV_M2_E16_MASK_TIED,
17838 0 : 3996 => Opcode::PseudoVFWSUB_WV_M2_E16_TIED,
17839 0 : 3997 => Opcode::PseudoVFWSUB_WV_M2_E32,
17840 0 : 3998 => Opcode::PseudoVFWSUB_WV_M2_E32_MASK,
17841 0 : 3999 => Opcode::PseudoVFWSUB_WV_M2_E32_MASK_TIED,
17842 0 : 4000 => Opcode::PseudoVFWSUB_WV_M2_E32_TIED,
17843 0 : 4001 => Opcode::PseudoVFWSUB_WV_M4_E16,
17844 0 : 4002 => Opcode::PseudoVFWSUB_WV_M4_E16_MASK,
17845 0 : 4003 => Opcode::PseudoVFWSUB_WV_M4_E16_MASK_TIED,
17846 0 : 4004 => Opcode::PseudoVFWSUB_WV_M4_E16_TIED,
17847 0 : 4005 => Opcode::PseudoVFWSUB_WV_M4_E32,
17848 0 : 4006 => Opcode::PseudoVFWSUB_WV_M4_E32_MASK,
17849 0 : 4007 => Opcode::PseudoVFWSUB_WV_M4_E32_MASK_TIED,
17850 0 : 4008 => Opcode::PseudoVFWSUB_WV_M4_E32_TIED,
17851 0 : 4009 => Opcode::PseudoVFWSUB_WV_MF2_E16,
17852 0 : 4010 => Opcode::PseudoVFWSUB_WV_MF2_E16_MASK,
17853 0 : 4011 => Opcode::PseudoVFWSUB_WV_MF2_E16_MASK_TIED,
17854 0 : 4012 => Opcode::PseudoVFWSUB_WV_MF2_E16_TIED,
17855 0 : 4013 => Opcode::PseudoVFWSUB_WV_MF2_E32,
17856 0 : 4014 => Opcode::PseudoVFWSUB_WV_MF2_E32_MASK,
17857 0 : 4015 => Opcode::PseudoVFWSUB_WV_MF2_E32_MASK_TIED,
17858 0 : 4016 => Opcode::PseudoVFWSUB_WV_MF2_E32_TIED,
17859 0 : 4017 => Opcode::PseudoVFWSUB_WV_MF4_E16,
17860 0 : 4018 => Opcode::PseudoVFWSUB_WV_MF4_E16_MASK,
17861 0 : 4019 => Opcode::PseudoVFWSUB_WV_MF4_E16_MASK_TIED,
17862 0 : 4020 => Opcode::PseudoVFWSUB_WV_MF4_E16_TIED,
17863 0 : 4021 => Opcode::PseudoVGHSH_VV_M1,
17864 0 : 4022 => Opcode::PseudoVGHSH_VV_M2,
17865 0 : 4023 => Opcode::PseudoVGHSH_VV_M4,
17866 0 : 4024 => Opcode::PseudoVGHSH_VV_M8,
17867 0 : 4025 => Opcode::PseudoVGHSH_VV_MF2,
17868 0 : 4026 => Opcode::PseudoVGMUL_VV_M1,
17869 0 : 4027 => Opcode::PseudoVGMUL_VV_M2,
17870 0 : 4028 => Opcode::PseudoVGMUL_VV_M4,
17871 0 : 4029 => Opcode::PseudoVGMUL_VV_M8,
17872 0 : 4030 => Opcode::PseudoVGMUL_VV_MF2,
17873 0 : 4031 => Opcode::PseudoVID_V_M1,
17874 0 : 4032 => Opcode::PseudoVID_V_M1_MASK,
17875 0 : 4033 => Opcode::PseudoVID_V_M2,
17876 0 : 4034 => Opcode::PseudoVID_V_M2_MASK,
17877 0 : 4035 => Opcode::PseudoVID_V_M4,
17878 0 : 4036 => Opcode::PseudoVID_V_M4_MASK,
17879 0 : 4037 => Opcode::PseudoVID_V_M8,
17880 0 : 4038 => Opcode::PseudoVID_V_M8_MASK,
17881 0 : 4039 => Opcode::PseudoVID_V_MF2,
17882 0 : 4040 => Opcode::PseudoVID_V_MF2_MASK,
17883 0 : 4041 => Opcode::PseudoVID_V_MF4,
17884 0 : 4042 => Opcode::PseudoVID_V_MF4_MASK,
17885 0 : 4043 => Opcode::PseudoVID_V_MF8,
17886 0 : 4044 => Opcode::PseudoVID_V_MF8_MASK,
17887 0 : 4045 => Opcode::PseudoVIOTA_M_M1,
17888 0 : 4046 => Opcode::PseudoVIOTA_M_M1_MASK,
17889 0 : 4047 => Opcode::PseudoVIOTA_M_M2,
17890 0 : 4048 => Opcode::PseudoVIOTA_M_M2_MASK,
17891 0 : 4049 => Opcode::PseudoVIOTA_M_M4,
17892 0 : 4050 => Opcode::PseudoVIOTA_M_M4_MASK,
17893 0 : 4051 => Opcode::PseudoVIOTA_M_M8,
17894 0 : 4052 => Opcode::PseudoVIOTA_M_M8_MASK,
17895 0 : 4053 => Opcode::PseudoVIOTA_M_MF2,
17896 0 : 4054 => Opcode::PseudoVIOTA_M_MF2_MASK,
17897 0 : 4055 => Opcode::PseudoVIOTA_M_MF4,
17898 0 : 4056 => Opcode::PseudoVIOTA_M_MF4_MASK,
17899 0 : 4057 => Opcode::PseudoVIOTA_M_MF8,
17900 0 : 4058 => Opcode::PseudoVIOTA_M_MF8_MASK,
17901 0 : 4059 => Opcode::PseudoVLE16FF_V_M1,
17902 0 : 4060 => Opcode::PseudoVLE16FF_V_M1_MASK,
17903 0 : 4061 => Opcode::PseudoVLE16FF_V_M2,
17904 0 : 4062 => Opcode::PseudoVLE16FF_V_M2_MASK,
17905 0 : 4063 => Opcode::PseudoVLE16FF_V_M4,
17906 0 : 4064 => Opcode::PseudoVLE16FF_V_M4_MASK,
17907 0 : 4065 => Opcode::PseudoVLE16FF_V_M8,
17908 0 : 4066 => Opcode::PseudoVLE16FF_V_M8_MASK,
17909 0 : 4067 => Opcode::PseudoVLE16FF_V_MF2,
17910 0 : 4068 => Opcode::PseudoVLE16FF_V_MF2_MASK,
17911 0 : 4069 => Opcode::PseudoVLE16FF_V_MF4,
17912 0 : 4070 => Opcode::PseudoVLE16FF_V_MF4_MASK,
17913 0 : 4071 => Opcode::PseudoVLE16_V_M1,
17914 0 : 4072 => Opcode::PseudoVLE16_V_M1_MASK,
17915 0 : 4073 => Opcode::PseudoVLE16_V_M2,
17916 0 : 4074 => Opcode::PseudoVLE16_V_M2_MASK,
17917 0 : 4075 => Opcode::PseudoVLE16_V_M4,
17918 0 : 4076 => Opcode::PseudoVLE16_V_M4_MASK,
17919 0 : 4077 => Opcode::PseudoVLE16_V_M8,
17920 0 : 4078 => Opcode::PseudoVLE16_V_M8_MASK,
17921 0 : 4079 => Opcode::PseudoVLE16_V_MF2,
17922 0 : 4080 => Opcode::PseudoVLE16_V_MF2_MASK,
17923 0 : 4081 => Opcode::PseudoVLE16_V_MF4,
17924 0 : 4082 => Opcode::PseudoVLE16_V_MF4_MASK,
17925 0 : 4083 => Opcode::PseudoVLE32FF_V_M1,
17926 0 : 4084 => Opcode::PseudoVLE32FF_V_M1_MASK,
17927 0 : 4085 => Opcode::PseudoVLE32FF_V_M2,
17928 0 : 4086 => Opcode::PseudoVLE32FF_V_M2_MASK,
17929 0 : 4087 => Opcode::PseudoVLE32FF_V_M4,
17930 0 : 4088 => Opcode::PseudoVLE32FF_V_M4_MASK,
17931 0 : 4089 => Opcode::PseudoVLE32FF_V_M8,
17932 0 : 4090 => Opcode::PseudoVLE32FF_V_M8_MASK,
17933 0 : 4091 => Opcode::PseudoVLE32FF_V_MF2,
17934 0 : 4092 => Opcode::PseudoVLE32FF_V_MF2_MASK,
17935 0 : 4093 => Opcode::PseudoVLE32_V_M1,
17936 0 : 4094 => Opcode::PseudoVLE32_V_M1_MASK,
17937 0 : 4095 => Opcode::PseudoVLE32_V_M2,
17938 0 : 4096 => Opcode::PseudoVLE32_V_M2_MASK,
17939 0 : 4097 => Opcode::PseudoVLE32_V_M4,
17940 0 : 4098 => Opcode::PseudoVLE32_V_M4_MASK,
17941 0 : 4099 => Opcode::PseudoVLE32_V_M8,
17942 0 : 4100 => Opcode::PseudoVLE32_V_M8_MASK,
17943 0 : 4101 => Opcode::PseudoVLE32_V_MF2,
17944 0 : 4102 => Opcode::PseudoVLE32_V_MF2_MASK,
17945 0 : 4103 => Opcode::PseudoVLE64FF_V_M1,
17946 0 : 4104 => Opcode::PseudoVLE64FF_V_M1_MASK,
17947 0 : 4105 => Opcode::PseudoVLE64FF_V_M2,
17948 0 : 4106 => Opcode::PseudoVLE64FF_V_M2_MASK,
17949 0 : 4107 => Opcode::PseudoVLE64FF_V_M4,
17950 0 : 4108 => Opcode::PseudoVLE64FF_V_M4_MASK,
17951 0 : 4109 => Opcode::PseudoVLE64FF_V_M8,
17952 0 : 4110 => Opcode::PseudoVLE64FF_V_M8_MASK,
17953 0 : 4111 => Opcode::PseudoVLE64_V_M1,
17954 0 : 4112 => Opcode::PseudoVLE64_V_M1_MASK,
17955 0 : 4113 => Opcode::PseudoVLE64_V_M2,
17956 0 : 4114 => Opcode::PseudoVLE64_V_M2_MASK,
17957 0 : 4115 => Opcode::PseudoVLE64_V_M4,
17958 0 : 4116 => Opcode::PseudoVLE64_V_M4_MASK,
17959 0 : 4117 => Opcode::PseudoVLE64_V_M8,
17960 0 : 4118 => Opcode::PseudoVLE64_V_M8_MASK,
17961 0 : 4119 => Opcode::PseudoVLE8FF_V_M1,
17962 0 : 4120 => Opcode::PseudoVLE8FF_V_M1_MASK,
17963 0 : 4121 => Opcode::PseudoVLE8FF_V_M2,
17964 0 : 4122 => Opcode::PseudoVLE8FF_V_M2_MASK,
17965 0 : 4123 => Opcode::PseudoVLE8FF_V_M4,
17966 0 : 4124 => Opcode::PseudoVLE8FF_V_M4_MASK,
17967 0 : 4125 => Opcode::PseudoVLE8FF_V_M8,
17968 0 : 4126 => Opcode::PseudoVLE8FF_V_M8_MASK,
17969 0 : 4127 => Opcode::PseudoVLE8FF_V_MF2,
17970 0 : 4128 => Opcode::PseudoVLE8FF_V_MF2_MASK,
17971 0 : 4129 => Opcode::PseudoVLE8FF_V_MF4,
17972 0 : 4130 => Opcode::PseudoVLE8FF_V_MF4_MASK,
17973 0 : 4131 => Opcode::PseudoVLE8FF_V_MF8,
17974 0 : 4132 => Opcode::PseudoVLE8FF_V_MF8_MASK,
17975 0 : 4133 => Opcode::PseudoVLE8_V_M1,
17976 0 : 4134 => Opcode::PseudoVLE8_V_M1_MASK,
17977 0 : 4135 => Opcode::PseudoVLE8_V_M2,
17978 0 : 4136 => Opcode::PseudoVLE8_V_M2_MASK,
17979 0 : 4137 => Opcode::PseudoVLE8_V_M4,
17980 0 : 4138 => Opcode::PseudoVLE8_V_M4_MASK,
17981 0 : 4139 => Opcode::PseudoVLE8_V_M8,
17982 0 : 4140 => Opcode::PseudoVLE8_V_M8_MASK,
17983 0 : 4141 => Opcode::PseudoVLE8_V_MF2,
17984 0 : 4142 => Opcode::PseudoVLE8_V_MF2_MASK,
17985 0 : 4143 => Opcode::PseudoVLE8_V_MF4,
17986 0 : 4144 => Opcode::PseudoVLE8_V_MF4_MASK,
17987 0 : 4145 => Opcode::PseudoVLE8_V_MF8,
17988 0 : 4146 => Opcode::PseudoVLE8_V_MF8_MASK,
17989 0 : 4147 => Opcode::PseudoVLM_V_B1,
17990 0 : 4148 => Opcode::PseudoVLM_V_B16,
17991 0 : 4149 => Opcode::PseudoVLM_V_B2,
17992 0 : 4150 => Opcode::PseudoVLM_V_B32,
17993 0 : 4151 => Opcode::PseudoVLM_V_B4,
17994 0 : 4152 => Opcode::PseudoVLM_V_B64,
17995 0 : 4153 => Opcode::PseudoVLM_V_B8,
17996 0 : 4154 => Opcode::PseudoVLOXEI16_V_M1_M1,
17997 0 : 4155 => Opcode::PseudoVLOXEI16_V_M1_M1_MASK,
17998 0 : 4156 => Opcode::PseudoVLOXEI16_V_M1_M2,
17999 0 : 4157 => Opcode::PseudoVLOXEI16_V_M1_M2_MASK,
18000 0 : 4158 => Opcode::PseudoVLOXEI16_V_M1_M4,
18001 0 : 4159 => Opcode::PseudoVLOXEI16_V_M1_M4_MASK,
18002 0 : 4160 => Opcode::PseudoVLOXEI16_V_M1_MF2,
18003 0 : 4161 => Opcode::PseudoVLOXEI16_V_M1_MF2_MASK,
18004 0 : 4162 => Opcode::PseudoVLOXEI16_V_M2_M1,
18005 0 : 4163 => Opcode::PseudoVLOXEI16_V_M2_M1_MASK,
18006 0 : 4164 => Opcode::PseudoVLOXEI16_V_M2_M2,
18007 0 : 4165 => Opcode::PseudoVLOXEI16_V_M2_M2_MASK,
18008 0 : 4166 => Opcode::PseudoVLOXEI16_V_M2_M4,
18009 0 : 4167 => Opcode::PseudoVLOXEI16_V_M2_M4_MASK,
18010 0 : 4168 => Opcode::PseudoVLOXEI16_V_M2_M8,
18011 0 : 4169 => Opcode::PseudoVLOXEI16_V_M2_M8_MASK,
18012 0 : 4170 => Opcode::PseudoVLOXEI16_V_M4_M2,
18013 0 : 4171 => Opcode::PseudoVLOXEI16_V_M4_M2_MASK,
18014 0 : 4172 => Opcode::PseudoVLOXEI16_V_M4_M4,
18015 0 : 4173 => Opcode::PseudoVLOXEI16_V_M4_M4_MASK,
18016 0 : 4174 => Opcode::PseudoVLOXEI16_V_M4_M8,
18017 0 : 4175 => Opcode::PseudoVLOXEI16_V_M4_M8_MASK,
18018 0 : 4176 => Opcode::PseudoVLOXEI16_V_M8_M4,
18019 0 : 4177 => Opcode::PseudoVLOXEI16_V_M8_M4_MASK,
18020 0 : 4178 => Opcode::PseudoVLOXEI16_V_M8_M8,
18021 0 : 4179 => Opcode::PseudoVLOXEI16_V_M8_M8_MASK,
18022 0 : 4180 => Opcode::PseudoVLOXEI16_V_MF2_M1,
18023 0 : 4181 => Opcode::PseudoVLOXEI16_V_MF2_M1_MASK,
18024 0 : 4182 => Opcode::PseudoVLOXEI16_V_MF2_M2,
18025 0 : 4183 => Opcode::PseudoVLOXEI16_V_MF2_M2_MASK,
18026 0 : 4184 => Opcode::PseudoVLOXEI16_V_MF2_MF2,
18027 0 : 4185 => Opcode::PseudoVLOXEI16_V_MF2_MF2_MASK,
18028 0 : 4186 => Opcode::PseudoVLOXEI16_V_MF2_MF4,
18029 0 : 4187 => Opcode::PseudoVLOXEI16_V_MF2_MF4_MASK,
18030 0 : 4188 => Opcode::PseudoVLOXEI16_V_MF4_M1,
18031 0 : 4189 => Opcode::PseudoVLOXEI16_V_MF4_M1_MASK,
18032 0 : 4190 => Opcode::PseudoVLOXEI16_V_MF4_MF2,
18033 0 : 4191 => Opcode::PseudoVLOXEI16_V_MF4_MF2_MASK,
18034 0 : 4192 => Opcode::PseudoVLOXEI16_V_MF4_MF4,
18035 0 : 4193 => Opcode::PseudoVLOXEI16_V_MF4_MF4_MASK,
18036 0 : 4194 => Opcode::PseudoVLOXEI16_V_MF4_MF8,
18037 0 : 4195 => Opcode::PseudoVLOXEI16_V_MF4_MF8_MASK,
18038 0 : 4196 => Opcode::PseudoVLOXEI32_V_M1_M1,
18039 0 : 4197 => Opcode::PseudoVLOXEI32_V_M1_M1_MASK,
18040 0 : 4198 => Opcode::PseudoVLOXEI32_V_M1_M2,
18041 0 : 4199 => Opcode::PseudoVLOXEI32_V_M1_M2_MASK,
18042 0 : 4200 => Opcode::PseudoVLOXEI32_V_M1_MF2,
18043 0 : 4201 => Opcode::PseudoVLOXEI32_V_M1_MF2_MASK,
18044 0 : 4202 => Opcode::PseudoVLOXEI32_V_M1_MF4,
18045 0 : 4203 => Opcode::PseudoVLOXEI32_V_M1_MF4_MASK,
18046 0 : 4204 => Opcode::PseudoVLOXEI32_V_M2_M1,
18047 0 : 4205 => Opcode::PseudoVLOXEI32_V_M2_M1_MASK,
18048 0 : 4206 => Opcode::PseudoVLOXEI32_V_M2_M2,
18049 0 : 4207 => Opcode::PseudoVLOXEI32_V_M2_M2_MASK,
18050 0 : 4208 => Opcode::PseudoVLOXEI32_V_M2_M4,
18051 0 : 4209 => Opcode::PseudoVLOXEI32_V_M2_M4_MASK,
18052 0 : 4210 => Opcode::PseudoVLOXEI32_V_M2_MF2,
18053 0 : 4211 => Opcode::PseudoVLOXEI32_V_M2_MF2_MASK,
18054 0 : 4212 => Opcode::PseudoVLOXEI32_V_M4_M1,
18055 0 : 4213 => Opcode::PseudoVLOXEI32_V_M4_M1_MASK,
18056 0 : 4214 => Opcode::PseudoVLOXEI32_V_M4_M2,
18057 0 : 4215 => Opcode::PseudoVLOXEI32_V_M4_M2_MASK,
18058 0 : 4216 => Opcode::PseudoVLOXEI32_V_M4_M4,
18059 0 : 4217 => Opcode::PseudoVLOXEI32_V_M4_M4_MASK,
18060 0 : 4218 => Opcode::PseudoVLOXEI32_V_M4_M8,
18061 0 : 4219 => Opcode::PseudoVLOXEI32_V_M4_M8_MASK,
18062 0 : 4220 => Opcode::PseudoVLOXEI32_V_M8_M2,
18063 0 : 4221 => Opcode::PseudoVLOXEI32_V_M8_M2_MASK,
18064 0 : 4222 => Opcode::PseudoVLOXEI32_V_M8_M4,
18065 0 : 4223 => Opcode::PseudoVLOXEI32_V_M8_M4_MASK,
18066 0 : 4224 => Opcode::PseudoVLOXEI32_V_M8_M8,
18067 0 : 4225 => Opcode::PseudoVLOXEI32_V_M8_M8_MASK,
18068 0 : 4226 => Opcode::PseudoVLOXEI32_V_MF2_M1,
18069 0 : 4227 => Opcode::PseudoVLOXEI32_V_MF2_M1_MASK,
18070 0 : 4228 => Opcode::PseudoVLOXEI32_V_MF2_MF2,
18071 0 : 4229 => Opcode::PseudoVLOXEI32_V_MF2_MF2_MASK,
18072 0 : 4230 => Opcode::PseudoVLOXEI32_V_MF2_MF4,
18073 0 : 4231 => Opcode::PseudoVLOXEI32_V_MF2_MF4_MASK,
18074 0 : 4232 => Opcode::PseudoVLOXEI32_V_MF2_MF8,
18075 0 : 4233 => Opcode::PseudoVLOXEI32_V_MF2_MF8_MASK,
18076 0 : 4234 => Opcode::PseudoVLOXEI64_V_M1_M1,
18077 0 : 4235 => Opcode::PseudoVLOXEI64_V_M1_M1_MASK,
18078 0 : 4236 => Opcode::PseudoVLOXEI64_V_M1_MF2,
18079 0 : 4237 => Opcode::PseudoVLOXEI64_V_M1_MF2_MASK,
18080 0 : 4238 => Opcode::PseudoVLOXEI64_V_M1_MF4,
18081 0 : 4239 => Opcode::PseudoVLOXEI64_V_M1_MF4_MASK,
18082 0 : 4240 => Opcode::PseudoVLOXEI64_V_M1_MF8,
18083 0 : 4241 => Opcode::PseudoVLOXEI64_V_M1_MF8_MASK,
18084 0 : 4242 => Opcode::PseudoVLOXEI64_V_M2_M1,
18085 0 : 4243 => Opcode::PseudoVLOXEI64_V_M2_M1_MASK,
18086 0 : 4244 => Opcode::PseudoVLOXEI64_V_M2_M2,
18087 0 : 4245 => Opcode::PseudoVLOXEI64_V_M2_M2_MASK,
18088 0 : 4246 => Opcode::PseudoVLOXEI64_V_M2_MF2,
18089 0 : 4247 => Opcode::PseudoVLOXEI64_V_M2_MF2_MASK,
18090 0 : 4248 => Opcode::PseudoVLOXEI64_V_M2_MF4,
18091 0 : 4249 => Opcode::PseudoVLOXEI64_V_M2_MF4_MASK,
18092 0 : 4250 => Opcode::PseudoVLOXEI64_V_M4_M1,
18093 0 : 4251 => Opcode::PseudoVLOXEI64_V_M4_M1_MASK,
18094 0 : 4252 => Opcode::PseudoVLOXEI64_V_M4_M2,
18095 0 : 4253 => Opcode::PseudoVLOXEI64_V_M4_M2_MASK,
18096 0 : 4254 => Opcode::PseudoVLOXEI64_V_M4_M4,
18097 0 : 4255 => Opcode::PseudoVLOXEI64_V_M4_M4_MASK,
18098 0 : 4256 => Opcode::PseudoVLOXEI64_V_M4_MF2,
18099 0 : 4257 => Opcode::PseudoVLOXEI64_V_M4_MF2_MASK,
18100 0 : 4258 => Opcode::PseudoVLOXEI64_V_M8_M1,
18101 0 : 4259 => Opcode::PseudoVLOXEI64_V_M8_M1_MASK,
18102 0 : 4260 => Opcode::PseudoVLOXEI64_V_M8_M2,
18103 0 : 4261 => Opcode::PseudoVLOXEI64_V_M8_M2_MASK,
18104 0 : 4262 => Opcode::PseudoVLOXEI64_V_M8_M4,
18105 0 : 4263 => Opcode::PseudoVLOXEI64_V_M8_M4_MASK,
18106 0 : 4264 => Opcode::PseudoVLOXEI64_V_M8_M8,
18107 0 : 4265 => Opcode::PseudoVLOXEI64_V_M8_M8_MASK,
18108 0 : 4266 => Opcode::PseudoVLOXEI8_V_M1_M1,
18109 0 : 4267 => Opcode::PseudoVLOXEI8_V_M1_M1_MASK,
18110 0 : 4268 => Opcode::PseudoVLOXEI8_V_M1_M2,
18111 0 : 4269 => Opcode::PseudoVLOXEI8_V_M1_M2_MASK,
18112 0 : 4270 => Opcode::PseudoVLOXEI8_V_M1_M4,
18113 0 : 4271 => Opcode::PseudoVLOXEI8_V_M1_M4_MASK,
18114 0 : 4272 => Opcode::PseudoVLOXEI8_V_M1_M8,
18115 0 : 4273 => Opcode::PseudoVLOXEI8_V_M1_M8_MASK,
18116 0 : 4274 => Opcode::PseudoVLOXEI8_V_M2_M2,
18117 0 : 4275 => Opcode::PseudoVLOXEI8_V_M2_M2_MASK,
18118 0 : 4276 => Opcode::PseudoVLOXEI8_V_M2_M4,
18119 0 : 4277 => Opcode::PseudoVLOXEI8_V_M2_M4_MASK,
18120 0 : 4278 => Opcode::PseudoVLOXEI8_V_M2_M8,
18121 0 : 4279 => Opcode::PseudoVLOXEI8_V_M2_M8_MASK,
18122 0 : 4280 => Opcode::PseudoVLOXEI8_V_M4_M4,
18123 0 : 4281 => Opcode::PseudoVLOXEI8_V_M4_M4_MASK,
18124 0 : 4282 => Opcode::PseudoVLOXEI8_V_M4_M8,
18125 0 : 4283 => Opcode::PseudoVLOXEI8_V_M4_M8_MASK,
18126 0 : 4284 => Opcode::PseudoVLOXEI8_V_M8_M8,
18127 0 : 4285 => Opcode::PseudoVLOXEI8_V_M8_M8_MASK,
18128 0 : 4286 => Opcode::PseudoVLOXEI8_V_MF2_M1,
18129 0 : 4287 => Opcode::PseudoVLOXEI8_V_MF2_M1_MASK,
18130 0 : 4288 => Opcode::PseudoVLOXEI8_V_MF2_M2,
18131 0 : 4289 => Opcode::PseudoVLOXEI8_V_MF2_M2_MASK,
18132 0 : 4290 => Opcode::PseudoVLOXEI8_V_MF2_M4,
18133 0 : 4291 => Opcode::PseudoVLOXEI8_V_MF2_M4_MASK,
18134 0 : 4292 => Opcode::PseudoVLOXEI8_V_MF2_MF2,
18135 0 : 4293 => Opcode::PseudoVLOXEI8_V_MF2_MF2_MASK,
18136 0 : 4294 => Opcode::PseudoVLOXEI8_V_MF4_M1,
18137 0 : 4295 => Opcode::PseudoVLOXEI8_V_MF4_M1_MASK,
18138 0 : 4296 => Opcode::PseudoVLOXEI8_V_MF4_M2,
18139 0 : 4297 => Opcode::PseudoVLOXEI8_V_MF4_M2_MASK,
18140 0 : 4298 => Opcode::PseudoVLOXEI8_V_MF4_MF2,
18141 0 : 4299 => Opcode::PseudoVLOXEI8_V_MF4_MF2_MASK,
18142 0 : 4300 => Opcode::PseudoVLOXEI8_V_MF4_MF4,
18143 0 : 4301 => Opcode::PseudoVLOXEI8_V_MF4_MF4_MASK,
18144 0 : 4302 => Opcode::PseudoVLOXEI8_V_MF8_M1,
18145 0 : 4303 => Opcode::PseudoVLOXEI8_V_MF8_M1_MASK,
18146 0 : 4304 => Opcode::PseudoVLOXEI8_V_MF8_MF2,
18147 0 : 4305 => Opcode::PseudoVLOXEI8_V_MF8_MF2_MASK,
18148 0 : 4306 => Opcode::PseudoVLOXEI8_V_MF8_MF4,
18149 0 : 4307 => Opcode::PseudoVLOXEI8_V_MF8_MF4_MASK,
18150 0 : 4308 => Opcode::PseudoVLOXEI8_V_MF8_MF8,
18151 0 : 4309 => Opcode::PseudoVLOXEI8_V_MF8_MF8_MASK,
18152 0 : 4310 => Opcode::PseudoVLOXSEG2EI16_V_M1_M1,
18153 0 : 4311 => Opcode::PseudoVLOXSEG2EI16_V_M1_M1_MASK,
18154 0 : 4312 => Opcode::PseudoVLOXSEG2EI16_V_M1_M2,
18155 0 : 4313 => Opcode::PseudoVLOXSEG2EI16_V_M1_M2_MASK,
18156 0 : 4314 => Opcode::PseudoVLOXSEG2EI16_V_M1_M4,
18157 0 : 4315 => Opcode::PseudoVLOXSEG2EI16_V_M1_M4_MASK,
18158 0 : 4316 => Opcode::PseudoVLOXSEG2EI16_V_M1_MF2,
18159 0 : 4317 => Opcode::PseudoVLOXSEG2EI16_V_M1_MF2_MASK,
18160 0 : 4318 => Opcode::PseudoVLOXSEG2EI16_V_M2_M1,
18161 0 : 4319 => Opcode::PseudoVLOXSEG2EI16_V_M2_M1_MASK,
18162 0 : 4320 => Opcode::PseudoVLOXSEG2EI16_V_M2_M2,
18163 0 : 4321 => Opcode::PseudoVLOXSEG2EI16_V_M2_M2_MASK,
18164 0 : 4322 => Opcode::PseudoVLOXSEG2EI16_V_M2_M4,
18165 0 : 4323 => Opcode::PseudoVLOXSEG2EI16_V_M2_M4_MASK,
18166 0 : 4324 => Opcode::PseudoVLOXSEG2EI16_V_M4_M2,
18167 0 : 4325 => Opcode::PseudoVLOXSEG2EI16_V_M4_M2_MASK,
18168 0 : 4326 => Opcode::PseudoVLOXSEG2EI16_V_M4_M4,
18169 0 : 4327 => Opcode::PseudoVLOXSEG2EI16_V_M4_M4_MASK,
18170 0 : 4328 => Opcode::PseudoVLOXSEG2EI16_V_M8_M4,
18171 0 : 4329 => Opcode::PseudoVLOXSEG2EI16_V_M8_M4_MASK,
18172 0 : 4330 => Opcode::PseudoVLOXSEG2EI16_V_MF2_M1,
18173 0 : 4331 => Opcode::PseudoVLOXSEG2EI16_V_MF2_M1_MASK,
18174 0 : 4332 => Opcode::PseudoVLOXSEG2EI16_V_MF2_M2,
18175 0 : 4333 => Opcode::PseudoVLOXSEG2EI16_V_MF2_M2_MASK,
18176 0 : 4334 => Opcode::PseudoVLOXSEG2EI16_V_MF2_MF2,
18177 0 : 4335 => Opcode::PseudoVLOXSEG2EI16_V_MF2_MF2_MASK,
18178 0 : 4336 => Opcode::PseudoVLOXSEG2EI16_V_MF2_MF4,
18179 0 : 4337 => Opcode::PseudoVLOXSEG2EI16_V_MF2_MF4_MASK,
18180 0 : 4338 => Opcode::PseudoVLOXSEG2EI16_V_MF4_M1,
18181 0 : 4339 => Opcode::PseudoVLOXSEG2EI16_V_MF4_M1_MASK,
18182 0 : 4340 => Opcode::PseudoVLOXSEG2EI16_V_MF4_MF2,
18183 0 : 4341 => Opcode::PseudoVLOXSEG2EI16_V_MF4_MF2_MASK,
18184 0 : 4342 => Opcode::PseudoVLOXSEG2EI16_V_MF4_MF4,
18185 0 : 4343 => Opcode::PseudoVLOXSEG2EI16_V_MF4_MF4_MASK,
18186 0 : 4344 => Opcode::PseudoVLOXSEG2EI16_V_MF4_MF8,
18187 0 : 4345 => Opcode::PseudoVLOXSEG2EI16_V_MF4_MF8_MASK,
18188 0 : 4346 => Opcode::PseudoVLOXSEG2EI32_V_M1_M1,
18189 0 : 4347 => Opcode::PseudoVLOXSEG2EI32_V_M1_M1_MASK,
18190 0 : 4348 => Opcode::PseudoVLOXSEG2EI32_V_M1_M2,
18191 0 : 4349 => Opcode::PseudoVLOXSEG2EI32_V_M1_M2_MASK,
18192 0 : 4350 => Opcode::PseudoVLOXSEG2EI32_V_M1_MF2,
18193 0 : 4351 => Opcode::PseudoVLOXSEG2EI32_V_M1_MF2_MASK,
18194 0 : 4352 => Opcode::PseudoVLOXSEG2EI32_V_M1_MF4,
18195 0 : 4353 => Opcode::PseudoVLOXSEG2EI32_V_M1_MF4_MASK,
18196 0 : 4354 => Opcode::PseudoVLOXSEG2EI32_V_M2_M1,
18197 0 : 4355 => Opcode::PseudoVLOXSEG2EI32_V_M2_M1_MASK,
18198 0 : 4356 => Opcode::PseudoVLOXSEG2EI32_V_M2_M2,
18199 0 : 4357 => Opcode::PseudoVLOXSEG2EI32_V_M2_M2_MASK,
18200 0 : 4358 => Opcode::PseudoVLOXSEG2EI32_V_M2_M4,
18201 0 : 4359 => Opcode::PseudoVLOXSEG2EI32_V_M2_M4_MASK,
18202 0 : 4360 => Opcode::PseudoVLOXSEG2EI32_V_M2_MF2,
18203 0 : 4361 => Opcode::PseudoVLOXSEG2EI32_V_M2_MF2_MASK,
18204 0 : 4362 => Opcode::PseudoVLOXSEG2EI32_V_M4_M1,
18205 0 : 4363 => Opcode::PseudoVLOXSEG2EI32_V_M4_M1_MASK,
18206 0 : 4364 => Opcode::PseudoVLOXSEG2EI32_V_M4_M2,
18207 0 : 4365 => Opcode::PseudoVLOXSEG2EI32_V_M4_M2_MASK,
18208 0 : 4366 => Opcode::PseudoVLOXSEG2EI32_V_M4_M4,
18209 0 : 4367 => Opcode::PseudoVLOXSEG2EI32_V_M4_M4_MASK,
18210 0 : 4368 => Opcode::PseudoVLOXSEG2EI32_V_M8_M2,
18211 0 : 4369 => Opcode::PseudoVLOXSEG2EI32_V_M8_M2_MASK,
18212 0 : 4370 => Opcode::PseudoVLOXSEG2EI32_V_M8_M4,
18213 0 : 4371 => Opcode::PseudoVLOXSEG2EI32_V_M8_M4_MASK,
18214 0 : 4372 => Opcode::PseudoVLOXSEG2EI32_V_MF2_M1,
18215 0 : 4373 => Opcode::PseudoVLOXSEG2EI32_V_MF2_M1_MASK,
18216 0 : 4374 => Opcode::PseudoVLOXSEG2EI32_V_MF2_MF2,
18217 0 : 4375 => Opcode::PseudoVLOXSEG2EI32_V_MF2_MF2_MASK,
18218 0 : 4376 => Opcode::PseudoVLOXSEG2EI32_V_MF2_MF4,
18219 0 : 4377 => Opcode::PseudoVLOXSEG2EI32_V_MF2_MF4_MASK,
18220 0 : 4378 => Opcode::PseudoVLOXSEG2EI32_V_MF2_MF8,
18221 0 : 4379 => Opcode::PseudoVLOXSEG2EI32_V_MF2_MF8_MASK,
18222 0 : 4380 => Opcode::PseudoVLOXSEG2EI64_V_M1_M1,
18223 0 : 4381 => Opcode::PseudoVLOXSEG2EI64_V_M1_M1_MASK,
18224 0 : 4382 => Opcode::PseudoVLOXSEG2EI64_V_M1_MF2,
18225 0 : 4383 => Opcode::PseudoVLOXSEG2EI64_V_M1_MF2_MASK,
18226 0 : 4384 => Opcode::PseudoVLOXSEG2EI64_V_M1_MF4,
18227 0 : 4385 => Opcode::PseudoVLOXSEG2EI64_V_M1_MF4_MASK,
18228 0 : 4386 => Opcode::PseudoVLOXSEG2EI64_V_M1_MF8,
18229 0 : 4387 => Opcode::PseudoVLOXSEG2EI64_V_M1_MF8_MASK,
18230 0 : 4388 => Opcode::PseudoVLOXSEG2EI64_V_M2_M1,
18231 0 : 4389 => Opcode::PseudoVLOXSEG2EI64_V_M2_M1_MASK,
18232 0 : 4390 => Opcode::PseudoVLOXSEG2EI64_V_M2_M2,
18233 0 : 4391 => Opcode::PseudoVLOXSEG2EI64_V_M2_M2_MASK,
18234 0 : 4392 => Opcode::PseudoVLOXSEG2EI64_V_M2_MF2,
18235 0 : 4393 => Opcode::PseudoVLOXSEG2EI64_V_M2_MF2_MASK,
18236 0 : 4394 => Opcode::PseudoVLOXSEG2EI64_V_M2_MF4,
18237 0 : 4395 => Opcode::PseudoVLOXSEG2EI64_V_M2_MF4_MASK,
18238 0 : 4396 => Opcode::PseudoVLOXSEG2EI64_V_M4_M1,
18239 0 : 4397 => Opcode::PseudoVLOXSEG2EI64_V_M4_M1_MASK,
18240 0 : 4398 => Opcode::PseudoVLOXSEG2EI64_V_M4_M2,
18241 0 : 4399 => Opcode::PseudoVLOXSEG2EI64_V_M4_M2_MASK,
18242 0 : 4400 => Opcode::PseudoVLOXSEG2EI64_V_M4_M4,
18243 0 : 4401 => Opcode::PseudoVLOXSEG2EI64_V_M4_M4_MASK,
18244 0 : 4402 => Opcode::PseudoVLOXSEG2EI64_V_M4_MF2,
18245 0 : 4403 => Opcode::PseudoVLOXSEG2EI64_V_M4_MF2_MASK,
18246 0 : 4404 => Opcode::PseudoVLOXSEG2EI64_V_M8_M1,
18247 0 : 4405 => Opcode::PseudoVLOXSEG2EI64_V_M8_M1_MASK,
18248 0 : 4406 => Opcode::PseudoVLOXSEG2EI64_V_M8_M2,
18249 0 : 4407 => Opcode::PseudoVLOXSEG2EI64_V_M8_M2_MASK,
18250 0 : 4408 => Opcode::PseudoVLOXSEG2EI64_V_M8_M4,
18251 0 : 4409 => Opcode::PseudoVLOXSEG2EI64_V_M8_M4_MASK,
18252 0 : 4410 => Opcode::PseudoVLOXSEG2EI8_V_M1_M1,
18253 0 : 4411 => Opcode::PseudoVLOXSEG2EI8_V_M1_M1_MASK,
18254 0 : 4412 => Opcode::PseudoVLOXSEG2EI8_V_M1_M2,
18255 0 : 4413 => Opcode::PseudoVLOXSEG2EI8_V_M1_M2_MASK,
18256 0 : 4414 => Opcode::PseudoVLOXSEG2EI8_V_M1_M4,
18257 0 : 4415 => Opcode::PseudoVLOXSEG2EI8_V_M1_M4_MASK,
18258 0 : 4416 => Opcode::PseudoVLOXSEG2EI8_V_M2_M2,
18259 0 : 4417 => Opcode::PseudoVLOXSEG2EI8_V_M2_M2_MASK,
18260 0 : 4418 => Opcode::PseudoVLOXSEG2EI8_V_M2_M4,
18261 0 : 4419 => Opcode::PseudoVLOXSEG2EI8_V_M2_M4_MASK,
18262 0 : 4420 => Opcode::PseudoVLOXSEG2EI8_V_M4_M4,
18263 0 : 4421 => Opcode::PseudoVLOXSEG2EI8_V_M4_M4_MASK,
18264 0 : 4422 => Opcode::PseudoVLOXSEG2EI8_V_MF2_M1,
18265 0 : 4423 => Opcode::PseudoVLOXSEG2EI8_V_MF2_M1_MASK,
18266 0 : 4424 => Opcode::PseudoVLOXSEG2EI8_V_MF2_M2,
18267 0 : 4425 => Opcode::PseudoVLOXSEG2EI8_V_MF2_M2_MASK,
18268 0 : 4426 => Opcode::PseudoVLOXSEG2EI8_V_MF2_M4,
18269 0 : 4427 => Opcode::PseudoVLOXSEG2EI8_V_MF2_M4_MASK,
18270 0 : 4428 => Opcode::PseudoVLOXSEG2EI8_V_MF2_MF2,
18271 0 : 4429 => Opcode::PseudoVLOXSEG2EI8_V_MF2_MF2_MASK,
18272 0 : 4430 => Opcode::PseudoVLOXSEG2EI8_V_MF4_M1,
18273 0 : 4431 => Opcode::PseudoVLOXSEG2EI8_V_MF4_M1_MASK,
18274 0 : 4432 => Opcode::PseudoVLOXSEG2EI8_V_MF4_M2,
18275 0 : 4433 => Opcode::PseudoVLOXSEG2EI8_V_MF4_M2_MASK,
18276 0 : 4434 => Opcode::PseudoVLOXSEG2EI8_V_MF4_MF2,
18277 0 : 4435 => Opcode::PseudoVLOXSEG2EI8_V_MF4_MF2_MASK,
18278 0 : 4436 => Opcode::PseudoVLOXSEG2EI8_V_MF4_MF4,
18279 0 : 4437 => Opcode::PseudoVLOXSEG2EI8_V_MF4_MF4_MASK,
18280 0 : 4438 => Opcode::PseudoVLOXSEG2EI8_V_MF8_M1,
18281 0 : 4439 => Opcode::PseudoVLOXSEG2EI8_V_MF8_M1_MASK,
18282 0 : 4440 => Opcode::PseudoVLOXSEG2EI8_V_MF8_MF2,
18283 0 : 4441 => Opcode::PseudoVLOXSEG2EI8_V_MF8_MF2_MASK,
18284 0 : 4442 => Opcode::PseudoVLOXSEG2EI8_V_MF8_MF4,
18285 0 : 4443 => Opcode::PseudoVLOXSEG2EI8_V_MF8_MF4_MASK,
18286 0 : 4444 => Opcode::PseudoVLOXSEG2EI8_V_MF8_MF8,
18287 0 : 4445 => Opcode::PseudoVLOXSEG2EI8_V_MF8_MF8_MASK,
18288 0 : 4446 => Opcode::PseudoVLOXSEG3EI16_V_M1_M1,
18289 0 : 4447 => Opcode::PseudoVLOXSEG3EI16_V_M1_M1_MASK,
18290 0 : 4448 => Opcode::PseudoVLOXSEG3EI16_V_M1_M2,
18291 0 : 4449 => Opcode::PseudoVLOXSEG3EI16_V_M1_M2_MASK,
18292 0 : 4450 => Opcode::PseudoVLOXSEG3EI16_V_M1_MF2,
18293 0 : 4451 => Opcode::PseudoVLOXSEG3EI16_V_M1_MF2_MASK,
18294 0 : 4452 => Opcode::PseudoVLOXSEG3EI16_V_M2_M1,
18295 0 : 4453 => Opcode::PseudoVLOXSEG3EI16_V_M2_M1_MASK,
18296 0 : 4454 => Opcode::PseudoVLOXSEG3EI16_V_M2_M2,
18297 0 : 4455 => Opcode::PseudoVLOXSEG3EI16_V_M2_M2_MASK,
18298 0 : 4456 => Opcode::PseudoVLOXSEG3EI16_V_M4_M2,
18299 0 : 4457 => Opcode::PseudoVLOXSEG3EI16_V_M4_M2_MASK,
18300 0 : 4458 => Opcode::PseudoVLOXSEG3EI16_V_MF2_M1,
18301 0 : 4459 => Opcode::PseudoVLOXSEG3EI16_V_MF2_M1_MASK,
18302 0 : 4460 => Opcode::PseudoVLOXSEG3EI16_V_MF2_M2,
18303 0 : 4461 => Opcode::PseudoVLOXSEG3EI16_V_MF2_M2_MASK,
18304 0 : 4462 => Opcode::PseudoVLOXSEG3EI16_V_MF2_MF2,
18305 0 : 4463 => Opcode::PseudoVLOXSEG3EI16_V_MF2_MF2_MASK,
18306 0 : 4464 => Opcode::PseudoVLOXSEG3EI16_V_MF2_MF4,
18307 0 : 4465 => Opcode::PseudoVLOXSEG3EI16_V_MF2_MF4_MASK,
18308 0 : 4466 => Opcode::PseudoVLOXSEG3EI16_V_MF4_M1,
18309 0 : 4467 => Opcode::PseudoVLOXSEG3EI16_V_MF4_M1_MASK,
18310 0 : 4468 => Opcode::PseudoVLOXSEG3EI16_V_MF4_MF2,
18311 0 : 4469 => Opcode::PseudoVLOXSEG3EI16_V_MF4_MF2_MASK,
18312 0 : 4470 => Opcode::PseudoVLOXSEG3EI16_V_MF4_MF4,
18313 0 : 4471 => Opcode::PseudoVLOXSEG3EI16_V_MF4_MF4_MASK,
18314 0 : 4472 => Opcode::PseudoVLOXSEG3EI16_V_MF4_MF8,
18315 0 : 4473 => Opcode::PseudoVLOXSEG3EI16_V_MF4_MF8_MASK,
18316 0 : 4474 => Opcode::PseudoVLOXSEG3EI32_V_M1_M1,
18317 0 : 4475 => Opcode::PseudoVLOXSEG3EI32_V_M1_M1_MASK,
18318 0 : 4476 => Opcode::PseudoVLOXSEG3EI32_V_M1_M2,
18319 0 : 4477 => Opcode::PseudoVLOXSEG3EI32_V_M1_M2_MASK,
18320 0 : 4478 => Opcode::PseudoVLOXSEG3EI32_V_M1_MF2,
18321 0 : 4479 => Opcode::PseudoVLOXSEG3EI32_V_M1_MF2_MASK,
18322 0 : 4480 => Opcode::PseudoVLOXSEG3EI32_V_M1_MF4,
18323 0 : 4481 => Opcode::PseudoVLOXSEG3EI32_V_M1_MF4_MASK,
18324 0 : 4482 => Opcode::PseudoVLOXSEG3EI32_V_M2_M1,
18325 0 : 4483 => Opcode::PseudoVLOXSEG3EI32_V_M2_M1_MASK,
18326 0 : 4484 => Opcode::PseudoVLOXSEG3EI32_V_M2_M2,
18327 0 : 4485 => Opcode::PseudoVLOXSEG3EI32_V_M2_M2_MASK,
18328 0 : 4486 => Opcode::PseudoVLOXSEG3EI32_V_M2_MF2,
18329 0 : 4487 => Opcode::PseudoVLOXSEG3EI32_V_M2_MF2_MASK,
18330 0 : 4488 => Opcode::PseudoVLOXSEG3EI32_V_M4_M1,
18331 0 : 4489 => Opcode::PseudoVLOXSEG3EI32_V_M4_M1_MASK,
18332 0 : 4490 => Opcode::PseudoVLOXSEG3EI32_V_M4_M2,
18333 0 : 4491 => Opcode::PseudoVLOXSEG3EI32_V_M4_M2_MASK,
18334 0 : 4492 => Opcode::PseudoVLOXSEG3EI32_V_M8_M2,
18335 0 : 4493 => Opcode::PseudoVLOXSEG3EI32_V_M8_M2_MASK,
18336 0 : 4494 => Opcode::PseudoVLOXSEG3EI32_V_MF2_M1,
18337 0 : 4495 => Opcode::PseudoVLOXSEG3EI32_V_MF2_M1_MASK,
18338 0 : 4496 => Opcode::PseudoVLOXSEG3EI32_V_MF2_MF2,
18339 0 : 4497 => Opcode::PseudoVLOXSEG3EI32_V_MF2_MF2_MASK,
18340 0 : 4498 => Opcode::PseudoVLOXSEG3EI32_V_MF2_MF4,
18341 0 : 4499 => Opcode::PseudoVLOXSEG3EI32_V_MF2_MF4_MASK,
18342 0 : 4500 => Opcode::PseudoVLOXSEG3EI32_V_MF2_MF8,
18343 0 : 4501 => Opcode::PseudoVLOXSEG3EI32_V_MF2_MF8_MASK,
18344 0 : 4502 => Opcode::PseudoVLOXSEG3EI64_V_M1_M1,
18345 0 : 4503 => Opcode::PseudoVLOXSEG3EI64_V_M1_M1_MASK,
18346 0 : 4504 => Opcode::PseudoVLOXSEG3EI64_V_M1_MF2,
18347 0 : 4505 => Opcode::PseudoVLOXSEG3EI64_V_M1_MF2_MASK,
18348 0 : 4506 => Opcode::PseudoVLOXSEG3EI64_V_M1_MF4,
18349 0 : 4507 => Opcode::PseudoVLOXSEG3EI64_V_M1_MF4_MASK,
18350 0 : 4508 => Opcode::PseudoVLOXSEG3EI64_V_M1_MF8,
18351 0 : 4509 => Opcode::PseudoVLOXSEG3EI64_V_M1_MF8_MASK,
18352 0 : 4510 => Opcode::PseudoVLOXSEG3EI64_V_M2_M1,
18353 0 : 4511 => Opcode::PseudoVLOXSEG3EI64_V_M2_M1_MASK,
18354 0 : 4512 => Opcode::PseudoVLOXSEG3EI64_V_M2_M2,
18355 0 : 4513 => Opcode::PseudoVLOXSEG3EI64_V_M2_M2_MASK,
18356 0 : 4514 => Opcode::PseudoVLOXSEG3EI64_V_M2_MF2,
18357 0 : 4515 => Opcode::PseudoVLOXSEG3EI64_V_M2_MF2_MASK,
18358 0 : 4516 => Opcode::PseudoVLOXSEG3EI64_V_M2_MF4,
18359 0 : 4517 => Opcode::PseudoVLOXSEG3EI64_V_M2_MF4_MASK,
18360 0 : 4518 => Opcode::PseudoVLOXSEG3EI64_V_M4_M1,
18361 0 : 4519 => Opcode::PseudoVLOXSEG3EI64_V_M4_M1_MASK,
18362 0 : 4520 => Opcode::PseudoVLOXSEG3EI64_V_M4_M2,
18363 0 : 4521 => Opcode::PseudoVLOXSEG3EI64_V_M4_M2_MASK,
18364 0 : 4522 => Opcode::PseudoVLOXSEG3EI64_V_M4_MF2,
18365 0 : 4523 => Opcode::PseudoVLOXSEG3EI64_V_M4_MF2_MASK,
18366 0 : 4524 => Opcode::PseudoVLOXSEG3EI64_V_M8_M1,
18367 0 : 4525 => Opcode::PseudoVLOXSEG3EI64_V_M8_M1_MASK,
18368 0 : 4526 => Opcode::PseudoVLOXSEG3EI64_V_M8_M2,
18369 0 : 4527 => Opcode::PseudoVLOXSEG3EI64_V_M8_M2_MASK,
18370 0 : 4528 => Opcode::PseudoVLOXSEG3EI8_V_M1_M1,
18371 0 : 4529 => Opcode::PseudoVLOXSEG3EI8_V_M1_M1_MASK,
18372 0 : 4530 => Opcode::PseudoVLOXSEG3EI8_V_M1_M2,
18373 0 : 4531 => Opcode::PseudoVLOXSEG3EI8_V_M1_M2_MASK,
18374 0 : 4532 => Opcode::PseudoVLOXSEG3EI8_V_M2_M2,
18375 0 : 4533 => Opcode::PseudoVLOXSEG3EI8_V_M2_M2_MASK,
18376 0 : 4534 => Opcode::PseudoVLOXSEG3EI8_V_MF2_M1,
18377 0 : 4535 => Opcode::PseudoVLOXSEG3EI8_V_MF2_M1_MASK,
18378 0 : 4536 => Opcode::PseudoVLOXSEG3EI8_V_MF2_M2,
18379 0 : 4537 => Opcode::PseudoVLOXSEG3EI8_V_MF2_M2_MASK,
18380 0 : 4538 => Opcode::PseudoVLOXSEG3EI8_V_MF2_MF2,
18381 0 : 4539 => Opcode::PseudoVLOXSEG3EI8_V_MF2_MF2_MASK,
18382 0 : 4540 => Opcode::PseudoVLOXSEG3EI8_V_MF4_M1,
18383 0 : 4541 => Opcode::PseudoVLOXSEG3EI8_V_MF4_M1_MASK,
18384 0 : 4542 => Opcode::PseudoVLOXSEG3EI8_V_MF4_M2,
18385 0 : 4543 => Opcode::PseudoVLOXSEG3EI8_V_MF4_M2_MASK,
18386 0 : 4544 => Opcode::PseudoVLOXSEG3EI8_V_MF4_MF2,
18387 0 : 4545 => Opcode::PseudoVLOXSEG3EI8_V_MF4_MF2_MASK,
18388 0 : 4546 => Opcode::PseudoVLOXSEG3EI8_V_MF4_MF4,
18389 0 : 4547 => Opcode::PseudoVLOXSEG3EI8_V_MF4_MF4_MASK,
18390 0 : 4548 => Opcode::PseudoVLOXSEG3EI8_V_MF8_M1,
18391 0 : 4549 => Opcode::PseudoVLOXSEG3EI8_V_MF8_M1_MASK,
18392 0 : 4550 => Opcode::PseudoVLOXSEG3EI8_V_MF8_MF2,
18393 0 : 4551 => Opcode::PseudoVLOXSEG3EI8_V_MF8_MF2_MASK,
18394 0 : 4552 => Opcode::PseudoVLOXSEG3EI8_V_MF8_MF4,
18395 0 : 4553 => Opcode::PseudoVLOXSEG3EI8_V_MF8_MF4_MASK,
18396 0 : 4554 => Opcode::PseudoVLOXSEG3EI8_V_MF8_MF8,
18397 0 : 4555 => Opcode::PseudoVLOXSEG3EI8_V_MF8_MF8_MASK,
18398 0 : 4556 => Opcode::PseudoVLOXSEG4EI16_V_M1_M1,
18399 0 : 4557 => Opcode::PseudoVLOXSEG4EI16_V_M1_M1_MASK,
18400 0 : 4558 => Opcode::PseudoVLOXSEG4EI16_V_M1_M2,
18401 0 : 4559 => Opcode::PseudoVLOXSEG4EI16_V_M1_M2_MASK,
18402 0 : 4560 => Opcode::PseudoVLOXSEG4EI16_V_M1_MF2,
18403 0 : 4561 => Opcode::PseudoVLOXSEG4EI16_V_M1_MF2_MASK,
18404 0 : 4562 => Opcode::PseudoVLOXSEG4EI16_V_M2_M1,
18405 0 : 4563 => Opcode::PseudoVLOXSEG4EI16_V_M2_M1_MASK,
18406 0 : 4564 => Opcode::PseudoVLOXSEG4EI16_V_M2_M2,
18407 0 : 4565 => Opcode::PseudoVLOXSEG4EI16_V_M2_M2_MASK,
18408 0 : 4566 => Opcode::PseudoVLOXSEG4EI16_V_M4_M2,
18409 0 : 4567 => Opcode::PseudoVLOXSEG4EI16_V_M4_M2_MASK,
18410 0 : 4568 => Opcode::PseudoVLOXSEG4EI16_V_MF2_M1,
18411 0 : 4569 => Opcode::PseudoVLOXSEG4EI16_V_MF2_M1_MASK,
18412 0 : 4570 => Opcode::PseudoVLOXSEG4EI16_V_MF2_M2,
18413 0 : 4571 => Opcode::PseudoVLOXSEG4EI16_V_MF2_M2_MASK,
18414 0 : 4572 => Opcode::PseudoVLOXSEG4EI16_V_MF2_MF2,
18415 0 : 4573 => Opcode::PseudoVLOXSEG4EI16_V_MF2_MF2_MASK,
18416 0 : 4574 => Opcode::PseudoVLOXSEG4EI16_V_MF2_MF4,
18417 0 : 4575 => Opcode::PseudoVLOXSEG4EI16_V_MF2_MF4_MASK,
18418 0 : 4576 => Opcode::PseudoVLOXSEG4EI16_V_MF4_M1,
18419 0 : 4577 => Opcode::PseudoVLOXSEG4EI16_V_MF4_M1_MASK,
18420 0 : 4578 => Opcode::PseudoVLOXSEG4EI16_V_MF4_MF2,
18421 0 : 4579 => Opcode::PseudoVLOXSEG4EI16_V_MF4_MF2_MASK,
18422 0 : 4580 => Opcode::PseudoVLOXSEG4EI16_V_MF4_MF4,
18423 0 : 4581 => Opcode::PseudoVLOXSEG4EI16_V_MF4_MF4_MASK,
18424 0 : 4582 => Opcode::PseudoVLOXSEG4EI16_V_MF4_MF8,
18425 0 : 4583 => Opcode::PseudoVLOXSEG4EI16_V_MF4_MF8_MASK,
18426 0 : 4584 => Opcode::PseudoVLOXSEG4EI32_V_M1_M1,
18427 0 : 4585 => Opcode::PseudoVLOXSEG4EI32_V_M1_M1_MASK,
18428 0 : 4586 => Opcode::PseudoVLOXSEG4EI32_V_M1_M2,
18429 0 : 4587 => Opcode::PseudoVLOXSEG4EI32_V_M1_M2_MASK,
18430 0 : 4588 => Opcode::PseudoVLOXSEG4EI32_V_M1_MF2,
18431 0 : 4589 => Opcode::PseudoVLOXSEG4EI32_V_M1_MF2_MASK,
18432 0 : 4590 => Opcode::PseudoVLOXSEG4EI32_V_M1_MF4,
18433 0 : 4591 => Opcode::PseudoVLOXSEG4EI32_V_M1_MF4_MASK,
18434 0 : 4592 => Opcode::PseudoVLOXSEG4EI32_V_M2_M1,
18435 0 : 4593 => Opcode::PseudoVLOXSEG4EI32_V_M2_M1_MASK,
18436 0 : 4594 => Opcode::PseudoVLOXSEG4EI32_V_M2_M2,
18437 0 : 4595 => Opcode::PseudoVLOXSEG4EI32_V_M2_M2_MASK,
18438 0 : 4596 => Opcode::PseudoVLOXSEG4EI32_V_M2_MF2,
18439 0 : 4597 => Opcode::PseudoVLOXSEG4EI32_V_M2_MF2_MASK,
18440 0 : 4598 => Opcode::PseudoVLOXSEG4EI32_V_M4_M1,
18441 0 : 4599 => Opcode::PseudoVLOXSEG4EI32_V_M4_M1_MASK,
18442 0 : 4600 => Opcode::PseudoVLOXSEG4EI32_V_M4_M2,
18443 0 : 4601 => Opcode::PseudoVLOXSEG4EI32_V_M4_M2_MASK,
18444 0 : 4602 => Opcode::PseudoVLOXSEG4EI32_V_M8_M2,
18445 0 : 4603 => Opcode::PseudoVLOXSEG4EI32_V_M8_M2_MASK,
18446 0 : 4604 => Opcode::PseudoVLOXSEG4EI32_V_MF2_M1,
18447 0 : 4605 => Opcode::PseudoVLOXSEG4EI32_V_MF2_M1_MASK,
18448 0 : 4606 => Opcode::PseudoVLOXSEG4EI32_V_MF2_MF2,
18449 0 : 4607 => Opcode::PseudoVLOXSEG4EI32_V_MF2_MF2_MASK,
18450 0 : 4608 => Opcode::PseudoVLOXSEG4EI32_V_MF2_MF4,
18451 0 : 4609 => Opcode::PseudoVLOXSEG4EI32_V_MF2_MF4_MASK,
18452 0 : 4610 => Opcode::PseudoVLOXSEG4EI32_V_MF2_MF8,
18453 0 : 4611 => Opcode::PseudoVLOXSEG4EI32_V_MF2_MF8_MASK,
18454 0 : 4612 => Opcode::PseudoVLOXSEG4EI64_V_M1_M1,
18455 0 : 4613 => Opcode::PseudoVLOXSEG4EI64_V_M1_M1_MASK,
18456 0 : 4614 => Opcode::PseudoVLOXSEG4EI64_V_M1_MF2,
18457 0 : 4615 => Opcode::PseudoVLOXSEG4EI64_V_M1_MF2_MASK,
18458 0 : 4616 => Opcode::PseudoVLOXSEG4EI64_V_M1_MF4,
18459 0 : 4617 => Opcode::PseudoVLOXSEG4EI64_V_M1_MF4_MASK,
18460 0 : 4618 => Opcode::PseudoVLOXSEG4EI64_V_M1_MF8,
18461 0 : 4619 => Opcode::PseudoVLOXSEG4EI64_V_M1_MF8_MASK,
18462 0 : 4620 => Opcode::PseudoVLOXSEG4EI64_V_M2_M1,
18463 0 : 4621 => Opcode::PseudoVLOXSEG4EI64_V_M2_M1_MASK,
18464 0 : 4622 => Opcode::PseudoVLOXSEG4EI64_V_M2_M2,
18465 0 : 4623 => Opcode::PseudoVLOXSEG4EI64_V_M2_M2_MASK,
18466 0 : 4624 => Opcode::PseudoVLOXSEG4EI64_V_M2_MF2,
18467 0 : 4625 => Opcode::PseudoVLOXSEG4EI64_V_M2_MF2_MASK,
18468 0 : 4626 => Opcode::PseudoVLOXSEG4EI64_V_M2_MF4,
18469 0 : 4627 => Opcode::PseudoVLOXSEG4EI64_V_M2_MF4_MASK,
18470 0 : 4628 => Opcode::PseudoVLOXSEG4EI64_V_M4_M1,
18471 0 : 4629 => Opcode::PseudoVLOXSEG4EI64_V_M4_M1_MASK,
18472 0 : 4630 => Opcode::PseudoVLOXSEG4EI64_V_M4_M2,
18473 0 : 4631 => Opcode::PseudoVLOXSEG4EI64_V_M4_M2_MASK,
18474 0 : 4632 => Opcode::PseudoVLOXSEG4EI64_V_M4_MF2,
18475 0 : 4633 => Opcode::PseudoVLOXSEG4EI64_V_M4_MF2_MASK,
18476 0 : 4634 => Opcode::PseudoVLOXSEG4EI64_V_M8_M1,
18477 0 : 4635 => Opcode::PseudoVLOXSEG4EI64_V_M8_M1_MASK,
18478 0 : 4636 => Opcode::PseudoVLOXSEG4EI64_V_M8_M2,
18479 0 : 4637 => Opcode::PseudoVLOXSEG4EI64_V_M8_M2_MASK,
18480 0 : 4638 => Opcode::PseudoVLOXSEG4EI8_V_M1_M1,
18481 0 : 4639 => Opcode::PseudoVLOXSEG4EI8_V_M1_M1_MASK,
18482 0 : 4640 => Opcode::PseudoVLOXSEG4EI8_V_M1_M2,
18483 0 : 4641 => Opcode::PseudoVLOXSEG4EI8_V_M1_M2_MASK,
18484 0 : 4642 => Opcode::PseudoVLOXSEG4EI8_V_M2_M2,
18485 0 : 4643 => Opcode::PseudoVLOXSEG4EI8_V_M2_M2_MASK,
18486 0 : 4644 => Opcode::PseudoVLOXSEG4EI8_V_MF2_M1,
18487 0 : 4645 => Opcode::PseudoVLOXSEG4EI8_V_MF2_M1_MASK,
18488 0 : 4646 => Opcode::PseudoVLOXSEG4EI8_V_MF2_M2,
18489 0 : 4647 => Opcode::PseudoVLOXSEG4EI8_V_MF2_M2_MASK,
18490 0 : 4648 => Opcode::PseudoVLOXSEG4EI8_V_MF2_MF2,
18491 0 : 4649 => Opcode::PseudoVLOXSEG4EI8_V_MF2_MF2_MASK,
18492 0 : 4650 => Opcode::PseudoVLOXSEG4EI8_V_MF4_M1,
18493 0 : 4651 => Opcode::PseudoVLOXSEG4EI8_V_MF4_M1_MASK,
18494 0 : 4652 => Opcode::PseudoVLOXSEG4EI8_V_MF4_M2,
18495 0 : 4653 => Opcode::PseudoVLOXSEG4EI8_V_MF4_M2_MASK,
18496 0 : 4654 => Opcode::PseudoVLOXSEG4EI8_V_MF4_MF2,
18497 0 : 4655 => Opcode::PseudoVLOXSEG4EI8_V_MF4_MF2_MASK,
18498 0 : 4656 => Opcode::PseudoVLOXSEG4EI8_V_MF4_MF4,
18499 0 : 4657 => Opcode::PseudoVLOXSEG4EI8_V_MF4_MF4_MASK,
18500 0 : 4658 => Opcode::PseudoVLOXSEG4EI8_V_MF8_M1,
18501 0 : 4659 => Opcode::PseudoVLOXSEG4EI8_V_MF8_M1_MASK,
18502 0 : 4660 => Opcode::PseudoVLOXSEG4EI8_V_MF8_MF2,
18503 0 : 4661 => Opcode::PseudoVLOXSEG4EI8_V_MF8_MF2_MASK,
18504 0 : 4662 => Opcode::PseudoVLOXSEG4EI8_V_MF8_MF4,
18505 0 : 4663 => Opcode::PseudoVLOXSEG4EI8_V_MF8_MF4_MASK,
18506 0 : 4664 => Opcode::PseudoVLOXSEG4EI8_V_MF8_MF8,
18507 0 : 4665 => Opcode::PseudoVLOXSEG4EI8_V_MF8_MF8_MASK,
18508 0 : 4666 => Opcode::PseudoVLOXSEG5EI16_V_M1_M1,
18509 0 : 4667 => Opcode::PseudoVLOXSEG5EI16_V_M1_M1_MASK,
18510 0 : 4668 => Opcode::PseudoVLOXSEG5EI16_V_M1_MF2,
18511 0 : 4669 => Opcode::PseudoVLOXSEG5EI16_V_M1_MF2_MASK,
18512 0 : 4670 => Opcode::PseudoVLOXSEG5EI16_V_M2_M1,
18513 0 : 4671 => Opcode::PseudoVLOXSEG5EI16_V_M2_M1_MASK,
18514 0 : 4672 => Opcode::PseudoVLOXSEG5EI16_V_MF2_M1,
18515 0 : 4673 => Opcode::PseudoVLOXSEG5EI16_V_MF2_M1_MASK,
18516 0 : 4674 => Opcode::PseudoVLOXSEG5EI16_V_MF2_MF2,
18517 0 : 4675 => Opcode::PseudoVLOXSEG5EI16_V_MF2_MF2_MASK,
18518 0 : 4676 => Opcode::PseudoVLOXSEG5EI16_V_MF2_MF4,
18519 0 : 4677 => Opcode::PseudoVLOXSEG5EI16_V_MF2_MF4_MASK,
18520 0 : 4678 => Opcode::PseudoVLOXSEG5EI16_V_MF4_M1,
18521 0 : 4679 => Opcode::PseudoVLOXSEG5EI16_V_MF4_M1_MASK,
18522 0 : 4680 => Opcode::PseudoVLOXSEG5EI16_V_MF4_MF2,
18523 0 : 4681 => Opcode::PseudoVLOXSEG5EI16_V_MF4_MF2_MASK,
18524 0 : 4682 => Opcode::PseudoVLOXSEG5EI16_V_MF4_MF4,
18525 0 : 4683 => Opcode::PseudoVLOXSEG5EI16_V_MF4_MF4_MASK,
18526 0 : 4684 => Opcode::PseudoVLOXSEG5EI16_V_MF4_MF8,
18527 0 : 4685 => Opcode::PseudoVLOXSEG5EI16_V_MF4_MF8_MASK,
18528 0 : 4686 => Opcode::PseudoVLOXSEG5EI32_V_M1_M1,
18529 0 : 4687 => Opcode::PseudoVLOXSEG5EI32_V_M1_M1_MASK,
18530 0 : 4688 => Opcode::PseudoVLOXSEG5EI32_V_M1_MF2,
18531 0 : 4689 => Opcode::PseudoVLOXSEG5EI32_V_M1_MF2_MASK,
18532 0 : 4690 => Opcode::PseudoVLOXSEG5EI32_V_M1_MF4,
18533 0 : 4691 => Opcode::PseudoVLOXSEG5EI32_V_M1_MF4_MASK,
18534 0 : 4692 => Opcode::PseudoVLOXSEG5EI32_V_M2_M1,
18535 0 : 4693 => Opcode::PseudoVLOXSEG5EI32_V_M2_M1_MASK,
18536 0 : 4694 => Opcode::PseudoVLOXSEG5EI32_V_M2_MF2,
18537 0 : 4695 => Opcode::PseudoVLOXSEG5EI32_V_M2_MF2_MASK,
18538 0 : 4696 => Opcode::PseudoVLOXSEG5EI32_V_M4_M1,
18539 0 : 4697 => Opcode::PseudoVLOXSEG5EI32_V_M4_M1_MASK,
18540 0 : 4698 => Opcode::PseudoVLOXSEG5EI32_V_MF2_M1,
18541 0 : 4699 => Opcode::PseudoVLOXSEG5EI32_V_MF2_M1_MASK,
18542 0 : 4700 => Opcode::PseudoVLOXSEG5EI32_V_MF2_MF2,
18543 0 : 4701 => Opcode::PseudoVLOXSEG5EI32_V_MF2_MF2_MASK,
18544 0 : 4702 => Opcode::PseudoVLOXSEG5EI32_V_MF2_MF4,
18545 0 : 4703 => Opcode::PseudoVLOXSEG5EI32_V_MF2_MF4_MASK,
18546 0 : 4704 => Opcode::PseudoVLOXSEG5EI32_V_MF2_MF8,
18547 0 : 4705 => Opcode::PseudoVLOXSEG5EI32_V_MF2_MF8_MASK,
18548 0 : 4706 => Opcode::PseudoVLOXSEG5EI64_V_M1_M1,
18549 0 : 4707 => Opcode::PseudoVLOXSEG5EI64_V_M1_M1_MASK,
18550 0 : 4708 => Opcode::PseudoVLOXSEG5EI64_V_M1_MF2,
18551 0 : 4709 => Opcode::PseudoVLOXSEG5EI64_V_M1_MF2_MASK,
18552 0 : 4710 => Opcode::PseudoVLOXSEG5EI64_V_M1_MF4,
18553 0 : 4711 => Opcode::PseudoVLOXSEG5EI64_V_M1_MF4_MASK,
18554 0 : 4712 => Opcode::PseudoVLOXSEG5EI64_V_M1_MF8,
18555 0 : 4713 => Opcode::PseudoVLOXSEG5EI64_V_M1_MF8_MASK,
18556 0 : 4714 => Opcode::PseudoVLOXSEG5EI64_V_M2_M1,
18557 0 : 4715 => Opcode::PseudoVLOXSEG5EI64_V_M2_M1_MASK,
18558 0 : 4716 => Opcode::PseudoVLOXSEG5EI64_V_M2_MF2,
18559 0 : 4717 => Opcode::PseudoVLOXSEG5EI64_V_M2_MF2_MASK,
18560 0 : 4718 => Opcode::PseudoVLOXSEG5EI64_V_M2_MF4,
18561 0 : 4719 => Opcode::PseudoVLOXSEG5EI64_V_M2_MF4_MASK,
18562 0 : 4720 => Opcode::PseudoVLOXSEG5EI64_V_M4_M1,
18563 0 : 4721 => Opcode::PseudoVLOXSEG5EI64_V_M4_M1_MASK,
18564 0 : 4722 => Opcode::PseudoVLOXSEG5EI64_V_M4_MF2,
18565 0 : 4723 => Opcode::PseudoVLOXSEG5EI64_V_M4_MF2_MASK,
18566 0 : 4724 => Opcode::PseudoVLOXSEG5EI64_V_M8_M1,
18567 0 : 4725 => Opcode::PseudoVLOXSEG5EI64_V_M8_M1_MASK,
18568 0 : 4726 => Opcode::PseudoVLOXSEG5EI8_V_M1_M1,
18569 0 : 4727 => Opcode::PseudoVLOXSEG5EI8_V_M1_M1_MASK,
18570 0 : 4728 => Opcode::PseudoVLOXSEG5EI8_V_MF2_M1,
18571 0 : 4729 => Opcode::PseudoVLOXSEG5EI8_V_MF2_M1_MASK,
18572 0 : 4730 => Opcode::PseudoVLOXSEG5EI8_V_MF2_MF2,
18573 0 : 4731 => Opcode::PseudoVLOXSEG5EI8_V_MF2_MF2_MASK,
18574 0 : 4732 => Opcode::PseudoVLOXSEG5EI8_V_MF4_M1,
18575 0 : 4733 => Opcode::PseudoVLOXSEG5EI8_V_MF4_M1_MASK,
18576 0 : 4734 => Opcode::PseudoVLOXSEG5EI8_V_MF4_MF2,
18577 0 : 4735 => Opcode::PseudoVLOXSEG5EI8_V_MF4_MF2_MASK,
18578 0 : 4736 => Opcode::PseudoVLOXSEG5EI8_V_MF4_MF4,
18579 0 : 4737 => Opcode::PseudoVLOXSEG5EI8_V_MF4_MF4_MASK,
18580 0 : 4738 => Opcode::PseudoVLOXSEG5EI8_V_MF8_M1,
18581 0 : 4739 => Opcode::PseudoVLOXSEG5EI8_V_MF8_M1_MASK,
18582 0 : 4740 => Opcode::PseudoVLOXSEG5EI8_V_MF8_MF2,
18583 0 : 4741 => Opcode::PseudoVLOXSEG5EI8_V_MF8_MF2_MASK,
18584 0 : 4742 => Opcode::PseudoVLOXSEG5EI8_V_MF8_MF4,
18585 0 : 4743 => Opcode::PseudoVLOXSEG5EI8_V_MF8_MF4_MASK,
18586 0 : 4744 => Opcode::PseudoVLOXSEG5EI8_V_MF8_MF8,
18587 0 : 4745 => Opcode::PseudoVLOXSEG5EI8_V_MF8_MF8_MASK,
18588 0 : 4746 => Opcode::PseudoVLOXSEG6EI16_V_M1_M1,
18589 0 : 4747 => Opcode::PseudoVLOXSEG6EI16_V_M1_M1_MASK,
18590 0 : 4748 => Opcode::PseudoVLOXSEG6EI16_V_M1_MF2,
18591 0 : 4749 => Opcode::PseudoVLOXSEG6EI16_V_M1_MF2_MASK,
18592 0 : 4750 => Opcode::PseudoVLOXSEG6EI16_V_M2_M1,
18593 0 : 4751 => Opcode::PseudoVLOXSEG6EI16_V_M2_M1_MASK,
18594 0 : 4752 => Opcode::PseudoVLOXSEG6EI16_V_MF2_M1,
18595 0 : 4753 => Opcode::PseudoVLOXSEG6EI16_V_MF2_M1_MASK,
18596 0 : 4754 => Opcode::PseudoVLOXSEG6EI16_V_MF2_MF2,
18597 0 : 4755 => Opcode::PseudoVLOXSEG6EI16_V_MF2_MF2_MASK,
18598 0 : 4756 => Opcode::PseudoVLOXSEG6EI16_V_MF2_MF4,
18599 0 : 4757 => Opcode::PseudoVLOXSEG6EI16_V_MF2_MF4_MASK,
18600 0 : 4758 => Opcode::PseudoVLOXSEG6EI16_V_MF4_M1,
18601 0 : 4759 => Opcode::PseudoVLOXSEG6EI16_V_MF4_M1_MASK,
18602 0 : 4760 => Opcode::PseudoVLOXSEG6EI16_V_MF4_MF2,
18603 0 : 4761 => Opcode::PseudoVLOXSEG6EI16_V_MF4_MF2_MASK,
18604 0 : 4762 => Opcode::PseudoVLOXSEG6EI16_V_MF4_MF4,
18605 0 : 4763 => Opcode::PseudoVLOXSEG6EI16_V_MF4_MF4_MASK,
18606 0 : 4764 => Opcode::PseudoVLOXSEG6EI16_V_MF4_MF8,
18607 0 : 4765 => Opcode::PseudoVLOXSEG6EI16_V_MF4_MF8_MASK,
18608 0 : 4766 => Opcode::PseudoVLOXSEG6EI32_V_M1_M1,
18609 0 : 4767 => Opcode::PseudoVLOXSEG6EI32_V_M1_M1_MASK,
18610 0 : 4768 => Opcode::PseudoVLOXSEG6EI32_V_M1_MF2,
18611 0 : 4769 => Opcode::PseudoVLOXSEG6EI32_V_M1_MF2_MASK,
18612 0 : 4770 => Opcode::PseudoVLOXSEG6EI32_V_M1_MF4,
18613 0 : 4771 => Opcode::PseudoVLOXSEG6EI32_V_M1_MF4_MASK,
18614 0 : 4772 => Opcode::PseudoVLOXSEG6EI32_V_M2_M1,
18615 0 : 4773 => Opcode::PseudoVLOXSEG6EI32_V_M2_M1_MASK,
18616 0 : 4774 => Opcode::PseudoVLOXSEG6EI32_V_M2_MF2,
18617 0 : 4775 => Opcode::PseudoVLOXSEG6EI32_V_M2_MF2_MASK,
18618 0 : 4776 => Opcode::PseudoVLOXSEG6EI32_V_M4_M1,
18619 0 : 4777 => Opcode::PseudoVLOXSEG6EI32_V_M4_M1_MASK,
18620 0 : 4778 => Opcode::PseudoVLOXSEG6EI32_V_MF2_M1,
18621 0 : 4779 => Opcode::PseudoVLOXSEG6EI32_V_MF2_M1_MASK,
18622 0 : 4780 => Opcode::PseudoVLOXSEG6EI32_V_MF2_MF2,
18623 0 : 4781 => Opcode::PseudoVLOXSEG6EI32_V_MF2_MF2_MASK,
18624 0 : 4782 => Opcode::PseudoVLOXSEG6EI32_V_MF2_MF4,
18625 0 : 4783 => Opcode::PseudoVLOXSEG6EI32_V_MF2_MF4_MASK,
18626 0 : 4784 => Opcode::PseudoVLOXSEG6EI32_V_MF2_MF8,
18627 0 : 4785 => Opcode::PseudoVLOXSEG6EI32_V_MF2_MF8_MASK,
18628 0 : 4786 => Opcode::PseudoVLOXSEG6EI64_V_M1_M1,
18629 0 : 4787 => Opcode::PseudoVLOXSEG6EI64_V_M1_M1_MASK,
18630 0 : 4788 => Opcode::PseudoVLOXSEG6EI64_V_M1_MF2,
18631 0 : 4789 => Opcode::PseudoVLOXSEG6EI64_V_M1_MF2_MASK,
18632 0 : 4790 => Opcode::PseudoVLOXSEG6EI64_V_M1_MF4,
18633 0 : 4791 => Opcode::PseudoVLOXSEG6EI64_V_M1_MF4_MASK,
18634 0 : 4792 => Opcode::PseudoVLOXSEG6EI64_V_M1_MF8,
18635 0 : 4793 => Opcode::PseudoVLOXSEG6EI64_V_M1_MF8_MASK,
18636 0 : 4794 => Opcode::PseudoVLOXSEG6EI64_V_M2_M1,
18637 0 : 4795 => Opcode::PseudoVLOXSEG6EI64_V_M2_M1_MASK,
18638 0 : 4796 => Opcode::PseudoVLOXSEG6EI64_V_M2_MF2,
18639 0 : 4797 => Opcode::PseudoVLOXSEG6EI64_V_M2_MF2_MASK,
18640 0 : 4798 => Opcode::PseudoVLOXSEG6EI64_V_M2_MF4,
18641 0 : 4799 => Opcode::PseudoVLOXSEG6EI64_V_M2_MF4_MASK,
18642 0 : 4800 => Opcode::PseudoVLOXSEG6EI64_V_M4_M1,
18643 0 : 4801 => Opcode::PseudoVLOXSEG6EI64_V_M4_M1_MASK,
18644 0 : 4802 => Opcode::PseudoVLOXSEG6EI64_V_M4_MF2,
18645 0 : 4803 => Opcode::PseudoVLOXSEG6EI64_V_M4_MF2_MASK,
18646 0 : 4804 => Opcode::PseudoVLOXSEG6EI64_V_M8_M1,
18647 0 : 4805 => Opcode::PseudoVLOXSEG6EI64_V_M8_M1_MASK,
18648 0 : 4806 => Opcode::PseudoVLOXSEG6EI8_V_M1_M1,
18649 0 : 4807 => Opcode::PseudoVLOXSEG6EI8_V_M1_M1_MASK,
18650 0 : 4808 => Opcode::PseudoVLOXSEG6EI8_V_MF2_M1,
18651 0 : 4809 => Opcode::PseudoVLOXSEG6EI8_V_MF2_M1_MASK,
18652 0 : 4810 => Opcode::PseudoVLOXSEG6EI8_V_MF2_MF2,
18653 0 : 4811 => Opcode::PseudoVLOXSEG6EI8_V_MF2_MF2_MASK,
18654 0 : 4812 => Opcode::PseudoVLOXSEG6EI8_V_MF4_M1,
18655 0 : 4813 => Opcode::PseudoVLOXSEG6EI8_V_MF4_M1_MASK,
18656 0 : 4814 => Opcode::PseudoVLOXSEG6EI8_V_MF4_MF2,
18657 0 : 4815 => Opcode::PseudoVLOXSEG6EI8_V_MF4_MF2_MASK,
18658 0 : 4816 => Opcode::PseudoVLOXSEG6EI8_V_MF4_MF4,
18659 0 : 4817 => Opcode::PseudoVLOXSEG6EI8_V_MF4_MF4_MASK,
18660 0 : 4818 => Opcode::PseudoVLOXSEG6EI8_V_MF8_M1,
18661 0 : 4819 => Opcode::PseudoVLOXSEG6EI8_V_MF8_M1_MASK,
18662 0 : 4820 => Opcode::PseudoVLOXSEG6EI8_V_MF8_MF2,
18663 0 : 4821 => Opcode::PseudoVLOXSEG6EI8_V_MF8_MF2_MASK,
18664 0 : 4822 => Opcode::PseudoVLOXSEG6EI8_V_MF8_MF4,
18665 0 : 4823 => Opcode::PseudoVLOXSEG6EI8_V_MF8_MF4_MASK,
18666 0 : 4824 => Opcode::PseudoVLOXSEG6EI8_V_MF8_MF8,
18667 0 : 4825 => Opcode::PseudoVLOXSEG6EI8_V_MF8_MF8_MASK,
18668 0 : 4826 => Opcode::PseudoVLOXSEG7EI16_V_M1_M1,
18669 0 : 4827 => Opcode::PseudoVLOXSEG7EI16_V_M1_M1_MASK,
18670 0 : 4828 => Opcode::PseudoVLOXSEG7EI16_V_M1_MF2,
18671 0 : 4829 => Opcode::PseudoVLOXSEG7EI16_V_M1_MF2_MASK,
18672 0 : 4830 => Opcode::PseudoVLOXSEG7EI16_V_M2_M1,
18673 0 : 4831 => Opcode::PseudoVLOXSEG7EI16_V_M2_M1_MASK,
18674 0 : 4832 => Opcode::PseudoVLOXSEG7EI16_V_MF2_M1,
18675 0 : 4833 => Opcode::PseudoVLOXSEG7EI16_V_MF2_M1_MASK,
18676 0 : 4834 => Opcode::PseudoVLOXSEG7EI16_V_MF2_MF2,
18677 0 : 4835 => Opcode::PseudoVLOXSEG7EI16_V_MF2_MF2_MASK,
18678 0 : 4836 => Opcode::PseudoVLOXSEG7EI16_V_MF2_MF4,
18679 0 : 4837 => Opcode::PseudoVLOXSEG7EI16_V_MF2_MF4_MASK,
18680 0 : 4838 => Opcode::PseudoVLOXSEG7EI16_V_MF4_M1,
18681 0 : 4839 => Opcode::PseudoVLOXSEG7EI16_V_MF4_M1_MASK,
18682 0 : 4840 => Opcode::PseudoVLOXSEG7EI16_V_MF4_MF2,
18683 0 : 4841 => Opcode::PseudoVLOXSEG7EI16_V_MF4_MF2_MASK,
18684 0 : 4842 => Opcode::PseudoVLOXSEG7EI16_V_MF4_MF4,
18685 0 : 4843 => Opcode::PseudoVLOXSEG7EI16_V_MF4_MF4_MASK,
18686 0 : 4844 => Opcode::PseudoVLOXSEG7EI16_V_MF4_MF8,
18687 0 : 4845 => Opcode::PseudoVLOXSEG7EI16_V_MF4_MF8_MASK,
18688 0 : 4846 => Opcode::PseudoVLOXSEG7EI32_V_M1_M1,
18689 0 : 4847 => Opcode::PseudoVLOXSEG7EI32_V_M1_M1_MASK,
18690 0 : 4848 => Opcode::PseudoVLOXSEG7EI32_V_M1_MF2,
18691 0 : 4849 => Opcode::PseudoVLOXSEG7EI32_V_M1_MF2_MASK,
18692 0 : 4850 => Opcode::PseudoVLOXSEG7EI32_V_M1_MF4,
18693 0 : 4851 => Opcode::PseudoVLOXSEG7EI32_V_M1_MF4_MASK,
18694 0 : 4852 => Opcode::PseudoVLOXSEG7EI32_V_M2_M1,
18695 0 : 4853 => Opcode::PseudoVLOXSEG7EI32_V_M2_M1_MASK,
18696 0 : 4854 => Opcode::PseudoVLOXSEG7EI32_V_M2_MF2,
18697 0 : 4855 => Opcode::PseudoVLOXSEG7EI32_V_M2_MF2_MASK,
18698 0 : 4856 => Opcode::PseudoVLOXSEG7EI32_V_M4_M1,
18699 0 : 4857 => Opcode::PseudoVLOXSEG7EI32_V_M4_M1_MASK,
18700 0 : 4858 => Opcode::PseudoVLOXSEG7EI32_V_MF2_M1,
18701 0 : 4859 => Opcode::PseudoVLOXSEG7EI32_V_MF2_M1_MASK,
18702 0 : 4860 => Opcode::PseudoVLOXSEG7EI32_V_MF2_MF2,
18703 0 : 4861 => Opcode::PseudoVLOXSEG7EI32_V_MF2_MF2_MASK,
18704 0 : 4862 => Opcode::PseudoVLOXSEG7EI32_V_MF2_MF4,
18705 0 : 4863 => Opcode::PseudoVLOXSEG7EI32_V_MF2_MF4_MASK,
18706 0 : 4864 => Opcode::PseudoVLOXSEG7EI32_V_MF2_MF8,
18707 0 : 4865 => Opcode::PseudoVLOXSEG7EI32_V_MF2_MF8_MASK,
18708 0 : 4866 => Opcode::PseudoVLOXSEG7EI64_V_M1_M1,
18709 0 : 4867 => Opcode::PseudoVLOXSEG7EI64_V_M1_M1_MASK,
18710 0 : 4868 => Opcode::PseudoVLOXSEG7EI64_V_M1_MF2,
18711 0 : 4869 => Opcode::PseudoVLOXSEG7EI64_V_M1_MF2_MASK,
18712 0 : 4870 => Opcode::PseudoVLOXSEG7EI64_V_M1_MF4,
18713 0 : 4871 => Opcode::PseudoVLOXSEG7EI64_V_M1_MF4_MASK,
18714 0 : 4872 => Opcode::PseudoVLOXSEG7EI64_V_M1_MF8,
18715 0 : 4873 => Opcode::PseudoVLOXSEG7EI64_V_M1_MF8_MASK,
18716 0 : 4874 => Opcode::PseudoVLOXSEG7EI64_V_M2_M1,
18717 0 : 4875 => Opcode::PseudoVLOXSEG7EI64_V_M2_M1_MASK,
18718 0 : 4876 => Opcode::PseudoVLOXSEG7EI64_V_M2_MF2,
18719 0 : 4877 => Opcode::PseudoVLOXSEG7EI64_V_M2_MF2_MASK,
18720 0 : 4878 => Opcode::PseudoVLOXSEG7EI64_V_M2_MF4,
18721 0 : 4879 => Opcode::PseudoVLOXSEG7EI64_V_M2_MF4_MASK,
18722 0 : 4880 => Opcode::PseudoVLOXSEG7EI64_V_M4_M1,
18723 0 : 4881 => Opcode::PseudoVLOXSEG7EI64_V_M4_M1_MASK,
18724 0 : 4882 => Opcode::PseudoVLOXSEG7EI64_V_M4_MF2,
18725 0 : 4883 => Opcode::PseudoVLOXSEG7EI64_V_M4_MF2_MASK,
18726 0 : 4884 => Opcode::PseudoVLOXSEG7EI64_V_M8_M1,
18727 0 : 4885 => Opcode::PseudoVLOXSEG7EI64_V_M8_M1_MASK,
18728 0 : 4886 => Opcode::PseudoVLOXSEG7EI8_V_M1_M1,
18729 0 : 4887 => Opcode::PseudoVLOXSEG7EI8_V_M1_M1_MASK,
18730 0 : 4888 => Opcode::PseudoVLOXSEG7EI8_V_MF2_M1,
18731 0 : 4889 => Opcode::PseudoVLOXSEG7EI8_V_MF2_M1_MASK,
18732 0 : 4890 => Opcode::PseudoVLOXSEG7EI8_V_MF2_MF2,
18733 0 : 4891 => Opcode::PseudoVLOXSEG7EI8_V_MF2_MF2_MASK,
18734 0 : 4892 => Opcode::PseudoVLOXSEG7EI8_V_MF4_M1,
18735 0 : 4893 => Opcode::PseudoVLOXSEG7EI8_V_MF4_M1_MASK,
18736 0 : 4894 => Opcode::PseudoVLOXSEG7EI8_V_MF4_MF2,
18737 0 : 4895 => Opcode::PseudoVLOXSEG7EI8_V_MF4_MF2_MASK,
18738 0 : 4896 => Opcode::PseudoVLOXSEG7EI8_V_MF4_MF4,
18739 0 : 4897 => Opcode::PseudoVLOXSEG7EI8_V_MF4_MF4_MASK,
18740 0 : 4898 => Opcode::PseudoVLOXSEG7EI8_V_MF8_M1,
18741 0 : 4899 => Opcode::PseudoVLOXSEG7EI8_V_MF8_M1_MASK,
18742 0 : 4900 => Opcode::PseudoVLOXSEG7EI8_V_MF8_MF2,
18743 0 : 4901 => Opcode::PseudoVLOXSEG7EI8_V_MF8_MF2_MASK,
18744 0 : 4902 => Opcode::PseudoVLOXSEG7EI8_V_MF8_MF4,
18745 0 : 4903 => Opcode::PseudoVLOXSEG7EI8_V_MF8_MF4_MASK,
18746 0 : 4904 => Opcode::PseudoVLOXSEG7EI8_V_MF8_MF8,
18747 0 : 4905 => Opcode::PseudoVLOXSEG7EI8_V_MF8_MF8_MASK,
18748 0 : 4906 => Opcode::PseudoVLOXSEG8EI16_V_M1_M1,
18749 0 : 4907 => Opcode::PseudoVLOXSEG8EI16_V_M1_M1_MASK,
18750 0 : 4908 => Opcode::PseudoVLOXSEG8EI16_V_M1_MF2,
18751 0 : 4909 => Opcode::PseudoVLOXSEG8EI16_V_M1_MF2_MASK,
18752 0 : 4910 => Opcode::PseudoVLOXSEG8EI16_V_M2_M1,
18753 0 : 4911 => Opcode::PseudoVLOXSEG8EI16_V_M2_M1_MASK,
18754 0 : 4912 => Opcode::PseudoVLOXSEG8EI16_V_MF2_M1,
18755 0 : 4913 => Opcode::PseudoVLOXSEG8EI16_V_MF2_M1_MASK,
18756 0 : 4914 => Opcode::PseudoVLOXSEG8EI16_V_MF2_MF2,
18757 0 : 4915 => Opcode::PseudoVLOXSEG8EI16_V_MF2_MF2_MASK,
18758 0 : 4916 => Opcode::PseudoVLOXSEG8EI16_V_MF2_MF4,
18759 0 : 4917 => Opcode::PseudoVLOXSEG8EI16_V_MF2_MF4_MASK,
18760 0 : 4918 => Opcode::PseudoVLOXSEG8EI16_V_MF4_M1,
18761 0 : 4919 => Opcode::PseudoVLOXSEG8EI16_V_MF4_M1_MASK,
18762 0 : 4920 => Opcode::PseudoVLOXSEG8EI16_V_MF4_MF2,
18763 0 : 4921 => Opcode::PseudoVLOXSEG8EI16_V_MF4_MF2_MASK,
18764 0 : 4922 => Opcode::PseudoVLOXSEG8EI16_V_MF4_MF4,
18765 0 : 4923 => Opcode::PseudoVLOXSEG8EI16_V_MF4_MF4_MASK,
18766 0 : 4924 => Opcode::PseudoVLOXSEG8EI16_V_MF4_MF8,
18767 0 : 4925 => Opcode::PseudoVLOXSEG8EI16_V_MF4_MF8_MASK,
18768 0 : 4926 => Opcode::PseudoVLOXSEG8EI32_V_M1_M1,
18769 0 : 4927 => Opcode::PseudoVLOXSEG8EI32_V_M1_M1_MASK,
18770 0 : 4928 => Opcode::PseudoVLOXSEG8EI32_V_M1_MF2,
18771 0 : 4929 => Opcode::PseudoVLOXSEG8EI32_V_M1_MF2_MASK,
18772 0 : 4930 => Opcode::PseudoVLOXSEG8EI32_V_M1_MF4,
18773 0 : 4931 => Opcode::PseudoVLOXSEG8EI32_V_M1_MF4_MASK,
18774 0 : 4932 => Opcode::PseudoVLOXSEG8EI32_V_M2_M1,
18775 0 : 4933 => Opcode::PseudoVLOXSEG8EI32_V_M2_M1_MASK,
18776 0 : 4934 => Opcode::PseudoVLOXSEG8EI32_V_M2_MF2,
18777 0 : 4935 => Opcode::PseudoVLOXSEG8EI32_V_M2_MF2_MASK,
18778 0 : 4936 => Opcode::PseudoVLOXSEG8EI32_V_M4_M1,
18779 0 : 4937 => Opcode::PseudoVLOXSEG8EI32_V_M4_M1_MASK,
18780 0 : 4938 => Opcode::PseudoVLOXSEG8EI32_V_MF2_M1,
18781 0 : 4939 => Opcode::PseudoVLOXSEG8EI32_V_MF2_M1_MASK,
18782 0 : 4940 => Opcode::PseudoVLOXSEG8EI32_V_MF2_MF2,
18783 0 : 4941 => Opcode::PseudoVLOXSEG8EI32_V_MF2_MF2_MASK,
18784 0 : 4942 => Opcode::PseudoVLOXSEG8EI32_V_MF2_MF4,
18785 0 : 4943 => Opcode::PseudoVLOXSEG8EI32_V_MF2_MF4_MASK,
18786 0 : 4944 => Opcode::PseudoVLOXSEG8EI32_V_MF2_MF8,
18787 0 : 4945 => Opcode::PseudoVLOXSEG8EI32_V_MF2_MF8_MASK,
18788 0 : 4946 => Opcode::PseudoVLOXSEG8EI64_V_M1_M1,
18789 0 : 4947 => Opcode::PseudoVLOXSEG8EI64_V_M1_M1_MASK,
18790 0 : 4948 => Opcode::PseudoVLOXSEG8EI64_V_M1_MF2,
18791 0 : 4949 => Opcode::PseudoVLOXSEG8EI64_V_M1_MF2_MASK,
18792 0 : 4950 => Opcode::PseudoVLOXSEG8EI64_V_M1_MF4,
18793 0 : 4951 => Opcode::PseudoVLOXSEG8EI64_V_M1_MF4_MASK,
18794 0 : 4952 => Opcode::PseudoVLOXSEG8EI64_V_M1_MF8,
18795 0 : 4953 => Opcode::PseudoVLOXSEG8EI64_V_M1_MF8_MASK,
18796 0 : 4954 => Opcode::PseudoVLOXSEG8EI64_V_M2_M1,
18797 0 : 4955 => Opcode::PseudoVLOXSEG8EI64_V_M2_M1_MASK,
18798 0 : 4956 => Opcode::PseudoVLOXSEG8EI64_V_M2_MF2,
18799 0 : 4957 => Opcode::PseudoVLOXSEG8EI64_V_M2_MF2_MASK,
18800 0 : 4958 => Opcode::PseudoVLOXSEG8EI64_V_M2_MF4,
18801 0 : 4959 => Opcode::PseudoVLOXSEG8EI64_V_M2_MF4_MASK,
18802 0 : 4960 => Opcode::PseudoVLOXSEG8EI64_V_M4_M1,
18803 0 : 4961 => Opcode::PseudoVLOXSEG8EI64_V_M4_M1_MASK,
18804 0 : 4962 => Opcode::PseudoVLOXSEG8EI64_V_M4_MF2,
18805 0 : 4963 => Opcode::PseudoVLOXSEG8EI64_V_M4_MF2_MASK,
18806 0 : 4964 => Opcode::PseudoVLOXSEG8EI64_V_M8_M1,
18807 0 : 4965 => Opcode::PseudoVLOXSEG8EI64_V_M8_M1_MASK,
18808 0 : 4966 => Opcode::PseudoVLOXSEG8EI8_V_M1_M1,
18809 0 : 4967 => Opcode::PseudoVLOXSEG8EI8_V_M1_M1_MASK,
18810 0 : 4968 => Opcode::PseudoVLOXSEG8EI8_V_MF2_M1,
18811 0 : 4969 => Opcode::PseudoVLOXSEG8EI8_V_MF2_M1_MASK,
18812 0 : 4970 => Opcode::PseudoVLOXSEG8EI8_V_MF2_MF2,
18813 0 : 4971 => Opcode::PseudoVLOXSEG8EI8_V_MF2_MF2_MASK,
18814 0 : 4972 => Opcode::PseudoVLOXSEG8EI8_V_MF4_M1,
18815 0 : 4973 => Opcode::PseudoVLOXSEG8EI8_V_MF4_M1_MASK,
18816 0 : 4974 => Opcode::PseudoVLOXSEG8EI8_V_MF4_MF2,
18817 0 : 4975 => Opcode::PseudoVLOXSEG8EI8_V_MF4_MF2_MASK,
18818 0 : 4976 => Opcode::PseudoVLOXSEG8EI8_V_MF4_MF4,
18819 0 : 4977 => Opcode::PseudoVLOXSEG8EI8_V_MF4_MF4_MASK,
18820 0 : 4978 => Opcode::PseudoVLOXSEG8EI8_V_MF8_M1,
18821 0 : 4979 => Opcode::PseudoVLOXSEG8EI8_V_MF8_M1_MASK,
18822 0 : 4980 => Opcode::PseudoVLOXSEG8EI8_V_MF8_MF2,
18823 0 : 4981 => Opcode::PseudoVLOXSEG8EI8_V_MF8_MF2_MASK,
18824 0 : 4982 => Opcode::PseudoVLOXSEG8EI8_V_MF8_MF4,
18825 0 : 4983 => Opcode::PseudoVLOXSEG8EI8_V_MF8_MF4_MASK,
18826 0 : 4984 => Opcode::PseudoVLOXSEG8EI8_V_MF8_MF8,
18827 0 : 4985 => Opcode::PseudoVLOXSEG8EI8_V_MF8_MF8_MASK,
18828 0 : 4986 => Opcode::PseudoVLSE16_V_M1,
18829 0 : 4987 => Opcode::PseudoVLSE16_V_M1_MASK,
18830 0 : 4988 => Opcode::PseudoVLSE16_V_M2,
18831 0 : 4989 => Opcode::PseudoVLSE16_V_M2_MASK,
18832 0 : 4990 => Opcode::PseudoVLSE16_V_M4,
18833 0 : 4991 => Opcode::PseudoVLSE16_V_M4_MASK,
18834 0 : 4992 => Opcode::PseudoVLSE16_V_M8,
18835 0 : 4993 => Opcode::PseudoVLSE16_V_M8_MASK,
18836 0 : 4994 => Opcode::PseudoVLSE16_V_MF2,
18837 0 : 4995 => Opcode::PseudoVLSE16_V_MF2_MASK,
18838 0 : 4996 => Opcode::PseudoVLSE16_V_MF4,
18839 0 : 4997 => Opcode::PseudoVLSE16_V_MF4_MASK,
18840 0 : 4998 => Opcode::PseudoVLSE32_V_M1,
18841 0 : 4999 => Opcode::PseudoVLSE32_V_M1_MASK,
18842 0 : 5000 => Opcode::PseudoVLSE32_V_M2,
18843 0 : 5001 => Opcode::PseudoVLSE32_V_M2_MASK,
18844 0 : 5002 => Opcode::PseudoVLSE32_V_M4,
18845 0 : 5003 => Opcode::PseudoVLSE32_V_M4_MASK,
18846 0 : 5004 => Opcode::PseudoVLSE32_V_M8,
18847 0 : 5005 => Opcode::PseudoVLSE32_V_M8_MASK,
18848 0 : 5006 => Opcode::PseudoVLSE32_V_MF2,
18849 0 : 5007 => Opcode::PseudoVLSE32_V_MF2_MASK,
18850 0 : 5008 => Opcode::PseudoVLSE64_V_M1,
18851 0 : 5009 => Opcode::PseudoVLSE64_V_M1_MASK,
18852 0 : 5010 => Opcode::PseudoVLSE64_V_M2,
18853 0 : 5011 => Opcode::PseudoVLSE64_V_M2_MASK,
18854 0 : 5012 => Opcode::PseudoVLSE64_V_M4,
18855 0 : 5013 => Opcode::PseudoVLSE64_V_M4_MASK,
18856 0 : 5014 => Opcode::PseudoVLSE64_V_M8,
18857 0 : 5015 => Opcode::PseudoVLSE64_V_M8_MASK,
18858 0 : 5016 => Opcode::PseudoVLSE8_V_M1,
18859 0 : 5017 => Opcode::PseudoVLSE8_V_M1_MASK,
18860 0 : 5018 => Opcode::PseudoVLSE8_V_M2,
18861 0 : 5019 => Opcode::PseudoVLSE8_V_M2_MASK,
18862 0 : 5020 => Opcode::PseudoVLSE8_V_M4,
18863 0 : 5021 => Opcode::PseudoVLSE8_V_M4_MASK,
18864 0 : 5022 => Opcode::PseudoVLSE8_V_M8,
18865 0 : 5023 => Opcode::PseudoVLSE8_V_M8_MASK,
18866 0 : 5024 => Opcode::PseudoVLSE8_V_MF2,
18867 0 : 5025 => Opcode::PseudoVLSE8_V_MF2_MASK,
18868 0 : 5026 => Opcode::PseudoVLSE8_V_MF4,
18869 0 : 5027 => Opcode::PseudoVLSE8_V_MF4_MASK,
18870 0 : 5028 => Opcode::PseudoVLSE8_V_MF8,
18871 0 : 5029 => Opcode::PseudoVLSE8_V_MF8_MASK,
18872 0 : 5030 => Opcode::PseudoVLSEG2E16FF_V_M1,
18873 0 : 5031 => Opcode::PseudoVLSEG2E16FF_V_M1_MASK,
18874 0 : 5032 => Opcode::PseudoVLSEG2E16FF_V_M2,
18875 0 : 5033 => Opcode::PseudoVLSEG2E16FF_V_M2_MASK,
18876 0 : 5034 => Opcode::PseudoVLSEG2E16FF_V_M4,
18877 0 : 5035 => Opcode::PseudoVLSEG2E16FF_V_M4_MASK,
18878 0 : 5036 => Opcode::PseudoVLSEG2E16FF_V_MF2,
18879 0 : 5037 => Opcode::PseudoVLSEG2E16FF_V_MF2_MASK,
18880 0 : 5038 => Opcode::PseudoVLSEG2E16FF_V_MF4,
18881 0 : 5039 => Opcode::PseudoVLSEG2E16FF_V_MF4_MASK,
18882 0 : 5040 => Opcode::PseudoVLSEG2E16_V_M1,
18883 0 : 5041 => Opcode::PseudoVLSEG2E16_V_M1_MASK,
18884 0 : 5042 => Opcode::PseudoVLSEG2E16_V_M2,
18885 0 : 5043 => Opcode::PseudoVLSEG2E16_V_M2_MASK,
18886 0 : 5044 => Opcode::PseudoVLSEG2E16_V_M4,
18887 0 : 5045 => Opcode::PseudoVLSEG2E16_V_M4_MASK,
18888 0 : 5046 => Opcode::PseudoVLSEG2E16_V_MF2,
18889 0 : 5047 => Opcode::PseudoVLSEG2E16_V_MF2_MASK,
18890 0 : 5048 => Opcode::PseudoVLSEG2E16_V_MF4,
18891 0 : 5049 => Opcode::PseudoVLSEG2E16_V_MF4_MASK,
18892 0 : 5050 => Opcode::PseudoVLSEG2E32FF_V_M1,
18893 0 : 5051 => Opcode::PseudoVLSEG2E32FF_V_M1_MASK,
18894 0 : 5052 => Opcode::PseudoVLSEG2E32FF_V_M2,
18895 0 : 5053 => Opcode::PseudoVLSEG2E32FF_V_M2_MASK,
18896 0 : 5054 => Opcode::PseudoVLSEG2E32FF_V_M4,
18897 0 : 5055 => Opcode::PseudoVLSEG2E32FF_V_M4_MASK,
18898 0 : 5056 => Opcode::PseudoVLSEG2E32FF_V_MF2,
18899 0 : 5057 => Opcode::PseudoVLSEG2E32FF_V_MF2_MASK,
18900 0 : 5058 => Opcode::PseudoVLSEG2E32_V_M1,
18901 0 : 5059 => Opcode::PseudoVLSEG2E32_V_M1_MASK,
18902 0 : 5060 => Opcode::PseudoVLSEG2E32_V_M2,
18903 0 : 5061 => Opcode::PseudoVLSEG2E32_V_M2_MASK,
18904 0 : 5062 => Opcode::PseudoVLSEG2E32_V_M4,
18905 0 : 5063 => Opcode::PseudoVLSEG2E32_V_M4_MASK,
18906 0 : 5064 => Opcode::PseudoVLSEG2E32_V_MF2,
18907 0 : 5065 => Opcode::PseudoVLSEG2E32_V_MF2_MASK,
18908 0 : 5066 => Opcode::PseudoVLSEG2E64FF_V_M1,
18909 0 : 5067 => Opcode::PseudoVLSEG2E64FF_V_M1_MASK,
18910 0 : 5068 => Opcode::PseudoVLSEG2E64FF_V_M2,
18911 0 : 5069 => Opcode::PseudoVLSEG2E64FF_V_M2_MASK,
18912 0 : 5070 => Opcode::PseudoVLSEG2E64FF_V_M4,
18913 0 : 5071 => Opcode::PseudoVLSEG2E64FF_V_M4_MASK,
18914 0 : 5072 => Opcode::PseudoVLSEG2E64_V_M1,
18915 0 : 5073 => Opcode::PseudoVLSEG2E64_V_M1_MASK,
18916 0 : 5074 => Opcode::PseudoVLSEG2E64_V_M2,
18917 0 : 5075 => Opcode::PseudoVLSEG2E64_V_M2_MASK,
18918 0 : 5076 => Opcode::PseudoVLSEG2E64_V_M4,
18919 0 : 5077 => Opcode::PseudoVLSEG2E64_V_M4_MASK,
18920 0 : 5078 => Opcode::PseudoVLSEG2E8FF_V_M1,
18921 0 : 5079 => Opcode::PseudoVLSEG2E8FF_V_M1_MASK,
18922 0 : 5080 => Opcode::PseudoVLSEG2E8FF_V_M2,
18923 0 : 5081 => Opcode::PseudoVLSEG2E8FF_V_M2_MASK,
18924 0 : 5082 => Opcode::PseudoVLSEG2E8FF_V_M4,
18925 0 : 5083 => Opcode::PseudoVLSEG2E8FF_V_M4_MASK,
18926 0 : 5084 => Opcode::PseudoVLSEG2E8FF_V_MF2,
18927 0 : 5085 => Opcode::PseudoVLSEG2E8FF_V_MF2_MASK,
18928 0 : 5086 => Opcode::PseudoVLSEG2E8FF_V_MF4,
18929 0 : 5087 => Opcode::PseudoVLSEG2E8FF_V_MF4_MASK,
18930 0 : 5088 => Opcode::PseudoVLSEG2E8FF_V_MF8,
18931 0 : 5089 => Opcode::PseudoVLSEG2E8FF_V_MF8_MASK,
18932 0 : 5090 => Opcode::PseudoVLSEG2E8_V_M1,
18933 0 : 5091 => Opcode::PseudoVLSEG2E8_V_M1_MASK,
18934 0 : 5092 => Opcode::PseudoVLSEG2E8_V_M2,
18935 0 : 5093 => Opcode::PseudoVLSEG2E8_V_M2_MASK,
18936 0 : 5094 => Opcode::PseudoVLSEG2E8_V_M4,
18937 0 : 5095 => Opcode::PseudoVLSEG2E8_V_M4_MASK,
18938 0 : 5096 => Opcode::PseudoVLSEG2E8_V_MF2,
18939 0 : 5097 => Opcode::PseudoVLSEG2E8_V_MF2_MASK,
18940 0 : 5098 => Opcode::PseudoVLSEG2E8_V_MF4,
18941 0 : 5099 => Opcode::PseudoVLSEG2E8_V_MF4_MASK,
18942 0 : 5100 => Opcode::PseudoVLSEG2E8_V_MF8,
18943 0 : 5101 => Opcode::PseudoVLSEG2E8_V_MF8_MASK,
18944 0 : 5102 => Opcode::PseudoVLSEG3E16FF_V_M1,
18945 0 : 5103 => Opcode::PseudoVLSEG3E16FF_V_M1_MASK,
18946 0 : 5104 => Opcode::PseudoVLSEG3E16FF_V_M2,
18947 0 : 5105 => Opcode::PseudoVLSEG3E16FF_V_M2_MASK,
18948 0 : 5106 => Opcode::PseudoVLSEG3E16FF_V_MF2,
18949 0 : 5107 => Opcode::PseudoVLSEG3E16FF_V_MF2_MASK,
18950 0 : 5108 => Opcode::PseudoVLSEG3E16FF_V_MF4,
18951 0 : 5109 => Opcode::PseudoVLSEG3E16FF_V_MF4_MASK,
18952 0 : 5110 => Opcode::PseudoVLSEG3E16_V_M1,
18953 0 : 5111 => Opcode::PseudoVLSEG3E16_V_M1_MASK,
18954 0 : 5112 => Opcode::PseudoVLSEG3E16_V_M2,
18955 0 : 5113 => Opcode::PseudoVLSEG3E16_V_M2_MASK,
18956 0 : 5114 => Opcode::PseudoVLSEG3E16_V_MF2,
18957 0 : 5115 => Opcode::PseudoVLSEG3E16_V_MF2_MASK,
18958 0 : 5116 => Opcode::PseudoVLSEG3E16_V_MF4,
18959 0 : 5117 => Opcode::PseudoVLSEG3E16_V_MF4_MASK,
18960 0 : 5118 => Opcode::PseudoVLSEG3E32FF_V_M1,
18961 0 : 5119 => Opcode::PseudoVLSEG3E32FF_V_M1_MASK,
18962 0 : 5120 => Opcode::PseudoVLSEG3E32FF_V_M2,
18963 0 : 5121 => Opcode::PseudoVLSEG3E32FF_V_M2_MASK,
18964 0 : 5122 => Opcode::PseudoVLSEG3E32FF_V_MF2,
18965 0 : 5123 => Opcode::PseudoVLSEG3E32FF_V_MF2_MASK,
18966 0 : 5124 => Opcode::PseudoVLSEG3E32_V_M1,
18967 0 : 5125 => Opcode::PseudoVLSEG3E32_V_M1_MASK,
18968 0 : 5126 => Opcode::PseudoVLSEG3E32_V_M2,
18969 0 : 5127 => Opcode::PseudoVLSEG3E32_V_M2_MASK,
18970 0 : 5128 => Opcode::PseudoVLSEG3E32_V_MF2,
18971 0 : 5129 => Opcode::PseudoVLSEG3E32_V_MF2_MASK,
18972 0 : 5130 => Opcode::PseudoVLSEG3E64FF_V_M1,
18973 0 : 5131 => Opcode::PseudoVLSEG3E64FF_V_M1_MASK,
18974 0 : 5132 => Opcode::PseudoVLSEG3E64FF_V_M2,
18975 0 : 5133 => Opcode::PseudoVLSEG3E64FF_V_M2_MASK,
18976 0 : 5134 => Opcode::PseudoVLSEG3E64_V_M1,
18977 0 : 5135 => Opcode::PseudoVLSEG3E64_V_M1_MASK,
18978 0 : 5136 => Opcode::PseudoVLSEG3E64_V_M2,
18979 0 : 5137 => Opcode::PseudoVLSEG3E64_V_M2_MASK,
18980 0 : 5138 => Opcode::PseudoVLSEG3E8FF_V_M1,
18981 0 : 5139 => Opcode::PseudoVLSEG3E8FF_V_M1_MASK,
18982 0 : 5140 => Opcode::PseudoVLSEG3E8FF_V_M2,
18983 0 : 5141 => Opcode::PseudoVLSEG3E8FF_V_M2_MASK,
18984 0 : 5142 => Opcode::PseudoVLSEG3E8FF_V_MF2,
18985 0 : 5143 => Opcode::PseudoVLSEG3E8FF_V_MF2_MASK,
18986 0 : 5144 => Opcode::PseudoVLSEG3E8FF_V_MF4,
18987 0 : 5145 => Opcode::PseudoVLSEG3E8FF_V_MF4_MASK,
18988 0 : 5146 => Opcode::PseudoVLSEG3E8FF_V_MF8,
18989 0 : 5147 => Opcode::PseudoVLSEG3E8FF_V_MF8_MASK,
18990 0 : 5148 => Opcode::PseudoVLSEG3E8_V_M1,
18991 0 : 5149 => Opcode::PseudoVLSEG3E8_V_M1_MASK,
18992 0 : 5150 => Opcode::PseudoVLSEG3E8_V_M2,
18993 0 : 5151 => Opcode::PseudoVLSEG3E8_V_M2_MASK,
18994 0 : 5152 => Opcode::PseudoVLSEG3E8_V_MF2,
18995 0 : 5153 => Opcode::PseudoVLSEG3E8_V_MF2_MASK,
18996 0 : 5154 => Opcode::PseudoVLSEG3E8_V_MF4,
18997 0 : 5155 => Opcode::PseudoVLSEG3E8_V_MF4_MASK,
18998 0 : 5156 => Opcode::PseudoVLSEG3E8_V_MF8,
18999 0 : 5157 => Opcode::PseudoVLSEG3E8_V_MF8_MASK,
19000 0 : 5158 => Opcode::PseudoVLSEG4E16FF_V_M1,
19001 0 : 5159 => Opcode::PseudoVLSEG4E16FF_V_M1_MASK,
19002 0 : 5160 => Opcode::PseudoVLSEG4E16FF_V_M2,
19003 0 : 5161 => Opcode::PseudoVLSEG4E16FF_V_M2_MASK,
19004 0 : 5162 => Opcode::PseudoVLSEG4E16FF_V_MF2,
19005 0 : 5163 => Opcode::PseudoVLSEG4E16FF_V_MF2_MASK,
19006 0 : 5164 => Opcode::PseudoVLSEG4E16FF_V_MF4,
19007 0 : 5165 => Opcode::PseudoVLSEG4E16FF_V_MF4_MASK,
19008 0 : 5166 => Opcode::PseudoVLSEG4E16_V_M1,
19009 0 : 5167 => Opcode::PseudoVLSEG4E16_V_M1_MASK,
19010 0 : 5168 => Opcode::PseudoVLSEG4E16_V_M2,
19011 0 : 5169 => Opcode::PseudoVLSEG4E16_V_M2_MASK,
19012 0 : 5170 => Opcode::PseudoVLSEG4E16_V_MF2,
19013 0 : 5171 => Opcode::PseudoVLSEG4E16_V_MF2_MASK,
19014 0 : 5172 => Opcode::PseudoVLSEG4E16_V_MF4,
19015 0 : 5173 => Opcode::PseudoVLSEG4E16_V_MF4_MASK,
19016 0 : 5174 => Opcode::PseudoVLSEG4E32FF_V_M1,
19017 0 : 5175 => Opcode::PseudoVLSEG4E32FF_V_M1_MASK,
19018 0 : 5176 => Opcode::PseudoVLSEG4E32FF_V_M2,
19019 0 : 5177 => Opcode::PseudoVLSEG4E32FF_V_M2_MASK,
19020 0 : 5178 => Opcode::PseudoVLSEG4E32FF_V_MF2,
19021 0 : 5179 => Opcode::PseudoVLSEG4E32FF_V_MF2_MASK,
19022 0 : 5180 => Opcode::PseudoVLSEG4E32_V_M1,
19023 0 : 5181 => Opcode::PseudoVLSEG4E32_V_M1_MASK,
19024 0 : 5182 => Opcode::PseudoVLSEG4E32_V_M2,
19025 0 : 5183 => Opcode::PseudoVLSEG4E32_V_M2_MASK,
19026 0 : 5184 => Opcode::PseudoVLSEG4E32_V_MF2,
19027 0 : 5185 => Opcode::PseudoVLSEG4E32_V_MF2_MASK,
19028 0 : 5186 => Opcode::PseudoVLSEG4E64FF_V_M1,
19029 0 : 5187 => Opcode::PseudoVLSEG4E64FF_V_M1_MASK,
19030 0 : 5188 => Opcode::PseudoVLSEG4E64FF_V_M2,
19031 0 : 5189 => Opcode::PseudoVLSEG4E64FF_V_M2_MASK,
19032 0 : 5190 => Opcode::PseudoVLSEG4E64_V_M1,
19033 0 : 5191 => Opcode::PseudoVLSEG4E64_V_M1_MASK,
19034 0 : 5192 => Opcode::PseudoVLSEG4E64_V_M2,
19035 0 : 5193 => Opcode::PseudoVLSEG4E64_V_M2_MASK,
19036 0 : 5194 => Opcode::PseudoVLSEG4E8FF_V_M1,
19037 0 : 5195 => Opcode::PseudoVLSEG4E8FF_V_M1_MASK,
19038 0 : 5196 => Opcode::PseudoVLSEG4E8FF_V_M2,
19039 0 : 5197 => Opcode::PseudoVLSEG4E8FF_V_M2_MASK,
19040 0 : 5198 => Opcode::PseudoVLSEG4E8FF_V_MF2,
19041 0 : 5199 => Opcode::PseudoVLSEG4E8FF_V_MF2_MASK,
19042 0 : 5200 => Opcode::PseudoVLSEG4E8FF_V_MF4,
19043 0 : 5201 => Opcode::PseudoVLSEG4E8FF_V_MF4_MASK,
19044 0 : 5202 => Opcode::PseudoVLSEG4E8FF_V_MF8,
19045 0 : 5203 => Opcode::PseudoVLSEG4E8FF_V_MF8_MASK,
19046 0 : 5204 => Opcode::PseudoVLSEG4E8_V_M1,
19047 0 : 5205 => Opcode::PseudoVLSEG4E8_V_M1_MASK,
19048 0 : 5206 => Opcode::PseudoVLSEG4E8_V_M2,
19049 0 : 5207 => Opcode::PseudoVLSEG4E8_V_M2_MASK,
19050 0 : 5208 => Opcode::PseudoVLSEG4E8_V_MF2,
19051 0 : 5209 => Opcode::PseudoVLSEG4E8_V_MF2_MASK,
19052 0 : 5210 => Opcode::PseudoVLSEG4E8_V_MF4,
19053 0 : 5211 => Opcode::PseudoVLSEG4E8_V_MF4_MASK,
19054 0 : 5212 => Opcode::PseudoVLSEG4E8_V_MF8,
19055 0 : 5213 => Opcode::PseudoVLSEG4E8_V_MF8_MASK,
19056 0 : 5214 => Opcode::PseudoVLSEG5E16FF_V_M1,
19057 0 : 5215 => Opcode::PseudoVLSEG5E16FF_V_M1_MASK,
19058 0 : 5216 => Opcode::PseudoVLSEG5E16FF_V_MF2,
19059 0 : 5217 => Opcode::PseudoVLSEG5E16FF_V_MF2_MASK,
19060 0 : 5218 => Opcode::PseudoVLSEG5E16FF_V_MF4,
19061 0 : 5219 => Opcode::PseudoVLSEG5E16FF_V_MF4_MASK,
19062 0 : 5220 => Opcode::PseudoVLSEG5E16_V_M1,
19063 0 : 5221 => Opcode::PseudoVLSEG5E16_V_M1_MASK,
19064 0 : 5222 => Opcode::PseudoVLSEG5E16_V_MF2,
19065 0 : 5223 => Opcode::PseudoVLSEG5E16_V_MF2_MASK,
19066 0 : 5224 => Opcode::PseudoVLSEG5E16_V_MF4,
19067 0 : 5225 => Opcode::PseudoVLSEG5E16_V_MF4_MASK,
19068 0 : 5226 => Opcode::PseudoVLSEG5E32FF_V_M1,
19069 0 : 5227 => Opcode::PseudoVLSEG5E32FF_V_M1_MASK,
19070 0 : 5228 => Opcode::PseudoVLSEG5E32FF_V_MF2,
19071 0 : 5229 => Opcode::PseudoVLSEG5E32FF_V_MF2_MASK,
19072 0 : 5230 => Opcode::PseudoVLSEG5E32_V_M1,
19073 0 : 5231 => Opcode::PseudoVLSEG5E32_V_M1_MASK,
19074 0 : 5232 => Opcode::PseudoVLSEG5E32_V_MF2,
19075 0 : 5233 => Opcode::PseudoVLSEG5E32_V_MF2_MASK,
19076 0 : 5234 => Opcode::PseudoVLSEG5E64FF_V_M1,
19077 0 : 5235 => Opcode::PseudoVLSEG5E64FF_V_M1_MASK,
19078 0 : 5236 => Opcode::PseudoVLSEG5E64_V_M1,
19079 0 : 5237 => Opcode::PseudoVLSEG5E64_V_M1_MASK,
19080 0 : 5238 => Opcode::PseudoVLSEG5E8FF_V_M1,
19081 0 : 5239 => Opcode::PseudoVLSEG5E8FF_V_M1_MASK,
19082 0 : 5240 => Opcode::PseudoVLSEG5E8FF_V_MF2,
19083 0 : 5241 => Opcode::PseudoVLSEG5E8FF_V_MF2_MASK,
19084 0 : 5242 => Opcode::PseudoVLSEG5E8FF_V_MF4,
19085 0 : 5243 => Opcode::PseudoVLSEG5E8FF_V_MF4_MASK,
19086 0 : 5244 => Opcode::PseudoVLSEG5E8FF_V_MF8,
19087 0 : 5245 => Opcode::PseudoVLSEG5E8FF_V_MF8_MASK,
19088 0 : 5246 => Opcode::PseudoVLSEG5E8_V_M1,
19089 0 : 5247 => Opcode::PseudoVLSEG5E8_V_M1_MASK,
19090 0 : 5248 => Opcode::PseudoVLSEG5E8_V_MF2,
19091 0 : 5249 => Opcode::PseudoVLSEG5E8_V_MF2_MASK,
19092 0 : 5250 => Opcode::PseudoVLSEG5E8_V_MF4,
19093 0 : 5251 => Opcode::PseudoVLSEG5E8_V_MF4_MASK,
19094 0 : 5252 => Opcode::PseudoVLSEG5E8_V_MF8,
19095 0 : 5253 => Opcode::PseudoVLSEG5E8_V_MF8_MASK,
19096 0 : 5254 => Opcode::PseudoVLSEG6E16FF_V_M1,
19097 0 : 5255 => Opcode::PseudoVLSEG6E16FF_V_M1_MASK,
19098 0 : 5256 => Opcode::PseudoVLSEG6E16FF_V_MF2,
19099 0 : 5257 => Opcode::PseudoVLSEG6E16FF_V_MF2_MASK,
19100 0 : 5258 => Opcode::PseudoVLSEG6E16FF_V_MF4,
19101 0 : 5259 => Opcode::PseudoVLSEG6E16FF_V_MF4_MASK,
19102 0 : 5260 => Opcode::PseudoVLSEG6E16_V_M1,
19103 0 : 5261 => Opcode::PseudoVLSEG6E16_V_M1_MASK,
19104 0 : 5262 => Opcode::PseudoVLSEG6E16_V_MF2,
19105 0 : 5263 => Opcode::PseudoVLSEG6E16_V_MF2_MASK,
19106 0 : 5264 => Opcode::PseudoVLSEG6E16_V_MF4,
19107 0 : 5265 => Opcode::PseudoVLSEG6E16_V_MF4_MASK,
19108 0 : 5266 => Opcode::PseudoVLSEG6E32FF_V_M1,
19109 0 : 5267 => Opcode::PseudoVLSEG6E32FF_V_M1_MASK,
19110 0 : 5268 => Opcode::PseudoVLSEG6E32FF_V_MF2,
19111 0 : 5269 => Opcode::PseudoVLSEG6E32FF_V_MF2_MASK,
19112 0 : 5270 => Opcode::PseudoVLSEG6E32_V_M1,
19113 0 : 5271 => Opcode::PseudoVLSEG6E32_V_M1_MASK,
19114 0 : 5272 => Opcode::PseudoVLSEG6E32_V_MF2,
19115 0 : 5273 => Opcode::PseudoVLSEG6E32_V_MF2_MASK,
19116 0 : 5274 => Opcode::PseudoVLSEG6E64FF_V_M1,
19117 0 : 5275 => Opcode::PseudoVLSEG6E64FF_V_M1_MASK,
19118 0 : 5276 => Opcode::PseudoVLSEG6E64_V_M1,
19119 0 : 5277 => Opcode::PseudoVLSEG6E64_V_M1_MASK,
19120 0 : 5278 => Opcode::PseudoVLSEG6E8FF_V_M1,
19121 0 : 5279 => Opcode::PseudoVLSEG6E8FF_V_M1_MASK,
19122 0 : 5280 => Opcode::PseudoVLSEG6E8FF_V_MF2,
19123 0 : 5281 => Opcode::PseudoVLSEG6E8FF_V_MF2_MASK,
19124 0 : 5282 => Opcode::PseudoVLSEG6E8FF_V_MF4,
19125 0 : 5283 => Opcode::PseudoVLSEG6E8FF_V_MF4_MASK,
19126 0 : 5284 => Opcode::PseudoVLSEG6E8FF_V_MF8,
19127 0 : 5285 => Opcode::PseudoVLSEG6E8FF_V_MF8_MASK,
19128 0 : 5286 => Opcode::PseudoVLSEG6E8_V_M1,
19129 0 : 5287 => Opcode::PseudoVLSEG6E8_V_M1_MASK,
19130 0 : 5288 => Opcode::PseudoVLSEG6E8_V_MF2,
19131 0 : 5289 => Opcode::PseudoVLSEG6E8_V_MF2_MASK,
19132 0 : 5290 => Opcode::PseudoVLSEG6E8_V_MF4,
19133 0 : 5291 => Opcode::PseudoVLSEG6E8_V_MF4_MASK,
19134 0 : 5292 => Opcode::PseudoVLSEG6E8_V_MF8,
19135 0 : 5293 => Opcode::PseudoVLSEG6E8_V_MF8_MASK,
19136 0 : 5294 => Opcode::PseudoVLSEG7E16FF_V_M1,
19137 0 : 5295 => Opcode::PseudoVLSEG7E16FF_V_M1_MASK,
19138 0 : 5296 => Opcode::PseudoVLSEG7E16FF_V_MF2,
19139 0 : 5297 => Opcode::PseudoVLSEG7E16FF_V_MF2_MASK,
19140 0 : 5298 => Opcode::PseudoVLSEG7E16FF_V_MF4,
19141 0 : 5299 => Opcode::PseudoVLSEG7E16FF_V_MF4_MASK,
19142 0 : 5300 => Opcode::PseudoVLSEG7E16_V_M1,
19143 0 : 5301 => Opcode::PseudoVLSEG7E16_V_M1_MASK,
19144 0 : 5302 => Opcode::PseudoVLSEG7E16_V_MF2,
19145 0 : 5303 => Opcode::PseudoVLSEG7E16_V_MF2_MASK,
19146 0 : 5304 => Opcode::PseudoVLSEG7E16_V_MF4,
19147 0 : 5305 => Opcode::PseudoVLSEG7E16_V_MF4_MASK,
19148 0 : 5306 => Opcode::PseudoVLSEG7E32FF_V_M1,
19149 0 : 5307 => Opcode::PseudoVLSEG7E32FF_V_M1_MASK,
19150 0 : 5308 => Opcode::PseudoVLSEG7E32FF_V_MF2,
19151 0 : 5309 => Opcode::PseudoVLSEG7E32FF_V_MF2_MASK,
19152 0 : 5310 => Opcode::PseudoVLSEG7E32_V_M1,
19153 0 : 5311 => Opcode::PseudoVLSEG7E32_V_M1_MASK,
19154 0 : 5312 => Opcode::PseudoVLSEG7E32_V_MF2,
19155 0 : 5313 => Opcode::PseudoVLSEG7E32_V_MF2_MASK,
19156 0 : 5314 => Opcode::PseudoVLSEG7E64FF_V_M1,
19157 0 : 5315 => Opcode::PseudoVLSEG7E64FF_V_M1_MASK,
19158 0 : 5316 => Opcode::PseudoVLSEG7E64_V_M1,
19159 0 : 5317 => Opcode::PseudoVLSEG7E64_V_M1_MASK,
19160 0 : 5318 => Opcode::PseudoVLSEG7E8FF_V_M1,
19161 0 : 5319 => Opcode::PseudoVLSEG7E8FF_V_M1_MASK,
19162 0 : 5320 => Opcode::PseudoVLSEG7E8FF_V_MF2,
19163 0 : 5321 => Opcode::PseudoVLSEG7E8FF_V_MF2_MASK,
19164 0 : 5322 => Opcode::PseudoVLSEG7E8FF_V_MF4,
19165 0 : 5323 => Opcode::PseudoVLSEG7E8FF_V_MF4_MASK,
19166 0 : 5324 => Opcode::PseudoVLSEG7E8FF_V_MF8,
19167 0 : 5325 => Opcode::PseudoVLSEG7E8FF_V_MF8_MASK,
19168 0 : 5326 => Opcode::PseudoVLSEG7E8_V_M1,
19169 0 : 5327 => Opcode::PseudoVLSEG7E8_V_M1_MASK,
19170 0 : 5328 => Opcode::PseudoVLSEG7E8_V_MF2,
19171 0 : 5329 => Opcode::PseudoVLSEG7E8_V_MF2_MASK,
19172 0 : 5330 => Opcode::PseudoVLSEG7E8_V_MF4,
19173 0 : 5331 => Opcode::PseudoVLSEG7E8_V_MF4_MASK,
19174 0 : 5332 => Opcode::PseudoVLSEG7E8_V_MF8,
19175 0 : 5333 => Opcode::PseudoVLSEG7E8_V_MF8_MASK,
19176 0 : 5334 => Opcode::PseudoVLSEG8E16FF_V_M1,
19177 0 : 5335 => Opcode::PseudoVLSEG8E16FF_V_M1_MASK,
19178 0 : 5336 => Opcode::PseudoVLSEG8E16FF_V_MF2,
19179 0 : 5337 => Opcode::PseudoVLSEG8E16FF_V_MF2_MASK,
19180 0 : 5338 => Opcode::PseudoVLSEG8E16FF_V_MF4,
19181 0 : 5339 => Opcode::PseudoVLSEG8E16FF_V_MF4_MASK,
19182 0 : 5340 => Opcode::PseudoVLSEG8E16_V_M1,
19183 0 : 5341 => Opcode::PseudoVLSEG8E16_V_M1_MASK,
19184 0 : 5342 => Opcode::PseudoVLSEG8E16_V_MF2,
19185 0 : 5343 => Opcode::PseudoVLSEG8E16_V_MF2_MASK,
19186 0 : 5344 => Opcode::PseudoVLSEG8E16_V_MF4,
19187 0 : 5345 => Opcode::PseudoVLSEG8E16_V_MF4_MASK,
19188 0 : 5346 => Opcode::PseudoVLSEG8E32FF_V_M1,
19189 0 : 5347 => Opcode::PseudoVLSEG8E32FF_V_M1_MASK,
19190 0 : 5348 => Opcode::PseudoVLSEG8E32FF_V_MF2,
19191 0 : 5349 => Opcode::PseudoVLSEG8E32FF_V_MF2_MASK,
19192 0 : 5350 => Opcode::PseudoVLSEG8E32_V_M1,
19193 0 : 5351 => Opcode::PseudoVLSEG8E32_V_M1_MASK,
19194 0 : 5352 => Opcode::PseudoVLSEG8E32_V_MF2,
19195 0 : 5353 => Opcode::PseudoVLSEG8E32_V_MF2_MASK,
19196 0 : 5354 => Opcode::PseudoVLSEG8E64FF_V_M1,
19197 0 : 5355 => Opcode::PseudoVLSEG8E64FF_V_M1_MASK,
19198 0 : 5356 => Opcode::PseudoVLSEG8E64_V_M1,
19199 0 : 5357 => Opcode::PseudoVLSEG8E64_V_M1_MASK,
19200 0 : 5358 => Opcode::PseudoVLSEG8E8FF_V_M1,
19201 0 : 5359 => Opcode::PseudoVLSEG8E8FF_V_M1_MASK,
19202 0 : 5360 => Opcode::PseudoVLSEG8E8FF_V_MF2,
19203 0 : 5361 => Opcode::PseudoVLSEG8E8FF_V_MF2_MASK,
19204 0 : 5362 => Opcode::PseudoVLSEG8E8FF_V_MF4,
19205 0 : 5363 => Opcode::PseudoVLSEG8E8FF_V_MF4_MASK,
19206 0 : 5364 => Opcode::PseudoVLSEG8E8FF_V_MF8,
19207 0 : 5365 => Opcode::PseudoVLSEG8E8FF_V_MF8_MASK,
19208 0 : 5366 => Opcode::PseudoVLSEG8E8_V_M1,
19209 0 : 5367 => Opcode::PseudoVLSEG8E8_V_M1_MASK,
19210 0 : 5368 => Opcode::PseudoVLSEG8E8_V_MF2,
19211 0 : 5369 => Opcode::PseudoVLSEG8E8_V_MF2_MASK,
19212 0 : 5370 => Opcode::PseudoVLSEG8E8_V_MF4,
19213 0 : 5371 => Opcode::PseudoVLSEG8E8_V_MF4_MASK,
19214 0 : 5372 => Opcode::PseudoVLSEG8E8_V_MF8,
19215 0 : 5373 => Opcode::PseudoVLSEG8E8_V_MF8_MASK,
19216 0 : 5374 => Opcode::PseudoVLSSEG2E16_V_M1,
19217 0 : 5375 => Opcode::PseudoVLSSEG2E16_V_M1_MASK,
19218 0 : 5376 => Opcode::PseudoVLSSEG2E16_V_M2,
19219 0 : 5377 => Opcode::PseudoVLSSEG2E16_V_M2_MASK,
19220 0 : 5378 => Opcode::PseudoVLSSEG2E16_V_M4,
19221 0 : 5379 => Opcode::PseudoVLSSEG2E16_V_M4_MASK,
19222 0 : 5380 => Opcode::PseudoVLSSEG2E16_V_MF2,
19223 0 : 5381 => Opcode::PseudoVLSSEG2E16_V_MF2_MASK,
19224 0 : 5382 => Opcode::PseudoVLSSEG2E16_V_MF4,
19225 0 : 5383 => Opcode::PseudoVLSSEG2E16_V_MF4_MASK,
19226 0 : 5384 => Opcode::PseudoVLSSEG2E32_V_M1,
19227 0 : 5385 => Opcode::PseudoVLSSEG2E32_V_M1_MASK,
19228 0 : 5386 => Opcode::PseudoVLSSEG2E32_V_M2,
19229 0 : 5387 => Opcode::PseudoVLSSEG2E32_V_M2_MASK,
19230 0 : 5388 => Opcode::PseudoVLSSEG2E32_V_M4,
19231 0 : 5389 => Opcode::PseudoVLSSEG2E32_V_M4_MASK,
19232 0 : 5390 => Opcode::PseudoVLSSEG2E32_V_MF2,
19233 0 : 5391 => Opcode::PseudoVLSSEG2E32_V_MF2_MASK,
19234 0 : 5392 => Opcode::PseudoVLSSEG2E64_V_M1,
19235 0 : 5393 => Opcode::PseudoVLSSEG2E64_V_M1_MASK,
19236 0 : 5394 => Opcode::PseudoVLSSEG2E64_V_M2,
19237 0 : 5395 => Opcode::PseudoVLSSEG2E64_V_M2_MASK,
19238 0 : 5396 => Opcode::PseudoVLSSEG2E64_V_M4,
19239 0 : 5397 => Opcode::PseudoVLSSEG2E64_V_M4_MASK,
19240 0 : 5398 => Opcode::PseudoVLSSEG2E8_V_M1,
19241 0 : 5399 => Opcode::PseudoVLSSEG2E8_V_M1_MASK,
19242 0 : 5400 => Opcode::PseudoVLSSEG2E8_V_M2,
19243 0 : 5401 => Opcode::PseudoVLSSEG2E8_V_M2_MASK,
19244 0 : 5402 => Opcode::PseudoVLSSEG2E8_V_M4,
19245 0 : 5403 => Opcode::PseudoVLSSEG2E8_V_M4_MASK,
19246 0 : 5404 => Opcode::PseudoVLSSEG2E8_V_MF2,
19247 0 : 5405 => Opcode::PseudoVLSSEG2E8_V_MF2_MASK,
19248 0 : 5406 => Opcode::PseudoVLSSEG2E8_V_MF4,
19249 0 : 5407 => Opcode::PseudoVLSSEG2E8_V_MF4_MASK,
19250 0 : 5408 => Opcode::PseudoVLSSEG2E8_V_MF8,
19251 0 : 5409 => Opcode::PseudoVLSSEG2E8_V_MF8_MASK,
19252 0 : 5410 => Opcode::PseudoVLSSEG3E16_V_M1,
19253 0 : 5411 => Opcode::PseudoVLSSEG3E16_V_M1_MASK,
19254 0 : 5412 => Opcode::PseudoVLSSEG3E16_V_M2,
19255 0 : 5413 => Opcode::PseudoVLSSEG3E16_V_M2_MASK,
19256 0 : 5414 => Opcode::PseudoVLSSEG3E16_V_MF2,
19257 0 : 5415 => Opcode::PseudoVLSSEG3E16_V_MF2_MASK,
19258 0 : 5416 => Opcode::PseudoVLSSEG3E16_V_MF4,
19259 0 : 5417 => Opcode::PseudoVLSSEG3E16_V_MF4_MASK,
19260 0 : 5418 => Opcode::PseudoVLSSEG3E32_V_M1,
19261 0 : 5419 => Opcode::PseudoVLSSEG3E32_V_M1_MASK,
19262 0 : 5420 => Opcode::PseudoVLSSEG3E32_V_M2,
19263 0 : 5421 => Opcode::PseudoVLSSEG3E32_V_M2_MASK,
19264 0 : 5422 => Opcode::PseudoVLSSEG3E32_V_MF2,
19265 0 : 5423 => Opcode::PseudoVLSSEG3E32_V_MF2_MASK,
19266 0 : 5424 => Opcode::PseudoVLSSEG3E64_V_M1,
19267 0 : 5425 => Opcode::PseudoVLSSEG3E64_V_M1_MASK,
19268 0 : 5426 => Opcode::PseudoVLSSEG3E64_V_M2,
19269 0 : 5427 => Opcode::PseudoVLSSEG3E64_V_M2_MASK,
19270 0 : 5428 => Opcode::PseudoVLSSEG3E8_V_M1,
19271 0 : 5429 => Opcode::PseudoVLSSEG3E8_V_M1_MASK,
19272 0 : 5430 => Opcode::PseudoVLSSEG3E8_V_M2,
19273 0 : 5431 => Opcode::PseudoVLSSEG3E8_V_M2_MASK,
19274 0 : 5432 => Opcode::PseudoVLSSEG3E8_V_MF2,
19275 0 : 5433 => Opcode::PseudoVLSSEG3E8_V_MF2_MASK,
19276 0 : 5434 => Opcode::PseudoVLSSEG3E8_V_MF4,
19277 0 : 5435 => Opcode::PseudoVLSSEG3E8_V_MF4_MASK,
19278 0 : 5436 => Opcode::PseudoVLSSEG3E8_V_MF8,
19279 0 : 5437 => Opcode::PseudoVLSSEG3E8_V_MF8_MASK,
19280 0 : 5438 => Opcode::PseudoVLSSEG4E16_V_M1,
19281 0 : 5439 => Opcode::PseudoVLSSEG4E16_V_M1_MASK,
19282 0 : 5440 => Opcode::PseudoVLSSEG4E16_V_M2,
19283 0 : 5441 => Opcode::PseudoVLSSEG4E16_V_M2_MASK,
19284 0 : 5442 => Opcode::PseudoVLSSEG4E16_V_MF2,
19285 0 : 5443 => Opcode::PseudoVLSSEG4E16_V_MF2_MASK,
19286 0 : 5444 => Opcode::PseudoVLSSEG4E16_V_MF4,
19287 0 : 5445 => Opcode::PseudoVLSSEG4E16_V_MF4_MASK,
19288 0 : 5446 => Opcode::PseudoVLSSEG4E32_V_M1,
19289 0 : 5447 => Opcode::PseudoVLSSEG4E32_V_M1_MASK,
19290 0 : 5448 => Opcode::PseudoVLSSEG4E32_V_M2,
19291 0 : 5449 => Opcode::PseudoVLSSEG4E32_V_M2_MASK,
19292 0 : 5450 => Opcode::PseudoVLSSEG4E32_V_MF2,
19293 0 : 5451 => Opcode::PseudoVLSSEG4E32_V_MF2_MASK,
19294 0 : 5452 => Opcode::PseudoVLSSEG4E64_V_M1,
19295 0 : 5453 => Opcode::PseudoVLSSEG4E64_V_M1_MASK,
19296 0 : 5454 => Opcode::PseudoVLSSEG4E64_V_M2,
19297 0 : 5455 => Opcode::PseudoVLSSEG4E64_V_M2_MASK,
19298 0 : 5456 => Opcode::PseudoVLSSEG4E8_V_M1,
19299 0 : 5457 => Opcode::PseudoVLSSEG4E8_V_M1_MASK,
19300 0 : 5458 => Opcode::PseudoVLSSEG4E8_V_M2,
19301 0 : 5459 => Opcode::PseudoVLSSEG4E8_V_M2_MASK,
19302 0 : 5460 => Opcode::PseudoVLSSEG4E8_V_MF2,
19303 0 : 5461 => Opcode::PseudoVLSSEG4E8_V_MF2_MASK,
19304 0 : 5462 => Opcode::PseudoVLSSEG4E8_V_MF4,
19305 0 : 5463 => Opcode::PseudoVLSSEG4E8_V_MF4_MASK,
19306 0 : 5464 => Opcode::PseudoVLSSEG4E8_V_MF8,
19307 0 : 5465 => Opcode::PseudoVLSSEG4E8_V_MF8_MASK,
19308 0 : 5466 => Opcode::PseudoVLSSEG5E16_V_M1,
19309 0 : 5467 => Opcode::PseudoVLSSEG5E16_V_M1_MASK,
19310 0 : 5468 => Opcode::PseudoVLSSEG5E16_V_MF2,
19311 0 : 5469 => Opcode::PseudoVLSSEG5E16_V_MF2_MASK,
19312 0 : 5470 => Opcode::PseudoVLSSEG5E16_V_MF4,
19313 0 : 5471 => Opcode::PseudoVLSSEG5E16_V_MF4_MASK,
19314 0 : 5472 => Opcode::PseudoVLSSEG5E32_V_M1,
19315 0 : 5473 => Opcode::PseudoVLSSEG5E32_V_M1_MASK,
19316 0 : 5474 => Opcode::PseudoVLSSEG5E32_V_MF2,
19317 0 : 5475 => Opcode::PseudoVLSSEG5E32_V_MF2_MASK,
19318 0 : 5476 => Opcode::PseudoVLSSEG5E64_V_M1,
19319 0 : 5477 => Opcode::PseudoVLSSEG5E64_V_M1_MASK,
19320 0 : 5478 => Opcode::PseudoVLSSEG5E8_V_M1,
19321 0 : 5479 => Opcode::PseudoVLSSEG5E8_V_M1_MASK,
19322 0 : 5480 => Opcode::PseudoVLSSEG5E8_V_MF2,
19323 0 : 5481 => Opcode::PseudoVLSSEG5E8_V_MF2_MASK,
19324 0 : 5482 => Opcode::PseudoVLSSEG5E8_V_MF4,
19325 0 : 5483 => Opcode::PseudoVLSSEG5E8_V_MF4_MASK,
19326 0 : 5484 => Opcode::PseudoVLSSEG5E8_V_MF8,
19327 0 : 5485 => Opcode::PseudoVLSSEG5E8_V_MF8_MASK,
19328 0 : 5486 => Opcode::PseudoVLSSEG6E16_V_M1,
19329 0 : 5487 => Opcode::PseudoVLSSEG6E16_V_M1_MASK,
19330 0 : 5488 => Opcode::PseudoVLSSEG6E16_V_MF2,
19331 0 : 5489 => Opcode::PseudoVLSSEG6E16_V_MF2_MASK,
19332 0 : 5490 => Opcode::PseudoVLSSEG6E16_V_MF4,
19333 0 : 5491 => Opcode::PseudoVLSSEG6E16_V_MF4_MASK,
19334 0 : 5492 => Opcode::PseudoVLSSEG6E32_V_M1,
19335 0 : 5493 => Opcode::PseudoVLSSEG6E32_V_M1_MASK,
19336 0 : 5494 => Opcode::PseudoVLSSEG6E32_V_MF2,
19337 0 : 5495 => Opcode::PseudoVLSSEG6E32_V_MF2_MASK,
19338 0 : 5496 => Opcode::PseudoVLSSEG6E64_V_M1,
19339 0 : 5497 => Opcode::PseudoVLSSEG6E64_V_M1_MASK,
19340 0 : 5498 => Opcode::PseudoVLSSEG6E8_V_M1,
19341 0 : 5499 => Opcode::PseudoVLSSEG6E8_V_M1_MASK,
19342 0 : 5500 => Opcode::PseudoVLSSEG6E8_V_MF2,
19343 0 : 5501 => Opcode::PseudoVLSSEG6E8_V_MF2_MASK,
19344 0 : 5502 => Opcode::PseudoVLSSEG6E8_V_MF4,
19345 0 : 5503 => Opcode::PseudoVLSSEG6E8_V_MF4_MASK,
19346 0 : 5504 => Opcode::PseudoVLSSEG6E8_V_MF8,
19347 0 : 5505 => Opcode::PseudoVLSSEG6E8_V_MF8_MASK,
19348 0 : 5506 => Opcode::PseudoVLSSEG7E16_V_M1,
19349 0 : 5507 => Opcode::PseudoVLSSEG7E16_V_M1_MASK,
19350 0 : 5508 => Opcode::PseudoVLSSEG7E16_V_MF2,
19351 0 : 5509 => Opcode::PseudoVLSSEG7E16_V_MF2_MASK,
19352 0 : 5510 => Opcode::PseudoVLSSEG7E16_V_MF4,
19353 0 : 5511 => Opcode::PseudoVLSSEG7E16_V_MF4_MASK,
19354 0 : 5512 => Opcode::PseudoVLSSEG7E32_V_M1,
19355 0 : 5513 => Opcode::PseudoVLSSEG7E32_V_M1_MASK,
19356 0 : 5514 => Opcode::PseudoVLSSEG7E32_V_MF2,
19357 0 : 5515 => Opcode::PseudoVLSSEG7E32_V_MF2_MASK,
19358 0 : 5516 => Opcode::PseudoVLSSEG7E64_V_M1,
19359 0 : 5517 => Opcode::PseudoVLSSEG7E64_V_M1_MASK,
19360 0 : 5518 => Opcode::PseudoVLSSEG7E8_V_M1,
19361 0 : 5519 => Opcode::PseudoVLSSEG7E8_V_M1_MASK,
19362 0 : 5520 => Opcode::PseudoVLSSEG7E8_V_MF2,
19363 0 : 5521 => Opcode::PseudoVLSSEG7E8_V_MF2_MASK,
19364 0 : 5522 => Opcode::PseudoVLSSEG7E8_V_MF4,
19365 0 : 5523 => Opcode::PseudoVLSSEG7E8_V_MF4_MASK,
19366 0 : 5524 => Opcode::PseudoVLSSEG7E8_V_MF8,
19367 0 : 5525 => Opcode::PseudoVLSSEG7E8_V_MF8_MASK,
19368 0 : 5526 => Opcode::PseudoVLSSEG8E16_V_M1,
19369 0 : 5527 => Opcode::PseudoVLSSEG8E16_V_M1_MASK,
19370 0 : 5528 => Opcode::PseudoVLSSEG8E16_V_MF2,
19371 0 : 5529 => Opcode::PseudoVLSSEG8E16_V_MF2_MASK,
19372 0 : 5530 => Opcode::PseudoVLSSEG8E16_V_MF4,
19373 0 : 5531 => Opcode::PseudoVLSSEG8E16_V_MF4_MASK,
19374 0 : 5532 => Opcode::PseudoVLSSEG8E32_V_M1,
19375 0 : 5533 => Opcode::PseudoVLSSEG8E32_V_M1_MASK,
19376 0 : 5534 => Opcode::PseudoVLSSEG8E32_V_MF2,
19377 0 : 5535 => Opcode::PseudoVLSSEG8E32_V_MF2_MASK,
19378 0 : 5536 => Opcode::PseudoVLSSEG8E64_V_M1,
19379 0 : 5537 => Opcode::PseudoVLSSEG8E64_V_M1_MASK,
19380 0 : 5538 => Opcode::PseudoVLSSEG8E8_V_M1,
19381 0 : 5539 => Opcode::PseudoVLSSEG8E8_V_M1_MASK,
19382 0 : 5540 => Opcode::PseudoVLSSEG8E8_V_MF2,
19383 0 : 5541 => Opcode::PseudoVLSSEG8E8_V_MF2_MASK,
19384 0 : 5542 => Opcode::PseudoVLSSEG8E8_V_MF4,
19385 0 : 5543 => Opcode::PseudoVLSSEG8E8_V_MF4_MASK,
19386 0 : 5544 => Opcode::PseudoVLSSEG8E8_V_MF8,
19387 0 : 5545 => Opcode::PseudoVLSSEG8E8_V_MF8_MASK,
19388 0 : 5546 => Opcode::PseudoVLUXEI16_V_M1_M1,
19389 0 : 5547 => Opcode::PseudoVLUXEI16_V_M1_M1_MASK,
19390 0 : 5548 => Opcode::PseudoVLUXEI16_V_M1_M2,
19391 0 : 5549 => Opcode::PseudoVLUXEI16_V_M1_M2_MASK,
19392 0 : 5550 => Opcode::PseudoVLUXEI16_V_M1_M4,
19393 0 : 5551 => Opcode::PseudoVLUXEI16_V_M1_M4_MASK,
19394 0 : 5552 => Opcode::PseudoVLUXEI16_V_M1_MF2,
19395 0 : 5553 => Opcode::PseudoVLUXEI16_V_M1_MF2_MASK,
19396 0 : 5554 => Opcode::PseudoVLUXEI16_V_M2_M1,
19397 0 : 5555 => Opcode::PseudoVLUXEI16_V_M2_M1_MASK,
19398 0 : 5556 => Opcode::PseudoVLUXEI16_V_M2_M2,
19399 0 : 5557 => Opcode::PseudoVLUXEI16_V_M2_M2_MASK,
19400 0 : 5558 => Opcode::PseudoVLUXEI16_V_M2_M4,
19401 0 : 5559 => Opcode::PseudoVLUXEI16_V_M2_M4_MASK,
19402 0 : 5560 => Opcode::PseudoVLUXEI16_V_M2_M8,
19403 0 : 5561 => Opcode::PseudoVLUXEI16_V_M2_M8_MASK,
19404 0 : 5562 => Opcode::PseudoVLUXEI16_V_M4_M2,
19405 0 : 5563 => Opcode::PseudoVLUXEI16_V_M4_M2_MASK,
19406 0 : 5564 => Opcode::PseudoVLUXEI16_V_M4_M4,
19407 0 : 5565 => Opcode::PseudoVLUXEI16_V_M4_M4_MASK,
19408 0 : 5566 => Opcode::PseudoVLUXEI16_V_M4_M8,
19409 0 : 5567 => Opcode::PseudoVLUXEI16_V_M4_M8_MASK,
19410 0 : 5568 => Opcode::PseudoVLUXEI16_V_M8_M4,
19411 0 : 5569 => Opcode::PseudoVLUXEI16_V_M8_M4_MASK,
19412 0 : 5570 => Opcode::PseudoVLUXEI16_V_M8_M8,
19413 0 : 5571 => Opcode::PseudoVLUXEI16_V_M8_M8_MASK,
19414 0 : 5572 => Opcode::PseudoVLUXEI16_V_MF2_M1,
19415 0 : 5573 => Opcode::PseudoVLUXEI16_V_MF2_M1_MASK,
19416 0 : 5574 => Opcode::PseudoVLUXEI16_V_MF2_M2,
19417 0 : 5575 => Opcode::PseudoVLUXEI16_V_MF2_M2_MASK,
19418 0 : 5576 => Opcode::PseudoVLUXEI16_V_MF2_MF2,
19419 0 : 5577 => Opcode::PseudoVLUXEI16_V_MF2_MF2_MASK,
19420 0 : 5578 => Opcode::PseudoVLUXEI16_V_MF2_MF4,
19421 0 : 5579 => Opcode::PseudoVLUXEI16_V_MF2_MF4_MASK,
19422 0 : 5580 => Opcode::PseudoVLUXEI16_V_MF4_M1,
19423 0 : 5581 => Opcode::PseudoVLUXEI16_V_MF4_M1_MASK,
19424 0 : 5582 => Opcode::PseudoVLUXEI16_V_MF4_MF2,
19425 0 : 5583 => Opcode::PseudoVLUXEI16_V_MF4_MF2_MASK,
19426 0 : 5584 => Opcode::PseudoVLUXEI16_V_MF4_MF4,
19427 0 : 5585 => Opcode::PseudoVLUXEI16_V_MF4_MF4_MASK,
19428 0 : 5586 => Opcode::PseudoVLUXEI16_V_MF4_MF8,
19429 0 : 5587 => Opcode::PseudoVLUXEI16_V_MF4_MF8_MASK,
19430 0 : 5588 => Opcode::PseudoVLUXEI32_V_M1_M1,
19431 0 : 5589 => Opcode::PseudoVLUXEI32_V_M1_M1_MASK,
19432 0 : 5590 => Opcode::PseudoVLUXEI32_V_M1_M2,
19433 0 : 5591 => Opcode::PseudoVLUXEI32_V_M1_M2_MASK,
19434 0 : 5592 => Opcode::PseudoVLUXEI32_V_M1_MF2,
19435 0 : 5593 => Opcode::PseudoVLUXEI32_V_M1_MF2_MASK,
19436 0 : 5594 => Opcode::PseudoVLUXEI32_V_M1_MF4,
19437 0 : 5595 => Opcode::PseudoVLUXEI32_V_M1_MF4_MASK,
19438 0 : 5596 => Opcode::PseudoVLUXEI32_V_M2_M1,
19439 0 : 5597 => Opcode::PseudoVLUXEI32_V_M2_M1_MASK,
19440 0 : 5598 => Opcode::PseudoVLUXEI32_V_M2_M2,
19441 0 : 5599 => Opcode::PseudoVLUXEI32_V_M2_M2_MASK,
19442 0 : 5600 => Opcode::PseudoVLUXEI32_V_M2_M4,
19443 0 : 5601 => Opcode::PseudoVLUXEI32_V_M2_M4_MASK,
19444 0 : 5602 => Opcode::PseudoVLUXEI32_V_M2_MF2,
19445 0 : 5603 => Opcode::PseudoVLUXEI32_V_M2_MF2_MASK,
19446 0 : 5604 => Opcode::PseudoVLUXEI32_V_M4_M1,
19447 0 : 5605 => Opcode::PseudoVLUXEI32_V_M4_M1_MASK,
19448 0 : 5606 => Opcode::PseudoVLUXEI32_V_M4_M2,
19449 0 : 5607 => Opcode::PseudoVLUXEI32_V_M4_M2_MASK,
19450 0 : 5608 => Opcode::PseudoVLUXEI32_V_M4_M4,
19451 0 : 5609 => Opcode::PseudoVLUXEI32_V_M4_M4_MASK,
19452 0 : 5610 => Opcode::PseudoVLUXEI32_V_M4_M8,
19453 0 : 5611 => Opcode::PseudoVLUXEI32_V_M4_M8_MASK,
19454 0 : 5612 => Opcode::PseudoVLUXEI32_V_M8_M2,
19455 0 : 5613 => Opcode::PseudoVLUXEI32_V_M8_M2_MASK,
19456 0 : 5614 => Opcode::PseudoVLUXEI32_V_M8_M4,
19457 0 : 5615 => Opcode::PseudoVLUXEI32_V_M8_M4_MASK,
19458 0 : 5616 => Opcode::PseudoVLUXEI32_V_M8_M8,
19459 0 : 5617 => Opcode::PseudoVLUXEI32_V_M8_M8_MASK,
19460 0 : 5618 => Opcode::PseudoVLUXEI32_V_MF2_M1,
19461 0 : 5619 => Opcode::PseudoVLUXEI32_V_MF2_M1_MASK,
19462 0 : 5620 => Opcode::PseudoVLUXEI32_V_MF2_MF2,
19463 0 : 5621 => Opcode::PseudoVLUXEI32_V_MF2_MF2_MASK,
19464 0 : 5622 => Opcode::PseudoVLUXEI32_V_MF2_MF4,
19465 0 : 5623 => Opcode::PseudoVLUXEI32_V_MF2_MF4_MASK,
19466 0 : 5624 => Opcode::PseudoVLUXEI32_V_MF2_MF8,
19467 0 : 5625 => Opcode::PseudoVLUXEI32_V_MF2_MF8_MASK,
19468 0 : 5626 => Opcode::PseudoVLUXEI64_V_M1_M1,
19469 0 : 5627 => Opcode::PseudoVLUXEI64_V_M1_M1_MASK,
19470 0 : 5628 => Opcode::PseudoVLUXEI64_V_M1_MF2,
19471 0 : 5629 => Opcode::PseudoVLUXEI64_V_M1_MF2_MASK,
19472 0 : 5630 => Opcode::PseudoVLUXEI64_V_M1_MF4,
19473 0 : 5631 => Opcode::PseudoVLUXEI64_V_M1_MF4_MASK,
19474 0 : 5632 => Opcode::PseudoVLUXEI64_V_M1_MF8,
19475 0 : 5633 => Opcode::PseudoVLUXEI64_V_M1_MF8_MASK,
19476 0 : 5634 => Opcode::PseudoVLUXEI64_V_M2_M1,
19477 0 : 5635 => Opcode::PseudoVLUXEI64_V_M2_M1_MASK,
19478 0 : 5636 => Opcode::PseudoVLUXEI64_V_M2_M2,
19479 0 : 5637 => Opcode::PseudoVLUXEI64_V_M2_M2_MASK,
19480 0 : 5638 => Opcode::PseudoVLUXEI64_V_M2_MF2,
19481 0 : 5639 => Opcode::PseudoVLUXEI64_V_M2_MF2_MASK,
19482 0 : 5640 => Opcode::PseudoVLUXEI64_V_M2_MF4,
19483 0 : 5641 => Opcode::PseudoVLUXEI64_V_M2_MF4_MASK,
19484 0 : 5642 => Opcode::PseudoVLUXEI64_V_M4_M1,
19485 0 : 5643 => Opcode::PseudoVLUXEI64_V_M4_M1_MASK,
19486 0 : 5644 => Opcode::PseudoVLUXEI64_V_M4_M2,
19487 0 : 5645 => Opcode::PseudoVLUXEI64_V_M4_M2_MASK,
19488 0 : 5646 => Opcode::PseudoVLUXEI64_V_M4_M4,
19489 0 : 5647 => Opcode::PseudoVLUXEI64_V_M4_M4_MASK,
19490 0 : 5648 => Opcode::PseudoVLUXEI64_V_M4_MF2,
19491 0 : 5649 => Opcode::PseudoVLUXEI64_V_M4_MF2_MASK,
19492 0 : 5650 => Opcode::PseudoVLUXEI64_V_M8_M1,
19493 0 : 5651 => Opcode::PseudoVLUXEI64_V_M8_M1_MASK,
19494 0 : 5652 => Opcode::PseudoVLUXEI64_V_M8_M2,
19495 0 : 5653 => Opcode::PseudoVLUXEI64_V_M8_M2_MASK,
19496 0 : 5654 => Opcode::PseudoVLUXEI64_V_M8_M4,
19497 0 : 5655 => Opcode::PseudoVLUXEI64_V_M8_M4_MASK,
19498 0 : 5656 => Opcode::PseudoVLUXEI64_V_M8_M8,
19499 0 : 5657 => Opcode::PseudoVLUXEI64_V_M8_M8_MASK,
19500 0 : 5658 => Opcode::PseudoVLUXEI8_V_M1_M1,
19501 0 : 5659 => Opcode::PseudoVLUXEI8_V_M1_M1_MASK,
19502 0 : 5660 => Opcode::PseudoVLUXEI8_V_M1_M2,
19503 0 : 5661 => Opcode::PseudoVLUXEI8_V_M1_M2_MASK,
19504 0 : 5662 => Opcode::PseudoVLUXEI8_V_M1_M4,
19505 0 : 5663 => Opcode::PseudoVLUXEI8_V_M1_M4_MASK,
19506 0 : 5664 => Opcode::PseudoVLUXEI8_V_M1_M8,
19507 0 : 5665 => Opcode::PseudoVLUXEI8_V_M1_M8_MASK,
19508 0 : 5666 => Opcode::PseudoVLUXEI8_V_M2_M2,
19509 0 : 5667 => Opcode::PseudoVLUXEI8_V_M2_M2_MASK,
19510 0 : 5668 => Opcode::PseudoVLUXEI8_V_M2_M4,
19511 0 : 5669 => Opcode::PseudoVLUXEI8_V_M2_M4_MASK,
19512 0 : 5670 => Opcode::PseudoVLUXEI8_V_M2_M8,
19513 0 : 5671 => Opcode::PseudoVLUXEI8_V_M2_M8_MASK,
19514 0 : 5672 => Opcode::PseudoVLUXEI8_V_M4_M4,
19515 0 : 5673 => Opcode::PseudoVLUXEI8_V_M4_M4_MASK,
19516 0 : 5674 => Opcode::PseudoVLUXEI8_V_M4_M8,
19517 0 : 5675 => Opcode::PseudoVLUXEI8_V_M4_M8_MASK,
19518 0 : 5676 => Opcode::PseudoVLUXEI8_V_M8_M8,
19519 0 : 5677 => Opcode::PseudoVLUXEI8_V_M8_M8_MASK,
19520 0 : 5678 => Opcode::PseudoVLUXEI8_V_MF2_M1,
19521 0 : 5679 => Opcode::PseudoVLUXEI8_V_MF2_M1_MASK,
19522 0 : 5680 => Opcode::PseudoVLUXEI8_V_MF2_M2,
19523 0 : 5681 => Opcode::PseudoVLUXEI8_V_MF2_M2_MASK,
19524 0 : 5682 => Opcode::PseudoVLUXEI8_V_MF2_M4,
19525 0 : 5683 => Opcode::PseudoVLUXEI8_V_MF2_M4_MASK,
19526 0 : 5684 => Opcode::PseudoVLUXEI8_V_MF2_MF2,
19527 0 : 5685 => Opcode::PseudoVLUXEI8_V_MF2_MF2_MASK,
19528 0 : 5686 => Opcode::PseudoVLUXEI8_V_MF4_M1,
19529 0 : 5687 => Opcode::PseudoVLUXEI8_V_MF4_M1_MASK,
19530 0 : 5688 => Opcode::PseudoVLUXEI8_V_MF4_M2,
19531 0 : 5689 => Opcode::PseudoVLUXEI8_V_MF4_M2_MASK,
19532 0 : 5690 => Opcode::PseudoVLUXEI8_V_MF4_MF2,
19533 0 : 5691 => Opcode::PseudoVLUXEI8_V_MF4_MF2_MASK,
19534 0 : 5692 => Opcode::PseudoVLUXEI8_V_MF4_MF4,
19535 0 : 5693 => Opcode::PseudoVLUXEI8_V_MF4_MF4_MASK,
19536 0 : 5694 => Opcode::PseudoVLUXEI8_V_MF8_M1,
19537 0 : 5695 => Opcode::PseudoVLUXEI8_V_MF8_M1_MASK,
19538 0 : 5696 => Opcode::PseudoVLUXEI8_V_MF8_MF2,
19539 0 : 5697 => Opcode::PseudoVLUXEI8_V_MF8_MF2_MASK,
19540 0 : 5698 => Opcode::PseudoVLUXEI8_V_MF8_MF4,
19541 0 : 5699 => Opcode::PseudoVLUXEI8_V_MF8_MF4_MASK,
19542 0 : 5700 => Opcode::PseudoVLUXEI8_V_MF8_MF8,
19543 0 : 5701 => Opcode::PseudoVLUXEI8_V_MF8_MF8_MASK,
19544 0 : 5702 => Opcode::PseudoVLUXSEG2EI16_V_M1_M1,
19545 0 : 5703 => Opcode::PseudoVLUXSEG2EI16_V_M1_M1_MASK,
19546 0 : 5704 => Opcode::PseudoVLUXSEG2EI16_V_M1_M2,
19547 0 : 5705 => Opcode::PseudoVLUXSEG2EI16_V_M1_M2_MASK,
19548 0 : 5706 => Opcode::PseudoVLUXSEG2EI16_V_M1_M4,
19549 0 : 5707 => Opcode::PseudoVLUXSEG2EI16_V_M1_M4_MASK,
19550 0 : 5708 => Opcode::PseudoVLUXSEG2EI16_V_M1_MF2,
19551 0 : 5709 => Opcode::PseudoVLUXSEG2EI16_V_M1_MF2_MASK,
19552 0 : 5710 => Opcode::PseudoVLUXSEG2EI16_V_M2_M1,
19553 0 : 5711 => Opcode::PseudoVLUXSEG2EI16_V_M2_M1_MASK,
19554 0 : 5712 => Opcode::PseudoVLUXSEG2EI16_V_M2_M2,
19555 0 : 5713 => Opcode::PseudoVLUXSEG2EI16_V_M2_M2_MASK,
19556 0 : 5714 => Opcode::PseudoVLUXSEG2EI16_V_M2_M4,
19557 0 : 5715 => Opcode::PseudoVLUXSEG2EI16_V_M2_M4_MASK,
19558 0 : 5716 => Opcode::PseudoVLUXSEG2EI16_V_M4_M2,
19559 0 : 5717 => Opcode::PseudoVLUXSEG2EI16_V_M4_M2_MASK,
19560 0 : 5718 => Opcode::PseudoVLUXSEG2EI16_V_M4_M4,
19561 0 : 5719 => Opcode::PseudoVLUXSEG2EI16_V_M4_M4_MASK,
19562 0 : 5720 => Opcode::PseudoVLUXSEG2EI16_V_M8_M4,
19563 0 : 5721 => Opcode::PseudoVLUXSEG2EI16_V_M8_M4_MASK,
19564 0 : 5722 => Opcode::PseudoVLUXSEG2EI16_V_MF2_M1,
19565 0 : 5723 => Opcode::PseudoVLUXSEG2EI16_V_MF2_M1_MASK,
19566 0 : 5724 => Opcode::PseudoVLUXSEG2EI16_V_MF2_M2,
19567 0 : 5725 => Opcode::PseudoVLUXSEG2EI16_V_MF2_M2_MASK,
19568 0 : 5726 => Opcode::PseudoVLUXSEG2EI16_V_MF2_MF2,
19569 0 : 5727 => Opcode::PseudoVLUXSEG2EI16_V_MF2_MF2_MASK,
19570 0 : 5728 => Opcode::PseudoVLUXSEG2EI16_V_MF2_MF4,
19571 0 : 5729 => Opcode::PseudoVLUXSEG2EI16_V_MF2_MF4_MASK,
19572 0 : 5730 => Opcode::PseudoVLUXSEG2EI16_V_MF4_M1,
19573 0 : 5731 => Opcode::PseudoVLUXSEG2EI16_V_MF4_M1_MASK,
19574 0 : 5732 => Opcode::PseudoVLUXSEG2EI16_V_MF4_MF2,
19575 0 : 5733 => Opcode::PseudoVLUXSEG2EI16_V_MF4_MF2_MASK,
19576 0 : 5734 => Opcode::PseudoVLUXSEG2EI16_V_MF4_MF4,
19577 0 : 5735 => Opcode::PseudoVLUXSEG2EI16_V_MF4_MF4_MASK,
19578 0 : 5736 => Opcode::PseudoVLUXSEG2EI16_V_MF4_MF8,
19579 0 : 5737 => Opcode::PseudoVLUXSEG2EI16_V_MF4_MF8_MASK,
19580 0 : 5738 => Opcode::PseudoVLUXSEG2EI32_V_M1_M1,
19581 0 : 5739 => Opcode::PseudoVLUXSEG2EI32_V_M1_M1_MASK,
19582 0 : 5740 => Opcode::PseudoVLUXSEG2EI32_V_M1_M2,
19583 0 : 5741 => Opcode::PseudoVLUXSEG2EI32_V_M1_M2_MASK,
19584 0 : 5742 => Opcode::PseudoVLUXSEG2EI32_V_M1_MF2,
19585 0 : 5743 => Opcode::PseudoVLUXSEG2EI32_V_M1_MF2_MASK,
19586 0 : 5744 => Opcode::PseudoVLUXSEG2EI32_V_M1_MF4,
19587 0 : 5745 => Opcode::PseudoVLUXSEG2EI32_V_M1_MF4_MASK,
19588 0 : 5746 => Opcode::PseudoVLUXSEG2EI32_V_M2_M1,
19589 0 : 5747 => Opcode::PseudoVLUXSEG2EI32_V_M2_M1_MASK,
19590 0 : 5748 => Opcode::PseudoVLUXSEG2EI32_V_M2_M2,
19591 0 : 5749 => Opcode::PseudoVLUXSEG2EI32_V_M2_M2_MASK,
19592 0 : 5750 => Opcode::PseudoVLUXSEG2EI32_V_M2_M4,
19593 0 : 5751 => Opcode::PseudoVLUXSEG2EI32_V_M2_M4_MASK,
19594 0 : 5752 => Opcode::PseudoVLUXSEG2EI32_V_M2_MF2,
19595 0 : 5753 => Opcode::PseudoVLUXSEG2EI32_V_M2_MF2_MASK,
19596 0 : 5754 => Opcode::PseudoVLUXSEG2EI32_V_M4_M1,
19597 0 : 5755 => Opcode::PseudoVLUXSEG2EI32_V_M4_M1_MASK,
19598 0 : 5756 => Opcode::PseudoVLUXSEG2EI32_V_M4_M2,
19599 0 : 5757 => Opcode::PseudoVLUXSEG2EI32_V_M4_M2_MASK,
19600 0 : 5758 => Opcode::PseudoVLUXSEG2EI32_V_M4_M4,
19601 0 : 5759 => Opcode::PseudoVLUXSEG2EI32_V_M4_M4_MASK,
19602 0 : 5760 => Opcode::PseudoVLUXSEG2EI32_V_M8_M2,
19603 0 : 5761 => Opcode::PseudoVLUXSEG2EI32_V_M8_M2_MASK,
19604 0 : 5762 => Opcode::PseudoVLUXSEG2EI32_V_M8_M4,
19605 0 : 5763 => Opcode::PseudoVLUXSEG2EI32_V_M8_M4_MASK,
19606 0 : 5764 => Opcode::PseudoVLUXSEG2EI32_V_MF2_M1,
19607 0 : 5765 => Opcode::PseudoVLUXSEG2EI32_V_MF2_M1_MASK,
19608 0 : 5766 => Opcode::PseudoVLUXSEG2EI32_V_MF2_MF2,
19609 0 : 5767 => Opcode::PseudoVLUXSEG2EI32_V_MF2_MF2_MASK,
19610 0 : 5768 => Opcode::PseudoVLUXSEG2EI32_V_MF2_MF4,
19611 0 : 5769 => Opcode::PseudoVLUXSEG2EI32_V_MF2_MF4_MASK,
19612 0 : 5770 => Opcode::PseudoVLUXSEG2EI32_V_MF2_MF8,
19613 0 : 5771 => Opcode::PseudoVLUXSEG2EI32_V_MF2_MF8_MASK,
19614 0 : 5772 => Opcode::PseudoVLUXSEG2EI64_V_M1_M1,
19615 0 : 5773 => Opcode::PseudoVLUXSEG2EI64_V_M1_M1_MASK,
19616 0 : 5774 => Opcode::PseudoVLUXSEG2EI64_V_M1_MF2,
19617 0 : 5775 => Opcode::PseudoVLUXSEG2EI64_V_M1_MF2_MASK,
19618 0 : 5776 => Opcode::PseudoVLUXSEG2EI64_V_M1_MF4,
19619 0 : 5777 => Opcode::PseudoVLUXSEG2EI64_V_M1_MF4_MASK,
19620 0 : 5778 => Opcode::PseudoVLUXSEG2EI64_V_M1_MF8,
19621 0 : 5779 => Opcode::PseudoVLUXSEG2EI64_V_M1_MF8_MASK,
19622 0 : 5780 => Opcode::PseudoVLUXSEG2EI64_V_M2_M1,
19623 0 : 5781 => Opcode::PseudoVLUXSEG2EI64_V_M2_M1_MASK,
19624 0 : 5782 => Opcode::PseudoVLUXSEG2EI64_V_M2_M2,
19625 0 : 5783 => Opcode::PseudoVLUXSEG2EI64_V_M2_M2_MASK,
19626 0 : 5784 => Opcode::PseudoVLUXSEG2EI64_V_M2_MF2,
19627 0 : 5785 => Opcode::PseudoVLUXSEG2EI64_V_M2_MF2_MASK,
19628 0 : 5786 => Opcode::PseudoVLUXSEG2EI64_V_M2_MF4,
19629 0 : 5787 => Opcode::PseudoVLUXSEG2EI64_V_M2_MF4_MASK,
19630 0 : 5788 => Opcode::PseudoVLUXSEG2EI64_V_M4_M1,
19631 0 : 5789 => Opcode::PseudoVLUXSEG2EI64_V_M4_M1_MASK,
19632 0 : 5790 => Opcode::PseudoVLUXSEG2EI64_V_M4_M2,
19633 0 : 5791 => Opcode::PseudoVLUXSEG2EI64_V_M4_M2_MASK,
19634 0 : 5792 => Opcode::PseudoVLUXSEG2EI64_V_M4_M4,
19635 0 : 5793 => Opcode::PseudoVLUXSEG2EI64_V_M4_M4_MASK,
19636 0 : 5794 => Opcode::PseudoVLUXSEG2EI64_V_M4_MF2,
19637 0 : 5795 => Opcode::PseudoVLUXSEG2EI64_V_M4_MF2_MASK,
19638 0 : 5796 => Opcode::PseudoVLUXSEG2EI64_V_M8_M1,
19639 0 : 5797 => Opcode::PseudoVLUXSEG2EI64_V_M8_M1_MASK,
19640 0 : 5798 => Opcode::PseudoVLUXSEG2EI64_V_M8_M2,
19641 0 : 5799 => Opcode::PseudoVLUXSEG2EI64_V_M8_M2_MASK,
19642 0 : 5800 => Opcode::PseudoVLUXSEG2EI64_V_M8_M4,
19643 0 : 5801 => Opcode::PseudoVLUXSEG2EI64_V_M8_M4_MASK,
19644 0 : 5802 => Opcode::PseudoVLUXSEG2EI8_V_M1_M1,
19645 0 : 5803 => Opcode::PseudoVLUXSEG2EI8_V_M1_M1_MASK,
19646 0 : 5804 => Opcode::PseudoVLUXSEG2EI8_V_M1_M2,
19647 0 : 5805 => Opcode::PseudoVLUXSEG2EI8_V_M1_M2_MASK,
19648 0 : 5806 => Opcode::PseudoVLUXSEG2EI8_V_M1_M4,
19649 0 : 5807 => Opcode::PseudoVLUXSEG2EI8_V_M1_M4_MASK,
19650 0 : 5808 => Opcode::PseudoVLUXSEG2EI8_V_M2_M2,
19651 0 : 5809 => Opcode::PseudoVLUXSEG2EI8_V_M2_M2_MASK,
19652 0 : 5810 => Opcode::PseudoVLUXSEG2EI8_V_M2_M4,
19653 0 : 5811 => Opcode::PseudoVLUXSEG2EI8_V_M2_M4_MASK,
19654 0 : 5812 => Opcode::PseudoVLUXSEG2EI8_V_M4_M4,
19655 0 : 5813 => Opcode::PseudoVLUXSEG2EI8_V_M4_M4_MASK,
19656 0 : 5814 => Opcode::PseudoVLUXSEG2EI8_V_MF2_M1,
19657 0 : 5815 => Opcode::PseudoVLUXSEG2EI8_V_MF2_M1_MASK,
19658 0 : 5816 => Opcode::PseudoVLUXSEG2EI8_V_MF2_M2,
19659 0 : 5817 => Opcode::PseudoVLUXSEG2EI8_V_MF2_M2_MASK,
19660 0 : 5818 => Opcode::PseudoVLUXSEG2EI8_V_MF2_M4,
19661 0 : 5819 => Opcode::PseudoVLUXSEG2EI8_V_MF2_M4_MASK,
19662 0 : 5820 => Opcode::PseudoVLUXSEG2EI8_V_MF2_MF2,
19663 0 : 5821 => Opcode::PseudoVLUXSEG2EI8_V_MF2_MF2_MASK,
19664 0 : 5822 => Opcode::PseudoVLUXSEG2EI8_V_MF4_M1,
19665 0 : 5823 => Opcode::PseudoVLUXSEG2EI8_V_MF4_M1_MASK,
19666 0 : 5824 => Opcode::PseudoVLUXSEG2EI8_V_MF4_M2,
19667 0 : 5825 => Opcode::PseudoVLUXSEG2EI8_V_MF4_M2_MASK,
19668 0 : 5826 => Opcode::PseudoVLUXSEG2EI8_V_MF4_MF2,
19669 0 : 5827 => Opcode::PseudoVLUXSEG2EI8_V_MF4_MF2_MASK,
19670 0 : 5828 => Opcode::PseudoVLUXSEG2EI8_V_MF4_MF4,
19671 0 : 5829 => Opcode::PseudoVLUXSEG2EI8_V_MF4_MF4_MASK,
19672 0 : 5830 => Opcode::PseudoVLUXSEG2EI8_V_MF8_M1,
19673 0 : 5831 => Opcode::PseudoVLUXSEG2EI8_V_MF8_M1_MASK,
19674 0 : 5832 => Opcode::PseudoVLUXSEG2EI8_V_MF8_MF2,
19675 0 : 5833 => Opcode::PseudoVLUXSEG2EI8_V_MF8_MF2_MASK,
19676 0 : 5834 => Opcode::PseudoVLUXSEG2EI8_V_MF8_MF4,
19677 0 : 5835 => Opcode::PseudoVLUXSEG2EI8_V_MF8_MF4_MASK,
19678 0 : 5836 => Opcode::PseudoVLUXSEG2EI8_V_MF8_MF8,
19679 0 : 5837 => Opcode::PseudoVLUXSEG2EI8_V_MF8_MF8_MASK,
19680 0 : 5838 => Opcode::PseudoVLUXSEG3EI16_V_M1_M1,
19681 0 : 5839 => Opcode::PseudoVLUXSEG3EI16_V_M1_M1_MASK,
19682 0 : 5840 => Opcode::PseudoVLUXSEG3EI16_V_M1_M2,
19683 0 : 5841 => Opcode::PseudoVLUXSEG3EI16_V_M1_M2_MASK,
19684 0 : 5842 => Opcode::PseudoVLUXSEG3EI16_V_M1_MF2,
19685 0 : 5843 => Opcode::PseudoVLUXSEG3EI16_V_M1_MF2_MASK,
19686 0 : 5844 => Opcode::PseudoVLUXSEG3EI16_V_M2_M1,
19687 0 : 5845 => Opcode::PseudoVLUXSEG3EI16_V_M2_M1_MASK,
19688 0 : 5846 => Opcode::PseudoVLUXSEG3EI16_V_M2_M2,
19689 0 : 5847 => Opcode::PseudoVLUXSEG3EI16_V_M2_M2_MASK,
19690 0 : 5848 => Opcode::PseudoVLUXSEG3EI16_V_M4_M2,
19691 0 : 5849 => Opcode::PseudoVLUXSEG3EI16_V_M4_M2_MASK,
19692 0 : 5850 => Opcode::PseudoVLUXSEG3EI16_V_MF2_M1,
19693 0 : 5851 => Opcode::PseudoVLUXSEG3EI16_V_MF2_M1_MASK,
19694 0 : 5852 => Opcode::PseudoVLUXSEG3EI16_V_MF2_M2,
19695 0 : 5853 => Opcode::PseudoVLUXSEG3EI16_V_MF2_M2_MASK,
19696 0 : 5854 => Opcode::PseudoVLUXSEG3EI16_V_MF2_MF2,
19697 0 : 5855 => Opcode::PseudoVLUXSEG3EI16_V_MF2_MF2_MASK,
19698 0 : 5856 => Opcode::PseudoVLUXSEG3EI16_V_MF2_MF4,
19699 0 : 5857 => Opcode::PseudoVLUXSEG3EI16_V_MF2_MF4_MASK,
19700 0 : 5858 => Opcode::PseudoVLUXSEG3EI16_V_MF4_M1,
19701 0 : 5859 => Opcode::PseudoVLUXSEG3EI16_V_MF4_M1_MASK,
19702 0 : 5860 => Opcode::PseudoVLUXSEG3EI16_V_MF4_MF2,
19703 0 : 5861 => Opcode::PseudoVLUXSEG3EI16_V_MF4_MF2_MASK,
19704 0 : 5862 => Opcode::PseudoVLUXSEG3EI16_V_MF4_MF4,
19705 0 : 5863 => Opcode::PseudoVLUXSEG3EI16_V_MF4_MF4_MASK,
19706 0 : 5864 => Opcode::PseudoVLUXSEG3EI16_V_MF4_MF8,
19707 0 : 5865 => Opcode::PseudoVLUXSEG3EI16_V_MF4_MF8_MASK,
19708 0 : 5866 => Opcode::PseudoVLUXSEG3EI32_V_M1_M1,
19709 0 : 5867 => Opcode::PseudoVLUXSEG3EI32_V_M1_M1_MASK,
19710 0 : 5868 => Opcode::PseudoVLUXSEG3EI32_V_M1_M2,
19711 0 : 5869 => Opcode::PseudoVLUXSEG3EI32_V_M1_M2_MASK,
19712 0 : 5870 => Opcode::PseudoVLUXSEG3EI32_V_M1_MF2,
19713 0 : 5871 => Opcode::PseudoVLUXSEG3EI32_V_M1_MF2_MASK,
19714 0 : 5872 => Opcode::PseudoVLUXSEG3EI32_V_M1_MF4,
19715 0 : 5873 => Opcode::PseudoVLUXSEG3EI32_V_M1_MF4_MASK,
19716 0 : 5874 => Opcode::PseudoVLUXSEG3EI32_V_M2_M1,
19717 0 : 5875 => Opcode::PseudoVLUXSEG3EI32_V_M2_M1_MASK,
19718 0 : 5876 => Opcode::PseudoVLUXSEG3EI32_V_M2_M2,
19719 0 : 5877 => Opcode::PseudoVLUXSEG3EI32_V_M2_M2_MASK,
19720 0 : 5878 => Opcode::PseudoVLUXSEG3EI32_V_M2_MF2,
19721 0 : 5879 => Opcode::PseudoVLUXSEG3EI32_V_M2_MF2_MASK,
19722 0 : 5880 => Opcode::PseudoVLUXSEG3EI32_V_M4_M1,
19723 0 : 5881 => Opcode::PseudoVLUXSEG3EI32_V_M4_M1_MASK,
19724 0 : 5882 => Opcode::PseudoVLUXSEG3EI32_V_M4_M2,
19725 0 : 5883 => Opcode::PseudoVLUXSEG3EI32_V_M4_M2_MASK,
19726 0 : 5884 => Opcode::PseudoVLUXSEG3EI32_V_M8_M2,
19727 0 : 5885 => Opcode::PseudoVLUXSEG3EI32_V_M8_M2_MASK,
19728 0 : 5886 => Opcode::PseudoVLUXSEG3EI32_V_MF2_M1,
19729 0 : 5887 => Opcode::PseudoVLUXSEG3EI32_V_MF2_M1_MASK,
19730 0 : 5888 => Opcode::PseudoVLUXSEG3EI32_V_MF2_MF2,
19731 0 : 5889 => Opcode::PseudoVLUXSEG3EI32_V_MF2_MF2_MASK,
19732 0 : 5890 => Opcode::PseudoVLUXSEG3EI32_V_MF2_MF4,
19733 0 : 5891 => Opcode::PseudoVLUXSEG3EI32_V_MF2_MF4_MASK,
19734 0 : 5892 => Opcode::PseudoVLUXSEG3EI32_V_MF2_MF8,
19735 0 : 5893 => Opcode::PseudoVLUXSEG3EI32_V_MF2_MF8_MASK,
19736 0 : 5894 => Opcode::PseudoVLUXSEG3EI64_V_M1_M1,
19737 0 : 5895 => Opcode::PseudoVLUXSEG3EI64_V_M1_M1_MASK,
19738 0 : 5896 => Opcode::PseudoVLUXSEG3EI64_V_M1_MF2,
19739 0 : 5897 => Opcode::PseudoVLUXSEG3EI64_V_M1_MF2_MASK,
19740 0 : 5898 => Opcode::PseudoVLUXSEG3EI64_V_M1_MF4,
19741 0 : 5899 => Opcode::PseudoVLUXSEG3EI64_V_M1_MF4_MASK,
19742 0 : 5900 => Opcode::PseudoVLUXSEG3EI64_V_M1_MF8,
19743 0 : 5901 => Opcode::PseudoVLUXSEG3EI64_V_M1_MF8_MASK,
19744 0 : 5902 => Opcode::PseudoVLUXSEG3EI64_V_M2_M1,
19745 0 : 5903 => Opcode::PseudoVLUXSEG3EI64_V_M2_M1_MASK,
19746 0 : 5904 => Opcode::PseudoVLUXSEG3EI64_V_M2_M2,
19747 0 : 5905 => Opcode::PseudoVLUXSEG3EI64_V_M2_M2_MASK,
19748 0 : 5906 => Opcode::PseudoVLUXSEG3EI64_V_M2_MF2,
19749 0 : 5907 => Opcode::PseudoVLUXSEG3EI64_V_M2_MF2_MASK,
19750 0 : 5908 => Opcode::PseudoVLUXSEG3EI64_V_M2_MF4,
19751 0 : 5909 => Opcode::PseudoVLUXSEG3EI64_V_M2_MF4_MASK,
19752 0 : 5910 => Opcode::PseudoVLUXSEG3EI64_V_M4_M1,
19753 0 : 5911 => Opcode::PseudoVLUXSEG3EI64_V_M4_M1_MASK,
19754 0 : 5912 => Opcode::PseudoVLUXSEG3EI64_V_M4_M2,
19755 0 : 5913 => Opcode::PseudoVLUXSEG3EI64_V_M4_M2_MASK,
19756 0 : 5914 => Opcode::PseudoVLUXSEG3EI64_V_M4_MF2,
19757 0 : 5915 => Opcode::PseudoVLUXSEG3EI64_V_M4_MF2_MASK,
19758 0 : 5916 => Opcode::PseudoVLUXSEG3EI64_V_M8_M1,
19759 0 : 5917 => Opcode::PseudoVLUXSEG3EI64_V_M8_M1_MASK,
19760 0 : 5918 => Opcode::PseudoVLUXSEG3EI64_V_M8_M2,
19761 0 : 5919 => Opcode::PseudoVLUXSEG3EI64_V_M8_M2_MASK,
19762 0 : 5920 => Opcode::PseudoVLUXSEG3EI8_V_M1_M1,
19763 0 : 5921 => Opcode::PseudoVLUXSEG3EI8_V_M1_M1_MASK,
19764 0 : 5922 => Opcode::PseudoVLUXSEG3EI8_V_M1_M2,
19765 0 : 5923 => Opcode::PseudoVLUXSEG3EI8_V_M1_M2_MASK,
19766 0 : 5924 => Opcode::PseudoVLUXSEG3EI8_V_M2_M2,
19767 0 : 5925 => Opcode::PseudoVLUXSEG3EI8_V_M2_M2_MASK,
19768 0 : 5926 => Opcode::PseudoVLUXSEG3EI8_V_MF2_M1,
19769 0 : 5927 => Opcode::PseudoVLUXSEG3EI8_V_MF2_M1_MASK,
19770 0 : 5928 => Opcode::PseudoVLUXSEG3EI8_V_MF2_M2,
19771 0 : 5929 => Opcode::PseudoVLUXSEG3EI8_V_MF2_M2_MASK,
19772 0 : 5930 => Opcode::PseudoVLUXSEG3EI8_V_MF2_MF2,
19773 0 : 5931 => Opcode::PseudoVLUXSEG3EI8_V_MF2_MF2_MASK,
19774 0 : 5932 => Opcode::PseudoVLUXSEG3EI8_V_MF4_M1,
19775 0 : 5933 => Opcode::PseudoVLUXSEG3EI8_V_MF4_M1_MASK,
19776 0 : 5934 => Opcode::PseudoVLUXSEG3EI8_V_MF4_M2,
19777 0 : 5935 => Opcode::PseudoVLUXSEG3EI8_V_MF4_M2_MASK,
19778 0 : 5936 => Opcode::PseudoVLUXSEG3EI8_V_MF4_MF2,
19779 0 : 5937 => Opcode::PseudoVLUXSEG3EI8_V_MF4_MF2_MASK,
19780 0 : 5938 => Opcode::PseudoVLUXSEG3EI8_V_MF4_MF4,
19781 0 : 5939 => Opcode::PseudoVLUXSEG3EI8_V_MF4_MF4_MASK,
19782 0 : 5940 => Opcode::PseudoVLUXSEG3EI8_V_MF8_M1,
19783 0 : 5941 => Opcode::PseudoVLUXSEG3EI8_V_MF8_M1_MASK,
19784 0 : 5942 => Opcode::PseudoVLUXSEG3EI8_V_MF8_MF2,
19785 0 : 5943 => Opcode::PseudoVLUXSEG3EI8_V_MF8_MF2_MASK,
19786 0 : 5944 => Opcode::PseudoVLUXSEG3EI8_V_MF8_MF4,
19787 0 : 5945 => Opcode::PseudoVLUXSEG3EI8_V_MF8_MF4_MASK,
19788 0 : 5946 => Opcode::PseudoVLUXSEG3EI8_V_MF8_MF8,
19789 0 : 5947 => Opcode::PseudoVLUXSEG3EI8_V_MF8_MF8_MASK,
19790 0 : 5948 => Opcode::PseudoVLUXSEG4EI16_V_M1_M1,
19791 0 : 5949 => Opcode::PseudoVLUXSEG4EI16_V_M1_M1_MASK,
19792 0 : 5950 => Opcode::PseudoVLUXSEG4EI16_V_M1_M2,
19793 0 : 5951 => Opcode::PseudoVLUXSEG4EI16_V_M1_M2_MASK,
19794 0 : 5952 => Opcode::PseudoVLUXSEG4EI16_V_M1_MF2,
19795 0 : 5953 => Opcode::PseudoVLUXSEG4EI16_V_M1_MF2_MASK,
19796 0 : 5954 => Opcode::PseudoVLUXSEG4EI16_V_M2_M1,
19797 0 : 5955 => Opcode::PseudoVLUXSEG4EI16_V_M2_M1_MASK,
19798 0 : 5956 => Opcode::PseudoVLUXSEG4EI16_V_M2_M2,
19799 0 : 5957 => Opcode::PseudoVLUXSEG4EI16_V_M2_M2_MASK,
19800 0 : 5958 => Opcode::PseudoVLUXSEG4EI16_V_M4_M2,
19801 0 : 5959 => Opcode::PseudoVLUXSEG4EI16_V_M4_M2_MASK,
19802 0 : 5960 => Opcode::PseudoVLUXSEG4EI16_V_MF2_M1,
19803 0 : 5961 => Opcode::PseudoVLUXSEG4EI16_V_MF2_M1_MASK,
19804 0 : 5962 => Opcode::PseudoVLUXSEG4EI16_V_MF2_M2,
19805 0 : 5963 => Opcode::PseudoVLUXSEG4EI16_V_MF2_M2_MASK,
19806 0 : 5964 => Opcode::PseudoVLUXSEG4EI16_V_MF2_MF2,
19807 0 : 5965 => Opcode::PseudoVLUXSEG4EI16_V_MF2_MF2_MASK,
19808 0 : 5966 => Opcode::PseudoVLUXSEG4EI16_V_MF2_MF4,
19809 0 : 5967 => Opcode::PseudoVLUXSEG4EI16_V_MF2_MF4_MASK,
19810 0 : 5968 => Opcode::PseudoVLUXSEG4EI16_V_MF4_M1,
19811 0 : 5969 => Opcode::PseudoVLUXSEG4EI16_V_MF4_M1_MASK,
19812 0 : 5970 => Opcode::PseudoVLUXSEG4EI16_V_MF4_MF2,
19813 0 : 5971 => Opcode::PseudoVLUXSEG4EI16_V_MF4_MF2_MASK,
19814 0 : 5972 => Opcode::PseudoVLUXSEG4EI16_V_MF4_MF4,
19815 0 : 5973 => Opcode::PseudoVLUXSEG4EI16_V_MF4_MF4_MASK,
19816 0 : 5974 => Opcode::PseudoVLUXSEG4EI16_V_MF4_MF8,
19817 0 : 5975 => Opcode::PseudoVLUXSEG4EI16_V_MF4_MF8_MASK,
19818 0 : 5976 => Opcode::PseudoVLUXSEG4EI32_V_M1_M1,
19819 0 : 5977 => Opcode::PseudoVLUXSEG4EI32_V_M1_M1_MASK,
19820 0 : 5978 => Opcode::PseudoVLUXSEG4EI32_V_M1_M2,
19821 0 : 5979 => Opcode::PseudoVLUXSEG4EI32_V_M1_M2_MASK,
19822 0 : 5980 => Opcode::PseudoVLUXSEG4EI32_V_M1_MF2,
19823 0 : 5981 => Opcode::PseudoVLUXSEG4EI32_V_M1_MF2_MASK,
19824 0 : 5982 => Opcode::PseudoVLUXSEG4EI32_V_M1_MF4,
19825 0 : 5983 => Opcode::PseudoVLUXSEG4EI32_V_M1_MF4_MASK,
19826 0 : 5984 => Opcode::PseudoVLUXSEG4EI32_V_M2_M1,
19827 0 : 5985 => Opcode::PseudoVLUXSEG4EI32_V_M2_M1_MASK,
19828 0 : 5986 => Opcode::PseudoVLUXSEG4EI32_V_M2_M2,
19829 0 : 5987 => Opcode::PseudoVLUXSEG4EI32_V_M2_M2_MASK,
19830 0 : 5988 => Opcode::PseudoVLUXSEG4EI32_V_M2_MF2,
19831 0 : 5989 => Opcode::PseudoVLUXSEG4EI32_V_M2_MF2_MASK,
19832 0 : 5990 => Opcode::PseudoVLUXSEG4EI32_V_M4_M1,
19833 0 : 5991 => Opcode::PseudoVLUXSEG4EI32_V_M4_M1_MASK,
19834 0 : 5992 => Opcode::PseudoVLUXSEG4EI32_V_M4_M2,
19835 0 : 5993 => Opcode::PseudoVLUXSEG4EI32_V_M4_M2_MASK,
19836 0 : 5994 => Opcode::PseudoVLUXSEG4EI32_V_M8_M2,
19837 0 : 5995 => Opcode::PseudoVLUXSEG4EI32_V_M8_M2_MASK,
19838 0 : 5996 => Opcode::PseudoVLUXSEG4EI32_V_MF2_M1,
19839 0 : 5997 => Opcode::PseudoVLUXSEG4EI32_V_MF2_M1_MASK,
19840 0 : 5998 => Opcode::PseudoVLUXSEG4EI32_V_MF2_MF2,
19841 0 : 5999 => Opcode::PseudoVLUXSEG4EI32_V_MF2_MF2_MASK,
19842 0 : 6000 => Opcode::PseudoVLUXSEG4EI32_V_MF2_MF4,
19843 0 : 6001 => Opcode::PseudoVLUXSEG4EI32_V_MF2_MF4_MASK,
19844 0 : 6002 => Opcode::PseudoVLUXSEG4EI32_V_MF2_MF8,
19845 0 : 6003 => Opcode::PseudoVLUXSEG4EI32_V_MF2_MF8_MASK,
19846 0 : 6004 => Opcode::PseudoVLUXSEG4EI64_V_M1_M1,
19847 0 : 6005 => Opcode::PseudoVLUXSEG4EI64_V_M1_M1_MASK,
19848 0 : 6006 => Opcode::PseudoVLUXSEG4EI64_V_M1_MF2,
19849 0 : 6007 => Opcode::PseudoVLUXSEG4EI64_V_M1_MF2_MASK,
19850 0 : 6008 => Opcode::PseudoVLUXSEG4EI64_V_M1_MF4,
19851 0 : 6009 => Opcode::PseudoVLUXSEG4EI64_V_M1_MF4_MASK,
19852 0 : 6010 => Opcode::PseudoVLUXSEG4EI64_V_M1_MF8,
19853 0 : 6011 => Opcode::PseudoVLUXSEG4EI64_V_M1_MF8_MASK,
19854 0 : 6012 => Opcode::PseudoVLUXSEG4EI64_V_M2_M1,
19855 0 : 6013 => Opcode::PseudoVLUXSEG4EI64_V_M2_M1_MASK,
19856 0 : 6014 => Opcode::PseudoVLUXSEG4EI64_V_M2_M2,
19857 0 : 6015 => Opcode::PseudoVLUXSEG4EI64_V_M2_M2_MASK,
19858 0 : 6016 => Opcode::PseudoVLUXSEG4EI64_V_M2_MF2,
19859 0 : 6017 => Opcode::PseudoVLUXSEG4EI64_V_M2_MF2_MASK,
19860 0 : 6018 => Opcode::PseudoVLUXSEG4EI64_V_M2_MF4,
19861 0 : 6019 => Opcode::PseudoVLUXSEG4EI64_V_M2_MF4_MASK,
19862 0 : 6020 => Opcode::PseudoVLUXSEG4EI64_V_M4_M1,
19863 0 : 6021 => Opcode::PseudoVLUXSEG4EI64_V_M4_M1_MASK,
19864 0 : 6022 => Opcode::PseudoVLUXSEG4EI64_V_M4_M2,
19865 0 : 6023 => Opcode::PseudoVLUXSEG4EI64_V_M4_M2_MASK,
19866 0 : 6024 => Opcode::PseudoVLUXSEG4EI64_V_M4_MF2,
19867 0 : 6025 => Opcode::PseudoVLUXSEG4EI64_V_M4_MF2_MASK,
19868 0 : 6026 => Opcode::PseudoVLUXSEG4EI64_V_M8_M1,
19869 0 : 6027 => Opcode::PseudoVLUXSEG4EI64_V_M8_M1_MASK,
19870 0 : 6028 => Opcode::PseudoVLUXSEG4EI64_V_M8_M2,
19871 0 : 6029 => Opcode::PseudoVLUXSEG4EI64_V_M8_M2_MASK,
19872 0 : 6030 => Opcode::PseudoVLUXSEG4EI8_V_M1_M1,
19873 0 : 6031 => Opcode::PseudoVLUXSEG4EI8_V_M1_M1_MASK,
19874 0 : 6032 => Opcode::PseudoVLUXSEG4EI8_V_M1_M2,
19875 0 : 6033 => Opcode::PseudoVLUXSEG4EI8_V_M1_M2_MASK,
19876 0 : 6034 => Opcode::PseudoVLUXSEG4EI8_V_M2_M2,
19877 0 : 6035 => Opcode::PseudoVLUXSEG4EI8_V_M2_M2_MASK,
19878 0 : 6036 => Opcode::PseudoVLUXSEG4EI8_V_MF2_M1,
19879 0 : 6037 => Opcode::PseudoVLUXSEG4EI8_V_MF2_M1_MASK,
19880 0 : 6038 => Opcode::PseudoVLUXSEG4EI8_V_MF2_M2,
19881 0 : 6039 => Opcode::PseudoVLUXSEG4EI8_V_MF2_M2_MASK,
19882 0 : 6040 => Opcode::PseudoVLUXSEG4EI8_V_MF2_MF2,
19883 0 : 6041 => Opcode::PseudoVLUXSEG4EI8_V_MF2_MF2_MASK,
19884 0 : 6042 => Opcode::PseudoVLUXSEG4EI8_V_MF4_M1,
19885 0 : 6043 => Opcode::PseudoVLUXSEG4EI8_V_MF4_M1_MASK,
19886 0 : 6044 => Opcode::PseudoVLUXSEG4EI8_V_MF4_M2,
19887 0 : 6045 => Opcode::PseudoVLUXSEG4EI8_V_MF4_M2_MASK,
19888 0 : 6046 => Opcode::PseudoVLUXSEG4EI8_V_MF4_MF2,
19889 0 : 6047 => Opcode::PseudoVLUXSEG4EI8_V_MF4_MF2_MASK,
19890 0 : 6048 => Opcode::PseudoVLUXSEG4EI8_V_MF4_MF4,
19891 0 : 6049 => Opcode::PseudoVLUXSEG4EI8_V_MF4_MF4_MASK,
19892 0 : 6050 => Opcode::PseudoVLUXSEG4EI8_V_MF8_M1,
19893 0 : 6051 => Opcode::PseudoVLUXSEG4EI8_V_MF8_M1_MASK,
19894 0 : 6052 => Opcode::PseudoVLUXSEG4EI8_V_MF8_MF2,
19895 0 : 6053 => Opcode::PseudoVLUXSEG4EI8_V_MF8_MF2_MASK,
19896 0 : 6054 => Opcode::PseudoVLUXSEG4EI8_V_MF8_MF4,
19897 0 : 6055 => Opcode::PseudoVLUXSEG4EI8_V_MF8_MF4_MASK,
19898 0 : 6056 => Opcode::PseudoVLUXSEG4EI8_V_MF8_MF8,
19899 0 : 6057 => Opcode::PseudoVLUXSEG4EI8_V_MF8_MF8_MASK,
19900 0 : 6058 => Opcode::PseudoVLUXSEG5EI16_V_M1_M1,
19901 0 : 6059 => Opcode::PseudoVLUXSEG5EI16_V_M1_M1_MASK,
19902 0 : 6060 => Opcode::PseudoVLUXSEG5EI16_V_M1_MF2,
19903 0 : 6061 => Opcode::PseudoVLUXSEG5EI16_V_M1_MF2_MASK,
19904 0 : 6062 => Opcode::PseudoVLUXSEG5EI16_V_M2_M1,
19905 0 : 6063 => Opcode::PseudoVLUXSEG5EI16_V_M2_M1_MASK,
19906 0 : 6064 => Opcode::PseudoVLUXSEG5EI16_V_MF2_M1,
19907 0 : 6065 => Opcode::PseudoVLUXSEG5EI16_V_MF2_M1_MASK,
19908 0 : 6066 => Opcode::PseudoVLUXSEG5EI16_V_MF2_MF2,
19909 0 : 6067 => Opcode::PseudoVLUXSEG5EI16_V_MF2_MF2_MASK,
19910 0 : 6068 => Opcode::PseudoVLUXSEG5EI16_V_MF2_MF4,
19911 0 : 6069 => Opcode::PseudoVLUXSEG5EI16_V_MF2_MF4_MASK,
19912 0 : 6070 => Opcode::PseudoVLUXSEG5EI16_V_MF4_M1,
19913 0 : 6071 => Opcode::PseudoVLUXSEG5EI16_V_MF4_M1_MASK,
19914 0 : 6072 => Opcode::PseudoVLUXSEG5EI16_V_MF4_MF2,
19915 0 : 6073 => Opcode::PseudoVLUXSEG5EI16_V_MF4_MF2_MASK,
19916 0 : 6074 => Opcode::PseudoVLUXSEG5EI16_V_MF4_MF4,
19917 0 : 6075 => Opcode::PseudoVLUXSEG5EI16_V_MF4_MF4_MASK,
19918 0 : 6076 => Opcode::PseudoVLUXSEG5EI16_V_MF4_MF8,
19919 0 : 6077 => Opcode::PseudoVLUXSEG5EI16_V_MF4_MF8_MASK,
19920 0 : 6078 => Opcode::PseudoVLUXSEG5EI32_V_M1_M1,
19921 0 : 6079 => Opcode::PseudoVLUXSEG5EI32_V_M1_M1_MASK,
19922 0 : 6080 => Opcode::PseudoVLUXSEG5EI32_V_M1_MF2,
19923 0 : 6081 => Opcode::PseudoVLUXSEG5EI32_V_M1_MF2_MASK,
19924 0 : 6082 => Opcode::PseudoVLUXSEG5EI32_V_M1_MF4,
19925 0 : 6083 => Opcode::PseudoVLUXSEG5EI32_V_M1_MF4_MASK,
19926 0 : 6084 => Opcode::PseudoVLUXSEG5EI32_V_M2_M1,
19927 0 : 6085 => Opcode::PseudoVLUXSEG5EI32_V_M2_M1_MASK,
19928 0 : 6086 => Opcode::PseudoVLUXSEG5EI32_V_M2_MF2,
19929 0 : 6087 => Opcode::PseudoVLUXSEG5EI32_V_M2_MF2_MASK,
19930 0 : 6088 => Opcode::PseudoVLUXSEG5EI32_V_M4_M1,
19931 0 : 6089 => Opcode::PseudoVLUXSEG5EI32_V_M4_M1_MASK,
19932 0 : 6090 => Opcode::PseudoVLUXSEG5EI32_V_MF2_M1,
19933 0 : 6091 => Opcode::PseudoVLUXSEG5EI32_V_MF2_M1_MASK,
19934 0 : 6092 => Opcode::PseudoVLUXSEG5EI32_V_MF2_MF2,
19935 0 : 6093 => Opcode::PseudoVLUXSEG5EI32_V_MF2_MF2_MASK,
19936 0 : 6094 => Opcode::PseudoVLUXSEG5EI32_V_MF2_MF4,
19937 0 : 6095 => Opcode::PseudoVLUXSEG5EI32_V_MF2_MF4_MASK,
19938 0 : 6096 => Opcode::PseudoVLUXSEG5EI32_V_MF2_MF8,
19939 0 : 6097 => Opcode::PseudoVLUXSEG5EI32_V_MF2_MF8_MASK,
19940 0 : 6098 => Opcode::PseudoVLUXSEG5EI64_V_M1_M1,
19941 0 : 6099 => Opcode::PseudoVLUXSEG5EI64_V_M1_M1_MASK,
19942 0 : 6100 => Opcode::PseudoVLUXSEG5EI64_V_M1_MF2,
19943 0 : 6101 => Opcode::PseudoVLUXSEG5EI64_V_M1_MF2_MASK,
19944 0 : 6102 => Opcode::PseudoVLUXSEG5EI64_V_M1_MF4,
19945 0 : 6103 => Opcode::PseudoVLUXSEG5EI64_V_M1_MF4_MASK,
19946 0 : 6104 => Opcode::PseudoVLUXSEG5EI64_V_M1_MF8,
19947 0 : 6105 => Opcode::PseudoVLUXSEG5EI64_V_M1_MF8_MASK,
19948 0 : 6106 => Opcode::PseudoVLUXSEG5EI64_V_M2_M1,
19949 0 : 6107 => Opcode::PseudoVLUXSEG5EI64_V_M2_M1_MASK,
19950 0 : 6108 => Opcode::PseudoVLUXSEG5EI64_V_M2_MF2,
19951 0 : 6109 => Opcode::PseudoVLUXSEG5EI64_V_M2_MF2_MASK,
19952 0 : 6110 => Opcode::PseudoVLUXSEG5EI64_V_M2_MF4,
19953 0 : 6111 => Opcode::PseudoVLUXSEG5EI64_V_M2_MF4_MASK,
19954 0 : 6112 => Opcode::PseudoVLUXSEG5EI64_V_M4_M1,
19955 0 : 6113 => Opcode::PseudoVLUXSEG5EI64_V_M4_M1_MASK,
19956 0 : 6114 => Opcode::PseudoVLUXSEG5EI64_V_M4_MF2,
19957 0 : 6115 => Opcode::PseudoVLUXSEG5EI64_V_M4_MF2_MASK,
19958 0 : 6116 => Opcode::PseudoVLUXSEG5EI64_V_M8_M1,
19959 0 : 6117 => Opcode::PseudoVLUXSEG5EI64_V_M8_M1_MASK,
19960 0 : 6118 => Opcode::PseudoVLUXSEG5EI8_V_M1_M1,
19961 0 : 6119 => Opcode::PseudoVLUXSEG5EI8_V_M1_M1_MASK,
19962 0 : 6120 => Opcode::PseudoVLUXSEG5EI8_V_MF2_M1,
19963 0 : 6121 => Opcode::PseudoVLUXSEG5EI8_V_MF2_M1_MASK,
19964 0 : 6122 => Opcode::PseudoVLUXSEG5EI8_V_MF2_MF2,
19965 0 : 6123 => Opcode::PseudoVLUXSEG5EI8_V_MF2_MF2_MASK,
19966 0 : 6124 => Opcode::PseudoVLUXSEG5EI8_V_MF4_M1,
19967 0 : 6125 => Opcode::PseudoVLUXSEG5EI8_V_MF4_M1_MASK,
19968 0 : 6126 => Opcode::PseudoVLUXSEG5EI8_V_MF4_MF2,
19969 0 : 6127 => Opcode::PseudoVLUXSEG5EI8_V_MF4_MF2_MASK,
19970 0 : 6128 => Opcode::PseudoVLUXSEG5EI8_V_MF4_MF4,
19971 0 : 6129 => Opcode::PseudoVLUXSEG5EI8_V_MF4_MF4_MASK,
19972 0 : 6130 => Opcode::PseudoVLUXSEG5EI8_V_MF8_M1,
19973 0 : 6131 => Opcode::PseudoVLUXSEG5EI8_V_MF8_M1_MASK,
19974 0 : 6132 => Opcode::PseudoVLUXSEG5EI8_V_MF8_MF2,
19975 0 : 6133 => Opcode::PseudoVLUXSEG5EI8_V_MF8_MF2_MASK,
19976 0 : 6134 => Opcode::PseudoVLUXSEG5EI8_V_MF8_MF4,
19977 0 : 6135 => Opcode::PseudoVLUXSEG5EI8_V_MF8_MF4_MASK,
19978 0 : 6136 => Opcode::PseudoVLUXSEG5EI8_V_MF8_MF8,
19979 0 : 6137 => Opcode::PseudoVLUXSEG5EI8_V_MF8_MF8_MASK,
19980 0 : 6138 => Opcode::PseudoVLUXSEG6EI16_V_M1_M1,
19981 0 : 6139 => Opcode::PseudoVLUXSEG6EI16_V_M1_M1_MASK,
19982 0 : 6140 => Opcode::PseudoVLUXSEG6EI16_V_M1_MF2,
19983 0 : 6141 => Opcode::PseudoVLUXSEG6EI16_V_M1_MF2_MASK,
19984 0 : 6142 => Opcode::PseudoVLUXSEG6EI16_V_M2_M1,
19985 0 : 6143 => Opcode::PseudoVLUXSEG6EI16_V_M2_M1_MASK,
19986 0 : 6144 => Opcode::PseudoVLUXSEG6EI16_V_MF2_M1,
19987 0 : 6145 => Opcode::PseudoVLUXSEG6EI16_V_MF2_M1_MASK,
19988 0 : 6146 => Opcode::PseudoVLUXSEG6EI16_V_MF2_MF2,
19989 0 : 6147 => Opcode::PseudoVLUXSEG6EI16_V_MF2_MF2_MASK,
19990 0 : 6148 => Opcode::PseudoVLUXSEG6EI16_V_MF2_MF4,
19991 0 : 6149 => Opcode::PseudoVLUXSEG6EI16_V_MF2_MF4_MASK,
19992 0 : 6150 => Opcode::PseudoVLUXSEG6EI16_V_MF4_M1,
19993 0 : 6151 => Opcode::PseudoVLUXSEG6EI16_V_MF4_M1_MASK,
19994 0 : 6152 => Opcode::PseudoVLUXSEG6EI16_V_MF4_MF2,
19995 0 : 6153 => Opcode::PseudoVLUXSEG6EI16_V_MF4_MF2_MASK,
19996 0 : 6154 => Opcode::PseudoVLUXSEG6EI16_V_MF4_MF4,
19997 0 : 6155 => Opcode::PseudoVLUXSEG6EI16_V_MF4_MF4_MASK,
19998 0 : 6156 => Opcode::PseudoVLUXSEG6EI16_V_MF4_MF8,
19999 0 : 6157 => Opcode::PseudoVLUXSEG6EI16_V_MF4_MF8_MASK,
20000 0 : 6158 => Opcode::PseudoVLUXSEG6EI32_V_M1_M1,
20001 0 : 6159 => Opcode::PseudoVLUXSEG6EI32_V_M1_M1_MASK,
20002 0 : 6160 => Opcode::PseudoVLUXSEG6EI32_V_M1_MF2,
20003 0 : 6161 => Opcode::PseudoVLUXSEG6EI32_V_M1_MF2_MASK,
20004 0 : 6162 => Opcode::PseudoVLUXSEG6EI32_V_M1_MF4,
20005 0 : 6163 => Opcode::PseudoVLUXSEG6EI32_V_M1_MF4_MASK,
20006 0 : 6164 => Opcode::PseudoVLUXSEG6EI32_V_M2_M1,
20007 0 : 6165 => Opcode::PseudoVLUXSEG6EI32_V_M2_M1_MASK,
20008 0 : 6166 => Opcode::PseudoVLUXSEG6EI32_V_M2_MF2,
20009 0 : 6167 => Opcode::PseudoVLUXSEG6EI32_V_M2_MF2_MASK,
20010 0 : 6168 => Opcode::PseudoVLUXSEG6EI32_V_M4_M1,
20011 0 : 6169 => Opcode::PseudoVLUXSEG6EI32_V_M4_M1_MASK,
20012 0 : 6170 => Opcode::PseudoVLUXSEG6EI32_V_MF2_M1,
20013 0 : 6171 => Opcode::PseudoVLUXSEG6EI32_V_MF2_M1_MASK,
20014 0 : 6172 => Opcode::PseudoVLUXSEG6EI32_V_MF2_MF2,
20015 0 : 6173 => Opcode::PseudoVLUXSEG6EI32_V_MF2_MF2_MASK,
20016 0 : 6174 => Opcode::PseudoVLUXSEG6EI32_V_MF2_MF4,
20017 0 : 6175 => Opcode::PseudoVLUXSEG6EI32_V_MF2_MF4_MASK,
20018 0 : 6176 => Opcode::PseudoVLUXSEG6EI32_V_MF2_MF8,
20019 0 : 6177 => Opcode::PseudoVLUXSEG6EI32_V_MF2_MF8_MASK,
20020 0 : 6178 => Opcode::PseudoVLUXSEG6EI64_V_M1_M1,
20021 0 : 6179 => Opcode::PseudoVLUXSEG6EI64_V_M1_M1_MASK,
20022 0 : 6180 => Opcode::PseudoVLUXSEG6EI64_V_M1_MF2,
20023 0 : 6181 => Opcode::PseudoVLUXSEG6EI64_V_M1_MF2_MASK,
20024 0 : 6182 => Opcode::PseudoVLUXSEG6EI64_V_M1_MF4,
20025 0 : 6183 => Opcode::PseudoVLUXSEG6EI64_V_M1_MF4_MASK,
20026 0 : 6184 => Opcode::PseudoVLUXSEG6EI64_V_M1_MF8,
20027 0 : 6185 => Opcode::PseudoVLUXSEG6EI64_V_M1_MF8_MASK,
20028 0 : 6186 => Opcode::PseudoVLUXSEG6EI64_V_M2_M1,
20029 0 : 6187 => Opcode::PseudoVLUXSEG6EI64_V_M2_M1_MASK,
20030 0 : 6188 => Opcode::PseudoVLUXSEG6EI64_V_M2_MF2,
20031 0 : 6189 => Opcode::PseudoVLUXSEG6EI64_V_M2_MF2_MASK,
20032 0 : 6190 => Opcode::PseudoVLUXSEG6EI64_V_M2_MF4,
20033 0 : 6191 => Opcode::PseudoVLUXSEG6EI64_V_M2_MF4_MASK,
20034 0 : 6192 => Opcode::PseudoVLUXSEG6EI64_V_M4_M1,
20035 0 : 6193 => Opcode::PseudoVLUXSEG6EI64_V_M4_M1_MASK,
20036 0 : 6194 => Opcode::PseudoVLUXSEG6EI64_V_M4_MF2,
20037 0 : 6195 => Opcode::PseudoVLUXSEG6EI64_V_M4_MF2_MASK,
20038 0 : 6196 => Opcode::PseudoVLUXSEG6EI64_V_M8_M1,
20039 0 : 6197 => Opcode::PseudoVLUXSEG6EI64_V_M8_M1_MASK,
20040 0 : 6198 => Opcode::PseudoVLUXSEG6EI8_V_M1_M1,
20041 0 : 6199 => Opcode::PseudoVLUXSEG6EI8_V_M1_M1_MASK,
20042 0 : 6200 => Opcode::PseudoVLUXSEG6EI8_V_MF2_M1,
20043 0 : 6201 => Opcode::PseudoVLUXSEG6EI8_V_MF2_M1_MASK,
20044 0 : 6202 => Opcode::PseudoVLUXSEG6EI8_V_MF2_MF2,
20045 0 : 6203 => Opcode::PseudoVLUXSEG6EI8_V_MF2_MF2_MASK,
20046 0 : 6204 => Opcode::PseudoVLUXSEG6EI8_V_MF4_M1,
20047 0 : 6205 => Opcode::PseudoVLUXSEG6EI8_V_MF4_M1_MASK,
20048 0 : 6206 => Opcode::PseudoVLUXSEG6EI8_V_MF4_MF2,
20049 0 : 6207 => Opcode::PseudoVLUXSEG6EI8_V_MF4_MF2_MASK,
20050 0 : 6208 => Opcode::PseudoVLUXSEG6EI8_V_MF4_MF4,
20051 0 : 6209 => Opcode::PseudoVLUXSEG6EI8_V_MF4_MF4_MASK,
20052 0 : 6210 => Opcode::PseudoVLUXSEG6EI8_V_MF8_M1,
20053 0 : 6211 => Opcode::PseudoVLUXSEG6EI8_V_MF8_M1_MASK,
20054 0 : 6212 => Opcode::PseudoVLUXSEG6EI8_V_MF8_MF2,
20055 0 : 6213 => Opcode::PseudoVLUXSEG6EI8_V_MF8_MF2_MASK,
20056 0 : 6214 => Opcode::PseudoVLUXSEG6EI8_V_MF8_MF4,
20057 0 : 6215 => Opcode::PseudoVLUXSEG6EI8_V_MF8_MF4_MASK,
20058 0 : 6216 => Opcode::PseudoVLUXSEG6EI8_V_MF8_MF8,
20059 0 : 6217 => Opcode::PseudoVLUXSEG6EI8_V_MF8_MF8_MASK,
20060 0 : 6218 => Opcode::PseudoVLUXSEG7EI16_V_M1_M1,
20061 0 : 6219 => Opcode::PseudoVLUXSEG7EI16_V_M1_M1_MASK,
20062 0 : 6220 => Opcode::PseudoVLUXSEG7EI16_V_M1_MF2,
20063 0 : 6221 => Opcode::PseudoVLUXSEG7EI16_V_M1_MF2_MASK,
20064 0 : 6222 => Opcode::PseudoVLUXSEG7EI16_V_M2_M1,
20065 0 : 6223 => Opcode::PseudoVLUXSEG7EI16_V_M2_M1_MASK,
20066 0 : 6224 => Opcode::PseudoVLUXSEG7EI16_V_MF2_M1,
20067 0 : 6225 => Opcode::PseudoVLUXSEG7EI16_V_MF2_M1_MASK,
20068 0 : 6226 => Opcode::PseudoVLUXSEG7EI16_V_MF2_MF2,
20069 0 : 6227 => Opcode::PseudoVLUXSEG7EI16_V_MF2_MF2_MASK,
20070 0 : 6228 => Opcode::PseudoVLUXSEG7EI16_V_MF2_MF4,
20071 0 : 6229 => Opcode::PseudoVLUXSEG7EI16_V_MF2_MF4_MASK,
20072 0 : 6230 => Opcode::PseudoVLUXSEG7EI16_V_MF4_M1,
20073 0 : 6231 => Opcode::PseudoVLUXSEG7EI16_V_MF4_M1_MASK,
20074 0 : 6232 => Opcode::PseudoVLUXSEG7EI16_V_MF4_MF2,
20075 0 : 6233 => Opcode::PseudoVLUXSEG7EI16_V_MF4_MF2_MASK,
20076 0 : 6234 => Opcode::PseudoVLUXSEG7EI16_V_MF4_MF4,
20077 0 : 6235 => Opcode::PseudoVLUXSEG7EI16_V_MF4_MF4_MASK,
20078 0 : 6236 => Opcode::PseudoVLUXSEG7EI16_V_MF4_MF8,
20079 0 : 6237 => Opcode::PseudoVLUXSEG7EI16_V_MF4_MF8_MASK,
20080 0 : 6238 => Opcode::PseudoVLUXSEG7EI32_V_M1_M1,
20081 0 : 6239 => Opcode::PseudoVLUXSEG7EI32_V_M1_M1_MASK,
20082 0 : 6240 => Opcode::PseudoVLUXSEG7EI32_V_M1_MF2,
20083 0 : 6241 => Opcode::PseudoVLUXSEG7EI32_V_M1_MF2_MASK,
20084 0 : 6242 => Opcode::PseudoVLUXSEG7EI32_V_M1_MF4,
20085 0 : 6243 => Opcode::PseudoVLUXSEG7EI32_V_M1_MF4_MASK,
20086 0 : 6244 => Opcode::PseudoVLUXSEG7EI32_V_M2_M1,
20087 0 : 6245 => Opcode::PseudoVLUXSEG7EI32_V_M2_M1_MASK,
20088 0 : 6246 => Opcode::PseudoVLUXSEG7EI32_V_M2_MF2,
20089 0 : 6247 => Opcode::PseudoVLUXSEG7EI32_V_M2_MF2_MASK,
20090 0 : 6248 => Opcode::PseudoVLUXSEG7EI32_V_M4_M1,
20091 0 : 6249 => Opcode::PseudoVLUXSEG7EI32_V_M4_M1_MASK,
20092 0 : 6250 => Opcode::PseudoVLUXSEG7EI32_V_MF2_M1,
20093 0 : 6251 => Opcode::PseudoVLUXSEG7EI32_V_MF2_M1_MASK,
20094 0 : 6252 => Opcode::PseudoVLUXSEG7EI32_V_MF2_MF2,
20095 0 : 6253 => Opcode::PseudoVLUXSEG7EI32_V_MF2_MF2_MASK,
20096 0 : 6254 => Opcode::PseudoVLUXSEG7EI32_V_MF2_MF4,
20097 0 : 6255 => Opcode::PseudoVLUXSEG7EI32_V_MF2_MF4_MASK,
20098 0 : 6256 => Opcode::PseudoVLUXSEG7EI32_V_MF2_MF8,
20099 0 : 6257 => Opcode::PseudoVLUXSEG7EI32_V_MF2_MF8_MASK,
20100 0 : 6258 => Opcode::PseudoVLUXSEG7EI64_V_M1_M1,
20101 0 : 6259 => Opcode::PseudoVLUXSEG7EI64_V_M1_M1_MASK,
20102 0 : 6260 => Opcode::PseudoVLUXSEG7EI64_V_M1_MF2,
20103 0 : 6261 => Opcode::PseudoVLUXSEG7EI64_V_M1_MF2_MASK,
20104 0 : 6262 => Opcode::PseudoVLUXSEG7EI64_V_M1_MF4,
20105 0 : 6263 => Opcode::PseudoVLUXSEG7EI64_V_M1_MF4_MASK,
20106 0 : 6264 => Opcode::PseudoVLUXSEG7EI64_V_M1_MF8,
20107 0 : 6265 => Opcode::PseudoVLUXSEG7EI64_V_M1_MF8_MASK,
20108 0 : 6266 => Opcode::PseudoVLUXSEG7EI64_V_M2_M1,
20109 0 : 6267 => Opcode::PseudoVLUXSEG7EI64_V_M2_M1_MASK,
20110 0 : 6268 => Opcode::PseudoVLUXSEG7EI64_V_M2_MF2,
20111 0 : 6269 => Opcode::PseudoVLUXSEG7EI64_V_M2_MF2_MASK,
20112 0 : 6270 => Opcode::PseudoVLUXSEG7EI64_V_M2_MF4,
20113 0 : 6271 => Opcode::PseudoVLUXSEG7EI64_V_M2_MF4_MASK,
20114 0 : 6272 => Opcode::PseudoVLUXSEG7EI64_V_M4_M1,
20115 0 : 6273 => Opcode::PseudoVLUXSEG7EI64_V_M4_M1_MASK,
20116 0 : 6274 => Opcode::PseudoVLUXSEG7EI64_V_M4_MF2,
20117 0 : 6275 => Opcode::PseudoVLUXSEG7EI64_V_M4_MF2_MASK,
20118 0 : 6276 => Opcode::PseudoVLUXSEG7EI64_V_M8_M1,
20119 0 : 6277 => Opcode::PseudoVLUXSEG7EI64_V_M8_M1_MASK,
20120 0 : 6278 => Opcode::PseudoVLUXSEG7EI8_V_M1_M1,
20121 0 : 6279 => Opcode::PseudoVLUXSEG7EI8_V_M1_M1_MASK,
20122 0 : 6280 => Opcode::PseudoVLUXSEG7EI8_V_MF2_M1,
20123 0 : 6281 => Opcode::PseudoVLUXSEG7EI8_V_MF2_M1_MASK,
20124 0 : 6282 => Opcode::PseudoVLUXSEG7EI8_V_MF2_MF2,
20125 0 : 6283 => Opcode::PseudoVLUXSEG7EI8_V_MF2_MF2_MASK,
20126 0 : 6284 => Opcode::PseudoVLUXSEG7EI8_V_MF4_M1,
20127 0 : 6285 => Opcode::PseudoVLUXSEG7EI8_V_MF4_M1_MASK,
20128 0 : 6286 => Opcode::PseudoVLUXSEG7EI8_V_MF4_MF2,
20129 0 : 6287 => Opcode::PseudoVLUXSEG7EI8_V_MF4_MF2_MASK,
20130 0 : 6288 => Opcode::PseudoVLUXSEG7EI8_V_MF4_MF4,
20131 0 : 6289 => Opcode::PseudoVLUXSEG7EI8_V_MF4_MF4_MASK,
20132 0 : 6290 => Opcode::PseudoVLUXSEG7EI8_V_MF8_M1,
20133 0 : 6291 => Opcode::PseudoVLUXSEG7EI8_V_MF8_M1_MASK,
20134 0 : 6292 => Opcode::PseudoVLUXSEG7EI8_V_MF8_MF2,
20135 0 : 6293 => Opcode::PseudoVLUXSEG7EI8_V_MF8_MF2_MASK,
20136 0 : 6294 => Opcode::PseudoVLUXSEG7EI8_V_MF8_MF4,
20137 0 : 6295 => Opcode::PseudoVLUXSEG7EI8_V_MF8_MF4_MASK,
20138 0 : 6296 => Opcode::PseudoVLUXSEG7EI8_V_MF8_MF8,
20139 0 : 6297 => Opcode::PseudoVLUXSEG7EI8_V_MF8_MF8_MASK,
20140 0 : 6298 => Opcode::PseudoVLUXSEG8EI16_V_M1_M1,
20141 0 : 6299 => Opcode::PseudoVLUXSEG8EI16_V_M1_M1_MASK,
20142 0 : 6300 => Opcode::PseudoVLUXSEG8EI16_V_M1_MF2,
20143 0 : 6301 => Opcode::PseudoVLUXSEG8EI16_V_M1_MF2_MASK,
20144 0 : 6302 => Opcode::PseudoVLUXSEG8EI16_V_M2_M1,
20145 0 : 6303 => Opcode::PseudoVLUXSEG8EI16_V_M2_M1_MASK,
20146 0 : 6304 => Opcode::PseudoVLUXSEG8EI16_V_MF2_M1,
20147 0 : 6305 => Opcode::PseudoVLUXSEG8EI16_V_MF2_M1_MASK,
20148 0 : 6306 => Opcode::PseudoVLUXSEG8EI16_V_MF2_MF2,
20149 0 : 6307 => Opcode::PseudoVLUXSEG8EI16_V_MF2_MF2_MASK,
20150 0 : 6308 => Opcode::PseudoVLUXSEG8EI16_V_MF2_MF4,
20151 0 : 6309 => Opcode::PseudoVLUXSEG8EI16_V_MF2_MF4_MASK,
20152 0 : 6310 => Opcode::PseudoVLUXSEG8EI16_V_MF4_M1,
20153 0 : 6311 => Opcode::PseudoVLUXSEG8EI16_V_MF4_M1_MASK,
20154 0 : 6312 => Opcode::PseudoVLUXSEG8EI16_V_MF4_MF2,
20155 0 : 6313 => Opcode::PseudoVLUXSEG8EI16_V_MF4_MF2_MASK,
20156 0 : 6314 => Opcode::PseudoVLUXSEG8EI16_V_MF4_MF4,
20157 0 : 6315 => Opcode::PseudoVLUXSEG8EI16_V_MF4_MF4_MASK,
20158 0 : 6316 => Opcode::PseudoVLUXSEG8EI16_V_MF4_MF8,
20159 0 : 6317 => Opcode::PseudoVLUXSEG8EI16_V_MF4_MF8_MASK,
20160 0 : 6318 => Opcode::PseudoVLUXSEG8EI32_V_M1_M1,
20161 0 : 6319 => Opcode::PseudoVLUXSEG8EI32_V_M1_M1_MASK,
20162 0 : 6320 => Opcode::PseudoVLUXSEG8EI32_V_M1_MF2,
20163 0 : 6321 => Opcode::PseudoVLUXSEG8EI32_V_M1_MF2_MASK,
20164 0 : 6322 => Opcode::PseudoVLUXSEG8EI32_V_M1_MF4,
20165 0 : 6323 => Opcode::PseudoVLUXSEG8EI32_V_M1_MF4_MASK,
20166 0 : 6324 => Opcode::PseudoVLUXSEG8EI32_V_M2_M1,
20167 0 : 6325 => Opcode::PseudoVLUXSEG8EI32_V_M2_M1_MASK,
20168 0 : 6326 => Opcode::PseudoVLUXSEG8EI32_V_M2_MF2,
20169 0 : 6327 => Opcode::PseudoVLUXSEG8EI32_V_M2_MF2_MASK,
20170 0 : 6328 => Opcode::PseudoVLUXSEG8EI32_V_M4_M1,
20171 0 : 6329 => Opcode::PseudoVLUXSEG8EI32_V_M4_M1_MASK,
20172 0 : 6330 => Opcode::PseudoVLUXSEG8EI32_V_MF2_M1,
20173 0 : 6331 => Opcode::PseudoVLUXSEG8EI32_V_MF2_M1_MASK,
20174 0 : 6332 => Opcode::PseudoVLUXSEG8EI32_V_MF2_MF2,
20175 0 : 6333 => Opcode::PseudoVLUXSEG8EI32_V_MF2_MF2_MASK,
20176 0 : 6334 => Opcode::PseudoVLUXSEG8EI32_V_MF2_MF4,
20177 0 : 6335 => Opcode::PseudoVLUXSEG8EI32_V_MF2_MF4_MASK,
20178 0 : 6336 => Opcode::PseudoVLUXSEG8EI32_V_MF2_MF8,
20179 0 : 6337 => Opcode::PseudoVLUXSEG8EI32_V_MF2_MF8_MASK,
20180 0 : 6338 => Opcode::PseudoVLUXSEG8EI64_V_M1_M1,
20181 0 : 6339 => Opcode::PseudoVLUXSEG8EI64_V_M1_M1_MASK,
20182 0 : 6340 => Opcode::PseudoVLUXSEG8EI64_V_M1_MF2,
20183 0 : 6341 => Opcode::PseudoVLUXSEG8EI64_V_M1_MF2_MASK,
20184 0 : 6342 => Opcode::PseudoVLUXSEG8EI64_V_M1_MF4,
20185 0 : 6343 => Opcode::PseudoVLUXSEG8EI64_V_M1_MF4_MASK,
20186 0 : 6344 => Opcode::PseudoVLUXSEG8EI64_V_M1_MF8,
20187 0 : 6345 => Opcode::PseudoVLUXSEG8EI64_V_M1_MF8_MASK,
20188 0 : 6346 => Opcode::PseudoVLUXSEG8EI64_V_M2_M1,
20189 0 : 6347 => Opcode::PseudoVLUXSEG8EI64_V_M2_M1_MASK,
20190 0 : 6348 => Opcode::PseudoVLUXSEG8EI64_V_M2_MF2,
20191 0 : 6349 => Opcode::PseudoVLUXSEG8EI64_V_M2_MF2_MASK,
20192 0 : 6350 => Opcode::PseudoVLUXSEG8EI64_V_M2_MF4,
20193 0 : 6351 => Opcode::PseudoVLUXSEG8EI64_V_M2_MF4_MASK,
20194 0 : 6352 => Opcode::PseudoVLUXSEG8EI64_V_M4_M1,
20195 0 : 6353 => Opcode::PseudoVLUXSEG8EI64_V_M4_M1_MASK,
20196 0 : 6354 => Opcode::PseudoVLUXSEG8EI64_V_M4_MF2,
20197 0 : 6355 => Opcode::PseudoVLUXSEG8EI64_V_M4_MF2_MASK,
20198 0 : 6356 => Opcode::PseudoVLUXSEG8EI64_V_M8_M1,
20199 0 : 6357 => Opcode::PseudoVLUXSEG8EI64_V_M8_M1_MASK,
20200 0 : 6358 => Opcode::PseudoVLUXSEG8EI8_V_M1_M1,
20201 0 : 6359 => Opcode::PseudoVLUXSEG8EI8_V_M1_M1_MASK,
20202 0 : 6360 => Opcode::PseudoVLUXSEG8EI8_V_MF2_M1,
20203 0 : 6361 => Opcode::PseudoVLUXSEG8EI8_V_MF2_M1_MASK,
20204 0 : 6362 => Opcode::PseudoVLUXSEG8EI8_V_MF2_MF2,
20205 0 : 6363 => Opcode::PseudoVLUXSEG8EI8_V_MF2_MF2_MASK,
20206 0 : 6364 => Opcode::PseudoVLUXSEG8EI8_V_MF4_M1,
20207 0 : 6365 => Opcode::PseudoVLUXSEG8EI8_V_MF4_M1_MASK,
20208 0 : 6366 => Opcode::PseudoVLUXSEG8EI8_V_MF4_MF2,
20209 0 : 6367 => Opcode::PseudoVLUXSEG8EI8_V_MF4_MF2_MASK,
20210 0 : 6368 => Opcode::PseudoVLUXSEG8EI8_V_MF4_MF4,
20211 0 : 6369 => Opcode::PseudoVLUXSEG8EI8_V_MF4_MF4_MASK,
20212 0 : 6370 => Opcode::PseudoVLUXSEG8EI8_V_MF8_M1,
20213 0 : 6371 => Opcode::PseudoVLUXSEG8EI8_V_MF8_M1_MASK,
20214 0 : 6372 => Opcode::PseudoVLUXSEG8EI8_V_MF8_MF2,
20215 0 : 6373 => Opcode::PseudoVLUXSEG8EI8_V_MF8_MF2_MASK,
20216 0 : 6374 => Opcode::PseudoVLUXSEG8EI8_V_MF8_MF4,
20217 0 : 6375 => Opcode::PseudoVLUXSEG8EI8_V_MF8_MF4_MASK,
20218 0 : 6376 => Opcode::PseudoVLUXSEG8EI8_V_MF8_MF8,
20219 0 : 6377 => Opcode::PseudoVLUXSEG8EI8_V_MF8_MF8_MASK,
20220 0 : 6378 => Opcode::PseudoVMACC_VV_M1,
20221 0 : 6379 => Opcode::PseudoVMACC_VV_M1_MASK,
20222 0 : 6380 => Opcode::PseudoVMACC_VV_M2,
20223 0 : 6381 => Opcode::PseudoVMACC_VV_M2_MASK,
20224 0 : 6382 => Opcode::PseudoVMACC_VV_M4,
20225 0 : 6383 => Opcode::PseudoVMACC_VV_M4_MASK,
20226 0 : 6384 => Opcode::PseudoVMACC_VV_M8,
20227 0 : 6385 => Opcode::PseudoVMACC_VV_M8_MASK,
20228 0 : 6386 => Opcode::PseudoVMACC_VV_MF2,
20229 0 : 6387 => Opcode::PseudoVMACC_VV_MF2_MASK,
20230 0 : 6388 => Opcode::PseudoVMACC_VV_MF4,
20231 0 : 6389 => Opcode::PseudoVMACC_VV_MF4_MASK,
20232 0 : 6390 => Opcode::PseudoVMACC_VV_MF8,
20233 0 : 6391 => Opcode::PseudoVMACC_VV_MF8_MASK,
20234 0 : 6392 => Opcode::PseudoVMACC_VX_M1,
20235 0 : 6393 => Opcode::PseudoVMACC_VX_M1_MASK,
20236 0 : 6394 => Opcode::PseudoVMACC_VX_M2,
20237 0 : 6395 => Opcode::PseudoVMACC_VX_M2_MASK,
20238 0 : 6396 => Opcode::PseudoVMACC_VX_M4,
20239 0 : 6397 => Opcode::PseudoVMACC_VX_M4_MASK,
20240 0 : 6398 => Opcode::PseudoVMACC_VX_M8,
20241 0 : 6399 => Opcode::PseudoVMACC_VX_M8_MASK,
20242 0 : 6400 => Opcode::PseudoVMACC_VX_MF2,
20243 0 : 6401 => Opcode::PseudoVMACC_VX_MF2_MASK,
20244 0 : 6402 => Opcode::PseudoVMACC_VX_MF4,
20245 0 : 6403 => Opcode::PseudoVMACC_VX_MF4_MASK,
20246 0 : 6404 => Opcode::PseudoVMACC_VX_MF8,
20247 0 : 6405 => Opcode::PseudoVMACC_VX_MF8_MASK,
20248 0 : 6406 => Opcode::PseudoVMADC_VIM_M1,
20249 0 : 6407 => Opcode::PseudoVMADC_VIM_M2,
20250 0 : 6408 => Opcode::PseudoVMADC_VIM_M4,
20251 0 : 6409 => Opcode::PseudoVMADC_VIM_M8,
20252 0 : 6410 => Opcode::PseudoVMADC_VIM_MF2,
20253 0 : 6411 => Opcode::PseudoVMADC_VIM_MF4,
20254 0 : 6412 => Opcode::PseudoVMADC_VIM_MF8,
20255 0 : 6413 => Opcode::PseudoVMADC_VI_M1,
20256 0 : 6414 => Opcode::PseudoVMADC_VI_M2,
20257 0 : 6415 => Opcode::PseudoVMADC_VI_M4,
20258 0 : 6416 => Opcode::PseudoVMADC_VI_M8,
20259 0 : 6417 => Opcode::PseudoVMADC_VI_MF2,
20260 0 : 6418 => Opcode::PseudoVMADC_VI_MF4,
20261 0 : 6419 => Opcode::PseudoVMADC_VI_MF8,
20262 0 : 6420 => Opcode::PseudoVMADC_VVM_M1,
20263 0 : 6421 => Opcode::PseudoVMADC_VVM_M2,
20264 0 : 6422 => Opcode::PseudoVMADC_VVM_M4,
20265 0 : 6423 => Opcode::PseudoVMADC_VVM_M8,
20266 0 : 6424 => Opcode::PseudoVMADC_VVM_MF2,
20267 0 : 6425 => Opcode::PseudoVMADC_VVM_MF4,
20268 0 : 6426 => Opcode::PseudoVMADC_VVM_MF8,
20269 0 : 6427 => Opcode::PseudoVMADC_VV_M1,
20270 0 : 6428 => Opcode::PseudoVMADC_VV_M2,
20271 0 : 6429 => Opcode::PseudoVMADC_VV_M4,
20272 0 : 6430 => Opcode::PseudoVMADC_VV_M8,
20273 0 : 6431 => Opcode::PseudoVMADC_VV_MF2,
20274 0 : 6432 => Opcode::PseudoVMADC_VV_MF4,
20275 0 : 6433 => Opcode::PseudoVMADC_VV_MF8,
20276 0 : 6434 => Opcode::PseudoVMADC_VXM_M1,
20277 0 : 6435 => Opcode::PseudoVMADC_VXM_M2,
20278 0 : 6436 => Opcode::PseudoVMADC_VXM_M4,
20279 0 : 6437 => Opcode::PseudoVMADC_VXM_M8,
20280 0 : 6438 => Opcode::PseudoVMADC_VXM_MF2,
20281 0 : 6439 => Opcode::PseudoVMADC_VXM_MF4,
20282 0 : 6440 => Opcode::PseudoVMADC_VXM_MF8,
20283 0 : 6441 => Opcode::PseudoVMADC_VX_M1,
20284 0 : 6442 => Opcode::PseudoVMADC_VX_M2,
20285 0 : 6443 => Opcode::PseudoVMADC_VX_M4,
20286 0 : 6444 => Opcode::PseudoVMADC_VX_M8,
20287 0 : 6445 => Opcode::PseudoVMADC_VX_MF2,
20288 0 : 6446 => Opcode::PseudoVMADC_VX_MF4,
20289 0 : 6447 => Opcode::PseudoVMADC_VX_MF8,
20290 0 : 6448 => Opcode::PseudoVMADD_VV_M1,
20291 0 : 6449 => Opcode::PseudoVMADD_VV_M1_MASK,
20292 0 : 6450 => Opcode::PseudoVMADD_VV_M2,
20293 0 : 6451 => Opcode::PseudoVMADD_VV_M2_MASK,
20294 0 : 6452 => Opcode::PseudoVMADD_VV_M4,
20295 0 : 6453 => Opcode::PseudoVMADD_VV_M4_MASK,
20296 0 : 6454 => Opcode::PseudoVMADD_VV_M8,
20297 0 : 6455 => Opcode::PseudoVMADD_VV_M8_MASK,
20298 0 : 6456 => Opcode::PseudoVMADD_VV_MF2,
20299 0 : 6457 => Opcode::PseudoVMADD_VV_MF2_MASK,
20300 0 : 6458 => Opcode::PseudoVMADD_VV_MF4,
20301 0 : 6459 => Opcode::PseudoVMADD_VV_MF4_MASK,
20302 0 : 6460 => Opcode::PseudoVMADD_VV_MF8,
20303 0 : 6461 => Opcode::PseudoVMADD_VV_MF8_MASK,
20304 0 : 6462 => Opcode::PseudoVMADD_VX_M1,
20305 0 : 6463 => Opcode::PseudoVMADD_VX_M1_MASK,
20306 0 : 6464 => Opcode::PseudoVMADD_VX_M2,
20307 0 : 6465 => Opcode::PseudoVMADD_VX_M2_MASK,
20308 0 : 6466 => Opcode::PseudoVMADD_VX_M4,
20309 0 : 6467 => Opcode::PseudoVMADD_VX_M4_MASK,
20310 0 : 6468 => Opcode::PseudoVMADD_VX_M8,
20311 0 : 6469 => Opcode::PseudoVMADD_VX_M8_MASK,
20312 0 : 6470 => Opcode::PseudoVMADD_VX_MF2,
20313 0 : 6471 => Opcode::PseudoVMADD_VX_MF2_MASK,
20314 0 : 6472 => Opcode::PseudoVMADD_VX_MF4,
20315 0 : 6473 => Opcode::PseudoVMADD_VX_MF4_MASK,
20316 0 : 6474 => Opcode::PseudoVMADD_VX_MF8,
20317 0 : 6475 => Opcode::PseudoVMADD_VX_MF8_MASK,
20318 0 : 6476 => Opcode::PseudoVMANDN_MM_M1,
20319 0 : 6477 => Opcode::PseudoVMANDN_MM_M2,
20320 0 : 6478 => Opcode::PseudoVMANDN_MM_M4,
20321 0 : 6479 => Opcode::PseudoVMANDN_MM_M8,
20322 0 : 6480 => Opcode::PseudoVMANDN_MM_MF2,
20323 0 : 6481 => Opcode::PseudoVMANDN_MM_MF4,
20324 0 : 6482 => Opcode::PseudoVMANDN_MM_MF8,
20325 0 : 6483 => Opcode::PseudoVMAND_MM_M1,
20326 0 : 6484 => Opcode::PseudoVMAND_MM_M2,
20327 0 : 6485 => Opcode::PseudoVMAND_MM_M4,
20328 0 : 6486 => Opcode::PseudoVMAND_MM_M8,
20329 0 : 6487 => Opcode::PseudoVMAND_MM_MF2,
20330 0 : 6488 => Opcode::PseudoVMAND_MM_MF4,
20331 0 : 6489 => Opcode::PseudoVMAND_MM_MF8,
20332 0 : 6490 => Opcode::PseudoVMAXU_VV_M1,
20333 0 : 6491 => Opcode::PseudoVMAXU_VV_M1_MASK,
20334 0 : 6492 => Opcode::PseudoVMAXU_VV_M2,
20335 0 : 6493 => Opcode::PseudoVMAXU_VV_M2_MASK,
20336 0 : 6494 => Opcode::PseudoVMAXU_VV_M4,
20337 0 : 6495 => Opcode::PseudoVMAXU_VV_M4_MASK,
20338 0 : 6496 => Opcode::PseudoVMAXU_VV_M8,
20339 0 : 6497 => Opcode::PseudoVMAXU_VV_M8_MASK,
20340 0 : 6498 => Opcode::PseudoVMAXU_VV_MF2,
20341 0 : 6499 => Opcode::PseudoVMAXU_VV_MF2_MASK,
20342 0 : 6500 => Opcode::PseudoVMAXU_VV_MF4,
20343 0 : 6501 => Opcode::PseudoVMAXU_VV_MF4_MASK,
20344 0 : 6502 => Opcode::PseudoVMAXU_VV_MF8,
20345 0 : 6503 => Opcode::PseudoVMAXU_VV_MF8_MASK,
20346 0 : 6504 => Opcode::PseudoVMAXU_VX_M1,
20347 0 : 6505 => Opcode::PseudoVMAXU_VX_M1_MASK,
20348 0 : 6506 => Opcode::PseudoVMAXU_VX_M2,
20349 0 : 6507 => Opcode::PseudoVMAXU_VX_M2_MASK,
20350 0 : 6508 => Opcode::PseudoVMAXU_VX_M4,
20351 0 : 6509 => Opcode::PseudoVMAXU_VX_M4_MASK,
20352 0 : 6510 => Opcode::PseudoVMAXU_VX_M8,
20353 0 : 6511 => Opcode::PseudoVMAXU_VX_M8_MASK,
20354 0 : 6512 => Opcode::PseudoVMAXU_VX_MF2,
20355 0 : 6513 => Opcode::PseudoVMAXU_VX_MF2_MASK,
20356 0 : 6514 => Opcode::PseudoVMAXU_VX_MF4,
20357 0 : 6515 => Opcode::PseudoVMAXU_VX_MF4_MASK,
20358 0 : 6516 => Opcode::PseudoVMAXU_VX_MF8,
20359 0 : 6517 => Opcode::PseudoVMAXU_VX_MF8_MASK,
20360 0 : 6518 => Opcode::PseudoVMAX_VV_M1,
20361 0 : 6519 => Opcode::PseudoVMAX_VV_M1_MASK,
20362 0 : 6520 => Opcode::PseudoVMAX_VV_M2,
20363 0 : 6521 => Opcode::PseudoVMAX_VV_M2_MASK,
20364 0 : 6522 => Opcode::PseudoVMAX_VV_M4,
20365 0 : 6523 => Opcode::PseudoVMAX_VV_M4_MASK,
20366 0 : 6524 => Opcode::PseudoVMAX_VV_M8,
20367 0 : 6525 => Opcode::PseudoVMAX_VV_M8_MASK,
20368 0 : 6526 => Opcode::PseudoVMAX_VV_MF2,
20369 0 : 6527 => Opcode::PseudoVMAX_VV_MF2_MASK,
20370 0 : 6528 => Opcode::PseudoVMAX_VV_MF4,
20371 0 : 6529 => Opcode::PseudoVMAX_VV_MF4_MASK,
20372 0 : 6530 => Opcode::PseudoVMAX_VV_MF8,
20373 0 : 6531 => Opcode::PseudoVMAX_VV_MF8_MASK,
20374 0 : 6532 => Opcode::PseudoVMAX_VX_M1,
20375 0 : 6533 => Opcode::PseudoVMAX_VX_M1_MASK,
20376 0 : 6534 => Opcode::PseudoVMAX_VX_M2,
20377 0 : 6535 => Opcode::PseudoVMAX_VX_M2_MASK,
20378 0 : 6536 => Opcode::PseudoVMAX_VX_M4,
20379 0 : 6537 => Opcode::PseudoVMAX_VX_M4_MASK,
20380 0 : 6538 => Opcode::PseudoVMAX_VX_M8,
20381 0 : 6539 => Opcode::PseudoVMAX_VX_M8_MASK,
20382 0 : 6540 => Opcode::PseudoVMAX_VX_MF2,
20383 0 : 6541 => Opcode::PseudoVMAX_VX_MF2_MASK,
20384 0 : 6542 => Opcode::PseudoVMAX_VX_MF4,
20385 0 : 6543 => Opcode::PseudoVMAX_VX_MF4_MASK,
20386 0 : 6544 => Opcode::PseudoVMAX_VX_MF8,
20387 0 : 6545 => Opcode::PseudoVMAX_VX_MF8_MASK,
20388 0 : 6546 => Opcode::PseudoVMCLR_M_B1,
20389 0 : 6547 => Opcode::PseudoVMCLR_M_B16,
20390 0 : 6548 => Opcode::PseudoVMCLR_M_B2,
20391 0 : 6549 => Opcode::PseudoVMCLR_M_B32,
20392 0 : 6550 => Opcode::PseudoVMCLR_M_B4,
20393 0 : 6551 => Opcode::PseudoVMCLR_M_B64,
20394 0 : 6552 => Opcode::PseudoVMCLR_M_B8,
20395 0 : 6553 => Opcode::PseudoVMERGE_VIM_M1,
20396 0 : 6554 => Opcode::PseudoVMERGE_VIM_M2,
20397 0 : 6555 => Opcode::PseudoVMERGE_VIM_M4,
20398 0 : 6556 => Opcode::PseudoVMERGE_VIM_M8,
20399 0 : 6557 => Opcode::PseudoVMERGE_VIM_MF2,
20400 0 : 6558 => Opcode::PseudoVMERGE_VIM_MF4,
20401 0 : 6559 => Opcode::PseudoVMERGE_VIM_MF8,
20402 0 : 6560 => Opcode::PseudoVMERGE_VVM_M1,
20403 0 : 6561 => Opcode::PseudoVMERGE_VVM_M2,
20404 0 : 6562 => Opcode::PseudoVMERGE_VVM_M4,
20405 0 : 6563 => Opcode::PseudoVMERGE_VVM_M8,
20406 0 : 6564 => Opcode::PseudoVMERGE_VVM_MF2,
20407 0 : 6565 => Opcode::PseudoVMERGE_VVM_MF4,
20408 0 : 6566 => Opcode::PseudoVMERGE_VVM_MF8,
20409 0 : 6567 => Opcode::PseudoVMERGE_VXM_M1,
20410 0 : 6568 => Opcode::PseudoVMERGE_VXM_M2,
20411 0 : 6569 => Opcode::PseudoVMERGE_VXM_M4,
20412 0 : 6570 => Opcode::PseudoVMERGE_VXM_M8,
20413 0 : 6571 => Opcode::PseudoVMERGE_VXM_MF2,
20414 0 : 6572 => Opcode::PseudoVMERGE_VXM_MF4,
20415 0 : 6573 => Opcode::PseudoVMERGE_VXM_MF8,
20416 0 : 6574 => Opcode::PseudoVMFEQ_VFPR16_M1,
20417 0 : 6575 => Opcode::PseudoVMFEQ_VFPR16_M1_MASK,
20418 0 : 6576 => Opcode::PseudoVMFEQ_VFPR16_M2,
20419 0 : 6577 => Opcode::PseudoVMFEQ_VFPR16_M2_MASK,
20420 0 : 6578 => Opcode::PseudoVMFEQ_VFPR16_M4,
20421 0 : 6579 => Opcode::PseudoVMFEQ_VFPR16_M4_MASK,
20422 0 : 6580 => Opcode::PseudoVMFEQ_VFPR16_M8,
20423 0 : 6581 => Opcode::PseudoVMFEQ_VFPR16_M8_MASK,
20424 0 : 6582 => Opcode::PseudoVMFEQ_VFPR16_MF2,
20425 0 : 6583 => Opcode::PseudoVMFEQ_VFPR16_MF2_MASK,
20426 0 : 6584 => Opcode::PseudoVMFEQ_VFPR16_MF4,
20427 0 : 6585 => Opcode::PseudoVMFEQ_VFPR16_MF4_MASK,
20428 0 : 6586 => Opcode::PseudoVMFEQ_VFPR32_M1,
20429 0 : 6587 => Opcode::PseudoVMFEQ_VFPR32_M1_MASK,
20430 0 : 6588 => Opcode::PseudoVMFEQ_VFPR32_M2,
20431 0 : 6589 => Opcode::PseudoVMFEQ_VFPR32_M2_MASK,
20432 0 : 6590 => Opcode::PseudoVMFEQ_VFPR32_M4,
20433 0 : 6591 => Opcode::PseudoVMFEQ_VFPR32_M4_MASK,
20434 0 : 6592 => Opcode::PseudoVMFEQ_VFPR32_M8,
20435 0 : 6593 => Opcode::PseudoVMFEQ_VFPR32_M8_MASK,
20436 0 : 6594 => Opcode::PseudoVMFEQ_VFPR32_MF2,
20437 0 : 6595 => Opcode::PseudoVMFEQ_VFPR32_MF2_MASK,
20438 0 : 6596 => Opcode::PseudoVMFEQ_VFPR64_M1,
20439 0 : 6597 => Opcode::PseudoVMFEQ_VFPR64_M1_MASK,
20440 0 : 6598 => Opcode::PseudoVMFEQ_VFPR64_M2,
20441 0 : 6599 => Opcode::PseudoVMFEQ_VFPR64_M2_MASK,
20442 0 : 6600 => Opcode::PseudoVMFEQ_VFPR64_M4,
20443 0 : 6601 => Opcode::PseudoVMFEQ_VFPR64_M4_MASK,
20444 0 : 6602 => Opcode::PseudoVMFEQ_VFPR64_M8,
20445 0 : 6603 => Opcode::PseudoVMFEQ_VFPR64_M8_MASK,
20446 0 : 6604 => Opcode::PseudoVMFEQ_VV_M1,
20447 0 : 6605 => Opcode::PseudoVMFEQ_VV_M1_MASK,
20448 0 : 6606 => Opcode::PseudoVMFEQ_VV_M2,
20449 0 : 6607 => Opcode::PseudoVMFEQ_VV_M2_MASK,
20450 0 : 6608 => Opcode::PseudoVMFEQ_VV_M4,
20451 0 : 6609 => Opcode::PseudoVMFEQ_VV_M4_MASK,
20452 0 : 6610 => Opcode::PseudoVMFEQ_VV_M8,
20453 0 : 6611 => Opcode::PseudoVMFEQ_VV_M8_MASK,
20454 0 : 6612 => Opcode::PseudoVMFEQ_VV_MF2,
20455 0 : 6613 => Opcode::PseudoVMFEQ_VV_MF2_MASK,
20456 0 : 6614 => Opcode::PseudoVMFEQ_VV_MF4,
20457 0 : 6615 => Opcode::PseudoVMFEQ_VV_MF4_MASK,
20458 0 : 6616 => Opcode::PseudoVMFGE_VFPR16_M1,
20459 0 : 6617 => Opcode::PseudoVMFGE_VFPR16_M1_MASK,
20460 0 : 6618 => Opcode::PseudoVMFGE_VFPR16_M2,
20461 0 : 6619 => Opcode::PseudoVMFGE_VFPR16_M2_MASK,
20462 0 : 6620 => Opcode::PseudoVMFGE_VFPR16_M4,
20463 0 : 6621 => Opcode::PseudoVMFGE_VFPR16_M4_MASK,
20464 0 : 6622 => Opcode::PseudoVMFGE_VFPR16_M8,
20465 0 : 6623 => Opcode::PseudoVMFGE_VFPR16_M8_MASK,
20466 0 : 6624 => Opcode::PseudoVMFGE_VFPR16_MF2,
20467 0 : 6625 => Opcode::PseudoVMFGE_VFPR16_MF2_MASK,
20468 0 : 6626 => Opcode::PseudoVMFGE_VFPR16_MF4,
20469 0 : 6627 => Opcode::PseudoVMFGE_VFPR16_MF4_MASK,
20470 0 : 6628 => Opcode::PseudoVMFGE_VFPR32_M1,
20471 0 : 6629 => Opcode::PseudoVMFGE_VFPR32_M1_MASK,
20472 0 : 6630 => Opcode::PseudoVMFGE_VFPR32_M2,
20473 0 : 6631 => Opcode::PseudoVMFGE_VFPR32_M2_MASK,
20474 0 : 6632 => Opcode::PseudoVMFGE_VFPR32_M4,
20475 0 : 6633 => Opcode::PseudoVMFGE_VFPR32_M4_MASK,
20476 0 : 6634 => Opcode::PseudoVMFGE_VFPR32_M8,
20477 0 : 6635 => Opcode::PseudoVMFGE_VFPR32_M8_MASK,
20478 0 : 6636 => Opcode::PseudoVMFGE_VFPR32_MF2,
20479 0 : 6637 => Opcode::PseudoVMFGE_VFPR32_MF2_MASK,
20480 0 : 6638 => Opcode::PseudoVMFGE_VFPR64_M1,
20481 0 : 6639 => Opcode::PseudoVMFGE_VFPR64_M1_MASK,
20482 0 : 6640 => Opcode::PseudoVMFGE_VFPR64_M2,
20483 0 : 6641 => Opcode::PseudoVMFGE_VFPR64_M2_MASK,
20484 0 : 6642 => Opcode::PseudoVMFGE_VFPR64_M4,
20485 0 : 6643 => Opcode::PseudoVMFGE_VFPR64_M4_MASK,
20486 0 : 6644 => Opcode::PseudoVMFGE_VFPR64_M8,
20487 0 : 6645 => Opcode::PseudoVMFGE_VFPR64_M8_MASK,
20488 0 : 6646 => Opcode::PseudoVMFGT_VFPR16_M1,
20489 0 : 6647 => Opcode::PseudoVMFGT_VFPR16_M1_MASK,
20490 0 : 6648 => Opcode::PseudoVMFGT_VFPR16_M2,
20491 0 : 6649 => Opcode::PseudoVMFGT_VFPR16_M2_MASK,
20492 0 : 6650 => Opcode::PseudoVMFGT_VFPR16_M4,
20493 0 : 6651 => Opcode::PseudoVMFGT_VFPR16_M4_MASK,
20494 0 : 6652 => Opcode::PseudoVMFGT_VFPR16_M8,
20495 0 : 6653 => Opcode::PseudoVMFGT_VFPR16_M8_MASK,
20496 0 : 6654 => Opcode::PseudoVMFGT_VFPR16_MF2,
20497 0 : 6655 => Opcode::PseudoVMFGT_VFPR16_MF2_MASK,
20498 0 : 6656 => Opcode::PseudoVMFGT_VFPR16_MF4,
20499 0 : 6657 => Opcode::PseudoVMFGT_VFPR16_MF4_MASK,
20500 0 : 6658 => Opcode::PseudoVMFGT_VFPR32_M1,
20501 0 : 6659 => Opcode::PseudoVMFGT_VFPR32_M1_MASK,
20502 0 : 6660 => Opcode::PseudoVMFGT_VFPR32_M2,
20503 0 : 6661 => Opcode::PseudoVMFGT_VFPR32_M2_MASK,
20504 0 : 6662 => Opcode::PseudoVMFGT_VFPR32_M4,
20505 0 : 6663 => Opcode::PseudoVMFGT_VFPR32_M4_MASK,
20506 0 : 6664 => Opcode::PseudoVMFGT_VFPR32_M8,
20507 0 : 6665 => Opcode::PseudoVMFGT_VFPR32_M8_MASK,
20508 0 : 6666 => Opcode::PseudoVMFGT_VFPR32_MF2,
20509 0 : 6667 => Opcode::PseudoVMFGT_VFPR32_MF2_MASK,
20510 0 : 6668 => Opcode::PseudoVMFGT_VFPR64_M1,
20511 0 : 6669 => Opcode::PseudoVMFGT_VFPR64_M1_MASK,
20512 0 : 6670 => Opcode::PseudoVMFGT_VFPR64_M2,
20513 0 : 6671 => Opcode::PseudoVMFGT_VFPR64_M2_MASK,
20514 0 : 6672 => Opcode::PseudoVMFGT_VFPR64_M4,
20515 0 : 6673 => Opcode::PseudoVMFGT_VFPR64_M4_MASK,
20516 0 : 6674 => Opcode::PseudoVMFGT_VFPR64_M8,
20517 0 : 6675 => Opcode::PseudoVMFGT_VFPR64_M8_MASK,
20518 0 : 6676 => Opcode::PseudoVMFLE_VFPR16_M1,
20519 0 : 6677 => Opcode::PseudoVMFLE_VFPR16_M1_MASK,
20520 0 : 6678 => Opcode::PseudoVMFLE_VFPR16_M2,
20521 0 : 6679 => Opcode::PseudoVMFLE_VFPR16_M2_MASK,
20522 0 : 6680 => Opcode::PseudoVMFLE_VFPR16_M4,
20523 0 : 6681 => Opcode::PseudoVMFLE_VFPR16_M4_MASK,
20524 0 : 6682 => Opcode::PseudoVMFLE_VFPR16_M8,
20525 0 : 6683 => Opcode::PseudoVMFLE_VFPR16_M8_MASK,
20526 0 : 6684 => Opcode::PseudoVMFLE_VFPR16_MF2,
20527 0 : 6685 => Opcode::PseudoVMFLE_VFPR16_MF2_MASK,
20528 0 : 6686 => Opcode::PseudoVMFLE_VFPR16_MF4,
20529 0 : 6687 => Opcode::PseudoVMFLE_VFPR16_MF4_MASK,
20530 0 : 6688 => Opcode::PseudoVMFLE_VFPR32_M1,
20531 0 : 6689 => Opcode::PseudoVMFLE_VFPR32_M1_MASK,
20532 0 : 6690 => Opcode::PseudoVMFLE_VFPR32_M2,
20533 0 : 6691 => Opcode::PseudoVMFLE_VFPR32_M2_MASK,
20534 0 : 6692 => Opcode::PseudoVMFLE_VFPR32_M4,
20535 0 : 6693 => Opcode::PseudoVMFLE_VFPR32_M4_MASK,
20536 0 : 6694 => Opcode::PseudoVMFLE_VFPR32_M8,
20537 0 : 6695 => Opcode::PseudoVMFLE_VFPR32_M8_MASK,
20538 0 : 6696 => Opcode::PseudoVMFLE_VFPR32_MF2,
20539 0 : 6697 => Opcode::PseudoVMFLE_VFPR32_MF2_MASK,
20540 0 : 6698 => Opcode::PseudoVMFLE_VFPR64_M1,
20541 0 : 6699 => Opcode::PseudoVMFLE_VFPR64_M1_MASK,
20542 0 : 6700 => Opcode::PseudoVMFLE_VFPR64_M2,
20543 0 : 6701 => Opcode::PseudoVMFLE_VFPR64_M2_MASK,
20544 0 : 6702 => Opcode::PseudoVMFLE_VFPR64_M4,
20545 0 : 6703 => Opcode::PseudoVMFLE_VFPR64_M4_MASK,
20546 0 : 6704 => Opcode::PseudoVMFLE_VFPR64_M8,
20547 0 : 6705 => Opcode::PseudoVMFLE_VFPR64_M8_MASK,
20548 0 : 6706 => Opcode::PseudoVMFLE_VV_M1,
20549 0 : 6707 => Opcode::PseudoVMFLE_VV_M1_MASK,
20550 0 : 6708 => Opcode::PseudoVMFLE_VV_M2,
20551 0 : 6709 => Opcode::PseudoVMFLE_VV_M2_MASK,
20552 0 : 6710 => Opcode::PseudoVMFLE_VV_M4,
20553 0 : 6711 => Opcode::PseudoVMFLE_VV_M4_MASK,
20554 0 : 6712 => Opcode::PseudoVMFLE_VV_M8,
20555 0 : 6713 => Opcode::PseudoVMFLE_VV_M8_MASK,
20556 0 : 6714 => Opcode::PseudoVMFLE_VV_MF2,
20557 0 : 6715 => Opcode::PseudoVMFLE_VV_MF2_MASK,
20558 0 : 6716 => Opcode::PseudoVMFLE_VV_MF4,
20559 0 : 6717 => Opcode::PseudoVMFLE_VV_MF4_MASK,
20560 0 : 6718 => Opcode::PseudoVMFLT_VFPR16_M1,
20561 0 : 6719 => Opcode::PseudoVMFLT_VFPR16_M1_MASK,
20562 0 : 6720 => Opcode::PseudoVMFLT_VFPR16_M2,
20563 0 : 6721 => Opcode::PseudoVMFLT_VFPR16_M2_MASK,
20564 0 : 6722 => Opcode::PseudoVMFLT_VFPR16_M4,
20565 0 : 6723 => Opcode::PseudoVMFLT_VFPR16_M4_MASK,
20566 0 : 6724 => Opcode::PseudoVMFLT_VFPR16_M8,
20567 0 : 6725 => Opcode::PseudoVMFLT_VFPR16_M8_MASK,
20568 0 : 6726 => Opcode::PseudoVMFLT_VFPR16_MF2,
20569 0 : 6727 => Opcode::PseudoVMFLT_VFPR16_MF2_MASK,
20570 0 : 6728 => Opcode::PseudoVMFLT_VFPR16_MF4,
20571 0 : 6729 => Opcode::PseudoVMFLT_VFPR16_MF4_MASK,
20572 0 : 6730 => Opcode::PseudoVMFLT_VFPR32_M1,
20573 0 : 6731 => Opcode::PseudoVMFLT_VFPR32_M1_MASK,
20574 0 : 6732 => Opcode::PseudoVMFLT_VFPR32_M2,
20575 0 : 6733 => Opcode::PseudoVMFLT_VFPR32_M2_MASK,
20576 0 : 6734 => Opcode::PseudoVMFLT_VFPR32_M4,
20577 0 : 6735 => Opcode::PseudoVMFLT_VFPR32_M4_MASK,
20578 0 : 6736 => Opcode::PseudoVMFLT_VFPR32_M8,
20579 0 : 6737 => Opcode::PseudoVMFLT_VFPR32_M8_MASK,
20580 0 : 6738 => Opcode::PseudoVMFLT_VFPR32_MF2,
20581 0 : 6739 => Opcode::PseudoVMFLT_VFPR32_MF2_MASK,
20582 0 : 6740 => Opcode::PseudoVMFLT_VFPR64_M1,
20583 0 : 6741 => Opcode::PseudoVMFLT_VFPR64_M1_MASK,
20584 0 : 6742 => Opcode::PseudoVMFLT_VFPR64_M2,
20585 0 : 6743 => Opcode::PseudoVMFLT_VFPR64_M2_MASK,
20586 0 : 6744 => Opcode::PseudoVMFLT_VFPR64_M4,
20587 0 : 6745 => Opcode::PseudoVMFLT_VFPR64_M4_MASK,
20588 0 : 6746 => Opcode::PseudoVMFLT_VFPR64_M8,
20589 0 : 6747 => Opcode::PseudoVMFLT_VFPR64_M8_MASK,
20590 0 : 6748 => Opcode::PseudoVMFLT_VV_M1,
20591 0 : 6749 => Opcode::PseudoVMFLT_VV_M1_MASK,
20592 0 : 6750 => Opcode::PseudoVMFLT_VV_M2,
20593 0 : 6751 => Opcode::PseudoVMFLT_VV_M2_MASK,
20594 0 : 6752 => Opcode::PseudoVMFLT_VV_M4,
20595 0 : 6753 => Opcode::PseudoVMFLT_VV_M4_MASK,
20596 0 : 6754 => Opcode::PseudoVMFLT_VV_M8,
20597 0 : 6755 => Opcode::PseudoVMFLT_VV_M8_MASK,
20598 0 : 6756 => Opcode::PseudoVMFLT_VV_MF2,
20599 0 : 6757 => Opcode::PseudoVMFLT_VV_MF2_MASK,
20600 0 : 6758 => Opcode::PseudoVMFLT_VV_MF4,
20601 0 : 6759 => Opcode::PseudoVMFLT_VV_MF4_MASK,
20602 0 : 6760 => Opcode::PseudoVMFNE_VFPR16_M1,
20603 0 : 6761 => Opcode::PseudoVMFNE_VFPR16_M1_MASK,
20604 0 : 6762 => Opcode::PseudoVMFNE_VFPR16_M2,
20605 0 : 6763 => Opcode::PseudoVMFNE_VFPR16_M2_MASK,
20606 0 : 6764 => Opcode::PseudoVMFNE_VFPR16_M4,
20607 0 : 6765 => Opcode::PseudoVMFNE_VFPR16_M4_MASK,
20608 0 : 6766 => Opcode::PseudoVMFNE_VFPR16_M8,
20609 0 : 6767 => Opcode::PseudoVMFNE_VFPR16_M8_MASK,
20610 0 : 6768 => Opcode::PseudoVMFNE_VFPR16_MF2,
20611 0 : 6769 => Opcode::PseudoVMFNE_VFPR16_MF2_MASK,
20612 0 : 6770 => Opcode::PseudoVMFNE_VFPR16_MF4,
20613 0 : 6771 => Opcode::PseudoVMFNE_VFPR16_MF4_MASK,
20614 0 : 6772 => Opcode::PseudoVMFNE_VFPR32_M1,
20615 0 : 6773 => Opcode::PseudoVMFNE_VFPR32_M1_MASK,
20616 0 : 6774 => Opcode::PseudoVMFNE_VFPR32_M2,
20617 0 : 6775 => Opcode::PseudoVMFNE_VFPR32_M2_MASK,
20618 0 : 6776 => Opcode::PseudoVMFNE_VFPR32_M4,
20619 0 : 6777 => Opcode::PseudoVMFNE_VFPR32_M4_MASK,
20620 0 : 6778 => Opcode::PseudoVMFNE_VFPR32_M8,
20621 0 : 6779 => Opcode::PseudoVMFNE_VFPR32_M8_MASK,
20622 0 : 6780 => Opcode::PseudoVMFNE_VFPR32_MF2,
20623 0 : 6781 => Opcode::PseudoVMFNE_VFPR32_MF2_MASK,
20624 0 : 6782 => Opcode::PseudoVMFNE_VFPR64_M1,
20625 0 : 6783 => Opcode::PseudoVMFNE_VFPR64_M1_MASK,
20626 0 : 6784 => Opcode::PseudoVMFNE_VFPR64_M2,
20627 0 : 6785 => Opcode::PseudoVMFNE_VFPR64_M2_MASK,
20628 0 : 6786 => Opcode::PseudoVMFNE_VFPR64_M4,
20629 0 : 6787 => Opcode::PseudoVMFNE_VFPR64_M4_MASK,
20630 0 : 6788 => Opcode::PseudoVMFNE_VFPR64_M8,
20631 0 : 6789 => Opcode::PseudoVMFNE_VFPR64_M8_MASK,
20632 0 : 6790 => Opcode::PseudoVMFNE_VV_M1,
20633 0 : 6791 => Opcode::PseudoVMFNE_VV_M1_MASK,
20634 0 : 6792 => Opcode::PseudoVMFNE_VV_M2,
20635 0 : 6793 => Opcode::PseudoVMFNE_VV_M2_MASK,
20636 0 : 6794 => Opcode::PseudoVMFNE_VV_M4,
20637 0 : 6795 => Opcode::PseudoVMFNE_VV_M4_MASK,
20638 0 : 6796 => Opcode::PseudoVMFNE_VV_M8,
20639 0 : 6797 => Opcode::PseudoVMFNE_VV_M8_MASK,
20640 0 : 6798 => Opcode::PseudoVMFNE_VV_MF2,
20641 0 : 6799 => Opcode::PseudoVMFNE_VV_MF2_MASK,
20642 0 : 6800 => Opcode::PseudoVMFNE_VV_MF4,
20643 0 : 6801 => Opcode::PseudoVMFNE_VV_MF4_MASK,
20644 0 : 6802 => Opcode::PseudoVMINU_VV_M1,
20645 0 : 6803 => Opcode::PseudoVMINU_VV_M1_MASK,
20646 0 : 6804 => Opcode::PseudoVMINU_VV_M2,
20647 0 : 6805 => Opcode::PseudoVMINU_VV_M2_MASK,
20648 0 : 6806 => Opcode::PseudoVMINU_VV_M4,
20649 0 : 6807 => Opcode::PseudoVMINU_VV_M4_MASK,
20650 0 : 6808 => Opcode::PseudoVMINU_VV_M8,
20651 0 : 6809 => Opcode::PseudoVMINU_VV_M8_MASK,
20652 0 : 6810 => Opcode::PseudoVMINU_VV_MF2,
20653 0 : 6811 => Opcode::PseudoVMINU_VV_MF2_MASK,
20654 0 : 6812 => Opcode::PseudoVMINU_VV_MF4,
20655 0 : 6813 => Opcode::PseudoVMINU_VV_MF4_MASK,
20656 0 : 6814 => Opcode::PseudoVMINU_VV_MF8,
20657 0 : 6815 => Opcode::PseudoVMINU_VV_MF8_MASK,
20658 0 : 6816 => Opcode::PseudoVMINU_VX_M1,
20659 0 : 6817 => Opcode::PseudoVMINU_VX_M1_MASK,
20660 0 : 6818 => Opcode::PseudoVMINU_VX_M2,
20661 0 : 6819 => Opcode::PseudoVMINU_VX_M2_MASK,
20662 0 : 6820 => Opcode::PseudoVMINU_VX_M4,
20663 0 : 6821 => Opcode::PseudoVMINU_VX_M4_MASK,
20664 0 : 6822 => Opcode::PseudoVMINU_VX_M8,
20665 0 : 6823 => Opcode::PseudoVMINU_VX_M8_MASK,
20666 0 : 6824 => Opcode::PseudoVMINU_VX_MF2,
20667 0 : 6825 => Opcode::PseudoVMINU_VX_MF2_MASK,
20668 0 : 6826 => Opcode::PseudoVMINU_VX_MF4,
20669 0 : 6827 => Opcode::PseudoVMINU_VX_MF4_MASK,
20670 0 : 6828 => Opcode::PseudoVMINU_VX_MF8,
20671 0 : 6829 => Opcode::PseudoVMINU_VX_MF8_MASK,
20672 0 : 6830 => Opcode::PseudoVMIN_VV_M1,
20673 0 : 6831 => Opcode::PseudoVMIN_VV_M1_MASK,
20674 0 : 6832 => Opcode::PseudoVMIN_VV_M2,
20675 0 : 6833 => Opcode::PseudoVMIN_VV_M2_MASK,
20676 0 : 6834 => Opcode::PseudoVMIN_VV_M4,
20677 0 : 6835 => Opcode::PseudoVMIN_VV_M4_MASK,
20678 0 : 6836 => Opcode::PseudoVMIN_VV_M8,
20679 0 : 6837 => Opcode::PseudoVMIN_VV_M8_MASK,
20680 0 : 6838 => Opcode::PseudoVMIN_VV_MF2,
20681 0 : 6839 => Opcode::PseudoVMIN_VV_MF2_MASK,
20682 0 : 6840 => Opcode::PseudoVMIN_VV_MF4,
20683 0 : 6841 => Opcode::PseudoVMIN_VV_MF4_MASK,
20684 0 : 6842 => Opcode::PseudoVMIN_VV_MF8,
20685 0 : 6843 => Opcode::PseudoVMIN_VV_MF8_MASK,
20686 0 : 6844 => Opcode::PseudoVMIN_VX_M1,
20687 0 : 6845 => Opcode::PseudoVMIN_VX_M1_MASK,
20688 0 : 6846 => Opcode::PseudoVMIN_VX_M2,
20689 0 : 6847 => Opcode::PseudoVMIN_VX_M2_MASK,
20690 0 : 6848 => Opcode::PseudoVMIN_VX_M4,
20691 0 : 6849 => Opcode::PseudoVMIN_VX_M4_MASK,
20692 0 : 6850 => Opcode::PseudoVMIN_VX_M8,
20693 0 : 6851 => Opcode::PseudoVMIN_VX_M8_MASK,
20694 0 : 6852 => Opcode::PseudoVMIN_VX_MF2,
20695 0 : 6853 => Opcode::PseudoVMIN_VX_MF2_MASK,
20696 0 : 6854 => Opcode::PseudoVMIN_VX_MF4,
20697 0 : 6855 => Opcode::PseudoVMIN_VX_MF4_MASK,
20698 0 : 6856 => Opcode::PseudoVMIN_VX_MF8,
20699 0 : 6857 => Opcode::PseudoVMIN_VX_MF8_MASK,
20700 0 : 6858 => Opcode::PseudoVMNAND_MM_M1,
20701 0 : 6859 => Opcode::PseudoVMNAND_MM_M2,
20702 0 : 6860 => Opcode::PseudoVMNAND_MM_M4,
20703 0 : 6861 => Opcode::PseudoVMNAND_MM_M8,
20704 0 : 6862 => Opcode::PseudoVMNAND_MM_MF2,
20705 0 : 6863 => Opcode::PseudoVMNAND_MM_MF4,
20706 0 : 6864 => Opcode::PseudoVMNAND_MM_MF8,
20707 0 : 6865 => Opcode::PseudoVMNOR_MM_M1,
20708 0 : 6866 => Opcode::PseudoVMNOR_MM_M2,
20709 0 : 6867 => Opcode::PseudoVMNOR_MM_M4,
20710 0 : 6868 => Opcode::PseudoVMNOR_MM_M8,
20711 0 : 6869 => Opcode::PseudoVMNOR_MM_MF2,
20712 0 : 6870 => Opcode::PseudoVMNOR_MM_MF4,
20713 0 : 6871 => Opcode::PseudoVMNOR_MM_MF8,
20714 0 : 6872 => Opcode::PseudoVMORN_MM_M1,
20715 0 : 6873 => Opcode::PseudoVMORN_MM_M2,
20716 0 : 6874 => Opcode::PseudoVMORN_MM_M4,
20717 0 : 6875 => Opcode::PseudoVMORN_MM_M8,
20718 0 : 6876 => Opcode::PseudoVMORN_MM_MF2,
20719 0 : 6877 => Opcode::PseudoVMORN_MM_MF4,
20720 0 : 6878 => Opcode::PseudoVMORN_MM_MF8,
20721 0 : 6879 => Opcode::PseudoVMOR_MM_M1,
20722 0 : 6880 => Opcode::PseudoVMOR_MM_M2,
20723 0 : 6881 => Opcode::PseudoVMOR_MM_M4,
20724 0 : 6882 => Opcode::PseudoVMOR_MM_M8,
20725 0 : 6883 => Opcode::PseudoVMOR_MM_MF2,
20726 0 : 6884 => Opcode::PseudoVMOR_MM_MF4,
20727 0 : 6885 => Opcode::PseudoVMOR_MM_MF8,
20728 0 : 6886 => Opcode::PseudoVMSBC_VVM_M1,
20729 0 : 6887 => Opcode::PseudoVMSBC_VVM_M2,
20730 0 : 6888 => Opcode::PseudoVMSBC_VVM_M4,
20731 0 : 6889 => Opcode::PseudoVMSBC_VVM_M8,
20732 0 : 6890 => Opcode::PseudoVMSBC_VVM_MF2,
20733 0 : 6891 => Opcode::PseudoVMSBC_VVM_MF4,
20734 0 : 6892 => Opcode::PseudoVMSBC_VVM_MF8,
20735 0 : 6893 => Opcode::PseudoVMSBC_VV_M1,
20736 0 : 6894 => Opcode::PseudoVMSBC_VV_M2,
20737 0 : 6895 => Opcode::PseudoVMSBC_VV_M4,
20738 0 : 6896 => Opcode::PseudoVMSBC_VV_M8,
20739 0 : 6897 => Opcode::PseudoVMSBC_VV_MF2,
20740 0 : 6898 => Opcode::PseudoVMSBC_VV_MF4,
20741 0 : 6899 => Opcode::PseudoVMSBC_VV_MF8,
20742 0 : 6900 => Opcode::PseudoVMSBC_VXM_M1,
20743 0 : 6901 => Opcode::PseudoVMSBC_VXM_M2,
20744 0 : 6902 => Opcode::PseudoVMSBC_VXM_M4,
20745 0 : 6903 => Opcode::PseudoVMSBC_VXM_M8,
20746 0 : 6904 => Opcode::PseudoVMSBC_VXM_MF2,
20747 0 : 6905 => Opcode::PseudoVMSBC_VXM_MF4,
20748 0 : 6906 => Opcode::PseudoVMSBC_VXM_MF8,
20749 0 : 6907 => Opcode::PseudoVMSBC_VX_M1,
20750 0 : 6908 => Opcode::PseudoVMSBC_VX_M2,
20751 0 : 6909 => Opcode::PseudoVMSBC_VX_M4,
20752 0 : 6910 => Opcode::PseudoVMSBC_VX_M8,
20753 0 : 6911 => Opcode::PseudoVMSBC_VX_MF2,
20754 0 : 6912 => Opcode::PseudoVMSBC_VX_MF4,
20755 0 : 6913 => Opcode::PseudoVMSBC_VX_MF8,
20756 0 : 6914 => Opcode::PseudoVMSBF_M_B1,
20757 0 : 6915 => Opcode::PseudoVMSBF_M_B16,
20758 0 : 6916 => Opcode::PseudoVMSBF_M_B16_MASK,
20759 0 : 6917 => Opcode::PseudoVMSBF_M_B1_MASK,
20760 0 : 6918 => Opcode::PseudoVMSBF_M_B2,
20761 0 : 6919 => Opcode::PseudoVMSBF_M_B2_MASK,
20762 0 : 6920 => Opcode::PseudoVMSBF_M_B32,
20763 0 : 6921 => Opcode::PseudoVMSBF_M_B32_MASK,
20764 0 : 6922 => Opcode::PseudoVMSBF_M_B4,
20765 0 : 6923 => Opcode::PseudoVMSBF_M_B4_MASK,
20766 0 : 6924 => Opcode::PseudoVMSBF_M_B64,
20767 0 : 6925 => Opcode::PseudoVMSBF_M_B64_MASK,
20768 0 : 6926 => Opcode::PseudoVMSBF_M_B8,
20769 0 : 6927 => Opcode::PseudoVMSBF_M_B8_MASK,
20770 0 : 6928 => Opcode::PseudoVMSEQ_VI_M1,
20771 0 : 6929 => Opcode::PseudoVMSEQ_VI_M1_MASK,
20772 0 : 6930 => Opcode::PseudoVMSEQ_VI_M2,
20773 0 : 6931 => Opcode::PseudoVMSEQ_VI_M2_MASK,
20774 0 : 6932 => Opcode::PseudoVMSEQ_VI_M4,
20775 0 : 6933 => Opcode::PseudoVMSEQ_VI_M4_MASK,
20776 0 : 6934 => Opcode::PseudoVMSEQ_VI_M8,
20777 0 : 6935 => Opcode::PseudoVMSEQ_VI_M8_MASK,
20778 0 : 6936 => Opcode::PseudoVMSEQ_VI_MF2,
20779 0 : 6937 => Opcode::PseudoVMSEQ_VI_MF2_MASK,
20780 0 : 6938 => Opcode::PseudoVMSEQ_VI_MF4,
20781 0 : 6939 => Opcode::PseudoVMSEQ_VI_MF4_MASK,
20782 0 : 6940 => Opcode::PseudoVMSEQ_VI_MF8,
20783 0 : 6941 => Opcode::PseudoVMSEQ_VI_MF8_MASK,
20784 0 : 6942 => Opcode::PseudoVMSEQ_VV_M1,
20785 0 : 6943 => Opcode::PseudoVMSEQ_VV_M1_MASK,
20786 0 : 6944 => Opcode::PseudoVMSEQ_VV_M2,
20787 0 : 6945 => Opcode::PseudoVMSEQ_VV_M2_MASK,
20788 0 : 6946 => Opcode::PseudoVMSEQ_VV_M4,
20789 0 : 6947 => Opcode::PseudoVMSEQ_VV_M4_MASK,
20790 0 : 6948 => Opcode::PseudoVMSEQ_VV_M8,
20791 0 : 6949 => Opcode::PseudoVMSEQ_VV_M8_MASK,
20792 0 : 6950 => Opcode::PseudoVMSEQ_VV_MF2,
20793 0 : 6951 => Opcode::PseudoVMSEQ_VV_MF2_MASK,
20794 0 : 6952 => Opcode::PseudoVMSEQ_VV_MF4,
20795 0 : 6953 => Opcode::PseudoVMSEQ_VV_MF4_MASK,
20796 0 : 6954 => Opcode::PseudoVMSEQ_VV_MF8,
20797 0 : 6955 => Opcode::PseudoVMSEQ_VV_MF8_MASK,
20798 0 : 6956 => Opcode::PseudoVMSEQ_VX_M1,
20799 0 : 6957 => Opcode::PseudoVMSEQ_VX_M1_MASK,
20800 0 : 6958 => Opcode::PseudoVMSEQ_VX_M2,
20801 0 : 6959 => Opcode::PseudoVMSEQ_VX_M2_MASK,
20802 0 : 6960 => Opcode::PseudoVMSEQ_VX_M4,
20803 0 : 6961 => Opcode::PseudoVMSEQ_VX_M4_MASK,
20804 0 : 6962 => Opcode::PseudoVMSEQ_VX_M8,
20805 0 : 6963 => Opcode::PseudoVMSEQ_VX_M8_MASK,
20806 0 : 6964 => Opcode::PseudoVMSEQ_VX_MF2,
20807 0 : 6965 => Opcode::PseudoVMSEQ_VX_MF2_MASK,
20808 0 : 6966 => Opcode::PseudoVMSEQ_VX_MF4,
20809 0 : 6967 => Opcode::PseudoVMSEQ_VX_MF4_MASK,
20810 0 : 6968 => Opcode::PseudoVMSEQ_VX_MF8,
20811 0 : 6969 => Opcode::PseudoVMSEQ_VX_MF8_MASK,
20812 0 : 6970 => Opcode::PseudoVMSET_M_B1,
20813 0 : 6971 => Opcode::PseudoVMSET_M_B16,
20814 0 : 6972 => Opcode::PseudoVMSET_M_B2,
20815 0 : 6973 => Opcode::PseudoVMSET_M_B32,
20816 0 : 6974 => Opcode::PseudoVMSET_M_B4,
20817 0 : 6975 => Opcode::PseudoVMSET_M_B64,
20818 0 : 6976 => Opcode::PseudoVMSET_M_B8,
20819 0 : 6977 => Opcode::PseudoVMSGEU_VI,
20820 0 : 6978 => Opcode::PseudoVMSGEU_VX,
20821 0 : 6979 => Opcode::PseudoVMSGEU_VX_M,
20822 0 : 6980 => Opcode::PseudoVMSGEU_VX_M_T,
20823 0 : 6981 => Opcode::PseudoVMSGE_VI,
20824 0 : 6982 => Opcode::PseudoVMSGE_VX,
20825 0 : 6983 => Opcode::PseudoVMSGE_VX_M,
20826 0 : 6984 => Opcode::PseudoVMSGE_VX_M_T,
20827 0 : 6985 => Opcode::PseudoVMSGTU_VI_M1,
20828 0 : 6986 => Opcode::PseudoVMSGTU_VI_M1_MASK,
20829 0 : 6987 => Opcode::PseudoVMSGTU_VI_M2,
20830 0 : 6988 => Opcode::PseudoVMSGTU_VI_M2_MASK,
20831 0 : 6989 => Opcode::PseudoVMSGTU_VI_M4,
20832 0 : 6990 => Opcode::PseudoVMSGTU_VI_M4_MASK,
20833 0 : 6991 => Opcode::PseudoVMSGTU_VI_M8,
20834 0 : 6992 => Opcode::PseudoVMSGTU_VI_M8_MASK,
20835 0 : 6993 => Opcode::PseudoVMSGTU_VI_MF2,
20836 0 : 6994 => Opcode::PseudoVMSGTU_VI_MF2_MASK,
20837 0 : 6995 => Opcode::PseudoVMSGTU_VI_MF4,
20838 0 : 6996 => Opcode::PseudoVMSGTU_VI_MF4_MASK,
20839 0 : 6997 => Opcode::PseudoVMSGTU_VI_MF8,
20840 0 : 6998 => Opcode::PseudoVMSGTU_VI_MF8_MASK,
20841 0 : 6999 => Opcode::PseudoVMSGTU_VX_M1,
20842 0 : 7000 => Opcode::PseudoVMSGTU_VX_M1_MASK,
20843 0 : 7001 => Opcode::PseudoVMSGTU_VX_M2,
20844 0 : 7002 => Opcode::PseudoVMSGTU_VX_M2_MASK,
20845 0 : 7003 => Opcode::PseudoVMSGTU_VX_M4,
20846 0 : 7004 => Opcode::PseudoVMSGTU_VX_M4_MASK,
20847 0 : 7005 => Opcode::PseudoVMSGTU_VX_M8,
20848 0 : 7006 => Opcode::PseudoVMSGTU_VX_M8_MASK,
20849 0 : 7007 => Opcode::PseudoVMSGTU_VX_MF2,
20850 0 : 7008 => Opcode::PseudoVMSGTU_VX_MF2_MASK,
20851 0 : 7009 => Opcode::PseudoVMSGTU_VX_MF4,
20852 0 : 7010 => Opcode::PseudoVMSGTU_VX_MF4_MASK,
20853 0 : 7011 => Opcode::PseudoVMSGTU_VX_MF8,
20854 0 : 7012 => Opcode::PseudoVMSGTU_VX_MF8_MASK,
20855 0 : 7013 => Opcode::PseudoVMSGT_VI_M1,
20856 0 : 7014 => Opcode::PseudoVMSGT_VI_M1_MASK,
20857 0 : 7015 => Opcode::PseudoVMSGT_VI_M2,
20858 0 : 7016 => Opcode::PseudoVMSGT_VI_M2_MASK,
20859 0 : 7017 => Opcode::PseudoVMSGT_VI_M4,
20860 0 : 7018 => Opcode::PseudoVMSGT_VI_M4_MASK,
20861 0 : 7019 => Opcode::PseudoVMSGT_VI_M8,
20862 0 : 7020 => Opcode::PseudoVMSGT_VI_M8_MASK,
20863 0 : 7021 => Opcode::PseudoVMSGT_VI_MF2,
20864 0 : 7022 => Opcode::PseudoVMSGT_VI_MF2_MASK,
20865 0 : 7023 => Opcode::PseudoVMSGT_VI_MF4,
20866 0 : 7024 => Opcode::PseudoVMSGT_VI_MF4_MASK,
20867 0 : 7025 => Opcode::PseudoVMSGT_VI_MF8,
20868 0 : 7026 => Opcode::PseudoVMSGT_VI_MF8_MASK,
20869 0 : 7027 => Opcode::PseudoVMSGT_VX_M1,
20870 0 : 7028 => Opcode::PseudoVMSGT_VX_M1_MASK,
20871 0 : 7029 => Opcode::PseudoVMSGT_VX_M2,
20872 0 : 7030 => Opcode::PseudoVMSGT_VX_M2_MASK,
20873 0 : 7031 => Opcode::PseudoVMSGT_VX_M4,
20874 0 : 7032 => Opcode::PseudoVMSGT_VX_M4_MASK,
20875 0 : 7033 => Opcode::PseudoVMSGT_VX_M8,
20876 0 : 7034 => Opcode::PseudoVMSGT_VX_M8_MASK,
20877 0 : 7035 => Opcode::PseudoVMSGT_VX_MF2,
20878 0 : 7036 => Opcode::PseudoVMSGT_VX_MF2_MASK,
20879 0 : 7037 => Opcode::PseudoVMSGT_VX_MF4,
20880 0 : 7038 => Opcode::PseudoVMSGT_VX_MF4_MASK,
20881 0 : 7039 => Opcode::PseudoVMSGT_VX_MF8,
20882 0 : 7040 => Opcode::PseudoVMSGT_VX_MF8_MASK,
20883 0 : 7041 => Opcode::PseudoVMSIF_M_B1,
20884 0 : 7042 => Opcode::PseudoVMSIF_M_B16,
20885 0 : 7043 => Opcode::PseudoVMSIF_M_B16_MASK,
20886 0 : 7044 => Opcode::PseudoVMSIF_M_B1_MASK,
20887 0 : 7045 => Opcode::PseudoVMSIF_M_B2,
20888 0 : 7046 => Opcode::PseudoVMSIF_M_B2_MASK,
20889 0 : 7047 => Opcode::PseudoVMSIF_M_B32,
20890 0 : 7048 => Opcode::PseudoVMSIF_M_B32_MASK,
20891 0 : 7049 => Opcode::PseudoVMSIF_M_B4,
20892 0 : 7050 => Opcode::PseudoVMSIF_M_B4_MASK,
20893 0 : 7051 => Opcode::PseudoVMSIF_M_B64,
20894 0 : 7052 => Opcode::PseudoVMSIF_M_B64_MASK,
20895 0 : 7053 => Opcode::PseudoVMSIF_M_B8,
20896 0 : 7054 => Opcode::PseudoVMSIF_M_B8_MASK,
20897 0 : 7055 => Opcode::PseudoVMSLEU_VI_M1,
20898 0 : 7056 => Opcode::PseudoVMSLEU_VI_M1_MASK,
20899 0 : 7057 => Opcode::PseudoVMSLEU_VI_M2,
20900 0 : 7058 => Opcode::PseudoVMSLEU_VI_M2_MASK,
20901 0 : 7059 => Opcode::PseudoVMSLEU_VI_M4,
20902 0 : 7060 => Opcode::PseudoVMSLEU_VI_M4_MASK,
20903 0 : 7061 => Opcode::PseudoVMSLEU_VI_M8,
20904 0 : 7062 => Opcode::PseudoVMSLEU_VI_M8_MASK,
20905 0 : 7063 => Opcode::PseudoVMSLEU_VI_MF2,
20906 0 : 7064 => Opcode::PseudoVMSLEU_VI_MF2_MASK,
20907 0 : 7065 => Opcode::PseudoVMSLEU_VI_MF4,
20908 0 : 7066 => Opcode::PseudoVMSLEU_VI_MF4_MASK,
20909 0 : 7067 => Opcode::PseudoVMSLEU_VI_MF8,
20910 0 : 7068 => Opcode::PseudoVMSLEU_VI_MF8_MASK,
20911 0 : 7069 => Opcode::PseudoVMSLEU_VV_M1,
20912 0 : 7070 => Opcode::PseudoVMSLEU_VV_M1_MASK,
20913 0 : 7071 => Opcode::PseudoVMSLEU_VV_M2,
20914 0 : 7072 => Opcode::PseudoVMSLEU_VV_M2_MASK,
20915 0 : 7073 => Opcode::PseudoVMSLEU_VV_M4,
20916 0 : 7074 => Opcode::PseudoVMSLEU_VV_M4_MASK,
20917 0 : 7075 => Opcode::PseudoVMSLEU_VV_M8,
20918 0 : 7076 => Opcode::PseudoVMSLEU_VV_M8_MASK,
20919 0 : 7077 => Opcode::PseudoVMSLEU_VV_MF2,
20920 0 : 7078 => Opcode::PseudoVMSLEU_VV_MF2_MASK,
20921 0 : 7079 => Opcode::PseudoVMSLEU_VV_MF4,
20922 0 : 7080 => Opcode::PseudoVMSLEU_VV_MF4_MASK,
20923 0 : 7081 => Opcode::PseudoVMSLEU_VV_MF8,
20924 0 : 7082 => Opcode::PseudoVMSLEU_VV_MF8_MASK,
20925 0 : 7083 => Opcode::PseudoVMSLEU_VX_M1,
20926 0 : 7084 => Opcode::PseudoVMSLEU_VX_M1_MASK,
20927 0 : 7085 => Opcode::PseudoVMSLEU_VX_M2,
20928 0 : 7086 => Opcode::PseudoVMSLEU_VX_M2_MASK,
20929 0 : 7087 => Opcode::PseudoVMSLEU_VX_M4,
20930 0 : 7088 => Opcode::PseudoVMSLEU_VX_M4_MASK,
20931 0 : 7089 => Opcode::PseudoVMSLEU_VX_M8,
20932 0 : 7090 => Opcode::PseudoVMSLEU_VX_M8_MASK,
20933 0 : 7091 => Opcode::PseudoVMSLEU_VX_MF2,
20934 0 : 7092 => Opcode::PseudoVMSLEU_VX_MF2_MASK,
20935 0 : 7093 => Opcode::PseudoVMSLEU_VX_MF4,
20936 0 : 7094 => Opcode::PseudoVMSLEU_VX_MF4_MASK,
20937 0 : 7095 => Opcode::PseudoVMSLEU_VX_MF8,
20938 0 : 7096 => Opcode::PseudoVMSLEU_VX_MF8_MASK,
20939 0 : 7097 => Opcode::PseudoVMSLE_VI_M1,
20940 0 : 7098 => Opcode::PseudoVMSLE_VI_M1_MASK,
20941 0 : 7099 => Opcode::PseudoVMSLE_VI_M2,
20942 0 : 7100 => Opcode::PseudoVMSLE_VI_M2_MASK,
20943 0 : 7101 => Opcode::PseudoVMSLE_VI_M4,
20944 0 : 7102 => Opcode::PseudoVMSLE_VI_M4_MASK,
20945 0 : 7103 => Opcode::PseudoVMSLE_VI_M8,
20946 0 : 7104 => Opcode::PseudoVMSLE_VI_M8_MASK,
20947 0 : 7105 => Opcode::PseudoVMSLE_VI_MF2,
20948 0 : 7106 => Opcode::PseudoVMSLE_VI_MF2_MASK,
20949 0 : 7107 => Opcode::PseudoVMSLE_VI_MF4,
20950 0 : 7108 => Opcode::PseudoVMSLE_VI_MF4_MASK,
20951 0 : 7109 => Opcode::PseudoVMSLE_VI_MF8,
20952 0 : 7110 => Opcode::PseudoVMSLE_VI_MF8_MASK,
20953 0 : 7111 => Opcode::PseudoVMSLE_VV_M1,
20954 0 : 7112 => Opcode::PseudoVMSLE_VV_M1_MASK,
20955 0 : 7113 => Opcode::PseudoVMSLE_VV_M2,
20956 0 : 7114 => Opcode::PseudoVMSLE_VV_M2_MASK,
20957 0 : 7115 => Opcode::PseudoVMSLE_VV_M4,
20958 0 : 7116 => Opcode::PseudoVMSLE_VV_M4_MASK,
20959 0 : 7117 => Opcode::PseudoVMSLE_VV_M8,
20960 0 : 7118 => Opcode::PseudoVMSLE_VV_M8_MASK,
20961 0 : 7119 => Opcode::PseudoVMSLE_VV_MF2,
20962 0 : 7120 => Opcode::PseudoVMSLE_VV_MF2_MASK,
20963 0 : 7121 => Opcode::PseudoVMSLE_VV_MF4,
20964 0 : 7122 => Opcode::PseudoVMSLE_VV_MF4_MASK,
20965 0 : 7123 => Opcode::PseudoVMSLE_VV_MF8,
20966 0 : 7124 => Opcode::PseudoVMSLE_VV_MF8_MASK,
20967 0 : 7125 => Opcode::PseudoVMSLE_VX_M1,
20968 0 : 7126 => Opcode::PseudoVMSLE_VX_M1_MASK,
20969 0 : 7127 => Opcode::PseudoVMSLE_VX_M2,
20970 0 : 7128 => Opcode::PseudoVMSLE_VX_M2_MASK,
20971 0 : 7129 => Opcode::PseudoVMSLE_VX_M4,
20972 0 : 7130 => Opcode::PseudoVMSLE_VX_M4_MASK,
20973 0 : 7131 => Opcode::PseudoVMSLE_VX_M8,
20974 0 : 7132 => Opcode::PseudoVMSLE_VX_M8_MASK,
20975 0 : 7133 => Opcode::PseudoVMSLE_VX_MF2,
20976 0 : 7134 => Opcode::PseudoVMSLE_VX_MF2_MASK,
20977 0 : 7135 => Opcode::PseudoVMSLE_VX_MF4,
20978 0 : 7136 => Opcode::PseudoVMSLE_VX_MF4_MASK,
20979 0 : 7137 => Opcode::PseudoVMSLE_VX_MF8,
20980 0 : 7138 => Opcode::PseudoVMSLE_VX_MF8_MASK,
20981 0 : 7139 => Opcode::PseudoVMSLTU_VI,
20982 0 : 7140 => Opcode::PseudoVMSLTU_VV_M1,
20983 0 : 7141 => Opcode::PseudoVMSLTU_VV_M1_MASK,
20984 0 : 7142 => Opcode::PseudoVMSLTU_VV_M2,
20985 0 : 7143 => Opcode::PseudoVMSLTU_VV_M2_MASK,
20986 0 : 7144 => Opcode::PseudoVMSLTU_VV_M4,
20987 0 : 7145 => Opcode::PseudoVMSLTU_VV_M4_MASK,
20988 0 : 7146 => Opcode::PseudoVMSLTU_VV_M8,
20989 0 : 7147 => Opcode::PseudoVMSLTU_VV_M8_MASK,
20990 0 : 7148 => Opcode::PseudoVMSLTU_VV_MF2,
20991 0 : 7149 => Opcode::PseudoVMSLTU_VV_MF2_MASK,
20992 0 : 7150 => Opcode::PseudoVMSLTU_VV_MF4,
20993 0 : 7151 => Opcode::PseudoVMSLTU_VV_MF4_MASK,
20994 0 : 7152 => Opcode::PseudoVMSLTU_VV_MF8,
20995 0 : 7153 => Opcode::PseudoVMSLTU_VV_MF8_MASK,
20996 0 : 7154 => Opcode::PseudoVMSLTU_VX_M1,
20997 0 : 7155 => Opcode::PseudoVMSLTU_VX_M1_MASK,
20998 0 : 7156 => Opcode::PseudoVMSLTU_VX_M2,
20999 0 : 7157 => Opcode::PseudoVMSLTU_VX_M2_MASK,
21000 0 : 7158 => Opcode::PseudoVMSLTU_VX_M4,
21001 0 : 7159 => Opcode::PseudoVMSLTU_VX_M4_MASK,
21002 0 : 7160 => Opcode::PseudoVMSLTU_VX_M8,
21003 0 : 7161 => Opcode::PseudoVMSLTU_VX_M8_MASK,
21004 0 : 7162 => Opcode::PseudoVMSLTU_VX_MF2,
21005 0 : 7163 => Opcode::PseudoVMSLTU_VX_MF2_MASK,
21006 0 : 7164 => Opcode::PseudoVMSLTU_VX_MF4,
21007 0 : 7165 => Opcode::PseudoVMSLTU_VX_MF4_MASK,
21008 0 : 7166 => Opcode::PseudoVMSLTU_VX_MF8,
21009 0 : 7167 => Opcode::PseudoVMSLTU_VX_MF8_MASK,
21010 0 : 7168 => Opcode::PseudoVMSLT_VI,
21011 0 : 7169 => Opcode::PseudoVMSLT_VV_M1,
21012 0 : 7170 => Opcode::PseudoVMSLT_VV_M1_MASK,
21013 0 : 7171 => Opcode::PseudoVMSLT_VV_M2,
21014 0 : 7172 => Opcode::PseudoVMSLT_VV_M2_MASK,
21015 0 : 7173 => Opcode::PseudoVMSLT_VV_M4,
21016 0 : 7174 => Opcode::PseudoVMSLT_VV_M4_MASK,
21017 0 : 7175 => Opcode::PseudoVMSLT_VV_M8,
21018 0 : 7176 => Opcode::PseudoVMSLT_VV_M8_MASK,
21019 0 : 7177 => Opcode::PseudoVMSLT_VV_MF2,
21020 0 : 7178 => Opcode::PseudoVMSLT_VV_MF2_MASK,
21021 0 : 7179 => Opcode::PseudoVMSLT_VV_MF4,
21022 0 : 7180 => Opcode::PseudoVMSLT_VV_MF4_MASK,
21023 0 : 7181 => Opcode::PseudoVMSLT_VV_MF8,
21024 0 : 7182 => Opcode::PseudoVMSLT_VV_MF8_MASK,
21025 0 : 7183 => Opcode::PseudoVMSLT_VX_M1,
21026 0 : 7184 => Opcode::PseudoVMSLT_VX_M1_MASK,
21027 0 : 7185 => Opcode::PseudoVMSLT_VX_M2,
21028 0 : 7186 => Opcode::PseudoVMSLT_VX_M2_MASK,
21029 0 : 7187 => Opcode::PseudoVMSLT_VX_M4,
21030 0 : 7188 => Opcode::PseudoVMSLT_VX_M4_MASK,
21031 0 : 7189 => Opcode::PseudoVMSLT_VX_M8,
21032 0 : 7190 => Opcode::PseudoVMSLT_VX_M8_MASK,
21033 0 : 7191 => Opcode::PseudoVMSLT_VX_MF2,
21034 0 : 7192 => Opcode::PseudoVMSLT_VX_MF2_MASK,
21035 0 : 7193 => Opcode::PseudoVMSLT_VX_MF4,
21036 0 : 7194 => Opcode::PseudoVMSLT_VX_MF4_MASK,
21037 0 : 7195 => Opcode::PseudoVMSLT_VX_MF8,
21038 0 : 7196 => Opcode::PseudoVMSLT_VX_MF8_MASK,
21039 0 : 7197 => Opcode::PseudoVMSNE_VI_M1,
21040 0 : 7198 => Opcode::PseudoVMSNE_VI_M1_MASK,
21041 0 : 7199 => Opcode::PseudoVMSNE_VI_M2,
21042 0 : 7200 => Opcode::PseudoVMSNE_VI_M2_MASK,
21043 0 : 7201 => Opcode::PseudoVMSNE_VI_M4,
21044 0 : 7202 => Opcode::PseudoVMSNE_VI_M4_MASK,
21045 0 : 7203 => Opcode::PseudoVMSNE_VI_M8,
21046 0 : 7204 => Opcode::PseudoVMSNE_VI_M8_MASK,
21047 0 : 7205 => Opcode::PseudoVMSNE_VI_MF2,
21048 0 : 7206 => Opcode::PseudoVMSNE_VI_MF2_MASK,
21049 0 : 7207 => Opcode::PseudoVMSNE_VI_MF4,
21050 0 : 7208 => Opcode::PseudoVMSNE_VI_MF4_MASK,
21051 0 : 7209 => Opcode::PseudoVMSNE_VI_MF8,
21052 0 : 7210 => Opcode::PseudoVMSNE_VI_MF8_MASK,
21053 0 : 7211 => Opcode::PseudoVMSNE_VV_M1,
21054 0 : 7212 => Opcode::PseudoVMSNE_VV_M1_MASK,
21055 0 : 7213 => Opcode::PseudoVMSNE_VV_M2,
21056 0 : 7214 => Opcode::PseudoVMSNE_VV_M2_MASK,
21057 0 : 7215 => Opcode::PseudoVMSNE_VV_M4,
21058 0 : 7216 => Opcode::PseudoVMSNE_VV_M4_MASK,
21059 0 : 7217 => Opcode::PseudoVMSNE_VV_M8,
21060 0 : 7218 => Opcode::PseudoVMSNE_VV_M8_MASK,
21061 0 : 7219 => Opcode::PseudoVMSNE_VV_MF2,
21062 0 : 7220 => Opcode::PseudoVMSNE_VV_MF2_MASK,
21063 0 : 7221 => Opcode::PseudoVMSNE_VV_MF4,
21064 0 : 7222 => Opcode::PseudoVMSNE_VV_MF4_MASK,
21065 0 : 7223 => Opcode::PseudoVMSNE_VV_MF8,
21066 0 : 7224 => Opcode::PseudoVMSNE_VV_MF8_MASK,
21067 0 : 7225 => Opcode::PseudoVMSNE_VX_M1,
21068 0 : 7226 => Opcode::PseudoVMSNE_VX_M1_MASK,
21069 0 : 7227 => Opcode::PseudoVMSNE_VX_M2,
21070 0 : 7228 => Opcode::PseudoVMSNE_VX_M2_MASK,
21071 0 : 7229 => Opcode::PseudoVMSNE_VX_M4,
21072 0 : 7230 => Opcode::PseudoVMSNE_VX_M4_MASK,
21073 0 : 7231 => Opcode::PseudoVMSNE_VX_M8,
21074 0 : 7232 => Opcode::PseudoVMSNE_VX_M8_MASK,
21075 0 : 7233 => Opcode::PseudoVMSNE_VX_MF2,
21076 0 : 7234 => Opcode::PseudoVMSNE_VX_MF2_MASK,
21077 0 : 7235 => Opcode::PseudoVMSNE_VX_MF4,
21078 0 : 7236 => Opcode::PseudoVMSNE_VX_MF4_MASK,
21079 0 : 7237 => Opcode::PseudoVMSNE_VX_MF8,
21080 0 : 7238 => Opcode::PseudoVMSNE_VX_MF8_MASK,
21081 0 : 7239 => Opcode::PseudoVMSOF_M_B1,
21082 0 : 7240 => Opcode::PseudoVMSOF_M_B16,
21083 0 : 7241 => Opcode::PseudoVMSOF_M_B16_MASK,
21084 0 : 7242 => Opcode::PseudoVMSOF_M_B1_MASK,
21085 0 : 7243 => Opcode::PseudoVMSOF_M_B2,
21086 0 : 7244 => Opcode::PseudoVMSOF_M_B2_MASK,
21087 0 : 7245 => Opcode::PseudoVMSOF_M_B32,
21088 0 : 7246 => Opcode::PseudoVMSOF_M_B32_MASK,
21089 0 : 7247 => Opcode::PseudoVMSOF_M_B4,
21090 0 : 7248 => Opcode::PseudoVMSOF_M_B4_MASK,
21091 0 : 7249 => Opcode::PseudoVMSOF_M_B64,
21092 0 : 7250 => Opcode::PseudoVMSOF_M_B64_MASK,
21093 0 : 7251 => Opcode::PseudoVMSOF_M_B8,
21094 0 : 7252 => Opcode::PseudoVMSOF_M_B8_MASK,
21095 0 : 7253 => Opcode::PseudoVMULHSU_VV_M1,
21096 0 : 7254 => Opcode::PseudoVMULHSU_VV_M1_MASK,
21097 0 : 7255 => Opcode::PseudoVMULHSU_VV_M2,
21098 0 : 7256 => Opcode::PseudoVMULHSU_VV_M2_MASK,
21099 0 : 7257 => Opcode::PseudoVMULHSU_VV_M4,
21100 0 : 7258 => Opcode::PseudoVMULHSU_VV_M4_MASK,
21101 0 : 7259 => Opcode::PseudoVMULHSU_VV_M8,
21102 0 : 7260 => Opcode::PseudoVMULHSU_VV_M8_MASK,
21103 0 : 7261 => Opcode::PseudoVMULHSU_VV_MF2,
21104 0 : 7262 => Opcode::PseudoVMULHSU_VV_MF2_MASK,
21105 0 : 7263 => Opcode::PseudoVMULHSU_VV_MF4,
21106 0 : 7264 => Opcode::PseudoVMULHSU_VV_MF4_MASK,
21107 0 : 7265 => Opcode::PseudoVMULHSU_VV_MF8,
21108 0 : 7266 => Opcode::PseudoVMULHSU_VV_MF8_MASK,
21109 0 : 7267 => Opcode::PseudoVMULHSU_VX_M1,
21110 0 : 7268 => Opcode::PseudoVMULHSU_VX_M1_MASK,
21111 0 : 7269 => Opcode::PseudoVMULHSU_VX_M2,
21112 0 : 7270 => Opcode::PseudoVMULHSU_VX_M2_MASK,
21113 0 : 7271 => Opcode::PseudoVMULHSU_VX_M4,
21114 0 : 7272 => Opcode::PseudoVMULHSU_VX_M4_MASK,
21115 0 : 7273 => Opcode::PseudoVMULHSU_VX_M8,
21116 0 : 7274 => Opcode::PseudoVMULHSU_VX_M8_MASK,
21117 0 : 7275 => Opcode::PseudoVMULHSU_VX_MF2,
21118 0 : 7276 => Opcode::PseudoVMULHSU_VX_MF2_MASK,
21119 0 : 7277 => Opcode::PseudoVMULHSU_VX_MF4,
21120 0 : 7278 => Opcode::PseudoVMULHSU_VX_MF4_MASK,
21121 0 : 7279 => Opcode::PseudoVMULHSU_VX_MF8,
21122 0 : 7280 => Opcode::PseudoVMULHSU_VX_MF8_MASK,
21123 0 : 7281 => Opcode::PseudoVMULHU_VV_M1,
21124 0 : 7282 => Opcode::PseudoVMULHU_VV_M1_MASK,
21125 0 : 7283 => Opcode::PseudoVMULHU_VV_M2,
21126 0 : 7284 => Opcode::PseudoVMULHU_VV_M2_MASK,
21127 0 : 7285 => Opcode::PseudoVMULHU_VV_M4,
21128 0 : 7286 => Opcode::PseudoVMULHU_VV_M4_MASK,
21129 0 : 7287 => Opcode::PseudoVMULHU_VV_M8,
21130 0 : 7288 => Opcode::PseudoVMULHU_VV_M8_MASK,
21131 0 : 7289 => Opcode::PseudoVMULHU_VV_MF2,
21132 0 : 7290 => Opcode::PseudoVMULHU_VV_MF2_MASK,
21133 0 : 7291 => Opcode::PseudoVMULHU_VV_MF4,
21134 0 : 7292 => Opcode::PseudoVMULHU_VV_MF4_MASK,
21135 0 : 7293 => Opcode::PseudoVMULHU_VV_MF8,
21136 0 : 7294 => Opcode::PseudoVMULHU_VV_MF8_MASK,
21137 0 : 7295 => Opcode::PseudoVMULHU_VX_M1,
21138 0 : 7296 => Opcode::PseudoVMULHU_VX_M1_MASK,
21139 0 : 7297 => Opcode::PseudoVMULHU_VX_M2,
21140 0 : 7298 => Opcode::PseudoVMULHU_VX_M2_MASK,
21141 0 : 7299 => Opcode::PseudoVMULHU_VX_M4,
21142 0 : 7300 => Opcode::PseudoVMULHU_VX_M4_MASK,
21143 0 : 7301 => Opcode::PseudoVMULHU_VX_M8,
21144 0 : 7302 => Opcode::PseudoVMULHU_VX_M8_MASK,
21145 0 : 7303 => Opcode::PseudoVMULHU_VX_MF2,
21146 0 : 7304 => Opcode::PseudoVMULHU_VX_MF2_MASK,
21147 0 : 7305 => Opcode::PseudoVMULHU_VX_MF4,
21148 0 : 7306 => Opcode::PseudoVMULHU_VX_MF4_MASK,
21149 0 : 7307 => Opcode::PseudoVMULHU_VX_MF8,
21150 0 : 7308 => Opcode::PseudoVMULHU_VX_MF8_MASK,
21151 0 : 7309 => Opcode::PseudoVMULH_VV_M1,
21152 0 : 7310 => Opcode::PseudoVMULH_VV_M1_MASK,
21153 0 : 7311 => Opcode::PseudoVMULH_VV_M2,
21154 0 : 7312 => Opcode::PseudoVMULH_VV_M2_MASK,
21155 0 : 7313 => Opcode::PseudoVMULH_VV_M4,
21156 0 : 7314 => Opcode::PseudoVMULH_VV_M4_MASK,
21157 0 : 7315 => Opcode::PseudoVMULH_VV_M8,
21158 0 : 7316 => Opcode::PseudoVMULH_VV_M8_MASK,
21159 0 : 7317 => Opcode::PseudoVMULH_VV_MF2,
21160 0 : 7318 => Opcode::PseudoVMULH_VV_MF2_MASK,
21161 0 : 7319 => Opcode::PseudoVMULH_VV_MF4,
21162 0 : 7320 => Opcode::PseudoVMULH_VV_MF4_MASK,
21163 0 : 7321 => Opcode::PseudoVMULH_VV_MF8,
21164 0 : 7322 => Opcode::PseudoVMULH_VV_MF8_MASK,
21165 0 : 7323 => Opcode::PseudoVMULH_VX_M1,
21166 0 : 7324 => Opcode::PseudoVMULH_VX_M1_MASK,
21167 0 : 7325 => Opcode::PseudoVMULH_VX_M2,
21168 0 : 7326 => Opcode::PseudoVMULH_VX_M2_MASK,
21169 0 : 7327 => Opcode::PseudoVMULH_VX_M4,
21170 0 : 7328 => Opcode::PseudoVMULH_VX_M4_MASK,
21171 0 : 7329 => Opcode::PseudoVMULH_VX_M8,
21172 0 : 7330 => Opcode::PseudoVMULH_VX_M8_MASK,
21173 0 : 7331 => Opcode::PseudoVMULH_VX_MF2,
21174 0 : 7332 => Opcode::PseudoVMULH_VX_MF2_MASK,
21175 0 : 7333 => Opcode::PseudoVMULH_VX_MF4,
21176 0 : 7334 => Opcode::PseudoVMULH_VX_MF4_MASK,
21177 0 : 7335 => Opcode::PseudoVMULH_VX_MF8,
21178 0 : 7336 => Opcode::PseudoVMULH_VX_MF8_MASK,
21179 0 : 7337 => Opcode::PseudoVMUL_VV_M1,
21180 0 : 7338 => Opcode::PseudoVMUL_VV_M1_MASK,
21181 0 : 7339 => Opcode::PseudoVMUL_VV_M2,
21182 0 : 7340 => Opcode::PseudoVMUL_VV_M2_MASK,
21183 0 : 7341 => Opcode::PseudoVMUL_VV_M4,
21184 0 : 7342 => Opcode::PseudoVMUL_VV_M4_MASK,
21185 0 : 7343 => Opcode::PseudoVMUL_VV_M8,
21186 0 : 7344 => Opcode::PseudoVMUL_VV_M8_MASK,
21187 0 : 7345 => Opcode::PseudoVMUL_VV_MF2,
21188 0 : 7346 => Opcode::PseudoVMUL_VV_MF2_MASK,
21189 0 : 7347 => Opcode::PseudoVMUL_VV_MF4,
21190 0 : 7348 => Opcode::PseudoVMUL_VV_MF4_MASK,
21191 0 : 7349 => Opcode::PseudoVMUL_VV_MF8,
21192 0 : 7350 => Opcode::PseudoVMUL_VV_MF8_MASK,
21193 0 : 7351 => Opcode::PseudoVMUL_VX_M1,
21194 0 : 7352 => Opcode::PseudoVMUL_VX_M1_MASK,
21195 0 : 7353 => Opcode::PseudoVMUL_VX_M2,
21196 0 : 7354 => Opcode::PseudoVMUL_VX_M2_MASK,
21197 0 : 7355 => Opcode::PseudoVMUL_VX_M4,
21198 0 : 7356 => Opcode::PseudoVMUL_VX_M4_MASK,
21199 0 : 7357 => Opcode::PseudoVMUL_VX_M8,
21200 0 : 7358 => Opcode::PseudoVMUL_VX_M8_MASK,
21201 0 : 7359 => Opcode::PseudoVMUL_VX_MF2,
21202 0 : 7360 => Opcode::PseudoVMUL_VX_MF2_MASK,
21203 0 : 7361 => Opcode::PseudoVMUL_VX_MF4,
21204 0 : 7362 => Opcode::PseudoVMUL_VX_MF4_MASK,
21205 0 : 7363 => Opcode::PseudoVMUL_VX_MF8,
21206 0 : 7364 => Opcode::PseudoVMUL_VX_MF8_MASK,
21207 0 : 7365 => Opcode::PseudoVMV_S_X,
21208 0 : 7366 => Opcode::PseudoVMV_V_I_M1,
21209 0 : 7367 => Opcode::PseudoVMV_V_I_M2,
21210 0 : 7368 => Opcode::PseudoVMV_V_I_M4,
21211 0 : 7369 => Opcode::PseudoVMV_V_I_M8,
21212 0 : 7370 => Opcode::PseudoVMV_V_I_MF2,
21213 0 : 7371 => Opcode::PseudoVMV_V_I_MF4,
21214 0 : 7372 => Opcode::PseudoVMV_V_I_MF8,
21215 0 : 7373 => Opcode::PseudoVMV_V_V_M1,
21216 0 : 7374 => Opcode::PseudoVMV_V_V_M2,
21217 0 : 7375 => Opcode::PseudoVMV_V_V_M4,
21218 0 : 7376 => Opcode::PseudoVMV_V_V_M8,
21219 0 : 7377 => Opcode::PseudoVMV_V_V_MF2,
21220 0 : 7378 => Opcode::PseudoVMV_V_V_MF4,
21221 0 : 7379 => Opcode::PseudoVMV_V_V_MF8,
21222 0 : 7380 => Opcode::PseudoVMV_V_X_M1,
21223 0 : 7381 => Opcode::PseudoVMV_V_X_M2,
21224 0 : 7382 => Opcode::PseudoVMV_V_X_M4,
21225 0 : 7383 => Opcode::PseudoVMV_V_X_M8,
21226 0 : 7384 => Opcode::PseudoVMV_V_X_MF2,
21227 0 : 7385 => Opcode::PseudoVMV_V_X_MF4,
21228 0 : 7386 => Opcode::PseudoVMV_V_X_MF8,
21229 0 : 7387 => Opcode::PseudoVMV_X_S,
21230 0 : 7388 => Opcode::PseudoVMXNOR_MM_M1,
21231 0 : 7389 => Opcode::PseudoVMXNOR_MM_M2,
21232 0 : 7390 => Opcode::PseudoVMXNOR_MM_M4,
21233 0 : 7391 => Opcode::PseudoVMXNOR_MM_M8,
21234 0 : 7392 => Opcode::PseudoVMXNOR_MM_MF2,
21235 0 : 7393 => Opcode::PseudoVMXNOR_MM_MF4,
21236 0 : 7394 => Opcode::PseudoVMXNOR_MM_MF8,
21237 0 : 7395 => Opcode::PseudoVMXOR_MM_M1,
21238 0 : 7396 => Opcode::PseudoVMXOR_MM_M2,
21239 0 : 7397 => Opcode::PseudoVMXOR_MM_M4,
21240 0 : 7398 => Opcode::PseudoVMXOR_MM_M8,
21241 0 : 7399 => Opcode::PseudoVMXOR_MM_MF2,
21242 0 : 7400 => Opcode::PseudoVMXOR_MM_MF4,
21243 0 : 7401 => Opcode::PseudoVMXOR_MM_MF8,
21244 0 : 7402 => Opcode::PseudoVNCLIPU_WI_M1,
21245 0 : 7403 => Opcode::PseudoVNCLIPU_WI_M1_MASK,
21246 0 : 7404 => Opcode::PseudoVNCLIPU_WI_M2,
21247 0 : 7405 => Opcode::PseudoVNCLIPU_WI_M2_MASK,
21248 0 : 7406 => Opcode::PseudoVNCLIPU_WI_M4,
21249 0 : 7407 => Opcode::PseudoVNCLIPU_WI_M4_MASK,
21250 0 : 7408 => Opcode::PseudoVNCLIPU_WI_MF2,
21251 0 : 7409 => Opcode::PseudoVNCLIPU_WI_MF2_MASK,
21252 0 : 7410 => Opcode::PseudoVNCLIPU_WI_MF4,
21253 0 : 7411 => Opcode::PseudoVNCLIPU_WI_MF4_MASK,
21254 0 : 7412 => Opcode::PseudoVNCLIPU_WI_MF8,
21255 0 : 7413 => Opcode::PseudoVNCLIPU_WI_MF8_MASK,
21256 0 : 7414 => Opcode::PseudoVNCLIPU_WV_M1,
21257 0 : 7415 => Opcode::PseudoVNCLIPU_WV_M1_MASK,
21258 0 : 7416 => Opcode::PseudoVNCLIPU_WV_M2,
21259 0 : 7417 => Opcode::PseudoVNCLIPU_WV_M2_MASK,
21260 0 : 7418 => Opcode::PseudoVNCLIPU_WV_M4,
21261 0 : 7419 => Opcode::PseudoVNCLIPU_WV_M4_MASK,
21262 0 : 7420 => Opcode::PseudoVNCLIPU_WV_MF2,
21263 0 : 7421 => Opcode::PseudoVNCLIPU_WV_MF2_MASK,
21264 0 : 7422 => Opcode::PseudoVNCLIPU_WV_MF4,
21265 0 : 7423 => Opcode::PseudoVNCLIPU_WV_MF4_MASK,
21266 0 : 7424 => Opcode::PseudoVNCLIPU_WV_MF8,
21267 0 : 7425 => Opcode::PseudoVNCLIPU_WV_MF8_MASK,
21268 0 : 7426 => Opcode::PseudoVNCLIPU_WX_M1,
21269 0 : 7427 => Opcode::PseudoVNCLIPU_WX_M1_MASK,
21270 0 : 7428 => Opcode::PseudoVNCLIPU_WX_M2,
21271 0 : 7429 => Opcode::PseudoVNCLIPU_WX_M2_MASK,
21272 0 : 7430 => Opcode::PseudoVNCLIPU_WX_M4,
21273 0 : 7431 => Opcode::PseudoVNCLIPU_WX_M4_MASK,
21274 0 : 7432 => Opcode::PseudoVNCLIPU_WX_MF2,
21275 0 : 7433 => Opcode::PseudoVNCLIPU_WX_MF2_MASK,
21276 0 : 7434 => Opcode::PseudoVNCLIPU_WX_MF4,
21277 0 : 7435 => Opcode::PseudoVNCLIPU_WX_MF4_MASK,
21278 0 : 7436 => Opcode::PseudoVNCLIPU_WX_MF8,
21279 0 : 7437 => Opcode::PseudoVNCLIPU_WX_MF8_MASK,
21280 0 : 7438 => Opcode::PseudoVNCLIP_WI_M1,
21281 0 : 7439 => Opcode::PseudoVNCLIP_WI_M1_MASK,
21282 0 : 7440 => Opcode::PseudoVNCLIP_WI_M2,
21283 0 : 7441 => Opcode::PseudoVNCLIP_WI_M2_MASK,
21284 0 : 7442 => Opcode::PseudoVNCLIP_WI_M4,
21285 0 : 7443 => Opcode::PseudoVNCLIP_WI_M4_MASK,
21286 0 : 7444 => Opcode::PseudoVNCLIP_WI_MF2,
21287 0 : 7445 => Opcode::PseudoVNCLIP_WI_MF2_MASK,
21288 0 : 7446 => Opcode::PseudoVNCLIP_WI_MF4,
21289 0 : 7447 => Opcode::PseudoVNCLIP_WI_MF4_MASK,
21290 0 : 7448 => Opcode::PseudoVNCLIP_WI_MF8,
21291 0 : 7449 => Opcode::PseudoVNCLIP_WI_MF8_MASK,
21292 0 : 7450 => Opcode::PseudoVNCLIP_WV_M1,
21293 0 : 7451 => Opcode::PseudoVNCLIP_WV_M1_MASK,
21294 0 : 7452 => Opcode::PseudoVNCLIP_WV_M2,
21295 0 : 7453 => Opcode::PseudoVNCLIP_WV_M2_MASK,
21296 0 : 7454 => Opcode::PseudoVNCLIP_WV_M4,
21297 0 : 7455 => Opcode::PseudoVNCLIP_WV_M4_MASK,
21298 0 : 7456 => Opcode::PseudoVNCLIP_WV_MF2,
21299 0 : 7457 => Opcode::PseudoVNCLIP_WV_MF2_MASK,
21300 0 : 7458 => Opcode::PseudoVNCLIP_WV_MF4,
21301 0 : 7459 => Opcode::PseudoVNCLIP_WV_MF4_MASK,
21302 0 : 7460 => Opcode::PseudoVNCLIP_WV_MF8,
21303 0 : 7461 => Opcode::PseudoVNCLIP_WV_MF8_MASK,
21304 0 : 7462 => Opcode::PseudoVNCLIP_WX_M1,
21305 0 : 7463 => Opcode::PseudoVNCLIP_WX_M1_MASK,
21306 0 : 7464 => Opcode::PseudoVNCLIP_WX_M2,
21307 0 : 7465 => Opcode::PseudoVNCLIP_WX_M2_MASK,
21308 0 : 7466 => Opcode::PseudoVNCLIP_WX_M4,
21309 0 : 7467 => Opcode::PseudoVNCLIP_WX_M4_MASK,
21310 0 : 7468 => Opcode::PseudoVNCLIP_WX_MF2,
21311 0 : 7469 => Opcode::PseudoVNCLIP_WX_MF2_MASK,
21312 0 : 7470 => Opcode::PseudoVNCLIP_WX_MF4,
21313 0 : 7471 => Opcode::PseudoVNCLIP_WX_MF4_MASK,
21314 0 : 7472 => Opcode::PseudoVNCLIP_WX_MF8,
21315 0 : 7473 => Opcode::PseudoVNCLIP_WX_MF8_MASK,
21316 0 : 7474 => Opcode::PseudoVNMSAC_VV_M1,
21317 0 : 7475 => Opcode::PseudoVNMSAC_VV_M1_MASK,
21318 0 : 7476 => Opcode::PseudoVNMSAC_VV_M2,
21319 0 : 7477 => Opcode::PseudoVNMSAC_VV_M2_MASK,
21320 0 : 7478 => Opcode::PseudoVNMSAC_VV_M4,
21321 0 : 7479 => Opcode::PseudoVNMSAC_VV_M4_MASK,
21322 0 : 7480 => Opcode::PseudoVNMSAC_VV_M8,
21323 0 : 7481 => Opcode::PseudoVNMSAC_VV_M8_MASK,
21324 0 : 7482 => Opcode::PseudoVNMSAC_VV_MF2,
21325 0 : 7483 => Opcode::PseudoVNMSAC_VV_MF2_MASK,
21326 0 : 7484 => Opcode::PseudoVNMSAC_VV_MF4,
21327 0 : 7485 => Opcode::PseudoVNMSAC_VV_MF4_MASK,
21328 0 : 7486 => Opcode::PseudoVNMSAC_VV_MF8,
21329 0 : 7487 => Opcode::PseudoVNMSAC_VV_MF8_MASK,
21330 0 : 7488 => Opcode::PseudoVNMSAC_VX_M1,
21331 0 : 7489 => Opcode::PseudoVNMSAC_VX_M1_MASK,
21332 0 : 7490 => Opcode::PseudoVNMSAC_VX_M2,
21333 0 : 7491 => Opcode::PseudoVNMSAC_VX_M2_MASK,
21334 0 : 7492 => Opcode::PseudoVNMSAC_VX_M4,
21335 0 : 7493 => Opcode::PseudoVNMSAC_VX_M4_MASK,
21336 0 : 7494 => Opcode::PseudoVNMSAC_VX_M8,
21337 0 : 7495 => Opcode::PseudoVNMSAC_VX_M8_MASK,
21338 0 : 7496 => Opcode::PseudoVNMSAC_VX_MF2,
21339 0 : 7497 => Opcode::PseudoVNMSAC_VX_MF2_MASK,
21340 0 : 7498 => Opcode::PseudoVNMSAC_VX_MF4,
21341 0 : 7499 => Opcode::PseudoVNMSAC_VX_MF4_MASK,
21342 0 : 7500 => Opcode::PseudoVNMSAC_VX_MF8,
21343 0 : 7501 => Opcode::PseudoVNMSAC_VX_MF8_MASK,
21344 0 : 7502 => Opcode::PseudoVNMSUB_VV_M1,
21345 0 : 7503 => Opcode::PseudoVNMSUB_VV_M1_MASK,
21346 0 : 7504 => Opcode::PseudoVNMSUB_VV_M2,
21347 0 : 7505 => Opcode::PseudoVNMSUB_VV_M2_MASK,
21348 0 : 7506 => Opcode::PseudoVNMSUB_VV_M4,
21349 0 : 7507 => Opcode::PseudoVNMSUB_VV_M4_MASK,
21350 0 : 7508 => Opcode::PseudoVNMSUB_VV_M8,
21351 0 : 7509 => Opcode::PseudoVNMSUB_VV_M8_MASK,
21352 0 : 7510 => Opcode::PseudoVNMSUB_VV_MF2,
21353 0 : 7511 => Opcode::PseudoVNMSUB_VV_MF2_MASK,
21354 0 : 7512 => Opcode::PseudoVNMSUB_VV_MF4,
21355 0 : 7513 => Opcode::PseudoVNMSUB_VV_MF4_MASK,
21356 0 : 7514 => Opcode::PseudoVNMSUB_VV_MF8,
21357 0 : 7515 => Opcode::PseudoVNMSUB_VV_MF8_MASK,
21358 0 : 7516 => Opcode::PseudoVNMSUB_VX_M1,
21359 0 : 7517 => Opcode::PseudoVNMSUB_VX_M1_MASK,
21360 0 : 7518 => Opcode::PseudoVNMSUB_VX_M2,
21361 0 : 7519 => Opcode::PseudoVNMSUB_VX_M2_MASK,
21362 0 : 7520 => Opcode::PseudoVNMSUB_VX_M4,
21363 0 : 7521 => Opcode::PseudoVNMSUB_VX_M4_MASK,
21364 0 : 7522 => Opcode::PseudoVNMSUB_VX_M8,
21365 0 : 7523 => Opcode::PseudoVNMSUB_VX_M8_MASK,
21366 0 : 7524 => Opcode::PseudoVNMSUB_VX_MF2,
21367 0 : 7525 => Opcode::PseudoVNMSUB_VX_MF2_MASK,
21368 0 : 7526 => Opcode::PseudoVNMSUB_VX_MF4,
21369 0 : 7527 => Opcode::PseudoVNMSUB_VX_MF4_MASK,
21370 0 : 7528 => Opcode::PseudoVNMSUB_VX_MF8,
21371 0 : 7529 => Opcode::PseudoVNMSUB_VX_MF8_MASK,
21372 0 : 7530 => Opcode::PseudoVNSRA_WI_M1,
21373 0 : 7531 => Opcode::PseudoVNSRA_WI_M1_MASK,
21374 0 : 7532 => Opcode::PseudoVNSRA_WI_M2,
21375 0 : 7533 => Opcode::PseudoVNSRA_WI_M2_MASK,
21376 0 : 7534 => Opcode::PseudoVNSRA_WI_M4,
21377 0 : 7535 => Opcode::PseudoVNSRA_WI_M4_MASK,
21378 0 : 7536 => Opcode::PseudoVNSRA_WI_MF2,
21379 0 : 7537 => Opcode::PseudoVNSRA_WI_MF2_MASK,
21380 0 : 7538 => Opcode::PseudoVNSRA_WI_MF4,
21381 0 : 7539 => Opcode::PseudoVNSRA_WI_MF4_MASK,
21382 0 : 7540 => Opcode::PseudoVNSRA_WI_MF8,
21383 0 : 7541 => Opcode::PseudoVNSRA_WI_MF8_MASK,
21384 0 : 7542 => Opcode::PseudoVNSRA_WV_M1,
21385 0 : 7543 => Opcode::PseudoVNSRA_WV_M1_MASK,
21386 0 : 7544 => Opcode::PseudoVNSRA_WV_M2,
21387 0 : 7545 => Opcode::PseudoVNSRA_WV_M2_MASK,
21388 0 : 7546 => Opcode::PseudoVNSRA_WV_M4,
21389 0 : 7547 => Opcode::PseudoVNSRA_WV_M4_MASK,
21390 0 : 7548 => Opcode::PseudoVNSRA_WV_MF2,
21391 0 : 7549 => Opcode::PseudoVNSRA_WV_MF2_MASK,
21392 0 : 7550 => Opcode::PseudoVNSRA_WV_MF4,
21393 0 : 7551 => Opcode::PseudoVNSRA_WV_MF4_MASK,
21394 0 : 7552 => Opcode::PseudoVNSRA_WV_MF8,
21395 0 : 7553 => Opcode::PseudoVNSRA_WV_MF8_MASK,
21396 0 : 7554 => Opcode::PseudoVNSRA_WX_M1,
21397 0 : 7555 => Opcode::PseudoVNSRA_WX_M1_MASK,
21398 0 : 7556 => Opcode::PseudoVNSRA_WX_M2,
21399 0 : 7557 => Opcode::PseudoVNSRA_WX_M2_MASK,
21400 0 : 7558 => Opcode::PseudoVNSRA_WX_M4,
21401 0 : 7559 => Opcode::PseudoVNSRA_WX_M4_MASK,
21402 0 : 7560 => Opcode::PseudoVNSRA_WX_MF2,
21403 0 : 7561 => Opcode::PseudoVNSRA_WX_MF2_MASK,
21404 0 : 7562 => Opcode::PseudoVNSRA_WX_MF4,
21405 0 : 7563 => Opcode::PseudoVNSRA_WX_MF4_MASK,
21406 0 : 7564 => Opcode::PseudoVNSRA_WX_MF8,
21407 0 : 7565 => Opcode::PseudoVNSRA_WX_MF8_MASK,
21408 0 : 7566 => Opcode::PseudoVNSRL_WI_M1,
21409 0 : 7567 => Opcode::PseudoVNSRL_WI_M1_MASK,
21410 0 : 7568 => Opcode::PseudoVNSRL_WI_M2,
21411 0 : 7569 => Opcode::PseudoVNSRL_WI_M2_MASK,
21412 0 : 7570 => Opcode::PseudoVNSRL_WI_M4,
21413 0 : 7571 => Opcode::PseudoVNSRL_WI_M4_MASK,
21414 0 : 7572 => Opcode::PseudoVNSRL_WI_MF2,
21415 0 : 7573 => Opcode::PseudoVNSRL_WI_MF2_MASK,
21416 0 : 7574 => Opcode::PseudoVNSRL_WI_MF4,
21417 0 : 7575 => Opcode::PseudoVNSRL_WI_MF4_MASK,
21418 0 : 7576 => Opcode::PseudoVNSRL_WI_MF8,
21419 0 : 7577 => Opcode::PseudoVNSRL_WI_MF8_MASK,
21420 0 : 7578 => Opcode::PseudoVNSRL_WV_M1,
21421 0 : 7579 => Opcode::PseudoVNSRL_WV_M1_MASK,
21422 0 : 7580 => Opcode::PseudoVNSRL_WV_M2,
21423 0 : 7581 => Opcode::PseudoVNSRL_WV_M2_MASK,
21424 0 : 7582 => Opcode::PseudoVNSRL_WV_M4,
21425 0 : 7583 => Opcode::PseudoVNSRL_WV_M4_MASK,
21426 0 : 7584 => Opcode::PseudoVNSRL_WV_MF2,
21427 0 : 7585 => Opcode::PseudoVNSRL_WV_MF2_MASK,
21428 0 : 7586 => Opcode::PseudoVNSRL_WV_MF4,
21429 0 : 7587 => Opcode::PseudoVNSRL_WV_MF4_MASK,
21430 0 : 7588 => Opcode::PseudoVNSRL_WV_MF8,
21431 0 : 7589 => Opcode::PseudoVNSRL_WV_MF8_MASK,
21432 0 : 7590 => Opcode::PseudoVNSRL_WX_M1,
21433 0 : 7591 => Opcode::PseudoVNSRL_WX_M1_MASK,
21434 0 : 7592 => Opcode::PseudoVNSRL_WX_M2,
21435 0 : 7593 => Opcode::PseudoVNSRL_WX_M2_MASK,
21436 0 : 7594 => Opcode::PseudoVNSRL_WX_M4,
21437 0 : 7595 => Opcode::PseudoVNSRL_WX_M4_MASK,
21438 0 : 7596 => Opcode::PseudoVNSRL_WX_MF2,
21439 0 : 7597 => Opcode::PseudoVNSRL_WX_MF2_MASK,
21440 0 : 7598 => Opcode::PseudoVNSRL_WX_MF4,
21441 0 : 7599 => Opcode::PseudoVNSRL_WX_MF4_MASK,
21442 0 : 7600 => Opcode::PseudoVNSRL_WX_MF8,
21443 0 : 7601 => Opcode::PseudoVNSRL_WX_MF8_MASK,
21444 0 : 7602 => Opcode::PseudoVOR_VI_M1,
21445 0 : 7603 => Opcode::PseudoVOR_VI_M1_MASK,
21446 0 : 7604 => Opcode::PseudoVOR_VI_M2,
21447 0 : 7605 => Opcode::PseudoVOR_VI_M2_MASK,
21448 0 : 7606 => Opcode::PseudoVOR_VI_M4,
21449 0 : 7607 => Opcode::PseudoVOR_VI_M4_MASK,
21450 0 : 7608 => Opcode::PseudoVOR_VI_M8,
21451 0 : 7609 => Opcode::PseudoVOR_VI_M8_MASK,
21452 0 : 7610 => Opcode::PseudoVOR_VI_MF2,
21453 0 : 7611 => Opcode::PseudoVOR_VI_MF2_MASK,
21454 0 : 7612 => Opcode::PseudoVOR_VI_MF4,
21455 0 : 7613 => Opcode::PseudoVOR_VI_MF4_MASK,
21456 0 : 7614 => Opcode::PseudoVOR_VI_MF8,
21457 0 : 7615 => Opcode::PseudoVOR_VI_MF8_MASK,
21458 0 : 7616 => Opcode::PseudoVOR_VV_M1,
21459 0 : 7617 => Opcode::PseudoVOR_VV_M1_MASK,
21460 0 : 7618 => Opcode::PseudoVOR_VV_M2,
21461 0 : 7619 => Opcode::PseudoVOR_VV_M2_MASK,
21462 0 : 7620 => Opcode::PseudoVOR_VV_M4,
21463 0 : 7621 => Opcode::PseudoVOR_VV_M4_MASK,
21464 0 : 7622 => Opcode::PseudoVOR_VV_M8,
21465 0 : 7623 => Opcode::PseudoVOR_VV_M8_MASK,
21466 0 : 7624 => Opcode::PseudoVOR_VV_MF2,
21467 0 : 7625 => Opcode::PseudoVOR_VV_MF2_MASK,
21468 0 : 7626 => Opcode::PseudoVOR_VV_MF4,
21469 0 : 7627 => Opcode::PseudoVOR_VV_MF4_MASK,
21470 0 : 7628 => Opcode::PseudoVOR_VV_MF8,
21471 0 : 7629 => Opcode::PseudoVOR_VV_MF8_MASK,
21472 0 : 7630 => Opcode::PseudoVOR_VX_M1,
21473 0 : 7631 => Opcode::PseudoVOR_VX_M1_MASK,
21474 0 : 7632 => Opcode::PseudoVOR_VX_M2,
21475 0 : 7633 => Opcode::PseudoVOR_VX_M2_MASK,
21476 0 : 7634 => Opcode::PseudoVOR_VX_M4,
21477 0 : 7635 => Opcode::PseudoVOR_VX_M4_MASK,
21478 0 : 7636 => Opcode::PseudoVOR_VX_M8,
21479 0 : 7637 => Opcode::PseudoVOR_VX_M8_MASK,
21480 0 : 7638 => Opcode::PseudoVOR_VX_MF2,
21481 0 : 7639 => Opcode::PseudoVOR_VX_MF2_MASK,
21482 0 : 7640 => Opcode::PseudoVOR_VX_MF4,
21483 0 : 7641 => Opcode::PseudoVOR_VX_MF4_MASK,
21484 0 : 7642 => Opcode::PseudoVOR_VX_MF8,
21485 0 : 7643 => Opcode::PseudoVOR_VX_MF8_MASK,
21486 0 : 7644 => Opcode::PseudoVQMACCSU_2x8x2_M1,
21487 0 : 7645 => Opcode::PseudoVQMACCSU_2x8x2_M2,
21488 0 : 7646 => Opcode::PseudoVQMACCSU_2x8x2_M4,
21489 0 : 7647 => Opcode::PseudoVQMACCSU_2x8x2_M8,
21490 0 : 7648 => Opcode::PseudoVQMACCSU_4x8x4_M1,
21491 0 : 7649 => Opcode::PseudoVQMACCSU_4x8x4_M2,
21492 0 : 7650 => Opcode::PseudoVQMACCSU_4x8x4_M4,
21493 0 : 7651 => Opcode::PseudoVQMACCSU_4x8x4_MF2,
21494 0 : 7652 => Opcode::PseudoVQMACCUS_2x8x2_M1,
21495 0 : 7653 => Opcode::PseudoVQMACCUS_2x8x2_M2,
21496 0 : 7654 => Opcode::PseudoVQMACCUS_2x8x2_M4,
21497 0 : 7655 => Opcode::PseudoVQMACCUS_2x8x2_M8,
21498 0 : 7656 => Opcode::PseudoVQMACCUS_4x8x4_M1,
21499 0 : 7657 => Opcode::PseudoVQMACCUS_4x8x4_M2,
21500 0 : 7658 => Opcode::PseudoVQMACCUS_4x8x4_M4,
21501 0 : 7659 => Opcode::PseudoVQMACCUS_4x8x4_MF2,
21502 0 : 7660 => Opcode::PseudoVQMACCU_2x8x2_M1,
21503 0 : 7661 => Opcode::PseudoVQMACCU_2x8x2_M2,
21504 0 : 7662 => Opcode::PseudoVQMACCU_2x8x2_M4,
21505 0 : 7663 => Opcode::PseudoVQMACCU_2x8x2_M8,
21506 0 : 7664 => Opcode::PseudoVQMACCU_4x8x4_M1,
21507 0 : 7665 => Opcode::PseudoVQMACCU_4x8x4_M2,
21508 0 : 7666 => Opcode::PseudoVQMACCU_4x8x4_M4,
21509 0 : 7667 => Opcode::PseudoVQMACCU_4x8x4_MF2,
21510 0 : 7668 => Opcode::PseudoVQMACC_2x8x2_M1,
21511 0 : 7669 => Opcode::PseudoVQMACC_2x8x2_M2,
21512 0 : 7670 => Opcode::PseudoVQMACC_2x8x2_M4,
21513 0 : 7671 => Opcode::PseudoVQMACC_2x8x2_M8,
21514 0 : 7672 => Opcode::PseudoVQMACC_4x8x4_M1,
21515 0 : 7673 => Opcode::PseudoVQMACC_4x8x4_M2,
21516 0 : 7674 => Opcode::PseudoVQMACC_4x8x4_M4,
21517 0 : 7675 => Opcode::PseudoVQMACC_4x8x4_MF2,
21518 0 : 7676 => Opcode::PseudoVREDAND_VS_M1_E16,
21519 0 : 7677 => Opcode::PseudoVREDAND_VS_M1_E16_MASK,
21520 0 : 7678 => Opcode::PseudoVREDAND_VS_M1_E32,
21521 0 : 7679 => Opcode::PseudoVREDAND_VS_M1_E32_MASK,
21522 0 : 7680 => Opcode::PseudoVREDAND_VS_M1_E64,
21523 0 : 7681 => Opcode::PseudoVREDAND_VS_M1_E64_MASK,
21524 0 : 7682 => Opcode::PseudoVREDAND_VS_M1_E8,
21525 0 : 7683 => Opcode::PseudoVREDAND_VS_M1_E8_MASK,
21526 0 : 7684 => Opcode::PseudoVREDAND_VS_M2_E16,
21527 0 : 7685 => Opcode::PseudoVREDAND_VS_M2_E16_MASK,
21528 0 : 7686 => Opcode::PseudoVREDAND_VS_M2_E32,
21529 0 : 7687 => Opcode::PseudoVREDAND_VS_M2_E32_MASK,
21530 0 : 7688 => Opcode::PseudoVREDAND_VS_M2_E64,
21531 0 : 7689 => Opcode::PseudoVREDAND_VS_M2_E64_MASK,
21532 0 : 7690 => Opcode::PseudoVREDAND_VS_M2_E8,
21533 0 : 7691 => Opcode::PseudoVREDAND_VS_M2_E8_MASK,
21534 0 : 7692 => Opcode::PseudoVREDAND_VS_M4_E16,
21535 0 : 7693 => Opcode::PseudoVREDAND_VS_M4_E16_MASK,
21536 0 : 7694 => Opcode::PseudoVREDAND_VS_M4_E32,
21537 0 : 7695 => Opcode::PseudoVREDAND_VS_M4_E32_MASK,
21538 0 : 7696 => Opcode::PseudoVREDAND_VS_M4_E64,
21539 0 : 7697 => Opcode::PseudoVREDAND_VS_M4_E64_MASK,
21540 0 : 7698 => Opcode::PseudoVREDAND_VS_M4_E8,
21541 0 : 7699 => Opcode::PseudoVREDAND_VS_M4_E8_MASK,
21542 0 : 7700 => Opcode::PseudoVREDAND_VS_M8_E16,
21543 0 : 7701 => Opcode::PseudoVREDAND_VS_M8_E16_MASK,
21544 0 : 7702 => Opcode::PseudoVREDAND_VS_M8_E32,
21545 0 : 7703 => Opcode::PseudoVREDAND_VS_M8_E32_MASK,
21546 0 : 7704 => Opcode::PseudoVREDAND_VS_M8_E64,
21547 0 : 7705 => Opcode::PseudoVREDAND_VS_M8_E64_MASK,
21548 0 : 7706 => Opcode::PseudoVREDAND_VS_M8_E8,
21549 0 : 7707 => Opcode::PseudoVREDAND_VS_M8_E8_MASK,
21550 0 : 7708 => Opcode::PseudoVREDAND_VS_MF2_E16,
21551 0 : 7709 => Opcode::PseudoVREDAND_VS_MF2_E16_MASK,
21552 0 : 7710 => Opcode::PseudoVREDAND_VS_MF2_E32,
21553 0 : 7711 => Opcode::PseudoVREDAND_VS_MF2_E32_MASK,
21554 0 : 7712 => Opcode::PseudoVREDAND_VS_MF2_E8,
21555 0 : 7713 => Opcode::PseudoVREDAND_VS_MF2_E8_MASK,
21556 0 : 7714 => Opcode::PseudoVREDAND_VS_MF4_E16,
21557 0 : 7715 => Opcode::PseudoVREDAND_VS_MF4_E16_MASK,
21558 0 : 7716 => Opcode::PseudoVREDAND_VS_MF4_E8,
21559 0 : 7717 => Opcode::PseudoVREDAND_VS_MF4_E8_MASK,
21560 0 : 7718 => Opcode::PseudoVREDAND_VS_MF8_E8,
21561 0 : 7719 => Opcode::PseudoVREDAND_VS_MF8_E8_MASK,
21562 0 : 7720 => Opcode::PseudoVREDMAXU_VS_M1_E16,
21563 0 : 7721 => Opcode::PseudoVREDMAXU_VS_M1_E16_MASK,
21564 0 : 7722 => Opcode::PseudoVREDMAXU_VS_M1_E32,
21565 0 : 7723 => Opcode::PseudoVREDMAXU_VS_M1_E32_MASK,
21566 0 : 7724 => Opcode::PseudoVREDMAXU_VS_M1_E64,
21567 0 : 7725 => Opcode::PseudoVREDMAXU_VS_M1_E64_MASK,
21568 0 : 7726 => Opcode::PseudoVREDMAXU_VS_M1_E8,
21569 0 : 7727 => Opcode::PseudoVREDMAXU_VS_M1_E8_MASK,
21570 0 : 7728 => Opcode::PseudoVREDMAXU_VS_M2_E16,
21571 0 : 7729 => Opcode::PseudoVREDMAXU_VS_M2_E16_MASK,
21572 0 : 7730 => Opcode::PseudoVREDMAXU_VS_M2_E32,
21573 0 : 7731 => Opcode::PseudoVREDMAXU_VS_M2_E32_MASK,
21574 0 : 7732 => Opcode::PseudoVREDMAXU_VS_M2_E64,
21575 0 : 7733 => Opcode::PseudoVREDMAXU_VS_M2_E64_MASK,
21576 0 : 7734 => Opcode::PseudoVREDMAXU_VS_M2_E8,
21577 0 : 7735 => Opcode::PseudoVREDMAXU_VS_M2_E8_MASK,
21578 0 : 7736 => Opcode::PseudoVREDMAXU_VS_M4_E16,
21579 0 : 7737 => Opcode::PseudoVREDMAXU_VS_M4_E16_MASK,
21580 0 : 7738 => Opcode::PseudoVREDMAXU_VS_M4_E32,
21581 0 : 7739 => Opcode::PseudoVREDMAXU_VS_M4_E32_MASK,
21582 0 : 7740 => Opcode::PseudoVREDMAXU_VS_M4_E64,
21583 0 : 7741 => Opcode::PseudoVREDMAXU_VS_M4_E64_MASK,
21584 0 : 7742 => Opcode::PseudoVREDMAXU_VS_M4_E8,
21585 0 : 7743 => Opcode::PseudoVREDMAXU_VS_M4_E8_MASK,
21586 0 : 7744 => Opcode::PseudoVREDMAXU_VS_M8_E16,
21587 0 : 7745 => Opcode::PseudoVREDMAXU_VS_M8_E16_MASK,
21588 0 : 7746 => Opcode::PseudoVREDMAXU_VS_M8_E32,
21589 0 : 7747 => Opcode::PseudoVREDMAXU_VS_M8_E32_MASK,
21590 0 : 7748 => Opcode::PseudoVREDMAXU_VS_M8_E64,
21591 0 : 7749 => Opcode::PseudoVREDMAXU_VS_M8_E64_MASK,
21592 0 : 7750 => Opcode::PseudoVREDMAXU_VS_M8_E8,
21593 0 : 7751 => Opcode::PseudoVREDMAXU_VS_M8_E8_MASK,
21594 0 : 7752 => Opcode::PseudoVREDMAXU_VS_MF2_E16,
21595 0 : 7753 => Opcode::PseudoVREDMAXU_VS_MF2_E16_MASK,
21596 0 : 7754 => Opcode::PseudoVREDMAXU_VS_MF2_E32,
21597 0 : 7755 => Opcode::PseudoVREDMAXU_VS_MF2_E32_MASK,
21598 0 : 7756 => Opcode::PseudoVREDMAXU_VS_MF2_E8,
21599 0 : 7757 => Opcode::PseudoVREDMAXU_VS_MF2_E8_MASK,
21600 0 : 7758 => Opcode::PseudoVREDMAXU_VS_MF4_E16,
21601 0 : 7759 => Opcode::PseudoVREDMAXU_VS_MF4_E16_MASK,
21602 0 : 7760 => Opcode::PseudoVREDMAXU_VS_MF4_E8,
21603 0 : 7761 => Opcode::PseudoVREDMAXU_VS_MF4_E8_MASK,
21604 0 : 7762 => Opcode::PseudoVREDMAXU_VS_MF8_E8,
21605 0 : 7763 => Opcode::PseudoVREDMAXU_VS_MF8_E8_MASK,
21606 0 : 7764 => Opcode::PseudoVREDMAX_VS_M1_E16,
21607 0 : 7765 => Opcode::PseudoVREDMAX_VS_M1_E16_MASK,
21608 0 : 7766 => Opcode::PseudoVREDMAX_VS_M1_E32,
21609 0 : 7767 => Opcode::PseudoVREDMAX_VS_M1_E32_MASK,
21610 0 : 7768 => Opcode::PseudoVREDMAX_VS_M1_E64,
21611 0 : 7769 => Opcode::PseudoVREDMAX_VS_M1_E64_MASK,
21612 0 : 7770 => Opcode::PseudoVREDMAX_VS_M1_E8,
21613 0 : 7771 => Opcode::PseudoVREDMAX_VS_M1_E8_MASK,
21614 0 : 7772 => Opcode::PseudoVREDMAX_VS_M2_E16,
21615 0 : 7773 => Opcode::PseudoVREDMAX_VS_M2_E16_MASK,
21616 0 : 7774 => Opcode::PseudoVREDMAX_VS_M2_E32,
21617 0 : 7775 => Opcode::PseudoVREDMAX_VS_M2_E32_MASK,
21618 0 : 7776 => Opcode::PseudoVREDMAX_VS_M2_E64,
21619 0 : 7777 => Opcode::PseudoVREDMAX_VS_M2_E64_MASK,
21620 0 : 7778 => Opcode::PseudoVREDMAX_VS_M2_E8,
21621 0 : 7779 => Opcode::PseudoVREDMAX_VS_M2_E8_MASK,
21622 0 : 7780 => Opcode::PseudoVREDMAX_VS_M4_E16,
21623 0 : 7781 => Opcode::PseudoVREDMAX_VS_M4_E16_MASK,
21624 0 : 7782 => Opcode::PseudoVREDMAX_VS_M4_E32,
21625 0 : 7783 => Opcode::PseudoVREDMAX_VS_M4_E32_MASK,
21626 0 : 7784 => Opcode::PseudoVREDMAX_VS_M4_E64,
21627 0 : 7785 => Opcode::PseudoVREDMAX_VS_M4_E64_MASK,
21628 0 : 7786 => Opcode::PseudoVREDMAX_VS_M4_E8,
21629 0 : 7787 => Opcode::PseudoVREDMAX_VS_M4_E8_MASK,
21630 0 : 7788 => Opcode::PseudoVREDMAX_VS_M8_E16,
21631 0 : 7789 => Opcode::PseudoVREDMAX_VS_M8_E16_MASK,
21632 0 : 7790 => Opcode::PseudoVREDMAX_VS_M8_E32,
21633 0 : 7791 => Opcode::PseudoVREDMAX_VS_M8_E32_MASK,
21634 0 : 7792 => Opcode::PseudoVREDMAX_VS_M8_E64,
21635 0 : 7793 => Opcode::PseudoVREDMAX_VS_M8_E64_MASK,
21636 0 : 7794 => Opcode::PseudoVREDMAX_VS_M8_E8,
21637 0 : 7795 => Opcode::PseudoVREDMAX_VS_M8_E8_MASK,
21638 0 : 7796 => Opcode::PseudoVREDMAX_VS_MF2_E16,
21639 0 : 7797 => Opcode::PseudoVREDMAX_VS_MF2_E16_MASK,
21640 0 : 7798 => Opcode::PseudoVREDMAX_VS_MF2_E32,
21641 0 : 7799 => Opcode::PseudoVREDMAX_VS_MF2_E32_MASK,
21642 0 : 7800 => Opcode::PseudoVREDMAX_VS_MF2_E8,
21643 0 : 7801 => Opcode::PseudoVREDMAX_VS_MF2_E8_MASK,
21644 0 : 7802 => Opcode::PseudoVREDMAX_VS_MF4_E16,
21645 0 : 7803 => Opcode::PseudoVREDMAX_VS_MF4_E16_MASK,
21646 0 : 7804 => Opcode::PseudoVREDMAX_VS_MF4_E8,
21647 0 : 7805 => Opcode::PseudoVREDMAX_VS_MF4_E8_MASK,
21648 0 : 7806 => Opcode::PseudoVREDMAX_VS_MF8_E8,
21649 0 : 7807 => Opcode::PseudoVREDMAX_VS_MF8_E8_MASK,
21650 0 : 7808 => Opcode::PseudoVREDMINU_VS_M1_E16,
21651 0 : 7809 => Opcode::PseudoVREDMINU_VS_M1_E16_MASK,
21652 0 : 7810 => Opcode::PseudoVREDMINU_VS_M1_E32,
21653 0 : 7811 => Opcode::PseudoVREDMINU_VS_M1_E32_MASK,
21654 0 : 7812 => Opcode::PseudoVREDMINU_VS_M1_E64,
21655 0 : 7813 => Opcode::PseudoVREDMINU_VS_M1_E64_MASK,
21656 0 : 7814 => Opcode::PseudoVREDMINU_VS_M1_E8,
21657 0 : 7815 => Opcode::PseudoVREDMINU_VS_M1_E8_MASK,
21658 0 : 7816 => Opcode::PseudoVREDMINU_VS_M2_E16,
21659 0 : 7817 => Opcode::PseudoVREDMINU_VS_M2_E16_MASK,
21660 0 : 7818 => Opcode::PseudoVREDMINU_VS_M2_E32,
21661 0 : 7819 => Opcode::PseudoVREDMINU_VS_M2_E32_MASK,
21662 0 : 7820 => Opcode::PseudoVREDMINU_VS_M2_E64,
21663 0 : 7821 => Opcode::PseudoVREDMINU_VS_M2_E64_MASK,
21664 0 : 7822 => Opcode::PseudoVREDMINU_VS_M2_E8,
21665 0 : 7823 => Opcode::PseudoVREDMINU_VS_M2_E8_MASK,
21666 0 : 7824 => Opcode::PseudoVREDMINU_VS_M4_E16,
21667 0 : 7825 => Opcode::PseudoVREDMINU_VS_M4_E16_MASK,
21668 0 : 7826 => Opcode::PseudoVREDMINU_VS_M4_E32,
21669 0 : 7827 => Opcode::PseudoVREDMINU_VS_M4_E32_MASK,
21670 0 : 7828 => Opcode::PseudoVREDMINU_VS_M4_E64,
21671 0 : 7829 => Opcode::PseudoVREDMINU_VS_M4_E64_MASK,
21672 0 : 7830 => Opcode::PseudoVREDMINU_VS_M4_E8,
21673 0 : 7831 => Opcode::PseudoVREDMINU_VS_M4_E8_MASK,
21674 0 : 7832 => Opcode::PseudoVREDMINU_VS_M8_E16,
21675 0 : 7833 => Opcode::PseudoVREDMINU_VS_M8_E16_MASK,
21676 0 : 7834 => Opcode::PseudoVREDMINU_VS_M8_E32,
21677 0 : 7835 => Opcode::PseudoVREDMINU_VS_M8_E32_MASK,
21678 0 : 7836 => Opcode::PseudoVREDMINU_VS_M8_E64,
21679 0 : 7837 => Opcode::PseudoVREDMINU_VS_M8_E64_MASK,
21680 0 : 7838 => Opcode::PseudoVREDMINU_VS_M8_E8,
21681 0 : 7839 => Opcode::PseudoVREDMINU_VS_M8_E8_MASK,
21682 0 : 7840 => Opcode::PseudoVREDMINU_VS_MF2_E16,
21683 0 : 7841 => Opcode::PseudoVREDMINU_VS_MF2_E16_MASK,
21684 0 : 7842 => Opcode::PseudoVREDMINU_VS_MF2_E32,
21685 0 : 7843 => Opcode::PseudoVREDMINU_VS_MF2_E32_MASK,
21686 0 : 7844 => Opcode::PseudoVREDMINU_VS_MF2_E8,
21687 0 : 7845 => Opcode::PseudoVREDMINU_VS_MF2_E8_MASK,
21688 0 : 7846 => Opcode::PseudoVREDMINU_VS_MF4_E16,
21689 0 : 7847 => Opcode::PseudoVREDMINU_VS_MF4_E16_MASK,
21690 0 : 7848 => Opcode::PseudoVREDMINU_VS_MF4_E8,
21691 0 : 7849 => Opcode::PseudoVREDMINU_VS_MF4_E8_MASK,
21692 0 : 7850 => Opcode::PseudoVREDMINU_VS_MF8_E8,
21693 0 : 7851 => Opcode::PseudoVREDMINU_VS_MF8_E8_MASK,
21694 0 : 7852 => Opcode::PseudoVREDMIN_VS_M1_E16,
21695 0 : 7853 => Opcode::PseudoVREDMIN_VS_M1_E16_MASK,
21696 0 : 7854 => Opcode::PseudoVREDMIN_VS_M1_E32,
21697 0 : 7855 => Opcode::PseudoVREDMIN_VS_M1_E32_MASK,
21698 0 : 7856 => Opcode::PseudoVREDMIN_VS_M1_E64,
21699 0 : 7857 => Opcode::PseudoVREDMIN_VS_M1_E64_MASK,
21700 0 : 7858 => Opcode::PseudoVREDMIN_VS_M1_E8,
21701 0 : 7859 => Opcode::PseudoVREDMIN_VS_M1_E8_MASK,
21702 0 : 7860 => Opcode::PseudoVREDMIN_VS_M2_E16,
21703 0 : 7861 => Opcode::PseudoVREDMIN_VS_M2_E16_MASK,
21704 0 : 7862 => Opcode::PseudoVREDMIN_VS_M2_E32,
21705 0 : 7863 => Opcode::PseudoVREDMIN_VS_M2_E32_MASK,
21706 0 : 7864 => Opcode::PseudoVREDMIN_VS_M2_E64,
21707 0 : 7865 => Opcode::PseudoVREDMIN_VS_M2_E64_MASK,
21708 0 : 7866 => Opcode::PseudoVREDMIN_VS_M2_E8,
21709 0 : 7867 => Opcode::PseudoVREDMIN_VS_M2_E8_MASK,
21710 0 : 7868 => Opcode::PseudoVREDMIN_VS_M4_E16,
21711 0 : 7869 => Opcode::PseudoVREDMIN_VS_M4_E16_MASK,
21712 0 : 7870 => Opcode::PseudoVREDMIN_VS_M4_E32,
21713 0 : 7871 => Opcode::PseudoVREDMIN_VS_M4_E32_MASK,
21714 0 : 7872 => Opcode::PseudoVREDMIN_VS_M4_E64,
21715 0 : 7873 => Opcode::PseudoVREDMIN_VS_M4_E64_MASK,
21716 0 : 7874 => Opcode::PseudoVREDMIN_VS_M4_E8,
21717 0 : 7875 => Opcode::PseudoVREDMIN_VS_M4_E8_MASK,
21718 0 : 7876 => Opcode::PseudoVREDMIN_VS_M8_E16,
21719 0 : 7877 => Opcode::PseudoVREDMIN_VS_M8_E16_MASK,
21720 0 : 7878 => Opcode::PseudoVREDMIN_VS_M8_E32,
21721 0 : 7879 => Opcode::PseudoVREDMIN_VS_M8_E32_MASK,
21722 0 : 7880 => Opcode::PseudoVREDMIN_VS_M8_E64,
21723 0 : 7881 => Opcode::PseudoVREDMIN_VS_M8_E64_MASK,
21724 0 : 7882 => Opcode::PseudoVREDMIN_VS_M8_E8,
21725 0 : 7883 => Opcode::PseudoVREDMIN_VS_M8_E8_MASK,
21726 0 : 7884 => Opcode::PseudoVREDMIN_VS_MF2_E16,
21727 0 : 7885 => Opcode::PseudoVREDMIN_VS_MF2_E16_MASK,
21728 0 : 7886 => Opcode::PseudoVREDMIN_VS_MF2_E32,
21729 0 : 7887 => Opcode::PseudoVREDMIN_VS_MF2_E32_MASK,
21730 0 : 7888 => Opcode::PseudoVREDMIN_VS_MF2_E8,
21731 0 : 7889 => Opcode::PseudoVREDMIN_VS_MF2_E8_MASK,
21732 0 : 7890 => Opcode::PseudoVREDMIN_VS_MF4_E16,
21733 0 : 7891 => Opcode::PseudoVREDMIN_VS_MF4_E16_MASK,
21734 0 : 7892 => Opcode::PseudoVREDMIN_VS_MF4_E8,
21735 0 : 7893 => Opcode::PseudoVREDMIN_VS_MF4_E8_MASK,
21736 0 : 7894 => Opcode::PseudoVREDMIN_VS_MF8_E8,
21737 0 : 7895 => Opcode::PseudoVREDMIN_VS_MF8_E8_MASK,
21738 0 : 7896 => Opcode::PseudoVREDOR_VS_M1_E16,
21739 0 : 7897 => Opcode::PseudoVREDOR_VS_M1_E16_MASK,
21740 0 : 7898 => Opcode::PseudoVREDOR_VS_M1_E32,
21741 0 : 7899 => Opcode::PseudoVREDOR_VS_M1_E32_MASK,
21742 0 : 7900 => Opcode::PseudoVREDOR_VS_M1_E64,
21743 0 : 7901 => Opcode::PseudoVREDOR_VS_M1_E64_MASK,
21744 0 : 7902 => Opcode::PseudoVREDOR_VS_M1_E8,
21745 0 : 7903 => Opcode::PseudoVREDOR_VS_M1_E8_MASK,
21746 0 : 7904 => Opcode::PseudoVREDOR_VS_M2_E16,
21747 0 : 7905 => Opcode::PseudoVREDOR_VS_M2_E16_MASK,
21748 0 : 7906 => Opcode::PseudoVREDOR_VS_M2_E32,
21749 0 : 7907 => Opcode::PseudoVREDOR_VS_M2_E32_MASK,
21750 0 : 7908 => Opcode::PseudoVREDOR_VS_M2_E64,
21751 0 : 7909 => Opcode::PseudoVREDOR_VS_M2_E64_MASK,
21752 0 : 7910 => Opcode::PseudoVREDOR_VS_M2_E8,
21753 0 : 7911 => Opcode::PseudoVREDOR_VS_M2_E8_MASK,
21754 0 : 7912 => Opcode::PseudoVREDOR_VS_M4_E16,
21755 0 : 7913 => Opcode::PseudoVREDOR_VS_M4_E16_MASK,
21756 0 : 7914 => Opcode::PseudoVREDOR_VS_M4_E32,
21757 0 : 7915 => Opcode::PseudoVREDOR_VS_M4_E32_MASK,
21758 0 : 7916 => Opcode::PseudoVREDOR_VS_M4_E64,
21759 0 : 7917 => Opcode::PseudoVREDOR_VS_M4_E64_MASK,
21760 0 : 7918 => Opcode::PseudoVREDOR_VS_M4_E8,
21761 0 : 7919 => Opcode::PseudoVREDOR_VS_M4_E8_MASK,
21762 0 : 7920 => Opcode::PseudoVREDOR_VS_M8_E16,
21763 0 : 7921 => Opcode::PseudoVREDOR_VS_M8_E16_MASK,
21764 0 : 7922 => Opcode::PseudoVREDOR_VS_M8_E32,
21765 0 : 7923 => Opcode::PseudoVREDOR_VS_M8_E32_MASK,
21766 0 : 7924 => Opcode::PseudoVREDOR_VS_M8_E64,
21767 0 : 7925 => Opcode::PseudoVREDOR_VS_M8_E64_MASK,
21768 0 : 7926 => Opcode::PseudoVREDOR_VS_M8_E8,
21769 0 : 7927 => Opcode::PseudoVREDOR_VS_M8_E8_MASK,
21770 0 : 7928 => Opcode::PseudoVREDOR_VS_MF2_E16,
21771 0 : 7929 => Opcode::PseudoVREDOR_VS_MF2_E16_MASK,
21772 0 : 7930 => Opcode::PseudoVREDOR_VS_MF2_E32,
21773 0 : 7931 => Opcode::PseudoVREDOR_VS_MF2_E32_MASK,
21774 0 : 7932 => Opcode::PseudoVREDOR_VS_MF2_E8,
21775 0 : 7933 => Opcode::PseudoVREDOR_VS_MF2_E8_MASK,
21776 0 : 7934 => Opcode::PseudoVREDOR_VS_MF4_E16,
21777 0 : 7935 => Opcode::PseudoVREDOR_VS_MF4_E16_MASK,
21778 0 : 7936 => Opcode::PseudoVREDOR_VS_MF4_E8,
21779 0 : 7937 => Opcode::PseudoVREDOR_VS_MF4_E8_MASK,
21780 0 : 7938 => Opcode::PseudoVREDOR_VS_MF8_E8,
21781 0 : 7939 => Opcode::PseudoVREDOR_VS_MF8_E8_MASK,
21782 0 : 7940 => Opcode::PseudoVREDSUM_VS_M1_E16,
21783 0 : 7941 => Opcode::PseudoVREDSUM_VS_M1_E16_MASK,
21784 0 : 7942 => Opcode::PseudoVREDSUM_VS_M1_E32,
21785 0 : 7943 => Opcode::PseudoVREDSUM_VS_M1_E32_MASK,
21786 0 : 7944 => Opcode::PseudoVREDSUM_VS_M1_E64,
21787 0 : 7945 => Opcode::PseudoVREDSUM_VS_M1_E64_MASK,
21788 0 : 7946 => Opcode::PseudoVREDSUM_VS_M1_E8,
21789 0 : 7947 => Opcode::PseudoVREDSUM_VS_M1_E8_MASK,
21790 0 : 7948 => Opcode::PseudoVREDSUM_VS_M2_E16,
21791 0 : 7949 => Opcode::PseudoVREDSUM_VS_M2_E16_MASK,
21792 0 : 7950 => Opcode::PseudoVREDSUM_VS_M2_E32,
21793 0 : 7951 => Opcode::PseudoVREDSUM_VS_M2_E32_MASK,
21794 0 : 7952 => Opcode::PseudoVREDSUM_VS_M2_E64,
21795 0 : 7953 => Opcode::PseudoVREDSUM_VS_M2_E64_MASK,
21796 0 : 7954 => Opcode::PseudoVREDSUM_VS_M2_E8,
21797 0 : 7955 => Opcode::PseudoVREDSUM_VS_M2_E8_MASK,
21798 0 : 7956 => Opcode::PseudoVREDSUM_VS_M4_E16,
21799 0 : 7957 => Opcode::PseudoVREDSUM_VS_M4_E16_MASK,
21800 0 : 7958 => Opcode::PseudoVREDSUM_VS_M4_E32,
21801 0 : 7959 => Opcode::PseudoVREDSUM_VS_M4_E32_MASK,
21802 0 : 7960 => Opcode::PseudoVREDSUM_VS_M4_E64,
21803 0 : 7961 => Opcode::PseudoVREDSUM_VS_M4_E64_MASK,
21804 0 : 7962 => Opcode::PseudoVREDSUM_VS_M4_E8,
21805 0 : 7963 => Opcode::PseudoVREDSUM_VS_M4_E8_MASK,
21806 0 : 7964 => Opcode::PseudoVREDSUM_VS_M8_E16,
21807 0 : 7965 => Opcode::PseudoVREDSUM_VS_M8_E16_MASK,
21808 0 : 7966 => Opcode::PseudoVREDSUM_VS_M8_E32,
21809 0 : 7967 => Opcode::PseudoVREDSUM_VS_M8_E32_MASK,
21810 0 : 7968 => Opcode::PseudoVREDSUM_VS_M8_E64,
21811 0 : 7969 => Opcode::PseudoVREDSUM_VS_M8_E64_MASK,
21812 0 : 7970 => Opcode::PseudoVREDSUM_VS_M8_E8,
21813 0 : 7971 => Opcode::PseudoVREDSUM_VS_M8_E8_MASK,
21814 0 : 7972 => Opcode::PseudoVREDSUM_VS_MF2_E16,
21815 0 : 7973 => Opcode::PseudoVREDSUM_VS_MF2_E16_MASK,
21816 0 : 7974 => Opcode::PseudoVREDSUM_VS_MF2_E32,
21817 0 : 7975 => Opcode::PseudoVREDSUM_VS_MF2_E32_MASK,
21818 0 : 7976 => Opcode::PseudoVREDSUM_VS_MF2_E8,
21819 0 : 7977 => Opcode::PseudoVREDSUM_VS_MF2_E8_MASK,
21820 0 : 7978 => Opcode::PseudoVREDSUM_VS_MF4_E16,
21821 0 : 7979 => Opcode::PseudoVREDSUM_VS_MF4_E16_MASK,
21822 0 : 7980 => Opcode::PseudoVREDSUM_VS_MF4_E8,
21823 0 : 7981 => Opcode::PseudoVREDSUM_VS_MF4_E8_MASK,
21824 0 : 7982 => Opcode::PseudoVREDSUM_VS_MF8_E8,
21825 0 : 7983 => Opcode::PseudoVREDSUM_VS_MF8_E8_MASK,
21826 0 : 7984 => Opcode::PseudoVREDXOR_VS_M1_E16,
21827 0 : 7985 => Opcode::PseudoVREDXOR_VS_M1_E16_MASK,
21828 0 : 7986 => Opcode::PseudoVREDXOR_VS_M1_E32,
21829 0 : 7987 => Opcode::PseudoVREDXOR_VS_M1_E32_MASK,
21830 0 : 7988 => Opcode::PseudoVREDXOR_VS_M1_E64,
21831 0 : 7989 => Opcode::PseudoVREDXOR_VS_M1_E64_MASK,
21832 0 : 7990 => Opcode::PseudoVREDXOR_VS_M1_E8,
21833 0 : 7991 => Opcode::PseudoVREDXOR_VS_M1_E8_MASK,
21834 0 : 7992 => Opcode::PseudoVREDXOR_VS_M2_E16,
21835 0 : 7993 => Opcode::PseudoVREDXOR_VS_M2_E16_MASK,
21836 0 : 7994 => Opcode::PseudoVREDXOR_VS_M2_E32,
21837 0 : 7995 => Opcode::PseudoVREDXOR_VS_M2_E32_MASK,
21838 0 : 7996 => Opcode::PseudoVREDXOR_VS_M2_E64,
21839 0 : 7997 => Opcode::PseudoVREDXOR_VS_M2_E64_MASK,
21840 0 : 7998 => Opcode::PseudoVREDXOR_VS_M2_E8,
21841 0 : 7999 => Opcode::PseudoVREDXOR_VS_M2_E8_MASK,
21842 0 : 8000 => Opcode::PseudoVREDXOR_VS_M4_E16,
21843 0 : 8001 => Opcode::PseudoVREDXOR_VS_M4_E16_MASK,
21844 0 : 8002 => Opcode::PseudoVREDXOR_VS_M4_E32,
21845 0 : 8003 => Opcode::PseudoVREDXOR_VS_M4_E32_MASK,
21846 0 : 8004 => Opcode::PseudoVREDXOR_VS_M4_E64,
21847 0 : 8005 => Opcode::PseudoVREDXOR_VS_M4_E64_MASK,
21848 0 : 8006 => Opcode::PseudoVREDXOR_VS_M4_E8,
21849 0 : 8007 => Opcode::PseudoVREDXOR_VS_M4_E8_MASK,
21850 0 : 8008 => Opcode::PseudoVREDXOR_VS_M8_E16,
21851 0 : 8009 => Opcode::PseudoVREDXOR_VS_M8_E16_MASK,
21852 0 : 8010 => Opcode::PseudoVREDXOR_VS_M8_E32,
21853 0 : 8011 => Opcode::PseudoVREDXOR_VS_M8_E32_MASK,
21854 0 : 8012 => Opcode::PseudoVREDXOR_VS_M8_E64,
21855 0 : 8013 => Opcode::PseudoVREDXOR_VS_M8_E64_MASK,
21856 0 : 8014 => Opcode::PseudoVREDXOR_VS_M8_E8,
21857 0 : 8015 => Opcode::PseudoVREDXOR_VS_M8_E8_MASK,
21858 0 : 8016 => Opcode::PseudoVREDXOR_VS_MF2_E16,
21859 0 : 8017 => Opcode::PseudoVREDXOR_VS_MF2_E16_MASK,
21860 0 : 8018 => Opcode::PseudoVREDXOR_VS_MF2_E32,
21861 0 : 8019 => Opcode::PseudoVREDXOR_VS_MF2_E32_MASK,
21862 0 : 8020 => Opcode::PseudoVREDXOR_VS_MF2_E8,
21863 0 : 8021 => Opcode::PseudoVREDXOR_VS_MF2_E8_MASK,
21864 0 : 8022 => Opcode::PseudoVREDXOR_VS_MF4_E16,
21865 0 : 8023 => Opcode::PseudoVREDXOR_VS_MF4_E16_MASK,
21866 0 : 8024 => Opcode::PseudoVREDXOR_VS_MF4_E8,
21867 0 : 8025 => Opcode::PseudoVREDXOR_VS_MF4_E8_MASK,
21868 0 : 8026 => Opcode::PseudoVREDXOR_VS_MF8_E8,
21869 0 : 8027 => Opcode::PseudoVREDXOR_VS_MF8_E8_MASK,
21870 0 : 8028 => Opcode::PseudoVRELOAD2_M1,
21871 0 : 8029 => Opcode::PseudoVRELOAD2_M2,
21872 0 : 8030 => Opcode::PseudoVRELOAD2_M4,
21873 0 : 8031 => Opcode::PseudoVRELOAD2_MF2,
21874 0 : 8032 => Opcode::PseudoVRELOAD2_MF4,
21875 0 : 8033 => Opcode::PseudoVRELOAD2_MF8,
21876 0 : 8034 => Opcode::PseudoVRELOAD3_M1,
21877 0 : 8035 => Opcode::PseudoVRELOAD3_M2,
21878 0 : 8036 => Opcode::PseudoVRELOAD3_MF2,
21879 0 : 8037 => Opcode::PseudoVRELOAD3_MF4,
21880 0 : 8038 => Opcode::PseudoVRELOAD3_MF8,
21881 0 : 8039 => Opcode::PseudoVRELOAD4_M1,
21882 0 : 8040 => Opcode::PseudoVRELOAD4_M2,
21883 0 : 8041 => Opcode::PseudoVRELOAD4_MF2,
21884 0 : 8042 => Opcode::PseudoVRELOAD4_MF4,
21885 0 : 8043 => Opcode::PseudoVRELOAD4_MF8,
21886 0 : 8044 => Opcode::PseudoVRELOAD5_M1,
21887 0 : 8045 => Opcode::PseudoVRELOAD5_MF2,
21888 0 : 8046 => Opcode::PseudoVRELOAD5_MF4,
21889 0 : 8047 => Opcode::PseudoVRELOAD5_MF8,
21890 0 : 8048 => Opcode::PseudoVRELOAD6_M1,
21891 0 : 8049 => Opcode::PseudoVRELOAD6_MF2,
21892 0 : 8050 => Opcode::PseudoVRELOAD6_MF4,
21893 0 : 8051 => Opcode::PseudoVRELOAD6_MF8,
21894 0 : 8052 => Opcode::PseudoVRELOAD7_M1,
21895 0 : 8053 => Opcode::PseudoVRELOAD7_MF2,
21896 0 : 8054 => Opcode::PseudoVRELOAD7_MF4,
21897 0 : 8055 => Opcode::PseudoVRELOAD7_MF8,
21898 0 : 8056 => Opcode::PseudoVRELOAD8_M1,
21899 0 : 8057 => Opcode::PseudoVRELOAD8_MF2,
21900 0 : 8058 => Opcode::PseudoVRELOAD8_MF4,
21901 0 : 8059 => Opcode::PseudoVRELOAD8_MF8,
21902 0 : 8060 => Opcode::PseudoVREMU_VV_M1_E16,
21903 0 : 8061 => Opcode::PseudoVREMU_VV_M1_E16_MASK,
21904 0 : 8062 => Opcode::PseudoVREMU_VV_M1_E32,
21905 0 : 8063 => Opcode::PseudoVREMU_VV_M1_E32_MASK,
21906 0 : 8064 => Opcode::PseudoVREMU_VV_M1_E64,
21907 0 : 8065 => Opcode::PseudoVREMU_VV_M1_E64_MASK,
21908 0 : 8066 => Opcode::PseudoVREMU_VV_M1_E8,
21909 0 : 8067 => Opcode::PseudoVREMU_VV_M1_E8_MASK,
21910 0 : 8068 => Opcode::PseudoVREMU_VV_M2_E16,
21911 0 : 8069 => Opcode::PseudoVREMU_VV_M2_E16_MASK,
21912 0 : 8070 => Opcode::PseudoVREMU_VV_M2_E32,
21913 0 : 8071 => Opcode::PseudoVREMU_VV_M2_E32_MASK,
21914 0 : 8072 => Opcode::PseudoVREMU_VV_M2_E64,
21915 0 : 8073 => Opcode::PseudoVREMU_VV_M2_E64_MASK,
21916 0 : 8074 => Opcode::PseudoVREMU_VV_M2_E8,
21917 0 : 8075 => Opcode::PseudoVREMU_VV_M2_E8_MASK,
21918 0 : 8076 => Opcode::PseudoVREMU_VV_M4_E16,
21919 0 : 8077 => Opcode::PseudoVREMU_VV_M4_E16_MASK,
21920 0 : 8078 => Opcode::PseudoVREMU_VV_M4_E32,
21921 0 : 8079 => Opcode::PseudoVREMU_VV_M4_E32_MASK,
21922 0 : 8080 => Opcode::PseudoVREMU_VV_M4_E64,
21923 0 : 8081 => Opcode::PseudoVREMU_VV_M4_E64_MASK,
21924 0 : 8082 => Opcode::PseudoVREMU_VV_M4_E8,
21925 0 : 8083 => Opcode::PseudoVREMU_VV_M4_E8_MASK,
21926 0 : 8084 => Opcode::PseudoVREMU_VV_M8_E16,
21927 0 : 8085 => Opcode::PseudoVREMU_VV_M8_E16_MASK,
21928 0 : 8086 => Opcode::PseudoVREMU_VV_M8_E32,
21929 0 : 8087 => Opcode::PseudoVREMU_VV_M8_E32_MASK,
21930 0 : 8088 => Opcode::PseudoVREMU_VV_M8_E64,
21931 0 : 8089 => Opcode::PseudoVREMU_VV_M8_E64_MASK,
21932 0 : 8090 => Opcode::PseudoVREMU_VV_M8_E8,
21933 0 : 8091 => Opcode::PseudoVREMU_VV_M8_E8_MASK,
21934 0 : 8092 => Opcode::PseudoVREMU_VV_MF2_E16,
21935 0 : 8093 => Opcode::PseudoVREMU_VV_MF2_E16_MASK,
21936 0 : 8094 => Opcode::PseudoVREMU_VV_MF2_E32,
21937 0 : 8095 => Opcode::PseudoVREMU_VV_MF2_E32_MASK,
21938 0 : 8096 => Opcode::PseudoVREMU_VV_MF2_E8,
21939 0 : 8097 => Opcode::PseudoVREMU_VV_MF2_E8_MASK,
21940 0 : 8098 => Opcode::PseudoVREMU_VV_MF4_E16,
21941 0 : 8099 => Opcode::PseudoVREMU_VV_MF4_E16_MASK,
21942 0 : 8100 => Opcode::PseudoVREMU_VV_MF4_E8,
21943 0 : 8101 => Opcode::PseudoVREMU_VV_MF4_E8_MASK,
21944 0 : 8102 => Opcode::PseudoVREMU_VV_MF8_E8,
21945 0 : 8103 => Opcode::PseudoVREMU_VV_MF8_E8_MASK,
21946 0 : 8104 => Opcode::PseudoVREMU_VX_M1_E16,
21947 0 : 8105 => Opcode::PseudoVREMU_VX_M1_E16_MASK,
21948 0 : 8106 => Opcode::PseudoVREMU_VX_M1_E32,
21949 0 : 8107 => Opcode::PseudoVREMU_VX_M1_E32_MASK,
21950 0 : 8108 => Opcode::PseudoVREMU_VX_M1_E64,
21951 0 : 8109 => Opcode::PseudoVREMU_VX_M1_E64_MASK,
21952 0 : 8110 => Opcode::PseudoVREMU_VX_M1_E8,
21953 0 : 8111 => Opcode::PseudoVREMU_VX_M1_E8_MASK,
21954 0 : 8112 => Opcode::PseudoVREMU_VX_M2_E16,
21955 0 : 8113 => Opcode::PseudoVREMU_VX_M2_E16_MASK,
21956 0 : 8114 => Opcode::PseudoVREMU_VX_M2_E32,
21957 0 : 8115 => Opcode::PseudoVREMU_VX_M2_E32_MASK,
21958 0 : 8116 => Opcode::PseudoVREMU_VX_M2_E64,
21959 0 : 8117 => Opcode::PseudoVREMU_VX_M2_E64_MASK,
21960 0 : 8118 => Opcode::PseudoVREMU_VX_M2_E8,
21961 0 : 8119 => Opcode::PseudoVREMU_VX_M2_E8_MASK,
21962 0 : 8120 => Opcode::PseudoVREMU_VX_M4_E16,
21963 0 : 8121 => Opcode::PseudoVREMU_VX_M4_E16_MASK,
21964 0 : 8122 => Opcode::PseudoVREMU_VX_M4_E32,
21965 0 : 8123 => Opcode::PseudoVREMU_VX_M4_E32_MASK,
21966 0 : 8124 => Opcode::PseudoVREMU_VX_M4_E64,
21967 0 : 8125 => Opcode::PseudoVREMU_VX_M4_E64_MASK,
21968 0 : 8126 => Opcode::PseudoVREMU_VX_M4_E8,
21969 0 : 8127 => Opcode::PseudoVREMU_VX_M4_E8_MASK,
21970 0 : 8128 => Opcode::PseudoVREMU_VX_M8_E16,
21971 0 : 8129 => Opcode::PseudoVREMU_VX_M8_E16_MASK,
21972 0 : 8130 => Opcode::PseudoVREMU_VX_M8_E32,
21973 0 : 8131 => Opcode::PseudoVREMU_VX_M8_E32_MASK,
21974 0 : 8132 => Opcode::PseudoVREMU_VX_M8_E64,
21975 0 : 8133 => Opcode::PseudoVREMU_VX_M8_E64_MASK,
21976 0 : 8134 => Opcode::PseudoVREMU_VX_M8_E8,
21977 0 : 8135 => Opcode::PseudoVREMU_VX_M8_E8_MASK,
21978 0 : 8136 => Opcode::PseudoVREMU_VX_MF2_E16,
21979 0 : 8137 => Opcode::PseudoVREMU_VX_MF2_E16_MASK,
21980 0 : 8138 => Opcode::PseudoVREMU_VX_MF2_E32,
21981 0 : 8139 => Opcode::PseudoVREMU_VX_MF2_E32_MASK,
21982 0 : 8140 => Opcode::PseudoVREMU_VX_MF2_E8,
21983 0 : 8141 => Opcode::PseudoVREMU_VX_MF2_E8_MASK,
21984 0 : 8142 => Opcode::PseudoVREMU_VX_MF4_E16,
21985 0 : 8143 => Opcode::PseudoVREMU_VX_MF4_E16_MASK,
21986 0 : 8144 => Opcode::PseudoVREMU_VX_MF4_E8,
21987 0 : 8145 => Opcode::PseudoVREMU_VX_MF4_E8_MASK,
21988 0 : 8146 => Opcode::PseudoVREMU_VX_MF8_E8,
21989 0 : 8147 => Opcode::PseudoVREMU_VX_MF8_E8_MASK,
21990 0 : 8148 => Opcode::PseudoVREM_VV_M1_E16,
21991 0 : 8149 => Opcode::PseudoVREM_VV_M1_E16_MASK,
21992 0 : 8150 => Opcode::PseudoVREM_VV_M1_E32,
21993 0 : 8151 => Opcode::PseudoVREM_VV_M1_E32_MASK,
21994 0 : 8152 => Opcode::PseudoVREM_VV_M1_E64,
21995 0 : 8153 => Opcode::PseudoVREM_VV_M1_E64_MASK,
21996 0 : 8154 => Opcode::PseudoVREM_VV_M1_E8,
21997 0 : 8155 => Opcode::PseudoVREM_VV_M1_E8_MASK,
21998 0 : 8156 => Opcode::PseudoVREM_VV_M2_E16,
21999 0 : 8157 => Opcode::PseudoVREM_VV_M2_E16_MASK,
22000 0 : 8158 => Opcode::PseudoVREM_VV_M2_E32,
22001 0 : 8159 => Opcode::PseudoVREM_VV_M2_E32_MASK,
22002 0 : 8160 => Opcode::PseudoVREM_VV_M2_E64,
22003 0 : 8161 => Opcode::PseudoVREM_VV_M2_E64_MASK,
22004 0 : 8162 => Opcode::PseudoVREM_VV_M2_E8,
22005 0 : 8163 => Opcode::PseudoVREM_VV_M2_E8_MASK,
22006 0 : 8164 => Opcode::PseudoVREM_VV_M4_E16,
22007 0 : 8165 => Opcode::PseudoVREM_VV_M4_E16_MASK,
22008 0 : 8166 => Opcode::PseudoVREM_VV_M4_E32,
22009 0 : 8167 => Opcode::PseudoVREM_VV_M4_E32_MASK,
22010 0 : 8168 => Opcode::PseudoVREM_VV_M4_E64,
22011 0 : 8169 => Opcode::PseudoVREM_VV_M4_E64_MASK,
22012 0 : 8170 => Opcode::PseudoVREM_VV_M4_E8,
22013 0 : 8171 => Opcode::PseudoVREM_VV_M4_E8_MASK,
22014 0 : 8172 => Opcode::PseudoVREM_VV_M8_E16,
22015 0 : 8173 => Opcode::PseudoVREM_VV_M8_E16_MASK,
22016 0 : 8174 => Opcode::PseudoVREM_VV_M8_E32,
22017 0 : 8175 => Opcode::PseudoVREM_VV_M8_E32_MASK,
22018 0 : 8176 => Opcode::PseudoVREM_VV_M8_E64,
22019 0 : 8177 => Opcode::PseudoVREM_VV_M8_E64_MASK,
22020 0 : 8178 => Opcode::PseudoVREM_VV_M8_E8,
22021 0 : 8179 => Opcode::PseudoVREM_VV_M8_E8_MASK,
22022 0 : 8180 => Opcode::PseudoVREM_VV_MF2_E16,
22023 0 : 8181 => Opcode::PseudoVREM_VV_MF2_E16_MASK,
22024 0 : 8182 => Opcode::PseudoVREM_VV_MF2_E32,
22025 0 : 8183 => Opcode::PseudoVREM_VV_MF2_E32_MASK,
22026 0 : 8184 => Opcode::PseudoVREM_VV_MF2_E8,
22027 0 : 8185 => Opcode::PseudoVREM_VV_MF2_E8_MASK,
22028 0 : 8186 => Opcode::PseudoVREM_VV_MF4_E16,
22029 0 : 8187 => Opcode::PseudoVREM_VV_MF4_E16_MASK,
22030 0 : 8188 => Opcode::PseudoVREM_VV_MF4_E8,
22031 0 : 8189 => Opcode::PseudoVREM_VV_MF4_E8_MASK,
22032 0 : 8190 => Opcode::PseudoVREM_VV_MF8_E8,
22033 0 : 8191 => Opcode::PseudoVREM_VV_MF8_E8_MASK,
22034 0 : 8192 => Opcode::PseudoVREM_VX_M1_E16,
22035 0 : 8193 => Opcode::PseudoVREM_VX_M1_E16_MASK,
22036 0 : 8194 => Opcode::PseudoVREM_VX_M1_E32,
22037 0 : 8195 => Opcode::PseudoVREM_VX_M1_E32_MASK,
22038 0 : 8196 => Opcode::PseudoVREM_VX_M1_E64,
22039 0 : 8197 => Opcode::PseudoVREM_VX_M1_E64_MASK,
22040 0 : 8198 => Opcode::PseudoVREM_VX_M1_E8,
22041 0 : 8199 => Opcode::PseudoVREM_VX_M1_E8_MASK,
22042 0 : 8200 => Opcode::PseudoVREM_VX_M2_E16,
22043 0 : 8201 => Opcode::PseudoVREM_VX_M2_E16_MASK,
22044 0 : 8202 => Opcode::PseudoVREM_VX_M2_E32,
22045 0 : 8203 => Opcode::PseudoVREM_VX_M2_E32_MASK,
22046 0 : 8204 => Opcode::PseudoVREM_VX_M2_E64,
22047 0 : 8205 => Opcode::PseudoVREM_VX_M2_E64_MASK,
22048 0 : 8206 => Opcode::PseudoVREM_VX_M2_E8,
22049 0 : 8207 => Opcode::PseudoVREM_VX_M2_E8_MASK,
22050 0 : 8208 => Opcode::PseudoVREM_VX_M4_E16,
22051 0 : 8209 => Opcode::PseudoVREM_VX_M4_E16_MASK,
22052 0 : 8210 => Opcode::PseudoVREM_VX_M4_E32,
22053 0 : 8211 => Opcode::PseudoVREM_VX_M4_E32_MASK,
22054 0 : 8212 => Opcode::PseudoVREM_VX_M4_E64,
22055 0 : 8213 => Opcode::PseudoVREM_VX_M4_E64_MASK,
22056 0 : 8214 => Opcode::PseudoVREM_VX_M4_E8,
22057 0 : 8215 => Opcode::PseudoVREM_VX_M4_E8_MASK,
22058 0 : 8216 => Opcode::PseudoVREM_VX_M8_E16,
22059 0 : 8217 => Opcode::PseudoVREM_VX_M8_E16_MASK,
22060 0 : 8218 => Opcode::PseudoVREM_VX_M8_E32,
22061 0 : 8219 => Opcode::PseudoVREM_VX_M8_E32_MASK,
22062 0 : 8220 => Opcode::PseudoVREM_VX_M8_E64,
22063 0 : 8221 => Opcode::PseudoVREM_VX_M8_E64_MASK,
22064 0 : 8222 => Opcode::PseudoVREM_VX_M8_E8,
22065 0 : 8223 => Opcode::PseudoVREM_VX_M8_E8_MASK,
22066 0 : 8224 => Opcode::PseudoVREM_VX_MF2_E16,
22067 0 : 8225 => Opcode::PseudoVREM_VX_MF2_E16_MASK,
22068 0 : 8226 => Opcode::PseudoVREM_VX_MF2_E32,
22069 0 : 8227 => Opcode::PseudoVREM_VX_MF2_E32_MASK,
22070 0 : 8228 => Opcode::PseudoVREM_VX_MF2_E8,
22071 0 : 8229 => Opcode::PseudoVREM_VX_MF2_E8_MASK,
22072 0 : 8230 => Opcode::PseudoVREM_VX_MF4_E16,
22073 0 : 8231 => Opcode::PseudoVREM_VX_MF4_E16_MASK,
22074 0 : 8232 => Opcode::PseudoVREM_VX_MF4_E8,
22075 0 : 8233 => Opcode::PseudoVREM_VX_MF4_E8_MASK,
22076 0 : 8234 => Opcode::PseudoVREM_VX_MF8_E8,
22077 0 : 8235 => Opcode::PseudoVREM_VX_MF8_E8_MASK,
22078 0 : 8236 => Opcode::PseudoVREV8_V_M1,
22079 0 : 8237 => Opcode::PseudoVREV8_V_M1_MASK,
22080 0 : 8238 => Opcode::PseudoVREV8_V_M2,
22081 0 : 8239 => Opcode::PseudoVREV8_V_M2_MASK,
22082 0 : 8240 => Opcode::PseudoVREV8_V_M4,
22083 0 : 8241 => Opcode::PseudoVREV8_V_M4_MASK,
22084 0 : 8242 => Opcode::PseudoVREV8_V_M8,
22085 0 : 8243 => Opcode::PseudoVREV8_V_M8_MASK,
22086 0 : 8244 => Opcode::PseudoVREV8_V_MF2,
22087 0 : 8245 => Opcode::PseudoVREV8_V_MF2_MASK,
22088 0 : 8246 => Opcode::PseudoVREV8_V_MF4,
22089 0 : 8247 => Opcode::PseudoVREV8_V_MF4_MASK,
22090 0 : 8248 => Opcode::PseudoVREV8_V_MF8,
22091 0 : 8249 => Opcode::PseudoVREV8_V_MF8_MASK,
22092 0 : 8250 => Opcode::PseudoVRGATHEREI16_VV_M1_E16_M1,
22093 0 : 8251 => Opcode::PseudoVRGATHEREI16_VV_M1_E16_M1_MASK,
22094 0 : 8252 => Opcode::PseudoVRGATHEREI16_VV_M1_E16_M2,
22095 0 : 8253 => Opcode::PseudoVRGATHEREI16_VV_M1_E16_M2_MASK,
22096 0 : 8254 => Opcode::PseudoVRGATHEREI16_VV_M1_E16_MF2,
22097 0 : 8255 => Opcode::PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK,
22098 0 : 8256 => Opcode::PseudoVRGATHEREI16_VV_M1_E16_MF4,
22099 0 : 8257 => Opcode::PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK,
22100 0 : 8258 => Opcode::PseudoVRGATHEREI16_VV_M1_E32_M1,
22101 0 : 8259 => Opcode::PseudoVRGATHEREI16_VV_M1_E32_M1_MASK,
22102 0 : 8260 => Opcode::PseudoVRGATHEREI16_VV_M1_E32_M2,
22103 0 : 8261 => Opcode::PseudoVRGATHEREI16_VV_M1_E32_M2_MASK,
22104 0 : 8262 => Opcode::PseudoVRGATHEREI16_VV_M1_E32_MF2,
22105 0 : 8263 => Opcode::PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK,
22106 0 : 8264 => Opcode::PseudoVRGATHEREI16_VV_M1_E32_MF4,
22107 0 : 8265 => Opcode::PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK,
22108 0 : 8266 => Opcode::PseudoVRGATHEREI16_VV_M1_E64_M1,
22109 0 : 8267 => Opcode::PseudoVRGATHEREI16_VV_M1_E64_M1_MASK,
22110 0 : 8268 => Opcode::PseudoVRGATHEREI16_VV_M1_E64_M2,
22111 0 : 8269 => Opcode::PseudoVRGATHEREI16_VV_M1_E64_M2_MASK,
22112 0 : 8270 => Opcode::PseudoVRGATHEREI16_VV_M1_E64_MF2,
22113 0 : 8271 => Opcode::PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK,
22114 0 : 8272 => Opcode::PseudoVRGATHEREI16_VV_M1_E64_MF4,
22115 0 : 8273 => Opcode::PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK,
22116 0 : 8274 => Opcode::PseudoVRGATHEREI16_VV_M1_E8_M1,
22117 0 : 8275 => Opcode::PseudoVRGATHEREI16_VV_M1_E8_M1_MASK,
22118 0 : 8276 => Opcode::PseudoVRGATHEREI16_VV_M1_E8_M2,
22119 0 : 8277 => Opcode::PseudoVRGATHEREI16_VV_M1_E8_M2_MASK,
22120 0 : 8278 => Opcode::PseudoVRGATHEREI16_VV_M1_E8_MF2,
22121 0 : 8279 => Opcode::PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK,
22122 0 : 8280 => Opcode::PseudoVRGATHEREI16_VV_M1_E8_MF4,
22123 0 : 8281 => Opcode::PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK,
22124 0 : 8282 => Opcode::PseudoVRGATHEREI16_VV_M2_E16_M1,
22125 0 : 8283 => Opcode::PseudoVRGATHEREI16_VV_M2_E16_M1_MASK,
22126 0 : 8284 => Opcode::PseudoVRGATHEREI16_VV_M2_E16_M2,
22127 0 : 8285 => Opcode::PseudoVRGATHEREI16_VV_M2_E16_M2_MASK,
22128 0 : 8286 => Opcode::PseudoVRGATHEREI16_VV_M2_E16_M4,
22129 0 : 8287 => Opcode::PseudoVRGATHEREI16_VV_M2_E16_M4_MASK,
22130 0 : 8288 => Opcode::PseudoVRGATHEREI16_VV_M2_E16_MF2,
22131 0 : 8289 => Opcode::PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK,
22132 0 : 8290 => Opcode::PseudoVRGATHEREI16_VV_M2_E32_M1,
22133 0 : 8291 => Opcode::PseudoVRGATHEREI16_VV_M2_E32_M1_MASK,
22134 0 : 8292 => Opcode::PseudoVRGATHEREI16_VV_M2_E32_M2,
22135 0 : 8293 => Opcode::PseudoVRGATHEREI16_VV_M2_E32_M2_MASK,
22136 0 : 8294 => Opcode::PseudoVRGATHEREI16_VV_M2_E32_M4,
22137 0 : 8295 => Opcode::PseudoVRGATHEREI16_VV_M2_E32_M4_MASK,
22138 0 : 8296 => Opcode::PseudoVRGATHEREI16_VV_M2_E32_MF2,
22139 0 : 8297 => Opcode::PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK,
22140 0 : 8298 => Opcode::PseudoVRGATHEREI16_VV_M2_E64_M1,
22141 0 : 8299 => Opcode::PseudoVRGATHEREI16_VV_M2_E64_M1_MASK,
22142 0 : 8300 => Opcode::PseudoVRGATHEREI16_VV_M2_E64_M2,
22143 0 : 8301 => Opcode::PseudoVRGATHEREI16_VV_M2_E64_M2_MASK,
22144 0 : 8302 => Opcode::PseudoVRGATHEREI16_VV_M2_E64_M4,
22145 0 : 8303 => Opcode::PseudoVRGATHEREI16_VV_M2_E64_M4_MASK,
22146 0 : 8304 => Opcode::PseudoVRGATHEREI16_VV_M2_E64_MF2,
22147 0 : 8305 => Opcode::PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK,
22148 0 : 8306 => Opcode::PseudoVRGATHEREI16_VV_M2_E8_M1,
22149 0 : 8307 => Opcode::PseudoVRGATHEREI16_VV_M2_E8_M1_MASK,
22150 0 : 8308 => Opcode::PseudoVRGATHEREI16_VV_M2_E8_M2,
22151 0 : 8309 => Opcode::PseudoVRGATHEREI16_VV_M2_E8_M2_MASK,
22152 0 : 8310 => Opcode::PseudoVRGATHEREI16_VV_M2_E8_M4,
22153 0 : 8311 => Opcode::PseudoVRGATHEREI16_VV_M2_E8_M4_MASK,
22154 0 : 8312 => Opcode::PseudoVRGATHEREI16_VV_M2_E8_MF2,
22155 0 : 8313 => Opcode::PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK,
22156 0 : 8314 => Opcode::PseudoVRGATHEREI16_VV_M4_E16_M1,
22157 0 : 8315 => Opcode::PseudoVRGATHEREI16_VV_M4_E16_M1_MASK,
22158 0 : 8316 => Opcode::PseudoVRGATHEREI16_VV_M4_E16_M2,
22159 0 : 8317 => Opcode::PseudoVRGATHEREI16_VV_M4_E16_M2_MASK,
22160 0 : 8318 => Opcode::PseudoVRGATHEREI16_VV_M4_E16_M4,
22161 0 : 8319 => Opcode::PseudoVRGATHEREI16_VV_M4_E16_M4_MASK,
22162 0 : 8320 => Opcode::PseudoVRGATHEREI16_VV_M4_E16_M8,
22163 0 : 8321 => Opcode::PseudoVRGATHEREI16_VV_M4_E16_M8_MASK,
22164 0 : 8322 => Opcode::PseudoVRGATHEREI16_VV_M4_E32_M1,
22165 0 : 8323 => Opcode::PseudoVRGATHEREI16_VV_M4_E32_M1_MASK,
22166 0 : 8324 => Opcode::PseudoVRGATHEREI16_VV_M4_E32_M2,
22167 0 : 8325 => Opcode::PseudoVRGATHEREI16_VV_M4_E32_M2_MASK,
22168 0 : 8326 => Opcode::PseudoVRGATHEREI16_VV_M4_E32_M4,
22169 0 : 8327 => Opcode::PseudoVRGATHEREI16_VV_M4_E32_M4_MASK,
22170 0 : 8328 => Opcode::PseudoVRGATHEREI16_VV_M4_E32_M8,
22171 0 : 8329 => Opcode::PseudoVRGATHEREI16_VV_M4_E32_M8_MASK,
22172 0 : 8330 => Opcode::PseudoVRGATHEREI16_VV_M4_E64_M1,
22173 0 : 8331 => Opcode::PseudoVRGATHEREI16_VV_M4_E64_M1_MASK,
22174 0 : 8332 => Opcode::PseudoVRGATHEREI16_VV_M4_E64_M2,
22175 0 : 8333 => Opcode::PseudoVRGATHEREI16_VV_M4_E64_M2_MASK,
22176 0 : 8334 => Opcode::PseudoVRGATHEREI16_VV_M4_E64_M4,
22177 0 : 8335 => Opcode::PseudoVRGATHEREI16_VV_M4_E64_M4_MASK,
22178 0 : 8336 => Opcode::PseudoVRGATHEREI16_VV_M4_E64_M8,
22179 0 : 8337 => Opcode::PseudoVRGATHEREI16_VV_M4_E64_M8_MASK,
22180 0 : 8338 => Opcode::PseudoVRGATHEREI16_VV_M4_E8_M1,
22181 0 : 8339 => Opcode::PseudoVRGATHEREI16_VV_M4_E8_M1_MASK,
22182 0 : 8340 => Opcode::PseudoVRGATHEREI16_VV_M4_E8_M2,
22183 0 : 8341 => Opcode::PseudoVRGATHEREI16_VV_M4_E8_M2_MASK,
22184 0 : 8342 => Opcode::PseudoVRGATHEREI16_VV_M4_E8_M4,
22185 0 : 8343 => Opcode::PseudoVRGATHEREI16_VV_M4_E8_M4_MASK,
22186 0 : 8344 => Opcode::PseudoVRGATHEREI16_VV_M4_E8_M8,
22187 0 : 8345 => Opcode::PseudoVRGATHEREI16_VV_M4_E8_M8_MASK,
22188 0 : 8346 => Opcode::PseudoVRGATHEREI16_VV_M8_E16_M2,
22189 0 : 8347 => Opcode::PseudoVRGATHEREI16_VV_M8_E16_M2_MASK,
22190 0 : 8348 => Opcode::PseudoVRGATHEREI16_VV_M8_E16_M4,
22191 0 : 8349 => Opcode::PseudoVRGATHEREI16_VV_M8_E16_M4_MASK,
22192 0 : 8350 => Opcode::PseudoVRGATHEREI16_VV_M8_E16_M8,
22193 0 : 8351 => Opcode::PseudoVRGATHEREI16_VV_M8_E16_M8_MASK,
22194 0 : 8352 => Opcode::PseudoVRGATHEREI16_VV_M8_E32_M2,
22195 0 : 8353 => Opcode::PseudoVRGATHEREI16_VV_M8_E32_M2_MASK,
22196 0 : 8354 => Opcode::PseudoVRGATHEREI16_VV_M8_E32_M4,
22197 0 : 8355 => Opcode::PseudoVRGATHEREI16_VV_M8_E32_M4_MASK,
22198 0 : 8356 => Opcode::PseudoVRGATHEREI16_VV_M8_E32_M8,
22199 0 : 8357 => Opcode::PseudoVRGATHEREI16_VV_M8_E32_M8_MASK,
22200 0 : 8358 => Opcode::PseudoVRGATHEREI16_VV_M8_E64_M2,
22201 0 : 8359 => Opcode::PseudoVRGATHEREI16_VV_M8_E64_M2_MASK,
22202 0 : 8360 => Opcode::PseudoVRGATHEREI16_VV_M8_E64_M4,
22203 0 : 8361 => Opcode::PseudoVRGATHEREI16_VV_M8_E64_M4_MASK,
22204 0 : 8362 => Opcode::PseudoVRGATHEREI16_VV_M8_E64_M8,
22205 0 : 8363 => Opcode::PseudoVRGATHEREI16_VV_M8_E64_M8_MASK,
22206 0 : 8364 => Opcode::PseudoVRGATHEREI16_VV_M8_E8_M2,
22207 0 : 8365 => Opcode::PseudoVRGATHEREI16_VV_M8_E8_M2_MASK,
22208 0 : 8366 => Opcode::PseudoVRGATHEREI16_VV_M8_E8_M4,
22209 0 : 8367 => Opcode::PseudoVRGATHEREI16_VV_M8_E8_M4_MASK,
22210 0 : 8368 => Opcode::PseudoVRGATHEREI16_VV_M8_E8_M8,
22211 0 : 8369 => Opcode::PseudoVRGATHEREI16_VV_M8_E8_M8_MASK,
22212 0 : 8370 => Opcode::PseudoVRGATHEREI16_VV_MF2_E16_M1,
22213 0 : 8371 => Opcode::PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK,
22214 0 : 8372 => Opcode::PseudoVRGATHEREI16_VV_MF2_E16_MF2,
22215 0 : 8373 => Opcode::PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK,
22216 0 : 8374 => Opcode::PseudoVRGATHEREI16_VV_MF2_E16_MF4,
22217 0 : 8375 => Opcode::PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK,
22218 0 : 8376 => Opcode::PseudoVRGATHEREI16_VV_MF2_E16_MF8,
22219 0 : 8377 => Opcode::PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK,
22220 0 : 8378 => Opcode::PseudoVRGATHEREI16_VV_MF2_E32_M1,
22221 0 : 8379 => Opcode::PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK,
22222 0 : 8380 => Opcode::PseudoVRGATHEREI16_VV_MF2_E32_MF2,
22223 0 : 8381 => Opcode::PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK,
22224 0 : 8382 => Opcode::PseudoVRGATHEREI16_VV_MF2_E32_MF4,
22225 0 : 8383 => Opcode::PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK,
22226 0 : 8384 => Opcode::PseudoVRGATHEREI16_VV_MF2_E32_MF8,
22227 0 : 8385 => Opcode::PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK,
22228 0 : 8386 => Opcode::PseudoVRGATHEREI16_VV_MF2_E8_M1,
22229 0 : 8387 => Opcode::PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK,
22230 0 : 8388 => Opcode::PseudoVRGATHEREI16_VV_MF2_E8_MF2,
22231 0 : 8389 => Opcode::PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK,
22232 0 : 8390 => Opcode::PseudoVRGATHEREI16_VV_MF2_E8_MF4,
22233 0 : 8391 => Opcode::PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK,
22234 0 : 8392 => Opcode::PseudoVRGATHEREI16_VV_MF2_E8_MF8,
22235 0 : 8393 => Opcode::PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK,
22236 0 : 8394 => Opcode::PseudoVRGATHEREI16_VV_MF4_E16_MF2,
22237 0 : 8395 => Opcode::PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK,
22238 0 : 8396 => Opcode::PseudoVRGATHEREI16_VV_MF4_E16_MF4,
22239 0 : 8397 => Opcode::PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK,
22240 0 : 8398 => Opcode::PseudoVRGATHEREI16_VV_MF4_E16_MF8,
22241 0 : 8399 => Opcode::PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK,
22242 0 : 8400 => Opcode::PseudoVRGATHEREI16_VV_MF4_E8_MF2,
22243 0 : 8401 => Opcode::PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK,
22244 0 : 8402 => Opcode::PseudoVRGATHEREI16_VV_MF4_E8_MF4,
22245 0 : 8403 => Opcode::PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK,
22246 0 : 8404 => Opcode::PseudoVRGATHEREI16_VV_MF4_E8_MF8,
22247 0 : 8405 => Opcode::PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK,
22248 0 : 8406 => Opcode::PseudoVRGATHEREI16_VV_MF8_E8_MF4,
22249 0 : 8407 => Opcode::PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK,
22250 0 : 8408 => Opcode::PseudoVRGATHEREI16_VV_MF8_E8_MF8,
22251 0 : 8409 => Opcode::PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK,
22252 0 : 8410 => Opcode::PseudoVRGATHER_VI_M1,
22253 0 : 8411 => Opcode::PseudoVRGATHER_VI_M1_MASK,
22254 0 : 8412 => Opcode::PseudoVRGATHER_VI_M2,
22255 0 : 8413 => Opcode::PseudoVRGATHER_VI_M2_MASK,
22256 0 : 8414 => Opcode::PseudoVRGATHER_VI_M4,
22257 0 : 8415 => Opcode::PseudoVRGATHER_VI_M4_MASK,
22258 0 : 8416 => Opcode::PseudoVRGATHER_VI_M8,
22259 0 : 8417 => Opcode::PseudoVRGATHER_VI_M8_MASK,
22260 0 : 8418 => Opcode::PseudoVRGATHER_VI_MF2,
22261 0 : 8419 => Opcode::PseudoVRGATHER_VI_MF2_MASK,
22262 0 : 8420 => Opcode::PseudoVRGATHER_VI_MF4,
22263 0 : 8421 => Opcode::PseudoVRGATHER_VI_MF4_MASK,
22264 0 : 8422 => Opcode::PseudoVRGATHER_VI_MF8,
22265 0 : 8423 => Opcode::PseudoVRGATHER_VI_MF8_MASK,
22266 0 : 8424 => Opcode::PseudoVRGATHER_VV_M1_E16,
22267 0 : 8425 => Opcode::PseudoVRGATHER_VV_M1_E16_MASK,
22268 0 : 8426 => Opcode::PseudoVRGATHER_VV_M1_E32,
22269 0 : 8427 => Opcode::PseudoVRGATHER_VV_M1_E32_MASK,
22270 0 : 8428 => Opcode::PseudoVRGATHER_VV_M1_E64,
22271 0 : 8429 => Opcode::PseudoVRGATHER_VV_M1_E64_MASK,
22272 0 : 8430 => Opcode::PseudoVRGATHER_VV_M1_E8,
22273 0 : 8431 => Opcode::PseudoVRGATHER_VV_M1_E8_MASK,
22274 0 : 8432 => Opcode::PseudoVRGATHER_VV_M2_E16,
22275 0 : 8433 => Opcode::PseudoVRGATHER_VV_M2_E16_MASK,
22276 0 : 8434 => Opcode::PseudoVRGATHER_VV_M2_E32,
22277 0 : 8435 => Opcode::PseudoVRGATHER_VV_M2_E32_MASK,
22278 0 : 8436 => Opcode::PseudoVRGATHER_VV_M2_E64,
22279 0 : 8437 => Opcode::PseudoVRGATHER_VV_M2_E64_MASK,
22280 0 : 8438 => Opcode::PseudoVRGATHER_VV_M2_E8,
22281 0 : 8439 => Opcode::PseudoVRGATHER_VV_M2_E8_MASK,
22282 0 : 8440 => Opcode::PseudoVRGATHER_VV_M4_E16,
22283 0 : 8441 => Opcode::PseudoVRGATHER_VV_M4_E16_MASK,
22284 0 : 8442 => Opcode::PseudoVRGATHER_VV_M4_E32,
22285 0 : 8443 => Opcode::PseudoVRGATHER_VV_M4_E32_MASK,
22286 0 : 8444 => Opcode::PseudoVRGATHER_VV_M4_E64,
22287 0 : 8445 => Opcode::PseudoVRGATHER_VV_M4_E64_MASK,
22288 0 : 8446 => Opcode::PseudoVRGATHER_VV_M4_E8,
22289 0 : 8447 => Opcode::PseudoVRGATHER_VV_M4_E8_MASK,
22290 0 : 8448 => Opcode::PseudoVRGATHER_VV_M8_E16,
22291 0 : 8449 => Opcode::PseudoVRGATHER_VV_M8_E16_MASK,
22292 0 : 8450 => Opcode::PseudoVRGATHER_VV_M8_E32,
22293 0 : 8451 => Opcode::PseudoVRGATHER_VV_M8_E32_MASK,
22294 0 : 8452 => Opcode::PseudoVRGATHER_VV_M8_E64,
22295 0 : 8453 => Opcode::PseudoVRGATHER_VV_M8_E64_MASK,
22296 0 : 8454 => Opcode::PseudoVRGATHER_VV_M8_E8,
22297 0 : 8455 => Opcode::PseudoVRGATHER_VV_M8_E8_MASK,
22298 0 : 8456 => Opcode::PseudoVRGATHER_VV_MF2_E16,
22299 0 : 8457 => Opcode::PseudoVRGATHER_VV_MF2_E16_MASK,
22300 0 : 8458 => Opcode::PseudoVRGATHER_VV_MF2_E32,
22301 0 : 8459 => Opcode::PseudoVRGATHER_VV_MF2_E32_MASK,
22302 0 : 8460 => Opcode::PseudoVRGATHER_VV_MF2_E8,
22303 0 : 8461 => Opcode::PseudoVRGATHER_VV_MF2_E8_MASK,
22304 0 : 8462 => Opcode::PseudoVRGATHER_VV_MF4_E16,
22305 0 : 8463 => Opcode::PseudoVRGATHER_VV_MF4_E16_MASK,
22306 0 : 8464 => Opcode::PseudoVRGATHER_VV_MF4_E8,
22307 0 : 8465 => Opcode::PseudoVRGATHER_VV_MF4_E8_MASK,
22308 0 : 8466 => Opcode::PseudoVRGATHER_VV_MF8_E8,
22309 0 : 8467 => Opcode::PseudoVRGATHER_VV_MF8_E8_MASK,
22310 0 : 8468 => Opcode::PseudoVRGATHER_VX_M1,
22311 0 : 8469 => Opcode::PseudoVRGATHER_VX_M1_MASK,
22312 0 : 8470 => Opcode::PseudoVRGATHER_VX_M2,
22313 0 : 8471 => Opcode::PseudoVRGATHER_VX_M2_MASK,
22314 0 : 8472 => Opcode::PseudoVRGATHER_VX_M4,
22315 0 : 8473 => Opcode::PseudoVRGATHER_VX_M4_MASK,
22316 0 : 8474 => Opcode::PseudoVRGATHER_VX_M8,
22317 0 : 8475 => Opcode::PseudoVRGATHER_VX_M8_MASK,
22318 0 : 8476 => Opcode::PseudoVRGATHER_VX_MF2,
22319 0 : 8477 => Opcode::PseudoVRGATHER_VX_MF2_MASK,
22320 0 : 8478 => Opcode::PseudoVRGATHER_VX_MF4,
22321 0 : 8479 => Opcode::PseudoVRGATHER_VX_MF4_MASK,
22322 0 : 8480 => Opcode::PseudoVRGATHER_VX_MF8,
22323 0 : 8481 => Opcode::PseudoVRGATHER_VX_MF8_MASK,
22324 0 : 8482 => Opcode::PseudoVROL_VV_M1,
22325 0 : 8483 => Opcode::PseudoVROL_VV_M1_MASK,
22326 0 : 8484 => Opcode::PseudoVROL_VV_M2,
22327 0 : 8485 => Opcode::PseudoVROL_VV_M2_MASK,
22328 0 : 8486 => Opcode::PseudoVROL_VV_M4,
22329 0 : 8487 => Opcode::PseudoVROL_VV_M4_MASK,
22330 0 : 8488 => Opcode::PseudoVROL_VV_M8,
22331 0 : 8489 => Opcode::PseudoVROL_VV_M8_MASK,
22332 0 : 8490 => Opcode::PseudoVROL_VV_MF2,
22333 0 : 8491 => Opcode::PseudoVROL_VV_MF2_MASK,
22334 0 : 8492 => Opcode::PseudoVROL_VV_MF4,
22335 0 : 8493 => Opcode::PseudoVROL_VV_MF4_MASK,
22336 0 : 8494 => Opcode::PseudoVROL_VV_MF8,
22337 0 : 8495 => Opcode::PseudoVROL_VV_MF8_MASK,
22338 0 : 8496 => Opcode::PseudoVROL_VX_M1,
22339 0 : 8497 => Opcode::PseudoVROL_VX_M1_MASK,
22340 0 : 8498 => Opcode::PseudoVROL_VX_M2,
22341 0 : 8499 => Opcode::PseudoVROL_VX_M2_MASK,
22342 0 : 8500 => Opcode::PseudoVROL_VX_M4,
22343 0 : 8501 => Opcode::PseudoVROL_VX_M4_MASK,
22344 0 : 8502 => Opcode::PseudoVROL_VX_M8,
22345 0 : 8503 => Opcode::PseudoVROL_VX_M8_MASK,
22346 0 : 8504 => Opcode::PseudoVROL_VX_MF2,
22347 0 : 8505 => Opcode::PseudoVROL_VX_MF2_MASK,
22348 0 : 8506 => Opcode::PseudoVROL_VX_MF4,
22349 0 : 8507 => Opcode::PseudoVROL_VX_MF4_MASK,
22350 0 : 8508 => Opcode::PseudoVROL_VX_MF8,
22351 0 : 8509 => Opcode::PseudoVROL_VX_MF8_MASK,
22352 0 : 8510 => Opcode::PseudoVROR_VI_M1,
22353 0 : 8511 => Opcode::PseudoVROR_VI_M1_MASK,
22354 0 : 8512 => Opcode::PseudoVROR_VI_M2,
22355 0 : 8513 => Opcode::PseudoVROR_VI_M2_MASK,
22356 0 : 8514 => Opcode::PseudoVROR_VI_M4,
22357 0 : 8515 => Opcode::PseudoVROR_VI_M4_MASK,
22358 0 : 8516 => Opcode::PseudoVROR_VI_M8,
22359 0 : 8517 => Opcode::PseudoVROR_VI_M8_MASK,
22360 0 : 8518 => Opcode::PseudoVROR_VI_MF2,
22361 0 : 8519 => Opcode::PseudoVROR_VI_MF2_MASK,
22362 0 : 8520 => Opcode::PseudoVROR_VI_MF4,
22363 0 : 8521 => Opcode::PseudoVROR_VI_MF4_MASK,
22364 0 : 8522 => Opcode::PseudoVROR_VI_MF8,
22365 0 : 8523 => Opcode::PseudoVROR_VI_MF8_MASK,
22366 0 : 8524 => Opcode::PseudoVROR_VV_M1,
22367 0 : 8525 => Opcode::PseudoVROR_VV_M1_MASK,
22368 0 : 8526 => Opcode::PseudoVROR_VV_M2,
22369 0 : 8527 => Opcode::PseudoVROR_VV_M2_MASK,
22370 0 : 8528 => Opcode::PseudoVROR_VV_M4,
22371 0 : 8529 => Opcode::PseudoVROR_VV_M4_MASK,
22372 0 : 8530 => Opcode::PseudoVROR_VV_M8,
22373 0 : 8531 => Opcode::PseudoVROR_VV_M8_MASK,
22374 0 : 8532 => Opcode::PseudoVROR_VV_MF2,
22375 0 : 8533 => Opcode::PseudoVROR_VV_MF2_MASK,
22376 0 : 8534 => Opcode::PseudoVROR_VV_MF4,
22377 0 : 8535 => Opcode::PseudoVROR_VV_MF4_MASK,
22378 0 : 8536 => Opcode::PseudoVROR_VV_MF8,
22379 0 : 8537 => Opcode::PseudoVROR_VV_MF8_MASK,
22380 0 : 8538 => Opcode::PseudoVROR_VX_M1,
22381 0 : 8539 => Opcode::PseudoVROR_VX_M1_MASK,
22382 0 : 8540 => Opcode::PseudoVROR_VX_M2,
22383 0 : 8541 => Opcode::PseudoVROR_VX_M2_MASK,
22384 0 : 8542 => Opcode::PseudoVROR_VX_M4,
22385 0 : 8543 => Opcode::PseudoVROR_VX_M4_MASK,
22386 0 : 8544 => Opcode::PseudoVROR_VX_M8,
22387 0 : 8545 => Opcode::PseudoVROR_VX_M8_MASK,
22388 0 : 8546 => Opcode::PseudoVROR_VX_MF2,
22389 0 : 8547 => Opcode::PseudoVROR_VX_MF2_MASK,
22390 0 : 8548 => Opcode::PseudoVROR_VX_MF4,
22391 0 : 8549 => Opcode::PseudoVROR_VX_MF4_MASK,
22392 0 : 8550 => Opcode::PseudoVROR_VX_MF8,
22393 0 : 8551 => Opcode::PseudoVROR_VX_MF8_MASK,
22394 0 : 8552 => Opcode::PseudoVRSUB_VI_M1,
22395 0 : 8553 => Opcode::PseudoVRSUB_VI_M1_MASK,
22396 0 : 8554 => Opcode::PseudoVRSUB_VI_M2,
22397 0 : 8555 => Opcode::PseudoVRSUB_VI_M2_MASK,
22398 0 : 8556 => Opcode::PseudoVRSUB_VI_M4,
22399 0 : 8557 => Opcode::PseudoVRSUB_VI_M4_MASK,
22400 0 : 8558 => Opcode::PseudoVRSUB_VI_M8,
22401 0 : 8559 => Opcode::PseudoVRSUB_VI_M8_MASK,
22402 0 : 8560 => Opcode::PseudoVRSUB_VI_MF2,
22403 0 : 8561 => Opcode::PseudoVRSUB_VI_MF2_MASK,
22404 0 : 8562 => Opcode::PseudoVRSUB_VI_MF4,
22405 0 : 8563 => Opcode::PseudoVRSUB_VI_MF4_MASK,
22406 0 : 8564 => Opcode::PseudoVRSUB_VI_MF8,
22407 0 : 8565 => Opcode::PseudoVRSUB_VI_MF8_MASK,
22408 0 : 8566 => Opcode::PseudoVRSUB_VX_M1,
22409 0 : 8567 => Opcode::PseudoVRSUB_VX_M1_MASK,
22410 0 : 8568 => Opcode::PseudoVRSUB_VX_M2,
22411 0 : 8569 => Opcode::PseudoVRSUB_VX_M2_MASK,
22412 0 : 8570 => Opcode::PseudoVRSUB_VX_M4,
22413 0 : 8571 => Opcode::PseudoVRSUB_VX_M4_MASK,
22414 0 : 8572 => Opcode::PseudoVRSUB_VX_M8,
22415 0 : 8573 => Opcode::PseudoVRSUB_VX_M8_MASK,
22416 0 : 8574 => Opcode::PseudoVRSUB_VX_MF2,
22417 0 : 8575 => Opcode::PseudoVRSUB_VX_MF2_MASK,
22418 0 : 8576 => Opcode::PseudoVRSUB_VX_MF4,
22419 0 : 8577 => Opcode::PseudoVRSUB_VX_MF4_MASK,
22420 0 : 8578 => Opcode::PseudoVRSUB_VX_MF8,
22421 0 : 8579 => Opcode::PseudoVRSUB_VX_MF8_MASK,
22422 0 : 8580 => Opcode::PseudoVSADDU_VI_M1,
22423 0 : 8581 => Opcode::PseudoVSADDU_VI_M1_MASK,
22424 0 : 8582 => Opcode::PseudoVSADDU_VI_M2,
22425 0 : 8583 => Opcode::PseudoVSADDU_VI_M2_MASK,
22426 0 : 8584 => Opcode::PseudoVSADDU_VI_M4,
22427 0 : 8585 => Opcode::PseudoVSADDU_VI_M4_MASK,
22428 0 : 8586 => Opcode::PseudoVSADDU_VI_M8,
22429 0 : 8587 => Opcode::PseudoVSADDU_VI_M8_MASK,
22430 0 : 8588 => Opcode::PseudoVSADDU_VI_MF2,
22431 0 : 8589 => Opcode::PseudoVSADDU_VI_MF2_MASK,
22432 0 : 8590 => Opcode::PseudoVSADDU_VI_MF4,
22433 0 : 8591 => Opcode::PseudoVSADDU_VI_MF4_MASK,
22434 0 : 8592 => Opcode::PseudoVSADDU_VI_MF8,
22435 0 : 8593 => Opcode::PseudoVSADDU_VI_MF8_MASK,
22436 0 : 8594 => Opcode::PseudoVSADDU_VV_M1,
22437 0 : 8595 => Opcode::PseudoVSADDU_VV_M1_MASK,
22438 0 : 8596 => Opcode::PseudoVSADDU_VV_M2,
22439 0 : 8597 => Opcode::PseudoVSADDU_VV_M2_MASK,
22440 0 : 8598 => Opcode::PseudoVSADDU_VV_M4,
22441 0 : 8599 => Opcode::PseudoVSADDU_VV_M4_MASK,
22442 0 : 8600 => Opcode::PseudoVSADDU_VV_M8,
22443 0 : 8601 => Opcode::PseudoVSADDU_VV_M8_MASK,
22444 0 : 8602 => Opcode::PseudoVSADDU_VV_MF2,
22445 0 : 8603 => Opcode::PseudoVSADDU_VV_MF2_MASK,
22446 0 : 8604 => Opcode::PseudoVSADDU_VV_MF4,
22447 0 : 8605 => Opcode::PseudoVSADDU_VV_MF4_MASK,
22448 0 : 8606 => Opcode::PseudoVSADDU_VV_MF8,
22449 0 : 8607 => Opcode::PseudoVSADDU_VV_MF8_MASK,
22450 0 : 8608 => Opcode::PseudoVSADDU_VX_M1,
22451 0 : 8609 => Opcode::PseudoVSADDU_VX_M1_MASK,
22452 0 : 8610 => Opcode::PseudoVSADDU_VX_M2,
22453 0 : 8611 => Opcode::PseudoVSADDU_VX_M2_MASK,
22454 0 : 8612 => Opcode::PseudoVSADDU_VX_M4,
22455 0 : 8613 => Opcode::PseudoVSADDU_VX_M4_MASK,
22456 0 : 8614 => Opcode::PseudoVSADDU_VX_M8,
22457 0 : 8615 => Opcode::PseudoVSADDU_VX_M8_MASK,
22458 0 : 8616 => Opcode::PseudoVSADDU_VX_MF2,
22459 0 : 8617 => Opcode::PseudoVSADDU_VX_MF2_MASK,
22460 0 : 8618 => Opcode::PseudoVSADDU_VX_MF4,
22461 0 : 8619 => Opcode::PseudoVSADDU_VX_MF4_MASK,
22462 0 : 8620 => Opcode::PseudoVSADDU_VX_MF8,
22463 0 : 8621 => Opcode::PseudoVSADDU_VX_MF8_MASK,
22464 0 : 8622 => Opcode::PseudoVSADD_VI_M1,
22465 0 : 8623 => Opcode::PseudoVSADD_VI_M1_MASK,
22466 0 : 8624 => Opcode::PseudoVSADD_VI_M2,
22467 0 : 8625 => Opcode::PseudoVSADD_VI_M2_MASK,
22468 0 : 8626 => Opcode::PseudoVSADD_VI_M4,
22469 0 : 8627 => Opcode::PseudoVSADD_VI_M4_MASK,
22470 0 : 8628 => Opcode::PseudoVSADD_VI_M8,
22471 0 : 8629 => Opcode::PseudoVSADD_VI_M8_MASK,
22472 0 : 8630 => Opcode::PseudoVSADD_VI_MF2,
22473 0 : 8631 => Opcode::PseudoVSADD_VI_MF2_MASK,
22474 0 : 8632 => Opcode::PseudoVSADD_VI_MF4,
22475 0 : 8633 => Opcode::PseudoVSADD_VI_MF4_MASK,
22476 0 : 8634 => Opcode::PseudoVSADD_VI_MF8,
22477 0 : 8635 => Opcode::PseudoVSADD_VI_MF8_MASK,
22478 0 : 8636 => Opcode::PseudoVSADD_VV_M1,
22479 0 : 8637 => Opcode::PseudoVSADD_VV_M1_MASK,
22480 0 : 8638 => Opcode::PseudoVSADD_VV_M2,
22481 0 : 8639 => Opcode::PseudoVSADD_VV_M2_MASK,
22482 0 : 8640 => Opcode::PseudoVSADD_VV_M4,
22483 0 : 8641 => Opcode::PseudoVSADD_VV_M4_MASK,
22484 0 : 8642 => Opcode::PseudoVSADD_VV_M8,
22485 0 : 8643 => Opcode::PseudoVSADD_VV_M8_MASK,
22486 0 : 8644 => Opcode::PseudoVSADD_VV_MF2,
22487 0 : 8645 => Opcode::PseudoVSADD_VV_MF2_MASK,
22488 0 : 8646 => Opcode::PseudoVSADD_VV_MF4,
22489 0 : 8647 => Opcode::PseudoVSADD_VV_MF4_MASK,
22490 0 : 8648 => Opcode::PseudoVSADD_VV_MF8,
22491 0 : 8649 => Opcode::PseudoVSADD_VV_MF8_MASK,
22492 0 : 8650 => Opcode::PseudoVSADD_VX_M1,
22493 0 : 8651 => Opcode::PseudoVSADD_VX_M1_MASK,
22494 0 : 8652 => Opcode::PseudoVSADD_VX_M2,
22495 0 : 8653 => Opcode::PseudoVSADD_VX_M2_MASK,
22496 0 : 8654 => Opcode::PseudoVSADD_VX_M4,
22497 0 : 8655 => Opcode::PseudoVSADD_VX_M4_MASK,
22498 0 : 8656 => Opcode::PseudoVSADD_VX_M8,
22499 0 : 8657 => Opcode::PseudoVSADD_VX_M8_MASK,
22500 0 : 8658 => Opcode::PseudoVSADD_VX_MF2,
22501 0 : 8659 => Opcode::PseudoVSADD_VX_MF2_MASK,
22502 0 : 8660 => Opcode::PseudoVSADD_VX_MF4,
22503 0 : 8661 => Opcode::PseudoVSADD_VX_MF4_MASK,
22504 0 : 8662 => Opcode::PseudoVSADD_VX_MF8,
22505 0 : 8663 => Opcode::PseudoVSADD_VX_MF8_MASK,
22506 0 : 8664 => Opcode::PseudoVSBC_VVM_M1,
22507 0 : 8665 => Opcode::PseudoVSBC_VVM_M2,
22508 0 : 8666 => Opcode::PseudoVSBC_VVM_M4,
22509 0 : 8667 => Opcode::PseudoVSBC_VVM_M8,
22510 0 : 8668 => Opcode::PseudoVSBC_VVM_MF2,
22511 0 : 8669 => Opcode::PseudoVSBC_VVM_MF4,
22512 0 : 8670 => Opcode::PseudoVSBC_VVM_MF8,
22513 0 : 8671 => Opcode::PseudoVSBC_VXM_M1,
22514 0 : 8672 => Opcode::PseudoVSBC_VXM_M2,
22515 0 : 8673 => Opcode::PseudoVSBC_VXM_M4,
22516 0 : 8674 => Opcode::PseudoVSBC_VXM_M8,
22517 0 : 8675 => Opcode::PseudoVSBC_VXM_MF2,
22518 0 : 8676 => Opcode::PseudoVSBC_VXM_MF4,
22519 0 : 8677 => Opcode::PseudoVSBC_VXM_MF8,
22520 0 : 8678 => Opcode::PseudoVSE16_V_M1,
22521 0 : 8679 => Opcode::PseudoVSE16_V_M1_MASK,
22522 0 : 8680 => Opcode::PseudoVSE16_V_M2,
22523 0 : 8681 => Opcode::PseudoVSE16_V_M2_MASK,
22524 0 : 8682 => Opcode::PseudoVSE16_V_M4,
22525 0 : 8683 => Opcode::PseudoVSE16_V_M4_MASK,
22526 0 : 8684 => Opcode::PseudoVSE16_V_M8,
22527 0 : 8685 => Opcode::PseudoVSE16_V_M8_MASK,
22528 0 : 8686 => Opcode::PseudoVSE16_V_MF2,
22529 0 : 8687 => Opcode::PseudoVSE16_V_MF2_MASK,
22530 0 : 8688 => Opcode::PseudoVSE16_V_MF4,
22531 0 : 8689 => Opcode::PseudoVSE16_V_MF4_MASK,
22532 0 : 8690 => Opcode::PseudoVSE32_V_M1,
22533 0 : 8691 => Opcode::PseudoVSE32_V_M1_MASK,
22534 0 : 8692 => Opcode::PseudoVSE32_V_M2,
22535 0 : 8693 => Opcode::PseudoVSE32_V_M2_MASK,
22536 0 : 8694 => Opcode::PseudoVSE32_V_M4,
22537 0 : 8695 => Opcode::PseudoVSE32_V_M4_MASK,
22538 0 : 8696 => Opcode::PseudoVSE32_V_M8,
22539 0 : 8697 => Opcode::PseudoVSE32_V_M8_MASK,
22540 0 : 8698 => Opcode::PseudoVSE32_V_MF2,
22541 0 : 8699 => Opcode::PseudoVSE32_V_MF2_MASK,
22542 0 : 8700 => Opcode::PseudoVSE64_V_M1,
22543 0 : 8701 => Opcode::PseudoVSE64_V_M1_MASK,
22544 0 : 8702 => Opcode::PseudoVSE64_V_M2,
22545 0 : 8703 => Opcode::PseudoVSE64_V_M2_MASK,
22546 0 : 8704 => Opcode::PseudoVSE64_V_M4,
22547 0 : 8705 => Opcode::PseudoVSE64_V_M4_MASK,
22548 0 : 8706 => Opcode::PseudoVSE64_V_M8,
22549 0 : 8707 => Opcode::PseudoVSE64_V_M8_MASK,
22550 0 : 8708 => Opcode::PseudoVSE8_V_M1,
22551 0 : 8709 => Opcode::PseudoVSE8_V_M1_MASK,
22552 0 : 8710 => Opcode::PseudoVSE8_V_M2,
22553 0 : 8711 => Opcode::PseudoVSE8_V_M2_MASK,
22554 0 : 8712 => Opcode::PseudoVSE8_V_M4,
22555 0 : 8713 => Opcode::PseudoVSE8_V_M4_MASK,
22556 0 : 8714 => Opcode::PseudoVSE8_V_M8,
22557 0 : 8715 => Opcode::PseudoVSE8_V_M8_MASK,
22558 0 : 8716 => Opcode::PseudoVSE8_V_MF2,
22559 0 : 8717 => Opcode::PseudoVSE8_V_MF2_MASK,
22560 0 : 8718 => Opcode::PseudoVSE8_V_MF4,
22561 0 : 8719 => Opcode::PseudoVSE8_V_MF4_MASK,
22562 0 : 8720 => Opcode::PseudoVSE8_V_MF8,
22563 0 : 8721 => Opcode::PseudoVSE8_V_MF8_MASK,
22564 0 : 8722 => Opcode::PseudoVSETIVLI,
22565 0 : 8723 => Opcode::PseudoVSETVLI,
22566 0 : 8724 => Opcode::PseudoVSETVLIX0,
22567 0 : 8725 => Opcode::PseudoVSEXT_VF2_M1,
22568 0 : 8726 => Opcode::PseudoVSEXT_VF2_M1_MASK,
22569 0 : 8727 => Opcode::PseudoVSEXT_VF2_M2,
22570 0 : 8728 => Opcode::PseudoVSEXT_VF2_M2_MASK,
22571 0 : 8729 => Opcode::PseudoVSEXT_VF2_M4,
22572 0 : 8730 => Opcode::PseudoVSEXT_VF2_M4_MASK,
22573 0 : 8731 => Opcode::PseudoVSEXT_VF2_M8,
22574 0 : 8732 => Opcode::PseudoVSEXT_VF2_M8_MASK,
22575 0 : 8733 => Opcode::PseudoVSEXT_VF2_MF2,
22576 0 : 8734 => Opcode::PseudoVSEXT_VF2_MF2_MASK,
22577 0 : 8735 => Opcode::PseudoVSEXT_VF2_MF4,
22578 0 : 8736 => Opcode::PseudoVSEXT_VF2_MF4_MASK,
22579 0 : 8737 => Opcode::PseudoVSEXT_VF4_M1,
22580 0 : 8738 => Opcode::PseudoVSEXT_VF4_M1_MASK,
22581 0 : 8739 => Opcode::PseudoVSEXT_VF4_M2,
22582 0 : 8740 => Opcode::PseudoVSEXT_VF4_M2_MASK,
22583 0 : 8741 => Opcode::PseudoVSEXT_VF4_M4,
22584 0 : 8742 => Opcode::PseudoVSEXT_VF4_M4_MASK,
22585 0 : 8743 => Opcode::PseudoVSEXT_VF4_M8,
22586 0 : 8744 => Opcode::PseudoVSEXT_VF4_M8_MASK,
22587 0 : 8745 => Opcode::PseudoVSEXT_VF4_MF2,
22588 0 : 8746 => Opcode::PseudoVSEXT_VF4_MF2_MASK,
22589 0 : 8747 => Opcode::PseudoVSEXT_VF8_M1,
22590 0 : 8748 => Opcode::PseudoVSEXT_VF8_M1_MASK,
22591 0 : 8749 => Opcode::PseudoVSEXT_VF8_M2,
22592 0 : 8750 => Opcode::PseudoVSEXT_VF8_M2_MASK,
22593 0 : 8751 => Opcode::PseudoVSEXT_VF8_M4,
22594 0 : 8752 => Opcode::PseudoVSEXT_VF8_M4_MASK,
22595 0 : 8753 => Opcode::PseudoVSEXT_VF8_M8,
22596 0 : 8754 => Opcode::PseudoVSEXT_VF8_M8_MASK,
22597 0 : 8755 => Opcode::PseudoVSHA2CH_VV_M1,
22598 0 : 8756 => Opcode::PseudoVSHA2CH_VV_M2,
22599 0 : 8757 => Opcode::PseudoVSHA2CH_VV_M4,
22600 0 : 8758 => Opcode::PseudoVSHA2CH_VV_M8,
22601 0 : 8759 => Opcode::PseudoVSHA2CH_VV_MF2,
22602 0 : 8760 => Opcode::PseudoVSHA2CL_VV_M1,
22603 0 : 8761 => Opcode::PseudoVSHA2CL_VV_M2,
22604 0 : 8762 => Opcode::PseudoVSHA2CL_VV_M4,
22605 0 : 8763 => Opcode::PseudoVSHA2CL_VV_M8,
22606 0 : 8764 => Opcode::PseudoVSHA2CL_VV_MF2,
22607 0 : 8765 => Opcode::PseudoVSHA2MS_VV_M1,
22608 0 : 8766 => Opcode::PseudoVSHA2MS_VV_M2,
22609 0 : 8767 => Opcode::PseudoVSHA2MS_VV_M4,
22610 0 : 8768 => Opcode::PseudoVSHA2MS_VV_M8,
22611 0 : 8769 => Opcode::PseudoVSHA2MS_VV_MF2,
22612 0 : 8770 => Opcode::PseudoVSLIDE1DOWN_VX_M1,
22613 0 : 8771 => Opcode::PseudoVSLIDE1DOWN_VX_M1_MASK,
22614 0 : 8772 => Opcode::PseudoVSLIDE1DOWN_VX_M2,
22615 0 : 8773 => Opcode::PseudoVSLIDE1DOWN_VX_M2_MASK,
22616 0 : 8774 => Opcode::PseudoVSLIDE1DOWN_VX_M4,
22617 0 : 8775 => Opcode::PseudoVSLIDE1DOWN_VX_M4_MASK,
22618 0 : 8776 => Opcode::PseudoVSLIDE1DOWN_VX_M8,
22619 0 : 8777 => Opcode::PseudoVSLIDE1DOWN_VX_M8_MASK,
22620 0 : 8778 => Opcode::PseudoVSLIDE1DOWN_VX_MF2,
22621 0 : 8779 => Opcode::PseudoVSLIDE1DOWN_VX_MF2_MASK,
22622 0 : 8780 => Opcode::PseudoVSLIDE1DOWN_VX_MF4,
22623 0 : 8781 => Opcode::PseudoVSLIDE1DOWN_VX_MF4_MASK,
22624 0 : 8782 => Opcode::PseudoVSLIDE1DOWN_VX_MF8,
22625 0 : 8783 => Opcode::PseudoVSLIDE1DOWN_VX_MF8_MASK,
22626 0 : 8784 => Opcode::PseudoVSLIDE1UP_VX_M1,
22627 0 : 8785 => Opcode::PseudoVSLIDE1UP_VX_M1_MASK,
22628 0 : 8786 => Opcode::PseudoVSLIDE1UP_VX_M2,
22629 0 : 8787 => Opcode::PseudoVSLIDE1UP_VX_M2_MASK,
22630 0 : 8788 => Opcode::PseudoVSLIDE1UP_VX_M4,
22631 0 : 8789 => Opcode::PseudoVSLIDE1UP_VX_M4_MASK,
22632 0 : 8790 => Opcode::PseudoVSLIDE1UP_VX_M8,
22633 0 : 8791 => Opcode::PseudoVSLIDE1UP_VX_M8_MASK,
22634 0 : 8792 => Opcode::PseudoVSLIDE1UP_VX_MF2,
22635 0 : 8793 => Opcode::PseudoVSLIDE1UP_VX_MF2_MASK,
22636 0 : 8794 => Opcode::PseudoVSLIDE1UP_VX_MF4,
22637 0 : 8795 => Opcode::PseudoVSLIDE1UP_VX_MF4_MASK,
22638 0 : 8796 => Opcode::PseudoVSLIDE1UP_VX_MF8,
22639 0 : 8797 => Opcode::PseudoVSLIDE1UP_VX_MF8_MASK,
22640 0 : 8798 => Opcode::PseudoVSLIDEDOWN_VI_M1,
22641 0 : 8799 => Opcode::PseudoVSLIDEDOWN_VI_M1_MASK,
22642 0 : 8800 => Opcode::PseudoVSLIDEDOWN_VI_M2,
22643 0 : 8801 => Opcode::PseudoVSLIDEDOWN_VI_M2_MASK,
22644 0 : 8802 => Opcode::PseudoVSLIDEDOWN_VI_M4,
22645 0 : 8803 => Opcode::PseudoVSLIDEDOWN_VI_M4_MASK,
22646 0 : 8804 => Opcode::PseudoVSLIDEDOWN_VI_M8,
22647 0 : 8805 => Opcode::PseudoVSLIDEDOWN_VI_M8_MASK,
22648 0 : 8806 => Opcode::PseudoVSLIDEDOWN_VI_MF2,
22649 0 : 8807 => Opcode::PseudoVSLIDEDOWN_VI_MF2_MASK,
22650 0 : 8808 => Opcode::PseudoVSLIDEDOWN_VI_MF4,
22651 0 : 8809 => Opcode::PseudoVSLIDEDOWN_VI_MF4_MASK,
22652 0 : 8810 => Opcode::PseudoVSLIDEDOWN_VI_MF8,
22653 0 : 8811 => Opcode::PseudoVSLIDEDOWN_VI_MF8_MASK,
22654 0 : 8812 => Opcode::PseudoVSLIDEDOWN_VX_M1,
22655 0 : 8813 => Opcode::PseudoVSLIDEDOWN_VX_M1_MASK,
22656 0 : 8814 => Opcode::PseudoVSLIDEDOWN_VX_M2,
22657 0 : 8815 => Opcode::PseudoVSLIDEDOWN_VX_M2_MASK,
22658 0 : 8816 => Opcode::PseudoVSLIDEDOWN_VX_M4,
22659 0 : 8817 => Opcode::PseudoVSLIDEDOWN_VX_M4_MASK,
22660 0 : 8818 => Opcode::PseudoVSLIDEDOWN_VX_M8,
22661 0 : 8819 => Opcode::PseudoVSLIDEDOWN_VX_M8_MASK,
22662 0 : 8820 => Opcode::PseudoVSLIDEDOWN_VX_MF2,
22663 0 : 8821 => Opcode::PseudoVSLIDEDOWN_VX_MF2_MASK,
22664 0 : 8822 => Opcode::PseudoVSLIDEDOWN_VX_MF4,
22665 0 : 8823 => Opcode::PseudoVSLIDEDOWN_VX_MF4_MASK,
22666 0 : 8824 => Opcode::PseudoVSLIDEDOWN_VX_MF8,
22667 0 : 8825 => Opcode::PseudoVSLIDEDOWN_VX_MF8_MASK,
22668 0 : 8826 => Opcode::PseudoVSLIDEUP_VI_M1,
22669 0 : 8827 => Opcode::PseudoVSLIDEUP_VI_M1_MASK,
22670 0 : 8828 => Opcode::PseudoVSLIDEUP_VI_M2,
22671 0 : 8829 => Opcode::PseudoVSLIDEUP_VI_M2_MASK,
22672 0 : 8830 => Opcode::PseudoVSLIDEUP_VI_M4,
22673 0 : 8831 => Opcode::PseudoVSLIDEUP_VI_M4_MASK,
22674 0 : 8832 => Opcode::PseudoVSLIDEUP_VI_M8,
22675 0 : 8833 => Opcode::PseudoVSLIDEUP_VI_M8_MASK,
22676 0 : 8834 => Opcode::PseudoVSLIDEUP_VI_MF2,
22677 0 : 8835 => Opcode::PseudoVSLIDEUP_VI_MF2_MASK,
22678 0 : 8836 => Opcode::PseudoVSLIDEUP_VI_MF4,
22679 0 : 8837 => Opcode::PseudoVSLIDEUP_VI_MF4_MASK,
22680 0 : 8838 => Opcode::PseudoVSLIDEUP_VI_MF8,
22681 0 : 8839 => Opcode::PseudoVSLIDEUP_VI_MF8_MASK,
22682 0 : 8840 => Opcode::PseudoVSLIDEUP_VX_M1,
22683 0 : 8841 => Opcode::PseudoVSLIDEUP_VX_M1_MASK,
22684 0 : 8842 => Opcode::PseudoVSLIDEUP_VX_M2,
22685 0 : 8843 => Opcode::PseudoVSLIDEUP_VX_M2_MASK,
22686 0 : 8844 => Opcode::PseudoVSLIDEUP_VX_M4,
22687 0 : 8845 => Opcode::PseudoVSLIDEUP_VX_M4_MASK,
22688 0 : 8846 => Opcode::PseudoVSLIDEUP_VX_M8,
22689 0 : 8847 => Opcode::PseudoVSLIDEUP_VX_M8_MASK,
22690 0 : 8848 => Opcode::PseudoVSLIDEUP_VX_MF2,
22691 0 : 8849 => Opcode::PseudoVSLIDEUP_VX_MF2_MASK,
22692 0 : 8850 => Opcode::PseudoVSLIDEUP_VX_MF4,
22693 0 : 8851 => Opcode::PseudoVSLIDEUP_VX_MF4_MASK,
22694 0 : 8852 => Opcode::PseudoVSLIDEUP_VX_MF8,
22695 0 : 8853 => Opcode::PseudoVSLIDEUP_VX_MF8_MASK,
22696 0 : 8854 => Opcode::PseudoVSLL_VI_M1,
22697 0 : 8855 => Opcode::PseudoVSLL_VI_M1_MASK,
22698 0 : 8856 => Opcode::PseudoVSLL_VI_M2,
22699 0 : 8857 => Opcode::PseudoVSLL_VI_M2_MASK,
22700 0 : 8858 => Opcode::PseudoVSLL_VI_M4,
22701 0 : 8859 => Opcode::PseudoVSLL_VI_M4_MASK,
22702 0 : 8860 => Opcode::PseudoVSLL_VI_M8,
22703 0 : 8861 => Opcode::PseudoVSLL_VI_M8_MASK,
22704 0 : 8862 => Opcode::PseudoVSLL_VI_MF2,
22705 0 : 8863 => Opcode::PseudoVSLL_VI_MF2_MASK,
22706 0 : 8864 => Opcode::PseudoVSLL_VI_MF4,
22707 0 : 8865 => Opcode::PseudoVSLL_VI_MF4_MASK,
22708 0 : 8866 => Opcode::PseudoVSLL_VI_MF8,
22709 0 : 8867 => Opcode::PseudoVSLL_VI_MF8_MASK,
22710 0 : 8868 => Opcode::PseudoVSLL_VV_M1,
22711 0 : 8869 => Opcode::PseudoVSLL_VV_M1_MASK,
22712 0 : 8870 => Opcode::PseudoVSLL_VV_M2,
22713 0 : 8871 => Opcode::PseudoVSLL_VV_M2_MASK,
22714 0 : 8872 => Opcode::PseudoVSLL_VV_M4,
22715 0 : 8873 => Opcode::PseudoVSLL_VV_M4_MASK,
22716 0 : 8874 => Opcode::PseudoVSLL_VV_M8,
22717 0 : 8875 => Opcode::PseudoVSLL_VV_M8_MASK,
22718 0 : 8876 => Opcode::PseudoVSLL_VV_MF2,
22719 0 : 8877 => Opcode::PseudoVSLL_VV_MF2_MASK,
22720 0 : 8878 => Opcode::PseudoVSLL_VV_MF4,
22721 0 : 8879 => Opcode::PseudoVSLL_VV_MF4_MASK,
22722 0 : 8880 => Opcode::PseudoVSLL_VV_MF8,
22723 0 : 8881 => Opcode::PseudoVSLL_VV_MF8_MASK,
22724 0 : 8882 => Opcode::PseudoVSLL_VX_M1,
22725 0 : 8883 => Opcode::PseudoVSLL_VX_M1_MASK,
22726 0 : 8884 => Opcode::PseudoVSLL_VX_M2,
22727 0 : 8885 => Opcode::PseudoVSLL_VX_M2_MASK,
22728 0 : 8886 => Opcode::PseudoVSLL_VX_M4,
22729 0 : 8887 => Opcode::PseudoVSLL_VX_M4_MASK,
22730 0 : 8888 => Opcode::PseudoVSLL_VX_M8,
22731 0 : 8889 => Opcode::PseudoVSLL_VX_M8_MASK,
22732 0 : 8890 => Opcode::PseudoVSLL_VX_MF2,
22733 0 : 8891 => Opcode::PseudoVSLL_VX_MF2_MASK,
22734 0 : 8892 => Opcode::PseudoVSLL_VX_MF4,
22735 0 : 8893 => Opcode::PseudoVSLL_VX_MF4_MASK,
22736 0 : 8894 => Opcode::PseudoVSLL_VX_MF8,
22737 0 : 8895 => Opcode::PseudoVSLL_VX_MF8_MASK,
22738 0 : 8896 => Opcode::PseudoVSM3C_VI_M1,
22739 0 : 8897 => Opcode::PseudoVSM3C_VI_M2,
22740 0 : 8898 => Opcode::PseudoVSM3C_VI_M4,
22741 0 : 8899 => Opcode::PseudoVSM3C_VI_M8,
22742 0 : 8900 => Opcode::PseudoVSM3C_VI_MF2,
22743 0 : 8901 => Opcode::PseudoVSM3ME_VV_M1,
22744 0 : 8902 => Opcode::PseudoVSM3ME_VV_M2,
22745 0 : 8903 => Opcode::PseudoVSM3ME_VV_M4,
22746 0 : 8904 => Opcode::PseudoVSM3ME_VV_M8,
22747 0 : 8905 => Opcode::PseudoVSM3ME_VV_MF2,
22748 0 : 8906 => Opcode::PseudoVSM4K_VI_M1,
22749 0 : 8907 => Opcode::PseudoVSM4K_VI_M2,
22750 0 : 8908 => Opcode::PseudoVSM4K_VI_M4,
22751 0 : 8909 => Opcode::PseudoVSM4K_VI_M8,
22752 0 : 8910 => Opcode::PseudoVSM4K_VI_MF2,
22753 0 : 8911 => Opcode::PseudoVSM4R_VS_M1_M1,
22754 0 : 8912 => Opcode::PseudoVSM4R_VS_M1_MF2,
22755 0 : 8913 => Opcode::PseudoVSM4R_VS_M1_MF4,
22756 0 : 8914 => Opcode::PseudoVSM4R_VS_M1_MF8,
22757 0 : 8915 => Opcode::PseudoVSM4R_VS_M2_M1,
22758 0 : 8916 => Opcode::PseudoVSM4R_VS_M2_M2,
22759 0 : 8917 => Opcode::PseudoVSM4R_VS_M2_MF2,
22760 0 : 8918 => Opcode::PseudoVSM4R_VS_M2_MF4,
22761 0 : 8919 => Opcode::PseudoVSM4R_VS_M2_MF8,
22762 0 : 8920 => Opcode::PseudoVSM4R_VS_M4_M1,
22763 0 : 8921 => Opcode::PseudoVSM4R_VS_M4_M2,
22764 0 : 8922 => Opcode::PseudoVSM4R_VS_M4_M4,
22765 0 : 8923 => Opcode::PseudoVSM4R_VS_M4_MF2,
22766 0 : 8924 => Opcode::PseudoVSM4R_VS_M4_MF4,
22767 0 : 8925 => Opcode::PseudoVSM4R_VS_M4_MF8,
22768 0 : 8926 => Opcode::PseudoVSM4R_VS_M8_M1,
22769 0 : 8927 => Opcode::PseudoVSM4R_VS_M8_M2,
22770 0 : 8928 => Opcode::PseudoVSM4R_VS_M8_M4,
22771 0 : 8929 => Opcode::PseudoVSM4R_VS_M8_MF2,
22772 0 : 8930 => Opcode::PseudoVSM4R_VS_M8_MF4,
22773 0 : 8931 => Opcode::PseudoVSM4R_VS_M8_MF8,
22774 0 : 8932 => Opcode::PseudoVSM4R_VS_MF2_MF2,
22775 0 : 8933 => Opcode::PseudoVSM4R_VS_MF2_MF4,
22776 0 : 8934 => Opcode::PseudoVSM4R_VS_MF2_MF8,
22777 0 : 8935 => Opcode::PseudoVSM4R_VV_M1,
22778 0 : 8936 => Opcode::PseudoVSM4R_VV_M2,
22779 0 : 8937 => Opcode::PseudoVSM4R_VV_M4,
22780 0 : 8938 => Opcode::PseudoVSM4R_VV_M8,
22781 0 : 8939 => Opcode::PseudoVSM4R_VV_MF2,
22782 0 : 8940 => Opcode::PseudoVSMUL_VV_M1,
22783 0 : 8941 => Opcode::PseudoVSMUL_VV_M1_MASK,
22784 0 : 8942 => Opcode::PseudoVSMUL_VV_M2,
22785 0 : 8943 => Opcode::PseudoVSMUL_VV_M2_MASK,
22786 0 : 8944 => Opcode::PseudoVSMUL_VV_M4,
22787 0 : 8945 => Opcode::PseudoVSMUL_VV_M4_MASK,
22788 0 : 8946 => Opcode::PseudoVSMUL_VV_M8,
22789 0 : 8947 => Opcode::PseudoVSMUL_VV_M8_MASK,
22790 0 : 8948 => Opcode::PseudoVSMUL_VV_MF2,
22791 0 : 8949 => Opcode::PseudoVSMUL_VV_MF2_MASK,
22792 0 : 8950 => Opcode::PseudoVSMUL_VV_MF4,
22793 0 : 8951 => Opcode::PseudoVSMUL_VV_MF4_MASK,
22794 0 : 8952 => Opcode::PseudoVSMUL_VV_MF8,
22795 0 : 8953 => Opcode::PseudoVSMUL_VV_MF8_MASK,
22796 0 : 8954 => Opcode::PseudoVSMUL_VX_M1,
22797 0 : 8955 => Opcode::PseudoVSMUL_VX_M1_MASK,
22798 0 : 8956 => Opcode::PseudoVSMUL_VX_M2,
22799 0 : 8957 => Opcode::PseudoVSMUL_VX_M2_MASK,
22800 0 : 8958 => Opcode::PseudoVSMUL_VX_M4,
22801 0 : 8959 => Opcode::PseudoVSMUL_VX_M4_MASK,
22802 0 : 8960 => Opcode::PseudoVSMUL_VX_M8,
22803 0 : 8961 => Opcode::PseudoVSMUL_VX_M8_MASK,
22804 0 : 8962 => Opcode::PseudoVSMUL_VX_MF2,
22805 0 : 8963 => Opcode::PseudoVSMUL_VX_MF2_MASK,
22806 0 : 8964 => Opcode::PseudoVSMUL_VX_MF4,
22807 0 : 8965 => Opcode::PseudoVSMUL_VX_MF4_MASK,
22808 0 : 8966 => Opcode::PseudoVSMUL_VX_MF8,
22809 0 : 8967 => Opcode::PseudoVSMUL_VX_MF8_MASK,
22810 0 : 8968 => Opcode::PseudoVSM_V_B1,
22811 0 : 8969 => Opcode::PseudoVSM_V_B16,
22812 0 : 8970 => Opcode::PseudoVSM_V_B2,
22813 0 : 8971 => Opcode::PseudoVSM_V_B32,
22814 0 : 8972 => Opcode::PseudoVSM_V_B4,
22815 0 : 8973 => Opcode::PseudoVSM_V_B64,
22816 0 : 8974 => Opcode::PseudoVSM_V_B8,
22817 0 : 8975 => Opcode::PseudoVSOXEI16_V_M1_M1,
22818 0 : 8976 => Opcode::PseudoVSOXEI16_V_M1_M1_MASK,
22819 0 : 8977 => Opcode::PseudoVSOXEI16_V_M1_M2,
22820 0 : 8978 => Opcode::PseudoVSOXEI16_V_M1_M2_MASK,
22821 0 : 8979 => Opcode::PseudoVSOXEI16_V_M1_M4,
22822 0 : 8980 => Opcode::PseudoVSOXEI16_V_M1_M4_MASK,
22823 0 : 8981 => Opcode::PseudoVSOXEI16_V_M1_MF2,
22824 0 : 8982 => Opcode::PseudoVSOXEI16_V_M1_MF2_MASK,
22825 0 : 8983 => Opcode::PseudoVSOXEI16_V_M2_M1,
22826 0 : 8984 => Opcode::PseudoVSOXEI16_V_M2_M1_MASK,
22827 0 : 8985 => Opcode::PseudoVSOXEI16_V_M2_M2,
22828 0 : 8986 => Opcode::PseudoVSOXEI16_V_M2_M2_MASK,
22829 0 : 8987 => Opcode::PseudoVSOXEI16_V_M2_M4,
22830 0 : 8988 => Opcode::PseudoVSOXEI16_V_M2_M4_MASK,
22831 0 : 8989 => Opcode::PseudoVSOXEI16_V_M2_M8,
22832 0 : 8990 => Opcode::PseudoVSOXEI16_V_M2_M8_MASK,
22833 0 : 8991 => Opcode::PseudoVSOXEI16_V_M4_M2,
22834 0 : 8992 => Opcode::PseudoVSOXEI16_V_M4_M2_MASK,
22835 0 : 8993 => Opcode::PseudoVSOXEI16_V_M4_M4,
22836 0 : 8994 => Opcode::PseudoVSOXEI16_V_M4_M4_MASK,
22837 0 : 8995 => Opcode::PseudoVSOXEI16_V_M4_M8,
22838 0 : 8996 => Opcode::PseudoVSOXEI16_V_M4_M8_MASK,
22839 0 : 8997 => Opcode::PseudoVSOXEI16_V_M8_M4,
22840 0 : 8998 => Opcode::PseudoVSOXEI16_V_M8_M4_MASK,
22841 0 : 8999 => Opcode::PseudoVSOXEI16_V_M8_M8,
22842 0 : 9000 => Opcode::PseudoVSOXEI16_V_M8_M8_MASK,
22843 0 : 9001 => Opcode::PseudoVSOXEI16_V_MF2_M1,
22844 0 : 9002 => Opcode::PseudoVSOXEI16_V_MF2_M1_MASK,
22845 0 : 9003 => Opcode::PseudoVSOXEI16_V_MF2_M2,
22846 0 : 9004 => Opcode::PseudoVSOXEI16_V_MF2_M2_MASK,
22847 0 : 9005 => Opcode::PseudoVSOXEI16_V_MF2_MF2,
22848 0 : 9006 => Opcode::PseudoVSOXEI16_V_MF2_MF2_MASK,
22849 0 : 9007 => Opcode::PseudoVSOXEI16_V_MF2_MF4,
22850 0 : 9008 => Opcode::PseudoVSOXEI16_V_MF2_MF4_MASK,
22851 0 : 9009 => Opcode::PseudoVSOXEI16_V_MF4_M1,
22852 0 : 9010 => Opcode::PseudoVSOXEI16_V_MF4_M1_MASK,
22853 0 : 9011 => Opcode::PseudoVSOXEI16_V_MF4_MF2,
22854 0 : 9012 => Opcode::PseudoVSOXEI16_V_MF4_MF2_MASK,
22855 0 : 9013 => Opcode::PseudoVSOXEI16_V_MF4_MF4,
22856 0 : 9014 => Opcode::PseudoVSOXEI16_V_MF4_MF4_MASK,
22857 0 : 9015 => Opcode::PseudoVSOXEI16_V_MF4_MF8,
22858 0 : 9016 => Opcode::PseudoVSOXEI16_V_MF4_MF8_MASK,
22859 0 : 9017 => Opcode::PseudoVSOXEI32_V_M1_M1,
22860 0 : 9018 => Opcode::PseudoVSOXEI32_V_M1_M1_MASK,
22861 0 : 9019 => Opcode::PseudoVSOXEI32_V_M1_M2,
22862 0 : 9020 => Opcode::PseudoVSOXEI32_V_M1_M2_MASK,
22863 0 : 9021 => Opcode::PseudoVSOXEI32_V_M1_MF2,
22864 0 : 9022 => Opcode::PseudoVSOXEI32_V_M1_MF2_MASK,
22865 0 : 9023 => Opcode::PseudoVSOXEI32_V_M1_MF4,
22866 0 : 9024 => Opcode::PseudoVSOXEI32_V_M1_MF4_MASK,
22867 0 : 9025 => Opcode::PseudoVSOXEI32_V_M2_M1,
22868 0 : 9026 => Opcode::PseudoVSOXEI32_V_M2_M1_MASK,
22869 0 : 9027 => Opcode::PseudoVSOXEI32_V_M2_M2,
22870 0 : 9028 => Opcode::PseudoVSOXEI32_V_M2_M2_MASK,
22871 0 : 9029 => Opcode::PseudoVSOXEI32_V_M2_M4,
22872 0 : 9030 => Opcode::PseudoVSOXEI32_V_M2_M4_MASK,
22873 0 : 9031 => Opcode::PseudoVSOXEI32_V_M2_MF2,
22874 0 : 9032 => Opcode::PseudoVSOXEI32_V_M2_MF2_MASK,
22875 0 : 9033 => Opcode::PseudoVSOXEI32_V_M4_M1,
22876 0 : 9034 => Opcode::PseudoVSOXEI32_V_M4_M1_MASK,
22877 0 : 9035 => Opcode::PseudoVSOXEI32_V_M4_M2,
22878 0 : 9036 => Opcode::PseudoVSOXEI32_V_M4_M2_MASK,
22879 0 : 9037 => Opcode::PseudoVSOXEI32_V_M4_M4,
22880 0 : 9038 => Opcode::PseudoVSOXEI32_V_M4_M4_MASK,
22881 0 : 9039 => Opcode::PseudoVSOXEI32_V_M4_M8,
22882 0 : 9040 => Opcode::PseudoVSOXEI32_V_M4_M8_MASK,
22883 0 : 9041 => Opcode::PseudoVSOXEI32_V_M8_M2,
22884 0 : 9042 => Opcode::PseudoVSOXEI32_V_M8_M2_MASK,
22885 0 : 9043 => Opcode::PseudoVSOXEI32_V_M8_M4,
22886 0 : 9044 => Opcode::PseudoVSOXEI32_V_M8_M4_MASK,
22887 0 : 9045 => Opcode::PseudoVSOXEI32_V_M8_M8,
22888 0 : 9046 => Opcode::PseudoVSOXEI32_V_M8_M8_MASK,
22889 0 : 9047 => Opcode::PseudoVSOXEI32_V_MF2_M1,
22890 0 : 9048 => Opcode::PseudoVSOXEI32_V_MF2_M1_MASK,
22891 0 : 9049 => Opcode::PseudoVSOXEI32_V_MF2_MF2,
22892 0 : 9050 => Opcode::PseudoVSOXEI32_V_MF2_MF2_MASK,
22893 0 : 9051 => Opcode::PseudoVSOXEI32_V_MF2_MF4,
22894 0 : 9052 => Opcode::PseudoVSOXEI32_V_MF2_MF4_MASK,
22895 0 : 9053 => Opcode::PseudoVSOXEI32_V_MF2_MF8,
22896 0 : 9054 => Opcode::PseudoVSOXEI32_V_MF2_MF8_MASK,
22897 0 : 9055 => Opcode::PseudoVSOXEI64_V_M1_M1,
22898 0 : 9056 => Opcode::PseudoVSOXEI64_V_M1_M1_MASK,
22899 0 : 9057 => Opcode::PseudoVSOXEI64_V_M1_MF2,
22900 0 : 9058 => Opcode::PseudoVSOXEI64_V_M1_MF2_MASK,
22901 0 : 9059 => Opcode::PseudoVSOXEI64_V_M1_MF4,
22902 0 : 9060 => Opcode::PseudoVSOXEI64_V_M1_MF4_MASK,
22903 0 : 9061 => Opcode::PseudoVSOXEI64_V_M1_MF8,
22904 0 : 9062 => Opcode::PseudoVSOXEI64_V_M1_MF8_MASK,
22905 0 : 9063 => Opcode::PseudoVSOXEI64_V_M2_M1,
22906 0 : 9064 => Opcode::PseudoVSOXEI64_V_M2_M1_MASK,
22907 0 : 9065 => Opcode::PseudoVSOXEI64_V_M2_M2,
22908 0 : 9066 => Opcode::PseudoVSOXEI64_V_M2_M2_MASK,
22909 0 : 9067 => Opcode::PseudoVSOXEI64_V_M2_MF2,
22910 0 : 9068 => Opcode::PseudoVSOXEI64_V_M2_MF2_MASK,
22911 0 : 9069 => Opcode::PseudoVSOXEI64_V_M2_MF4,
22912 0 : 9070 => Opcode::PseudoVSOXEI64_V_M2_MF4_MASK,
22913 0 : 9071 => Opcode::PseudoVSOXEI64_V_M4_M1,
22914 0 : 9072 => Opcode::PseudoVSOXEI64_V_M4_M1_MASK,
22915 0 : 9073 => Opcode::PseudoVSOXEI64_V_M4_M2,
22916 0 : 9074 => Opcode::PseudoVSOXEI64_V_M4_M2_MASK,
22917 0 : 9075 => Opcode::PseudoVSOXEI64_V_M4_M4,
22918 0 : 9076 => Opcode::PseudoVSOXEI64_V_M4_M4_MASK,
22919 0 : 9077 => Opcode::PseudoVSOXEI64_V_M4_MF2,
22920 0 : 9078 => Opcode::PseudoVSOXEI64_V_M4_MF2_MASK,
22921 0 : 9079 => Opcode::PseudoVSOXEI64_V_M8_M1,
22922 0 : 9080 => Opcode::PseudoVSOXEI64_V_M8_M1_MASK,
22923 0 : 9081 => Opcode::PseudoVSOXEI64_V_M8_M2,
22924 0 : 9082 => Opcode::PseudoVSOXEI64_V_M8_M2_MASK,
22925 0 : 9083 => Opcode::PseudoVSOXEI64_V_M8_M4,
22926 0 : 9084 => Opcode::PseudoVSOXEI64_V_M8_M4_MASK,
22927 0 : 9085 => Opcode::PseudoVSOXEI64_V_M8_M8,
22928 0 : 9086 => Opcode::PseudoVSOXEI64_V_M8_M8_MASK,
22929 0 : 9087 => Opcode::PseudoVSOXEI8_V_M1_M1,
22930 0 : 9088 => Opcode::PseudoVSOXEI8_V_M1_M1_MASK,
22931 0 : 9089 => Opcode::PseudoVSOXEI8_V_M1_M2,
22932 0 : 9090 => Opcode::PseudoVSOXEI8_V_M1_M2_MASK,
22933 0 : 9091 => Opcode::PseudoVSOXEI8_V_M1_M4,
22934 0 : 9092 => Opcode::PseudoVSOXEI8_V_M1_M4_MASK,
22935 0 : 9093 => Opcode::PseudoVSOXEI8_V_M1_M8,
22936 0 : 9094 => Opcode::PseudoVSOXEI8_V_M1_M8_MASK,
22937 0 : 9095 => Opcode::PseudoVSOXEI8_V_M2_M2,
22938 0 : 9096 => Opcode::PseudoVSOXEI8_V_M2_M2_MASK,
22939 0 : 9097 => Opcode::PseudoVSOXEI8_V_M2_M4,
22940 0 : 9098 => Opcode::PseudoVSOXEI8_V_M2_M4_MASK,
22941 0 : 9099 => Opcode::PseudoVSOXEI8_V_M2_M8,
22942 0 : 9100 => Opcode::PseudoVSOXEI8_V_M2_M8_MASK,
22943 0 : 9101 => Opcode::PseudoVSOXEI8_V_M4_M4,
22944 0 : 9102 => Opcode::PseudoVSOXEI8_V_M4_M4_MASK,
22945 0 : 9103 => Opcode::PseudoVSOXEI8_V_M4_M8,
22946 0 : 9104 => Opcode::PseudoVSOXEI8_V_M4_M8_MASK,
22947 0 : 9105 => Opcode::PseudoVSOXEI8_V_M8_M8,
22948 0 : 9106 => Opcode::PseudoVSOXEI8_V_M8_M8_MASK,
22949 0 : 9107 => Opcode::PseudoVSOXEI8_V_MF2_M1,
22950 0 : 9108 => Opcode::PseudoVSOXEI8_V_MF2_M1_MASK,
22951 0 : 9109 => Opcode::PseudoVSOXEI8_V_MF2_M2,
22952 0 : 9110 => Opcode::PseudoVSOXEI8_V_MF2_M2_MASK,
22953 0 : 9111 => Opcode::PseudoVSOXEI8_V_MF2_M4,
22954 0 : 9112 => Opcode::PseudoVSOXEI8_V_MF2_M4_MASK,
22955 0 : 9113 => Opcode::PseudoVSOXEI8_V_MF2_MF2,
22956 0 : 9114 => Opcode::PseudoVSOXEI8_V_MF2_MF2_MASK,
22957 0 : 9115 => Opcode::PseudoVSOXEI8_V_MF4_M1,
22958 0 : 9116 => Opcode::PseudoVSOXEI8_V_MF4_M1_MASK,
22959 0 : 9117 => Opcode::PseudoVSOXEI8_V_MF4_M2,
22960 0 : 9118 => Opcode::PseudoVSOXEI8_V_MF4_M2_MASK,
22961 0 : 9119 => Opcode::PseudoVSOXEI8_V_MF4_MF2,
22962 0 : 9120 => Opcode::PseudoVSOXEI8_V_MF4_MF2_MASK,
22963 0 : 9121 => Opcode::PseudoVSOXEI8_V_MF4_MF4,
22964 0 : 9122 => Opcode::PseudoVSOXEI8_V_MF4_MF4_MASK,
22965 0 : 9123 => Opcode::PseudoVSOXEI8_V_MF8_M1,
22966 0 : 9124 => Opcode::PseudoVSOXEI8_V_MF8_M1_MASK,
22967 0 : 9125 => Opcode::PseudoVSOXEI8_V_MF8_MF2,
22968 0 : 9126 => Opcode::PseudoVSOXEI8_V_MF8_MF2_MASK,
22969 0 : 9127 => Opcode::PseudoVSOXEI8_V_MF8_MF4,
22970 0 : 9128 => Opcode::PseudoVSOXEI8_V_MF8_MF4_MASK,
22971 0 : 9129 => Opcode::PseudoVSOXEI8_V_MF8_MF8,
22972 0 : 9130 => Opcode::PseudoVSOXEI8_V_MF8_MF8_MASK,
22973 0 : 9131 => Opcode::PseudoVSOXSEG2EI16_V_M1_M1,
22974 0 : 9132 => Opcode::PseudoVSOXSEG2EI16_V_M1_M1_MASK,
22975 0 : 9133 => Opcode::PseudoVSOXSEG2EI16_V_M1_M2,
22976 0 : 9134 => Opcode::PseudoVSOXSEG2EI16_V_M1_M2_MASK,
22977 0 : 9135 => Opcode::PseudoVSOXSEG2EI16_V_M1_M4,
22978 0 : 9136 => Opcode::PseudoVSOXSEG2EI16_V_M1_M4_MASK,
22979 0 : 9137 => Opcode::PseudoVSOXSEG2EI16_V_M1_MF2,
22980 0 : 9138 => Opcode::PseudoVSOXSEG2EI16_V_M1_MF2_MASK,
22981 0 : 9139 => Opcode::PseudoVSOXSEG2EI16_V_M2_M1,
22982 0 : 9140 => Opcode::PseudoVSOXSEG2EI16_V_M2_M1_MASK,
22983 0 : 9141 => Opcode::PseudoVSOXSEG2EI16_V_M2_M2,
22984 0 : 9142 => Opcode::PseudoVSOXSEG2EI16_V_M2_M2_MASK,
22985 0 : 9143 => Opcode::PseudoVSOXSEG2EI16_V_M2_M4,
22986 0 : 9144 => Opcode::PseudoVSOXSEG2EI16_V_M2_M4_MASK,
22987 0 : 9145 => Opcode::PseudoVSOXSEG2EI16_V_M4_M2,
22988 0 : 9146 => Opcode::PseudoVSOXSEG2EI16_V_M4_M2_MASK,
22989 0 : 9147 => Opcode::PseudoVSOXSEG2EI16_V_M4_M4,
22990 0 : 9148 => Opcode::PseudoVSOXSEG2EI16_V_M4_M4_MASK,
22991 0 : 9149 => Opcode::PseudoVSOXSEG2EI16_V_M8_M4,
22992 0 : 9150 => Opcode::PseudoVSOXSEG2EI16_V_M8_M4_MASK,
22993 0 : 9151 => Opcode::PseudoVSOXSEG2EI16_V_MF2_M1,
22994 0 : 9152 => Opcode::PseudoVSOXSEG2EI16_V_MF2_M1_MASK,
22995 0 : 9153 => Opcode::PseudoVSOXSEG2EI16_V_MF2_M2,
22996 0 : 9154 => Opcode::PseudoVSOXSEG2EI16_V_MF2_M2_MASK,
22997 0 : 9155 => Opcode::PseudoVSOXSEG2EI16_V_MF2_MF2,
22998 0 : 9156 => Opcode::PseudoVSOXSEG2EI16_V_MF2_MF2_MASK,
22999 0 : 9157 => Opcode::PseudoVSOXSEG2EI16_V_MF2_MF4,
23000 0 : 9158 => Opcode::PseudoVSOXSEG2EI16_V_MF2_MF4_MASK,
23001 0 : 9159 => Opcode::PseudoVSOXSEG2EI16_V_MF4_M1,
23002 0 : 9160 => Opcode::PseudoVSOXSEG2EI16_V_MF4_M1_MASK,
23003 0 : 9161 => Opcode::PseudoVSOXSEG2EI16_V_MF4_MF2,
23004 0 : 9162 => Opcode::PseudoVSOXSEG2EI16_V_MF4_MF2_MASK,
23005 0 : 9163 => Opcode::PseudoVSOXSEG2EI16_V_MF4_MF4,
23006 0 : 9164 => Opcode::PseudoVSOXSEG2EI16_V_MF4_MF4_MASK,
23007 0 : 9165 => Opcode::PseudoVSOXSEG2EI16_V_MF4_MF8,
23008 0 : 9166 => Opcode::PseudoVSOXSEG2EI16_V_MF4_MF8_MASK,
23009 0 : 9167 => Opcode::PseudoVSOXSEG2EI32_V_M1_M1,
23010 0 : 9168 => Opcode::PseudoVSOXSEG2EI32_V_M1_M1_MASK,
23011 0 : 9169 => Opcode::PseudoVSOXSEG2EI32_V_M1_M2,
23012 0 : 9170 => Opcode::PseudoVSOXSEG2EI32_V_M1_M2_MASK,
23013 0 : 9171 => Opcode::PseudoVSOXSEG2EI32_V_M1_MF2,
23014 0 : 9172 => Opcode::PseudoVSOXSEG2EI32_V_M1_MF2_MASK,
23015 0 : 9173 => Opcode::PseudoVSOXSEG2EI32_V_M1_MF4,
23016 0 : 9174 => Opcode::PseudoVSOXSEG2EI32_V_M1_MF4_MASK,
23017 0 : 9175 => Opcode::PseudoVSOXSEG2EI32_V_M2_M1,
23018 0 : 9176 => Opcode::PseudoVSOXSEG2EI32_V_M2_M1_MASK,
23019 0 : 9177 => Opcode::PseudoVSOXSEG2EI32_V_M2_M2,
23020 0 : 9178 => Opcode::PseudoVSOXSEG2EI32_V_M2_M2_MASK,
23021 0 : 9179 => Opcode::PseudoVSOXSEG2EI32_V_M2_M4,
23022 0 : 9180 => Opcode::PseudoVSOXSEG2EI32_V_M2_M4_MASK,
23023 0 : 9181 => Opcode::PseudoVSOXSEG2EI32_V_M2_MF2,
23024 0 : 9182 => Opcode::PseudoVSOXSEG2EI32_V_M2_MF2_MASK,
23025 0 : 9183 => Opcode::PseudoVSOXSEG2EI32_V_M4_M1,
23026 0 : 9184 => Opcode::PseudoVSOXSEG2EI32_V_M4_M1_MASK,
23027 0 : 9185 => Opcode::PseudoVSOXSEG2EI32_V_M4_M2,
23028 0 : 9186 => Opcode::PseudoVSOXSEG2EI32_V_M4_M2_MASK,
23029 0 : 9187 => Opcode::PseudoVSOXSEG2EI32_V_M4_M4,
23030 0 : 9188 => Opcode::PseudoVSOXSEG2EI32_V_M4_M4_MASK,
23031 0 : 9189 => Opcode::PseudoVSOXSEG2EI32_V_M8_M2,
23032 0 : 9190 => Opcode::PseudoVSOXSEG2EI32_V_M8_M2_MASK,
23033 0 : 9191 => Opcode::PseudoVSOXSEG2EI32_V_M8_M4,
23034 0 : 9192 => Opcode::PseudoVSOXSEG2EI32_V_M8_M4_MASK,
23035 0 : 9193 => Opcode::PseudoVSOXSEG2EI32_V_MF2_M1,
23036 0 : 9194 => Opcode::PseudoVSOXSEG2EI32_V_MF2_M1_MASK,
23037 0 : 9195 => Opcode::PseudoVSOXSEG2EI32_V_MF2_MF2,
23038 0 : 9196 => Opcode::PseudoVSOXSEG2EI32_V_MF2_MF2_MASK,
23039 0 : 9197 => Opcode::PseudoVSOXSEG2EI32_V_MF2_MF4,
23040 0 : 9198 => Opcode::PseudoVSOXSEG2EI32_V_MF2_MF4_MASK,
23041 0 : 9199 => Opcode::PseudoVSOXSEG2EI32_V_MF2_MF8,
23042 0 : 9200 => Opcode::PseudoVSOXSEG2EI32_V_MF2_MF8_MASK,
23043 0 : 9201 => Opcode::PseudoVSOXSEG2EI64_V_M1_M1,
23044 0 : 9202 => Opcode::PseudoVSOXSEG2EI64_V_M1_M1_MASK,
23045 0 : 9203 => Opcode::PseudoVSOXSEG2EI64_V_M1_MF2,
23046 0 : 9204 => Opcode::PseudoVSOXSEG2EI64_V_M1_MF2_MASK,
23047 0 : 9205 => Opcode::PseudoVSOXSEG2EI64_V_M1_MF4,
23048 0 : 9206 => Opcode::PseudoVSOXSEG2EI64_V_M1_MF4_MASK,
23049 0 : 9207 => Opcode::PseudoVSOXSEG2EI64_V_M1_MF8,
23050 0 : 9208 => Opcode::PseudoVSOXSEG2EI64_V_M1_MF8_MASK,
23051 0 : 9209 => Opcode::PseudoVSOXSEG2EI64_V_M2_M1,
23052 0 : 9210 => Opcode::PseudoVSOXSEG2EI64_V_M2_M1_MASK,
23053 0 : 9211 => Opcode::PseudoVSOXSEG2EI64_V_M2_M2,
23054 0 : 9212 => Opcode::PseudoVSOXSEG2EI64_V_M2_M2_MASK,
23055 0 : 9213 => Opcode::PseudoVSOXSEG2EI64_V_M2_MF2,
23056 0 : 9214 => Opcode::PseudoVSOXSEG2EI64_V_M2_MF2_MASK,
23057 0 : 9215 => Opcode::PseudoVSOXSEG2EI64_V_M2_MF4,
23058 0 : 9216 => Opcode::PseudoVSOXSEG2EI64_V_M2_MF4_MASK,
23059 0 : 9217 => Opcode::PseudoVSOXSEG2EI64_V_M4_M1,
23060 0 : 9218 => Opcode::PseudoVSOXSEG2EI64_V_M4_M1_MASK,
23061 0 : 9219 => Opcode::PseudoVSOXSEG2EI64_V_M4_M2,
23062 0 : 9220 => Opcode::PseudoVSOXSEG2EI64_V_M4_M2_MASK,
23063 0 : 9221 => Opcode::PseudoVSOXSEG2EI64_V_M4_M4,
23064 0 : 9222 => Opcode::PseudoVSOXSEG2EI64_V_M4_M4_MASK,
23065 0 : 9223 => Opcode::PseudoVSOXSEG2EI64_V_M4_MF2,
23066 0 : 9224 => Opcode::PseudoVSOXSEG2EI64_V_M4_MF2_MASK,
23067 0 : 9225 => Opcode::PseudoVSOXSEG2EI64_V_M8_M1,
23068 0 : 9226 => Opcode::PseudoVSOXSEG2EI64_V_M8_M1_MASK,
23069 0 : 9227 => Opcode::PseudoVSOXSEG2EI64_V_M8_M2,
23070 0 : 9228 => Opcode::PseudoVSOXSEG2EI64_V_M8_M2_MASK,
23071 0 : 9229 => Opcode::PseudoVSOXSEG2EI64_V_M8_M4,
23072 0 : 9230 => Opcode::PseudoVSOXSEG2EI64_V_M8_M4_MASK,
23073 0 : 9231 => Opcode::PseudoVSOXSEG2EI8_V_M1_M1,
23074 0 : 9232 => Opcode::PseudoVSOXSEG2EI8_V_M1_M1_MASK,
23075 0 : 9233 => Opcode::PseudoVSOXSEG2EI8_V_M1_M2,
23076 0 : 9234 => Opcode::PseudoVSOXSEG2EI8_V_M1_M2_MASK,
23077 0 : 9235 => Opcode::PseudoVSOXSEG2EI8_V_M1_M4,
23078 0 : 9236 => Opcode::PseudoVSOXSEG2EI8_V_M1_M4_MASK,
23079 0 : 9237 => Opcode::PseudoVSOXSEG2EI8_V_M2_M2,
23080 0 : 9238 => Opcode::PseudoVSOXSEG2EI8_V_M2_M2_MASK,
23081 0 : 9239 => Opcode::PseudoVSOXSEG2EI8_V_M2_M4,
23082 0 : 9240 => Opcode::PseudoVSOXSEG2EI8_V_M2_M4_MASK,
23083 0 : 9241 => Opcode::PseudoVSOXSEG2EI8_V_M4_M4,
23084 0 : 9242 => Opcode::PseudoVSOXSEG2EI8_V_M4_M4_MASK,
23085 0 : 9243 => Opcode::PseudoVSOXSEG2EI8_V_MF2_M1,
23086 0 : 9244 => Opcode::PseudoVSOXSEG2EI8_V_MF2_M1_MASK,
23087 0 : 9245 => Opcode::PseudoVSOXSEG2EI8_V_MF2_M2,
23088 0 : 9246 => Opcode::PseudoVSOXSEG2EI8_V_MF2_M2_MASK,
23089 0 : 9247 => Opcode::PseudoVSOXSEG2EI8_V_MF2_M4,
23090 0 : 9248 => Opcode::PseudoVSOXSEG2EI8_V_MF2_M4_MASK,
23091 0 : 9249 => Opcode::PseudoVSOXSEG2EI8_V_MF2_MF2,
23092 0 : 9250 => Opcode::PseudoVSOXSEG2EI8_V_MF2_MF2_MASK,
23093 0 : 9251 => Opcode::PseudoVSOXSEG2EI8_V_MF4_M1,
23094 0 : 9252 => Opcode::PseudoVSOXSEG2EI8_V_MF4_M1_MASK,
23095 0 : 9253 => Opcode::PseudoVSOXSEG2EI8_V_MF4_M2,
23096 0 : 9254 => Opcode::PseudoVSOXSEG2EI8_V_MF4_M2_MASK,
23097 0 : 9255 => Opcode::PseudoVSOXSEG2EI8_V_MF4_MF2,
23098 0 : 9256 => Opcode::PseudoVSOXSEG2EI8_V_MF4_MF2_MASK,
23099 0 : 9257 => Opcode::PseudoVSOXSEG2EI8_V_MF4_MF4,
23100 0 : 9258 => Opcode::PseudoVSOXSEG2EI8_V_MF4_MF4_MASK,
23101 0 : 9259 => Opcode::PseudoVSOXSEG2EI8_V_MF8_M1,
23102 0 : 9260 => Opcode::PseudoVSOXSEG2EI8_V_MF8_M1_MASK,
23103 0 : 9261 => Opcode::PseudoVSOXSEG2EI8_V_MF8_MF2,
23104 0 : 9262 => Opcode::PseudoVSOXSEG2EI8_V_MF8_MF2_MASK,
23105 0 : 9263 => Opcode::PseudoVSOXSEG2EI8_V_MF8_MF4,
23106 0 : 9264 => Opcode::PseudoVSOXSEG2EI8_V_MF8_MF4_MASK,
23107 0 : 9265 => Opcode::PseudoVSOXSEG2EI8_V_MF8_MF8,
23108 0 : 9266 => Opcode::PseudoVSOXSEG2EI8_V_MF8_MF8_MASK,
23109 0 : 9267 => Opcode::PseudoVSOXSEG3EI16_V_M1_M1,
23110 0 : 9268 => Opcode::PseudoVSOXSEG3EI16_V_M1_M1_MASK,
23111 0 : 9269 => Opcode::PseudoVSOXSEG3EI16_V_M1_M2,
23112 0 : 9270 => Opcode::PseudoVSOXSEG3EI16_V_M1_M2_MASK,
23113 0 : 9271 => Opcode::PseudoVSOXSEG3EI16_V_M1_MF2,
23114 0 : 9272 => Opcode::PseudoVSOXSEG3EI16_V_M1_MF2_MASK,
23115 0 : 9273 => Opcode::PseudoVSOXSEG3EI16_V_M2_M1,
23116 0 : 9274 => Opcode::PseudoVSOXSEG3EI16_V_M2_M1_MASK,
23117 0 : 9275 => Opcode::PseudoVSOXSEG3EI16_V_M2_M2,
23118 0 : 9276 => Opcode::PseudoVSOXSEG3EI16_V_M2_M2_MASK,
23119 0 : 9277 => Opcode::PseudoVSOXSEG3EI16_V_M4_M2,
23120 0 : 9278 => Opcode::PseudoVSOXSEG3EI16_V_M4_M2_MASK,
23121 0 : 9279 => Opcode::PseudoVSOXSEG3EI16_V_MF2_M1,
23122 0 : 9280 => Opcode::PseudoVSOXSEG3EI16_V_MF2_M1_MASK,
23123 0 : 9281 => Opcode::PseudoVSOXSEG3EI16_V_MF2_M2,
23124 0 : 9282 => Opcode::PseudoVSOXSEG3EI16_V_MF2_M2_MASK,
23125 0 : 9283 => Opcode::PseudoVSOXSEG3EI16_V_MF2_MF2,
23126 0 : 9284 => Opcode::PseudoVSOXSEG3EI16_V_MF2_MF2_MASK,
23127 0 : 9285 => Opcode::PseudoVSOXSEG3EI16_V_MF2_MF4,
23128 0 : 9286 => Opcode::PseudoVSOXSEG3EI16_V_MF2_MF4_MASK,
23129 0 : 9287 => Opcode::PseudoVSOXSEG3EI16_V_MF4_M1,
23130 0 : 9288 => Opcode::PseudoVSOXSEG3EI16_V_MF4_M1_MASK,
23131 0 : 9289 => Opcode::PseudoVSOXSEG3EI16_V_MF4_MF2,
23132 0 : 9290 => Opcode::PseudoVSOXSEG3EI16_V_MF4_MF2_MASK,
23133 0 : 9291 => Opcode::PseudoVSOXSEG3EI16_V_MF4_MF4,
23134 0 : 9292 => Opcode::PseudoVSOXSEG3EI16_V_MF4_MF4_MASK,
23135 0 : 9293 => Opcode::PseudoVSOXSEG3EI16_V_MF4_MF8,
23136 0 : 9294 => Opcode::PseudoVSOXSEG3EI16_V_MF4_MF8_MASK,
23137 0 : 9295 => Opcode::PseudoVSOXSEG3EI32_V_M1_M1,
23138 0 : 9296 => Opcode::PseudoVSOXSEG3EI32_V_M1_M1_MASK,
23139 0 : 9297 => Opcode::PseudoVSOXSEG3EI32_V_M1_M2,
23140 0 : 9298 => Opcode::PseudoVSOXSEG3EI32_V_M1_M2_MASK,
23141 0 : 9299 => Opcode::PseudoVSOXSEG3EI32_V_M1_MF2,
23142 0 : 9300 => Opcode::PseudoVSOXSEG3EI32_V_M1_MF2_MASK,
23143 0 : 9301 => Opcode::PseudoVSOXSEG3EI32_V_M1_MF4,
23144 0 : 9302 => Opcode::PseudoVSOXSEG3EI32_V_M1_MF4_MASK,
23145 0 : 9303 => Opcode::PseudoVSOXSEG3EI32_V_M2_M1,
23146 0 : 9304 => Opcode::PseudoVSOXSEG3EI32_V_M2_M1_MASK,
23147 0 : 9305 => Opcode::PseudoVSOXSEG3EI32_V_M2_M2,
23148 0 : 9306 => Opcode::PseudoVSOXSEG3EI32_V_M2_M2_MASK,
23149 0 : 9307 => Opcode::PseudoVSOXSEG3EI32_V_M2_MF2,
23150 0 : 9308 => Opcode::PseudoVSOXSEG3EI32_V_M2_MF2_MASK,
23151 0 : 9309 => Opcode::PseudoVSOXSEG3EI32_V_M4_M1,
23152 0 : 9310 => Opcode::PseudoVSOXSEG3EI32_V_M4_M1_MASK,
23153 0 : 9311 => Opcode::PseudoVSOXSEG3EI32_V_M4_M2,
23154 0 : 9312 => Opcode::PseudoVSOXSEG3EI32_V_M4_M2_MASK,
23155 0 : 9313 => Opcode::PseudoVSOXSEG3EI32_V_M8_M2,
23156 0 : 9314 => Opcode::PseudoVSOXSEG3EI32_V_M8_M2_MASK,
23157 0 : 9315 => Opcode::PseudoVSOXSEG3EI32_V_MF2_M1,
23158 0 : 9316 => Opcode::PseudoVSOXSEG3EI32_V_MF2_M1_MASK,
23159 0 : 9317 => Opcode::PseudoVSOXSEG3EI32_V_MF2_MF2,
23160 0 : 9318 => Opcode::PseudoVSOXSEG3EI32_V_MF2_MF2_MASK,
23161 0 : 9319 => Opcode::PseudoVSOXSEG3EI32_V_MF2_MF4,
23162 0 : 9320 => Opcode::PseudoVSOXSEG3EI32_V_MF2_MF4_MASK,
23163 0 : 9321 => Opcode::PseudoVSOXSEG3EI32_V_MF2_MF8,
23164 0 : 9322 => Opcode::PseudoVSOXSEG3EI32_V_MF2_MF8_MASK,
23165 0 : 9323 => Opcode::PseudoVSOXSEG3EI64_V_M1_M1,
23166 0 : 9324 => Opcode::PseudoVSOXSEG3EI64_V_M1_M1_MASK,
23167 0 : 9325 => Opcode::PseudoVSOXSEG3EI64_V_M1_MF2,
23168 0 : 9326 => Opcode::PseudoVSOXSEG3EI64_V_M1_MF2_MASK,
23169 0 : 9327 => Opcode::PseudoVSOXSEG3EI64_V_M1_MF4,
23170 0 : 9328 => Opcode::PseudoVSOXSEG3EI64_V_M1_MF4_MASK,
23171 0 : 9329 => Opcode::PseudoVSOXSEG3EI64_V_M1_MF8,
23172 0 : 9330 => Opcode::PseudoVSOXSEG3EI64_V_M1_MF8_MASK,
23173 0 : 9331 => Opcode::PseudoVSOXSEG3EI64_V_M2_M1,
23174 0 : 9332 => Opcode::PseudoVSOXSEG3EI64_V_M2_M1_MASK,
23175 0 : 9333 => Opcode::PseudoVSOXSEG3EI64_V_M2_M2,
23176 0 : 9334 => Opcode::PseudoVSOXSEG3EI64_V_M2_M2_MASK,
23177 0 : 9335 => Opcode::PseudoVSOXSEG3EI64_V_M2_MF2,
23178 0 : 9336 => Opcode::PseudoVSOXSEG3EI64_V_M2_MF2_MASK,
23179 0 : 9337 => Opcode::PseudoVSOXSEG3EI64_V_M2_MF4,
23180 0 : 9338 => Opcode::PseudoVSOXSEG3EI64_V_M2_MF4_MASK,
23181 0 : 9339 => Opcode::PseudoVSOXSEG3EI64_V_M4_M1,
23182 0 : 9340 => Opcode::PseudoVSOXSEG3EI64_V_M4_M1_MASK,
23183 0 : 9341 => Opcode::PseudoVSOXSEG3EI64_V_M4_M2,
23184 0 : 9342 => Opcode::PseudoVSOXSEG3EI64_V_M4_M2_MASK,
23185 0 : 9343 => Opcode::PseudoVSOXSEG3EI64_V_M4_MF2,
23186 0 : 9344 => Opcode::PseudoVSOXSEG3EI64_V_M4_MF2_MASK,
23187 0 : 9345 => Opcode::PseudoVSOXSEG3EI64_V_M8_M1,
23188 0 : 9346 => Opcode::PseudoVSOXSEG3EI64_V_M8_M1_MASK,
23189 0 : 9347 => Opcode::PseudoVSOXSEG3EI64_V_M8_M2,
23190 0 : 9348 => Opcode::PseudoVSOXSEG3EI64_V_M8_M2_MASK,
23191 0 : 9349 => Opcode::PseudoVSOXSEG3EI8_V_M1_M1,
23192 0 : 9350 => Opcode::PseudoVSOXSEG3EI8_V_M1_M1_MASK,
23193 0 : 9351 => Opcode::PseudoVSOXSEG3EI8_V_M1_M2,
23194 0 : 9352 => Opcode::PseudoVSOXSEG3EI8_V_M1_M2_MASK,
23195 0 : 9353 => Opcode::PseudoVSOXSEG3EI8_V_M2_M2,
23196 0 : 9354 => Opcode::PseudoVSOXSEG3EI8_V_M2_M2_MASK,
23197 0 : 9355 => Opcode::PseudoVSOXSEG3EI8_V_MF2_M1,
23198 0 : 9356 => Opcode::PseudoVSOXSEG3EI8_V_MF2_M1_MASK,
23199 0 : 9357 => Opcode::PseudoVSOXSEG3EI8_V_MF2_M2,
23200 0 : 9358 => Opcode::PseudoVSOXSEG3EI8_V_MF2_M2_MASK,
23201 0 : 9359 => Opcode::PseudoVSOXSEG3EI8_V_MF2_MF2,
23202 0 : 9360 => Opcode::PseudoVSOXSEG3EI8_V_MF2_MF2_MASK,
23203 0 : 9361 => Opcode::PseudoVSOXSEG3EI8_V_MF4_M1,
23204 0 : 9362 => Opcode::PseudoVSOXSEG3EI8_V_MF4_M1_MASK,
23205 0 : 9363 => Opcode::PseudoVSOXSEG3EI8_V_MF4_M2,
23206 0 : 9364 => Opcode::PseudoVSOXSEG3EI8_V_MF4_M2_MASK,
23207 0 : 9365 => Opcode::PseudoVSOXSEG3EI8_V_MF4_MF2,
23208 0 : 9366 => Opcode::PseudoVSOXSEG3EI8_V_MF4_MF2_MASK,
23209 0 : 9367 => Opcode::PseudoVSOXSEG3EI8_V_MF4_MF4,
23210 0 : 9368 => Opcode::PseudoVSOXSEG3EI8_V_MF4_MF4_MASK,
23211 0 : 9369 => Opcode::PseudoVSOXSEG3EI8_V_MF8_M1,
23212 0 : 9370 => Opcode::PseudoVSOXSEG3EI8_V_MF8_M1_MASK,
23213 0 : 9371 => Opcode::PseudoVSOXSEG3EI8_V_MF8_MF2,
23214 0 : 9372 => Opcode::PseudoVSOXSEG3EI8_V_MF8_MF2_MASK,
23215 0 : 9373 => Opcode::PseudoVSOXSEG3EI8_V_MF8_MF4,
23216 0 : 9374 => Opcode::PseudoVSOXSEG3EI8_V_MF8_MF4_MASK,
23217 0 : 9375 => Opcode::PseudoVSOXSEG3EI8_V_MF8_MF8,
23218 0 : 9376 => Opcode::PseudoVSOXSEG3EI8_V_MF8_MF8_MASK,
23219 0 : 9377 => Opcode::PseudoVSOXSEG4EI16_V_M1_M1,
23220 0 : 9378 => Opcode::PseudoVSOXSEG4EI16_V_M1_M1_MASK,
23221 0 : 9379 => Opcode::PseudoVSOXSEG4EI16_V_M1_M2,
23222 0 : 9380 => Opcode::PseudoVSOXSEG4EI16_V_M1_M2_MASK,
23223 0 : 9381 => Opcode::PseudoVSOXSEG4EI16_V_M1_MF2,
23224 0 : 9382 => Opcode::PseudoVSOXSEG4EI16_V_M1_MF2_MASK,
23225 0 : 9383 => Opcode::PseudoVSOXSEG4EI16_V_M2_M1,
23226 0 : 9384 => Opcode::PseudoVSOXSEG4EI16_V_M2_M1_MASK,
23227 0 : 9385 => Opcode::PseudoVSOXSEG4EI16_V_M2_M2,
23228 0 : 9386 => Opcode::PseudoVSOXSEG4EI16_V_M2_M2_MASK,
23229 0 : 9387 => Opcode::PseudoVSOXSEG4EI16_V_M4_M2,
23230 0 : 9388 => Opcode::PseudoVSOXSEG4EI16_V_M4_M2_MASK,
23231 0 : 9389 => Opcode::PseudoVSOXSEG4EI16_V_MF2_M1,
23232 0 : 9390 => Opcode::PseudoVSOXSEG4EI16_V_MF2_M1_MASK,
23233 0 : 9391 => Opcode::PseudoVSOXSEG4EI16_V_MF2_M2,
23234 0 : 9392 => Opcode::PseudoVSOXSEG4EI16_V_MF2_M2_MASK,
23235 0 : 9393 => Opcode::PseudoVSOXSEG4EI16_V_MF2_MF2,
23236 0 : 9394 => Opcode::PseudoVSOXSEG4EI16_V_MF2_MF2_MASK,
23237 0 : 9395 => Opcode::PseudoVSOXSEG4EI16_V_MF2_MF4,
23238 0 : 9396 => Opcode::PseudoVSOXSEG4EI16_V_MF2_MF4_MASK,
23239 0 : 9397 => Opcode::PseudoVSOXSEG4EI16_V_MF4_M1,
23240 0 : 9398 => Opcode::PseudoVSOXSEG4EI16_V_MF4_M1_MASK,
23241 0 : 9399 => Opcode::PseudoVSOXSEG4EI16_V_MF4_MF2,
23242 0 : 9400 => Opcode::PseudoVSOXSEG4EI16_V_MF4_MF2_MASK,
23243 0 : 9401 => Opcode::PseudoVSOXSEG4EI16_V_MF4_MF4,
23244 0 : 9402 => Opcode::PseudoVSOXSEG4EI16_V_MF4_MF4_MASK,
23245 0 : 9403 => Opcode::PseudoVSOXSEG4EI16_V_MF4_MF8,
23246 0 : 9404 => Opcode::PseudoVSOXSEG4EI16_V_MF4_MF8_MASK,
23247 0 : 9405 => Opcode::PseudoVSOXSEG4EI32_V_M1_M1,
23248 0 : 9406 => Opcode::PseudoVSOXSEG4EI32_V_M1_M1_MASK,
23249 0 : 9407 => Opcode::PseudoVSOXSEG4EI32_V_M1_M2,
23250 0 : 9408 => Opcode::PseudoVSOXSEG4EI32_V_M1_M2_MASK,
23251 0 : 9409 => Opcode::PseudoVSOXSEG4EI32_V_M1_MF2,
23252 0 : 9410 => Opcode::PseudoVSOXSEG4EI32_V_M1_MF2_MASK,
23253 0 : 9411 => Opcode::PseudoVSOXSEG4EI32_V_M1_MF4,
23254 0 : 9412 => Opcode::PseudoVSOXSEG4EI32_V_M1_MF4_MASK,
23255 0 : 9413 => Opcode::PseudoVSOXSEG4EI32_V_M2_M1,
23256 0 : 9414 => Opcode::PseudoVSOXSEG4EI32_V_M2_M1_MASK,
23257 0 : 9415 => Opcode::PseudoVSOXSEG4EI32_V_M2_M2,
23258 0 : 9416 => Opcode::PseudoVSOXSEG4EI32_V_M2_M2_MASK,
23259 0 : 9417 => Opcode::PseudoVSOXSEG4EI32_V_M2_MF2,
23260 0 : 9418 => Opcode::PseudoVSOXSEG4EI32_V_M2_MF2_MASK,
23261 0 : 9419 => Opcode::PseudoVSOXSEG4EI32_V_M4_M1,
23262 0 : 9420 => Opcode::PseudoVSOXSEG4EI32_V_M4_M1_MASK,
23263 0 : 9421 => Opcode::PseudoVSOXSEG4EI32_V_M4_M2,
23264 0 : 9422 => Opcode::PseudoVSOXSEG4EI32_V_M4_M2_MASK,
23265 0 : 9423 => Opcode::PseudoVSOXSEG4EI32_V_M8_M2,
23266 0 : 9424 => Opcode::PseudoVSOXSEG4EI32_V_M8_M2_MASK,
23267 0 : 9425 => Opcode::PseudoVSOXSEG4EI32_V_MF2_M1,
23268 0 : 9426 => Opcode::PseudoVSOXSEG4EI32_V_MF2_M1_MASK,
23269 0 : 9427 => Opcode::PseudoVSOXSEG4EI32_V_MF2_MF2,
23270 0 : 9428 => Opcode::PseudoVSOXSEG4EI32_V_MF2_MF2_MASK,
23271 0 : 9429 => Opcode::PseudoVSOXSEG4EI32_V_MF2_MF4,
23272 0 : 9430 => Opcode::PseudoVSOXSEG4EI32_V_MF2_MF4_MASK,
23273 0 : 9431 => Opcode::PseudoVSOXSEG4EI32_V_MF2_MF8,
23274 0 : 9432 => Opcode::PseudoVSOXSEG4EI32_V_MF2_MF8_MASK,
23275 0 : 9433 => Opcode::PseudoVSOXSEG4EI64_V_M1_M1,
23276 0 : 9434 => Opcode::PseudoVSOXSEG4EI64_V_M1_M1_MASK,
23277 0 : 9435 => Opcode::PseudoVSOXSEG4EI64_V_M1_MF2,
23278 0 : 9436 => Opcode::PseudoVSOXSEG4EI64_V_M1_MF2_MASK,
23279 0 : 9437 => Opcode::PseudoVSOXSEG4EI64_V_M1_MF4,
23280 0 : 9438 => Opcode::PseudoVSOXSEG4EI64_V_M1_MF4_MASK,
23281 0 : 9439 => Opcode::PseudoVSOXSEG4EI64_V_M1_MF8,
23282 0 : 9440 => Opcode::PseudoVSOXSEG4EI64_V_M1_MF8_MASK,
23283 0 : 9441 => Opcode::PseudoVSOXSEG4EI64_V_M2_M1,
23284 0 : 9442 => Opcode::PseudoVSOXSEG4EI64_V_M2_M1_MASK,
23285 0 : 9443 => Opcode::PseudoVSOXSEG4EI64_V_M2_M2,
23286 0 : 9444 => Opcode::PseudoVSOXSEG4EI64_V_M2_M2_MASK,
23287 0 : 9445 => Opcode::PseudoVSOXSEG4EI64_V_M2_MF2,
23288 0 : 9446 => Opcode::PseudoVSOXSEG4EI64_V_M2_MF2_MASK,
23289 0 : 9447 => Opcode::PseudoVSOXSEG4EI64_V_M2_MF4,
23290 0 : 9448 => Opcode::PseudoVSOXSEG4EI64_V_M2_MF4_MASK,
23291 0 : 9449 => Opcode::PseudoVSOXSEG4EI64_V_M4_M1,
23292 0 : 9450 => Opcode::PseudoVSOXSEG4EI64_V_M4_M1_MASK,
23293 0 : 9451 => Opcode::PseudoVSOXSEG4EI64_V_M4_M2,
23294 0 : 9452 => Opcode::PseudoVSOXSEG4EI64_V_M4_M2_MASK,
23295 0 : 9453 => Opcode::PseudoVSOXSEG4EI64_V_M4_MF2,
23296 0 : 9454 => Opcode::PseudoVSOXSEG4EI64_V_M4_MF2_MASK,
23297 0 : 9455 => Opcode::PseudoVSOXSEG4EI64_V_M8_M1,
23298 0 : 9456 => Opcode::PseudoVSOXSEG4EI64_V_M8_M1_MASK,
23299 0 : 9457 => Opcode::PseudoVSOXSEG4EI64_V_M8_M2,
23300 0 : 9458 => Opcode::PseudoVSOXSEG4EI64_V_M8_M2_MASK,
23301 0 : 9459 => Opcode::PseudoVSOXSEG4EI8_V_M1_M1,
23302 0 : 9460 => Opcode::PseudoVSOXSEG4EI8_V_M1_M1_MASK,
23303 0 : 9461 => Opcode::PseudoVSOXSEG4EI8_V_M1_M2,
23304 0 : 9462 => Opcode::PseudoVSOXSEG4EI8_V_M1_M2_MASK,
23305 0 : 9463 => Opcode::PseudoVSOXSEG4EI8_V_M2_M2,
23306 0 : 9464 => Opcode::PseudoVSOXSEG4EI8_V_M2_M2_MASK,
23307 0 : 9465 => Opcode::PseudoVSOXSEG4EI8_V_MF2_M1,
23308 0 : 9466 => Opcode::PseudoVSOXSEG4EI8_V_MF2_M1_MASK,
23309 0 : 9467 => Opcode::PseudoVSOXSEG4EI8_V_MF2_M2,
23310 0 : 9468 => Opcode::PseudoVSOXSEG4EI8_V_MF2_M2_MASK,
23311 0 : 9469 => Opcode::PseudoVSOXSEG4EI8_V_MF2_MF2,
23312 0 : 9470 => Opcode::PseudoVSOXSEG4EI8_V_MF2_MF2_MASK,
23313 0 : 9471 => Opcode::PseudoVSOXSEG4EI8_V_MF4_M1,
23314 0 : 9472 => Opcode::PseudoVSOXSEG4EI8_V_MF4_M1_MASK,
23315 0 : 9473 => Opcode::PseudoVSOXSEG4EI8_V_MF4_M2,
23316 0 : 9474 => Opcode::PseudoVSOXSEG4EI8_V_MF4_M2_MASK,
23317 0 : 9475 => Opcode::PseudoVSOXSEG4EI8_V_MF4_MF2,
23318 0 : 9476 => Opcode::PseudoVSOXSEG4EI8_V_MF4_MF2_MASK,
23319 0 : 9477 => Opcode::PseudoVSOXSEG4EI8_V_MF4_MF4,
23320 0 : 9478 => Opcode::PseudoVSOXSEG4EI8_V_MF4_MF4_MASK,
23321 0 : 9479 => Opcode::PseudoVSOXSEG4EI8_V_MF8_M1,
23322 0 : 9480 => Opcode::PseudoVSOXSEG4EI8_V_MF8_M1_MASK,
23323 0 : 9481 => Opcode::PseudoVSOXSEG4EI8_V_MF8_MF2,
23324 0 : 9482 => Opcode::PseudoVSOXSEG4EI8_V_MF8_MF2_MASK,
23325 0 : 9483 => Opcode::PseudoVSOXSEG4EI8_V_MF8_MF4,
23326 0 : 9484 => Opcode::PseudoVSOXSEG4EI8_V_MF8_MF4_MASK,
23327 0 : 9485 => Opcode::PseudoVSOXSEG4EI8_V_MF8_MF8,
23328 0 : 9486 => Opcode::PseudoVSOXSEG4EI8_V_MF8_MF8_MASK,
23329 0 : 9487 => Opcode::PseudoVSOXSEG5EI16_V_M1_M1,
23330 0 : 9488 => Opcode::PseudoVSOXSEG5EI16_V_M1_M1_MASK,
23331 0 : 9489 => Opcode::PseudoVSOXSEG5EI16_V_M1_MF2,
23332 0 : 9490 => Opcode::PseudoVSOXSEG5EI16_V_M1_MF2_MASK,
23333 0 : 9491 => Opcode::PseudoVSOXSEG5EI16_V_M2_M1,
23334 0 : 9492 => Opcode::PseudoVSOXSEG5EI16_V_M2_M1_MASK,
23335 0 : 9493 => Opcode::PseudoVSOXSEG5EI16_V_MF2_M1,
23336 0 : 9494 => Opcode::PseudoVSOXSEG5EI16_V_MF2_M1_MASK,
23337 0 : 9495 => Opcode::PseudoVSOXSEG5EI16_V_MF2_MF2,
23338 0 : 9496 => Opcode::PseudoVSOXSEG5EI16_V_MF2_MF2_MASK,
23339 0 : 9497 => Opcode::PseudoVSOXSEG5EI16_V_MF2_MF4,
23340 0 : 9498 => Opcode::PseudoVSOXSEG5EI16_V_MF2_MF4_MASK,
23341 0 : 9499 => Opcode::PseudoVSOXSEG5EI16_V_MF4_M1,
23342 0 : 9500 => Opcode::PseudoVSOXSEG5EI16_V_MF4_M1_MASK,
23343 0 : 9501 => Opcode::PseudoVSOXSEG5EI16_V_MF4_MF2,
23344 0 : 9502 => Opcode::PseudoVSOXSEG5EI16_V_MF4_MF2_MASK,
23345 0 : 9503 => Opcode::PseudoVSOXSEG5EI16_V_MF4_MF4,
23346 0 : 9504 => Opcode::PseudoVSOXSEG5EI16_V_MF4_MF4_MASK,
23347 0 : 9505 => Opcode::PseudoVSOXSEG5EI16_V_MF4_MF8,
23348 0 : 9506 => Opcode::PseudoVSOXSEG5EI16_V_MF4_MF8_MASK,
23349 0 : 9507 => Opcode::PseudoVSOXSEG5EI32_V_M1_M1,
23350 0 : 9508 => Opcode::PseudoVSOXSEG5EI32_V_M1_M1_MASK,
23351 0 : 9509 => Opcode::PseudoVSOXSEG5EI32_V_M1_MF2,
23352 0 : 9510 => Opcode::PseudoVSOXSEG5EI32_V_M1_MF2_MASK,
23353 0 : 9511 => Opcode::PseudoVSOXSEG5EI32_V_M1_MF4,
23354 0 : 9512 => Opcode::PseudoVSOXSEG5EI32_V_M1_MF4_MASK,
23355 0 : 9513 => Opcode::PseudoVSOXSEG5EI32_V_M2_M1,
23356 0 : 9514 => Opcode::PseudoVSOXSEG5EI32_V_M2_M1_MASK,
23357 0 : 9515 => Opcode::PseudoVSOXSEG5EI32_V_M2_MF2,
23358 0 : 9516 => Opcode::PseudoVSOXSEG5EI32_V_M2_MF2_MASK,
23359 0 : 9517 => Opcode::PseudoVSOXSEG5EI32_V_M4_M1,
23360 0 : 9518 => Opcode::PseudoVSOXSEG5EI32_V_M4_M1_MASK,
23361 0 : 9519 => Opcode::PseudoVSOXSEG5EI32_V_MF2_M1,
23362 0 : 9520 => Opcode::PseudoVSOXSEG5EI32_V_MF2_M1_MASK,
23363 0 : 9521 => Opcode::PseudoVSOXSEG5EI32_V_MF2_MF2,
23364 0 : 9522 => Opcode::PseudoVSOXSEG5EI32_V_MF2_MF2_MASK,
23365 0 : 9523 => Opcode::PseudoVSOXSEG5EI32_V_MF2_MF4,
23366 0 : 9524 => Opcode::PseudoVSOXSEG5EI32_V_MF2_MF4_MASK,
23367 0 : 9525 => Opcode::PseudoVSOXSEG5EI32_V_MF2_MF8,
23368 0 : 9526 => Opcode::PseudoVSOXSEG5EI32_V_MF2_MF8_MASK,
23369 0 : 9527 => Opcode::PseudoVSOXSEG5EI64_V_M1_M1,
23370 0 : 9528 => Opcode::PseudoVSOXSEG5EI64_V_M1_M1_MASK,
23371 0 : 9529 => Opcode::PseudoVSOXSEG5EI64_V_M1_MF2,
23372 0 : 9530 => Opcode::PseudoVSOXSEG5EI64_V_M1_MF2_MASK,
23373 0 : 9531 => Opcode::PseudoVSOXSEG5EI64_V_M1_MF4,
23374 0 : 9532 => Opcode::PseudoVSOXSEG5EI64_V_M1_MF4_MASK,
23375 0 : 9533 => Opcode::PseudoVSOXSEG5EI64_V_M1_MF8,
23376 0 : 9534 => Opcode::PseudoVSOXSEG5EI64_V_M1_MF8_MASK,
23377 0 : 9535 => Opcode::PseudoVSOXSEG5EI64_V_M2_M1,
23378 0 : 9536 => Opcode::PseudoVSOXSEG5EI64_V_M2_M1_MASK,
23379 0 : 9537 => Opcode::PseudoVSOXSEG5EI64_V_M2_MF2,
23380 0 : 9538 => Opcode::PseudoVSOXSEG5EI64_V_M2_MF2_MASK,
23381 0 : 9539 => Opcode::PseudoVSOXSEG5EI64_V_M2_MF4,
23382 0 : 9540 => Opcode::PseudoVSOXSEG5EI64_V_M2_MF4_MASK,
23383 0 : 9541 => Opcode::PseudoVSOXSEG5EI64_V_M4_M1,
23384 0 : 9542 => Opcode::PseudoVSOXSEG5EI64_V_M4_M1_MASK,
23385 0 : 9543 => Opcode::PseudoVSOXSEG5EI64_V_M4_MF2,
23386 0 : 9544 => Opcode::PseudoVSOXSEG5EI64_V_M4_MF2_MASK,
23387 0 : 9545 => Opcode::PseudoVSOXSEG5EI64_V_M8_M1,
23388 0 : 9546 => Opcode::PseudoVSOXSEG5EI64_V_M8_M1_MASK,
23389 0 : 9547 => Opcode::PseudoVSOXSEG5EI8_V_M1_M1,
23390 0 : 9548 => Opcode::PseudoVSOXSEG5EI8_V_M1_M1_MASK,
23391 0 : 9549 => Opcode::PseudoVSOXSEG5EI8_V_MF2_M1,
23392 0 : 9550 => Opcode::PseudoVSOXSEG5EI8_V_MF2_M1_MASK,
23393 0 : 9551 => Opcode::PseudoVSOXSEG5EI8_V_MF2_MF2,
23394 0 : 9552 => Opcode::PseudoVSOXSEG5EI8_V_MF2_MF2_MASK,
23395 0 : 9553 => Opcode::PseudoVSOXSEG5EI8_V_MF4_M1,
23396 0 : 9554 => Opcode::PseudoVSOXSEG5EI8_V_MF4_M1_MASK,
23397 0 : 9555 => Opcode::PseudoVSOXSEG5EI8_V_MF4_MF2,
23398 0 : 9556 => Opcode::PseudoVSOXSEG5EI8_V_MF4_MF2_MASK,
23399 0 : 9557 => Opcode::PseudoVSOXSEG5EI8_V_MF4_MF4,
23400 0 : 9558 => Opcode::PseudoVSOXSEG5EI8_V_MF4_MF4_MASK,
23401 0 : 9559 => Opcode::PseudoVSOXSEG5EI8_V_MF8_M1,
23402 0 : 9560 => Opcode::PseudoVSOXSEG5EI8_V_MF8_M1_MASK,
23403 0 : 9561 => Opcode::PseudoVSOXSEG5EI8_V_MF8_MF2,
23404 0 : 9562 => Opcode::PseudoVSOXSEG5EI8_V_MF8_MF2_MASK,
23405 0 : 9563 => Opcode::PseudoVSOXSEG5EI8_V_MF8_MF4,
23406 0 : 9564 => Opcode::PseudoVSOXSEG5EI8_V_MF8_MF4_MASK,
23407 0 : 9565 => Opcode::PseudoVSOXSEG5EI8_V_MF8_MF8,
23408 0 : 9566 => Opcode::PseudoVSOXSEG5EI8_V_MF8_MF8_MASK,
23409 0 : 9567 => Opcode::PseudoVSOXSEG6EI16_V_M1_M1,
23410 0 : 9568 => Opcode::PseudoVSOXSEG6EI16_V_M1_M1_MASK,
23411 0 : 9569 => Opcode::PseudoVSOXSEG6EI16_V_M1_MF2,
23412 0 : 9570 => Opcode::PseudoVSOXSEG6EI16_V_M1_MF2_MASK,
23413 0 : 9571 => Opcode::PseudoVSOXSEG6EI16_V_M2_M1,
23414 0 : 9572 => Opcode::PseudoVSOXSEG6EI16_V_M2_M1_MASK,
23415 0 : 9573 => Opcode::PseudoVSOXSEG6EI16_V_MF2_M1,
23416 0 : 9574 => Opcode::PseudoVSOXSEG6EI16_V_MF2_M1_MASK,
23417 0 : 9575 => Opcode::PseudoVSOXSEG6EI16_V_MF2_MF2,
23418 0 : 9576 => Opcode::PseudoVSOXSEG6EI16_V_MF2_MF2_MASK,
23419 0 : 9577 => Opcode::PseudoVSOXSEG6EI16_V_MF2_MF4,
23420 0 : 9578 => Opcode::PseudoVSOXSEG6EI16_V_MF2_MF4_MASK,
23421 0 : 9579 => Opcode::PseudoVSOXSEG6EI16_V_MF4_M1,
23422 0 : 9580 => Opcode::PseudoVSOXSEG6EI16_V_MF4_M1_MASK,
23423 0 : 9581 => Opcode::PseudoVSOXSEG6EI16_V_MF4_MF2,
23424 0 : 9582 => Opcode::PseudoVSOXSEG6EI16_V_MF4_MF2_MASK,
23425 0 : 9583 => Opcode::PseudoVSOXSEG6EI16_V_MF4_MF4,
23426 0 : 9584 => Opcode::PseudoVSOXSEG6EI16_V_MF4_MF4_MASK,
23427 0 : 9585 => Opcode::PseudoVSOXSEG6EI16_V_MF4_MF8,
23428 0 : 9586 => Opcode::PseudoVSOXSEG6EI16_V_MF4_MF8_MASK,
23429 0 : 9587 => Opcode::PseudoVSOXSEG6EI32_V_M1_M1,
23430 0 : 9588 => Opcode::PseudoVSOXSEG6EI32_V_M1_M1_MASK,
23431 0 : 9589 => Opcode::PseudoVSOXSEG6EI32_V_M1_MF2,
23432 0 : 9590 => Opcode::PseudoVSOXSEG6EI32_V_M1_MF2_MASK,
23433 0 : 9591 => Opcode::PseudoVSOXSEG6EI32_V_M1_MF4,
23434 0 : 9592 => Opcode::PseudoVSOXSEG6EI32_V_M1_MF4_MASK,
23435 0 : 9593 => Opcode::PseudoVSOXSEG6EI32_V_M2_M1,
23436 0 : 9594 => Opcode::PseudoVSOXSEG6EI32_V_M2_M1_MASK,
23437 0 : 9595 => Opcode::PseudoVSOXSEG6EI32_V_M2_MF2,
23438 0 : 9596 => Opcode::PseudoVSOXSEG6EI32_V_M2_MF2_MASK,
23439 0 : 9597 => Opcode::PseudoVSOXSEG6EI32_V_M4_M1,
23440 0 : 9598 => Opcode::PseudoVSOXSEG6EI32_V_M4_M1_MASK,
23441 0 : 9599 => Opcode::PseudoVSOXSEG6EI32_V_MF2_M1,
23442 0 : 9600 => Opcode::PseudoVSOXSEG6EI32_V_MF2_M1_MASK,
23443 0 : 9601 => Opcode::PseudoVSOXSEG6EI32_V_MF2_MF2,
23444 0 : 9602 => Opcode::PseudoVSOXSEG6EI32_V_MF2_MF2_MASK,
23445 0 : 9603 => Opcode::PseudoVSOXSEG6EI32_V_MF2_MF4,
23446 0 : 9604 => Opcode::PseudoVSOXSEG6EI32_V_MF2_MF4_MASK,
23447 0 : 9605 => Opcode::PseudoVSOXSEG6EI32_V_MF2_MF8,
23448 0 : 9606 => Opcode::PseudoVSOXSEG6EI32_V_MF2_MF8_MASK,
23449 0 : 9607 => Opcode::PseudoVSOXSEG6EI64_V_M1_M1,
23450 0 : 9608 => Opcode::PseudoVSOXSEG6EI64_V_M1_M1_MASK,
23451 0 : 9609 => Opcode::PseudoVSOXSEG6EI64_V_M1_MF2,
23452 0 : 9610 => Opcode::PseudoVSOXSEG6EI64_V_M1_MF2_MASK,
23453 0 : 9611 => Opcode::PseudoVSOXSEG6EI64_V_M1_MF4,
23454 0 : 9612 => Opcode::PseudoVSOXSEG6EI64_V_M1_MF4_MASK,
23455 0 : 9613 => Opcode::PseudoVSOXSEG6EI64_V_M1_MF8,
23456 0 : 9614 => Opcode::PseudoVSOXSEG6EI64_V_M1_MF8_MASK,
23457 0 : 9615 => Opcode::PseudoVSOXSEG6EI64_V_M2_M1,
23458 0 : 9616 => Opcode::PseudoVSOXSEG6EI64_V_M2_M1_MASK,
23459 0 : 9617 => Opcode::PseudoVSOXSEG6EI64_V_M2_MF2,
23460 0 : 9618 => Opcode::PseudoVSOXSEG6EI64_V_M2_MF2_MASK,
23461 0 : 9619 => Opcode::PseudoVSOXSEG6EI64_V_M2_MF4,
23462 0 : 9620 => Opcode::PseudoVSOXSEG6EI64_V_M2_MF4_MASK,
23463 0 : 9621 => Opcode::PseudoVSOXSEG6EI64_V_M4_M1,
23464 0 : 9622 => Opcode::PseudoVSOXSEG6EI64_V_M4_M1_MASK,
23465 0 : 9623 => Opcode::PseudoVSOXSEG6EI64_V_M4_MF2,
23466 0 : 9624 => Opcode::PseudoVSOXSEG6EI64_V_M4_MF2_MASK,
23467 0 : 9625 => Opcode::PseudoVSOXSEG6EI64_V_M8_M1,
23468 0 : 9626 => Opcode::PseudoVSOXSEG6EI64_V_M8_M1_MASK,
23469 0 : 9627 => Opcode::PseudoVSOXSEG6EI8_V_M1_M1,
23470 0 : 9628 => Opcode::PseudoVSOXSEG6EI8_V_M1_M1_MASK,
23471 0 : 9629 => Opcode::PseudoVSOXSEG6EI8_V_MF2_M1,
23472 0 : 9630 => Opcode::PseudoVSOXSEG6EI8_V_MF2_M1_MASK,
23473 0 : 9631 => Opcode::PseudoVSOXSEG6EI8_V_MF2_MF2,
23474 0 : 9632 => Opcode::PseudoVSOXSEG6EI8_V_MF2_MF2_MASK,
23475 0 : 9633 => Opcode::PseudoVSOXSEG6EI8_V_MF4_M1,
23476 0 : 9634 => Opcode::PseudoVSOXSEG6EI8_V_MF4_M1_MASK,
23477 0 : 9635 => Opcode::PseudoVSOXSEG6EI8_V_MF4_MF2,
23478 0 : 9636 => Opcode::PseudoVSOXSEG6EI8_V_MF4_MF2_MASK,
23479 0 : 9637 => Opcode::PseudoVSOXSEG6EI8_V_MF4_MF4,
23480 0 : 9638 => Opcode::PseudoVSOXSEG6EI8_V_MF4_MF4_MASK,
23481 0 : 9639 => Opcode::PseudoVSOXSEG6EI8_V_MF8_M1,
23482 0 : 9640 => Opcode::PseudoVSOXSEG6EI8_V_MF8_M1_MASK,
23483 0 : 9641 => Opcode::PseudoVSOXSEG6EI8_V_MF8_MF2,
23484 0 : 9642 => Opcode::PseudoVSOXSEG6EI8_V_MF8_MF2_MASK,
23485 0 : 9643 => Opcode::PseudoVSOXSEG6EI8_V_MF8_MF4,
23486 0 : 9644 => Opcode::PseudoVSOXSEG6EI8_V_MF8_MF4_MASK,
23487 0 : 9645 => Opcode::PseudoVSOXSEG6EI8_V_MF8_MF8,
23488 0 : 9646 => Opcode::PseudoVSOXSEG6EI8_V_MF8_MF8_MASK,
23489 0 : 9647 => Opcode::PseudoVSOXSEG7EI16_V_M1_M1,
23490 0 : 9648 => Opcode::PseudoVSOXSEG7EI16_V_M1_M1_MASK,
23491 0 : 9649 => Opcode::PseudoVSOXSEG7EI16_V_M1_MF2,
23492 0 : 9650 => Opcode::PseudoVSOXSEG7EI16_V_M1_MF2_MASK,
23493 0 : 9651 => Opcode::PseudoVSOXSEG7EI16_V_M2_M1,
23494 0 : 9652 => Opcode::PseudoVSOXSEG7EI16_V_M2_M1_MASK,
23495 0 : 9653 => Opcode::PseudoVSOXSEG7EI16_V_MF2_M1,
23496 0 : 9654 => Opcode::PseudoVSOXSEG7EI16_V_MF2_M1_MASK,
23497 0 : 9655 => Opcode::PseudoVSOXSEG7EI16_V_MF2_MF2,
23498 0 : 9656 => Opcode::PseudoVSOXSEG7EI16_V_MF2_MF2_MASK,
23499 0 : 9657 => Opcode::PseudoVSOXSEG7EI16_V_MF2_MF4,
23500 0 : 9658 => Opcode::PseudoVSOXSEG7EI16_V_MF2_MF4_MASK,
23501 0 : 9659 => Opcode::PseudoVSOXSEG7EI16_V_MF4_M1,
23502 0 : 9660 => Opcode::PseudoVSOXSEG7EI16_V_MF4_M1_MASK,
23503 0 : 9661 => Opcode::PseudoVSOXSEG7EI16_V_MF4_MF2,
23504 0 : 9662 => Opcode::PseudoVSOXSEG7EI16_V_MF4_MF2_MASK,
23505 0 : 9663 => Opcode::PseudoVSOXSEG7EI16_V_MF4_MF4,
23506 0 : 9664 => Opcode::PseudoVSOXSEG7EI16_V_MF4_MF4_MASK,
23507 0 : 9665 => Opcode::PseudoVSOXSEG7EI16_V_MF4_MF8,
23508 0 : 9666 => Opcode::PseudoVSOXSEG7EI16_V_MF4_MF8_MASK,
23509 0 : 9667 => Opcode::PseudoVSOXSEG7EI32_V_M1_M1,
23510 0 : 9668 => Opcode::PseudoVSOXSEG7EI32_V_M1_M1_MASK,
23511 0 : 9669 => Opcode::PseudoVSOXSEG7EI32_V_M1_MF2,
23512 0 : 9670 => Opcode::PseudoVSOXSEG7EI32_V_M1_MF2_MASK,
23513 0 : 9671 => Opcode::PseudoVSOXSEG7EI32_V_M1_MF4,
23514 0 : 9672 => Opcode::PseudoVSOXSEG7EI32_V_M1_MF4_MASK,
23515 0 : 9673 => Opcode::PseudoVSOXSEG7EI32_V_M2_M1,
23516 0 : 9674 => Opcode::PseudoVSOXSEG7EI32_V_M2_M1_MASK,
23517 0 : 9675 => Opcode::PseudoVSOXSEG7EI32_V_M2_MF2,
23518 0 : 9676 => Opcode::PseudoVSOXSEG7EI32_V_M2_MF2_MASK,
23519 0 : 9677 => Opcode::PseudoVSOXSEG7EI32_V_M4_M1,
23520 0 : 9678 => Opcode::PseudoVSOXSEG7EI32_V_M4_M1_MASK,
23521 0 : 9679 => Opcode::PseudoVSOXSEG7EI32_V_MF2_M1,
23522 0 : 9680 => Opcode::PseudoVSOXSEG7EI32_V_MF2_M1_MASK,
23523 0 : 9681 => Opcode::PseudoVSOXSEG7EI32_V_MF2_MF2,
23524 0 : 9682 => Opcode::PseudoVSOXSEG7EI32_V_MF2_MF2_MASK,
23525 0 : 9683 => Opcode::PseudoVSOXSEG7EI32_V_MF2_MF4,
23526 0 : 9684 => Opcode::PseudoVSOXSEG7EI32_V_MF2_MF4_MASK,
23527 0 : 9685 => Opcode::PseudoVSOXSEG7EI32_V_MF2_MF8,
23528 0 : 9686 => Opcode::PseudoVSOXSEG7EI32_V_MF2_MF8_MASK,
23529 0 : 9687 => Opcode::PseudoVSOXSEG7EI64_V_M1_M1,
23530 0 : 9688 => Opcode::PseudoVSOXSEG7EI64_V_M1_M1_MASK,
23531 0 : 9689 => Opcode::PseudoVSOXSEG7EI64_V_M1_MF2,
23532 0 : 9690 => Opcode::PseudoVSOXSEG7EI64_V_M1_MF2_MASK,
23533 0 : 9691 => Opcode::PseudoVSOXSEG7EI64_V_M1_MF4,
23534 0 : 9692 => Opcode::PseudoVSOXSEG7EI64_V_M1_MF4_MASK,
23535 0 : 9693 => Opcode::PseudoVSOXSEG7EI64_V_M1_MF8,
23536 0 : 9694 => Opcode::PseudoVSOXSEG7EI64_V_M1_MF8_MASK,
23537 0 : 9695 => Opcode::PseudoVSOXSEG7EI64_V_M2_M1,
23538 0 : 9696 => Opcode::PseudoVSOXSEG7EI64_V_M2_M1_MASK,
23539 0 : 9697 => Opcode::PseudoVSOXSEG7EI64_V_M2_MF2,
23540 0 : 9698 => Opcode::PseudoVSOXSEG7EI64_V_M2_MF2_MASK,
23541 0 : 9699 => Opcode::PseudoVSOXSEG7EI64_V_M2_MF4,
23542 0 : 9700 => Opcode::PseudoVSOXSEG7EI64_V_M2_MF4_MASK,
23543 0 : 9701 => Opcode::PseudoVSOXSEG7EI64_V_M4_M1,
23544 0 : 9702 => Opcode::PseudoVSOXSEG7EI64_V_M4_M1_MASK,
23545 0 : 9703 => Opcode::PseudoVSOXSEG7EI64_V_M4_MF2,
23546 0 : 9704 => Opcode::PseudoVSOXSEG7EI64_V_M4_MF2_MASK,
23547 0 : 9705 => Opcode::PseudoVSOXSEG7EI64_V_M8_M1,
23548 0 : 9706 => Opcode::PseudoVSOXSEG7EI64_V_M8_M1_MASK,
23549 0 : 9707 => Opcode::PseudoVSOXSEG7EI8_V_M1_M1,
23550 0 : 9708 => Opcode::PseudoVSOXSEG7EI8_V_M1_M1_MASK,
23551 0 : 9709 => Opcode::PseudoVSOXSEG7EI8_V_MF2_M1,
23552 0 : 9710 => Opcode::PseudoVSOXSEG7EI8_V_MF2_M1_MASK,
23553 0 : 9711 => Opcode::PseudoVSOXSEG7EI8_V_MF2_MF2,
23554 0 : 9712 => Opcode::PseudoVSOXSEG7EI8_V_MF2_MF2_MASK,
23555 0 : 9713 => Opcode::PseudoVSOXSEG7EI8_V_MF4_M1,
23556 0 : 9714 => Opcode::PseudoVSOXSEG7EI8_V_MF4_M1_MASK,
23557 0 : 9715 => Opcode::PseudoVSOXSEG7EI8_V_MF4_MF2,
23558 0 : 9716 => Opcode::PseudoVSOXSEG7EI8_V_MF4_MF2_MASK,
23559 0 : 9717 => Opcode::PseudoVSOXSEG7EI8_V_MF4_MF4,
23560 0 : 9718 => Opcode::PseudoVSOXSEG7EI8_V_MF4_MF4_MASK,
23561 0 : 9719 => Opcode::PseudoVSOXSEG7EI8_V_MF8_M1,
23562 0 : 9720 => Opcode::PseudoVSOXSEG7EI8_V_MF8_M1_MASK,
23563 0 : 9721 => Opcode::PseudoVSOXSEG7EI8_V_MF8_MF2,
23564 0 : 9722 => Opcode::PseudoVSOXSEG7EI8_V_MF8_MF2_MASK,
23565 0 : 9723 => Opcode::PseudoVSOXSEG7EI8_V_MF8_MF4,
23566 0 : 9724 => Opcode::PseudoVSOXSEG7EI8_V_MF8_MF4_MASK,
23567 0 : 9725 => Opcode::PseudoVSOXSEG7EI8_V_MF8_MF8,
23568 0 : 9726 => Opcode::PseudoVSOXSEG7EI8_V_MF8_MF8_MASK,
23569 0 : 9727 => Opcode::PseudoVSOXSEG8EI16_V_M1_M1,
23570 0 : 9728 => Opcode::PseudoVSOXSEG8EI16_V_M1_M1_MASK,
23571 0 : 9729 => Opcode::PseudoVSOXSEG8EI16_V_M1_MF2,
23572 0 : 9730 => Opcode::PseudoVSOXSEG8EI16_V_M1_MF2_MASK,
23573 0 : 9731 => Opcode::PseudoVSOXSEG8EI16_V_M2_M1,
23574 0 : 9732 => Opcode::PseudoVSOXSEG8EI16_V_M2_M1_MASK,
23575 0 : 9733 => Opcode::PseudoVSOXSEG8EI16_V_MF2_M1,
23576 0 : 9734 => Opcode::PseudoVSOXSEG8EI16_V_MF2_M1_MASK,
23577 0 : 9735 => Opcode::PseudoVSOXSEG8EI16_V_MF2_MF2,
23578 0 : 9736 => Opcode::PseudoVSOXSEG8EI16_V_MF2_MF2_MASK,
23579 0 : 9737 => Opcode::PseudoVSOXSEG8EI16_V_MF2_MF4,
23580 0 : 9738 => Opcode::PseudoVSOXSEG8EI16_V_MF2_MF4_MASK,
23581 0 : 9739 => Opcode::PseudoVSOXSEG8EI16_V_MF4_M1,
23582 0 : 9740 => Opcode::PseudoVSOXSEG8EI16_V_MF4_M1_MASK,
23583 0 : 9741 => Opcode::PseudoVSOXSEG8EI16_V_MF4_MF2,
23584 0 : 9742 => Opcode::PseudoVSOXSEG8EI16_V_MF4_MF2_MASK,
23585 0 : 9743 => Opcode::PseudoVSOXSEG8EI16_V_MF4_MF4,
23586 0 : 9744 => Opcode::PseudoVSOXSEG8EI16_V_MF4_MF4_MASK,
23587 0 : 9745 => Opcode::PseudoVSOXSEG8EI16_V_MF4_MF8,
23588 0 : 9746 => Opcode::PseudoVSOXSEG8EI16_V_MF4_MF8_MASK,
23589 0 : 9747 => Opcode::PseudoVSOXSEG8EI32_V_M1_M1,
23590 0 : 9748 => Opcode::PseudoVSOXSEG8EI32_V_M1_M1_MASK,
23591 0 : 9749 => Opcode::PseudoVSOXSEG8EI32_V_M1_MF2,
23592 0 : 9750 => Opcode::PseudoVSOXSEG8EI32_V_M1_MF2_MASK,
23593 0 : 9751 => Opcode::PseudoVSOXSEG8EI32_V_M1_MF4,
23594 0 : 9752 => Opcode::PseudoVSOXSEG8EI32_V_M1_MF4_MASK,
23595 0 : 9753 => Opcode::PseudoVSOXSEG8EI32_V_M2_M1,
23596 0 : 9754 => Opcode::PseudoVSOXSEG8EI32_V_M2_M1_MASK,
23597 0 : 9755 => Opcode::PseudoVSOXSEG8EI32_V_M2_MF2,
23598 0 : 9756 => Opcode::PseudoVSOXSEG8EI32_V_M2_MF2_MASK,
23599 0 : 9757 => Opcode::PseudoVSOXSEG8EI32_V_M4_M1,
23600 0 : 9758 => Opcode::PseudoVSOXSEG8EI32_V_M4_M1_MASK,
23601 0 : 9759 => Opcode::PseudoVSOXSEG8EI32_V_MF2_M1,
23602 0 : 9760 => Opcode::PseudoVSOXSEG8EI32_V_MF2_M1_MASK,
23603 0 : 9761 => Opcode::PseudoVSOXSEG8EI32_V_MF2_MF2,
23604 0 : 9762 => Opcode::PseudoVSOXSEG8EI32_V_MF2_MF2_MASK,
23605 0 : 9763 => Opcode::PseudoVSOXSEG8EI32_V_MF2_MF4,
23606 0 : 9764 => Opcode::PseudoVSOXSEG8EI32_V_MF2_MF4_MASK,
23607 0 : 9765 => Opcode::PseudoVSOXSEG8EI32_V_MF2_MF8,
23608 0 : 9766 => Opcode::PseudoVSOXSEG8EI32_V_MF2_MF8_MASK,
23609 0 : 9767 => Opcode::PseudoVSOXSEG8EI64_V_M1_M1,
23610 0 : 9768 => Opcode::PseudoVSOXSEG8EI64_V_M1_M1_MASK,
23611 0 : 9769 => Opcode::PseudoVSOXSEG8EI64_V_M1_MF2,
23612 0 : 9770 => Opcode::PseudoVSOXSEG8EI64_V_M1_MF2_MASK,
23613 0 : 9771 => Opcode::PseudoVSOXSEG8EI64_V_M1_MF4,
23614 0 : 9772 => Opcode::PseudoVSOXSEG8EI64_V_M1_MF4_MASK,
23615 0 : 9773 => Opcode::PseudoVSOXSEG8EI64_V_M1_MF8,
23616 0 : 9774 => Opcode::PseudoVSOXSEG8EI64_V_M1_MF8_MASK,
23617 0 : 9775 => Opcode::PseudoVSOXSEG8EI64_V_M2_M1,
23618 0 : 9776 => Opcode::PseudoVSOXSEG8EI64_V_M2_M1_MASK,
23619 0 : 9777 => Opcode::PseudoVSOXSEG8EI64_V_M2_MF2,
23620 0 : 9778 => Opcode::PseudoVSOXSEG8EI64_V_M2_MF2_MASK,
23621 0 : 9779 => Opcode::PseudoVSOXSEG8EI64_V_M2_MF4,
23622 0 : 9780 => Opcode::PseudoVSOXSEG8EI64_V_M2_MF4_MASK,
23623 0 : 9781 => Opcode::PseudoVSOXSEG8EI64_V_M4_M1,
23624 0 : 9782 => Opcode::PseudoVSOXSEG8EI64_V_M4_M1_MASK,
23625 0 : 9783 => Opcode::PseudoVSOXSEG8EI64_V_M4_MF2,
23626 0 : 9784 => Opcode::PseudoVSOXSEG8EI64_V_M4_MF2_MASK,
23627 0 : 9785 => Opcode::PseudoVSOXSEG8EI64_V_M8_M1,
23628 0 : 9786 => Opcode::PseudoVSOXSEG8EI64_V_M8_M1_MASK,
23629 0 : 9787 => Opcode::PseudoVSOXSEG8EI8_V_M1_M1,
23630 0 : 9788 => Opcode::PseudoVSOXSEG8EI8_V_M1_M1_MASK,
23631 0 : 9789 => Opcode::PseudoVSOXSEG8EI8_V_MF2_M1,
23632 0 : 9790 => Opcode::PseudoVSOXSEG8EI8_V_MF2_M1_MASK,
23633 0 : 9791 => Opcode::PseudoVSOXSEG8EI8_V_MF2_MF2,
23634 0 : 9792 => Opcode::PseudoVSOXSEG8EI8_V_MF2_MF2_MASK,
23635 0 : 9793 => Opcode::PseudoVSOXSEG8EI8_V_MF4_M1,
23636 0 : 9794 => Opcode::PseudoVSOXSEG8EI8_V_MF4_M1_MASK,
23637 0 : 9795 => Opcode::PseudoVSOXSEG8EI8_V_MF4_MF2,
23638 0 : 9796 => Opcode::PseudoVSOXSEG8EI8_V_MF4_MF2_MASK,
23639 0 : 9797 => Opcode::PseudoVSOXSEG8EI8_V_MF4_MF4,
23640 0 : 9798 => Opcode::PseudoVSOXSEG8EI8_V_MF4_MF4_MASK,
23641 0 : 9799 => Opcode::PseudoVSOXSEG8EI8_V_MF8_M1,
23642 0 : 9800 => Opcode::PseudoVSOXSEG8EI8_V_MF8_M1_MASK,
23643 0 : 9801 => Opcode::PseudoVSOXSEG8EI8_V_MF8_MF2,
23644 0 : 9802 => Opcode::PseudoVSOXSEG8EI8_V_MF8_MF2_MASK,
23645 0 : 9803 => Opcode::PseudoVSOXSEG8EI8_V_MF8_MF4,
23646 0 : 9804 => Opcode::PseudoVSOXSEG8EI8_V_MF8_MF4_MASK,
23647 0 : 9805 => Opcode::PseudoVSOXSEG8EI8_V_MF8_MF8,
23648 0 : 9806 => Opcode::PseudoVSOXSEG8EI8_V_MF8_MF8_MASK,
23649 0 : 9807 => Opcode::PseudoVSPILL2_M1,
23650 0 : 9808 => Opcode::PseudoVSPILL2_M2,
23651 0 : 9809 => Opcode::PseudoVSPILL2_M4,
23652 0 : 9810 => Opcode::PseudoVSPILL2_MF2,
23653 0 : 9811 => Opcode::PseudoVSPILL2_MF4,
23654 0 : 9812 => Opcode::PseudoVSPILL2_MF8,
23655 0 : 9813 => Opcode::PseudoVSPILL3_M1,
23656 0 : 9814 => Opcode::PseudoVSPILL3_M2,
23657 0 : 9815 => Opcode::PseudoVSPILL3_MF2,
23658 0 : 9816 => Opcode::PseudoVSPILL3_MF4,
23659 0 : 9817 => Opcode::PseudoVSPILL3_MF8,
23660 0 : 9818 => Opcode::PseudoVSPILL4_M1,
23661 0 : 9819 => Opcode::PseudoVSPILL4_M2,
23662 0 : 9820 => Opcode::PseudoVSPILL4_MF2,
23663 0 : 9821 => Opcode::PseudoVSPILL4_MF4,
23664 0 : 9822 => Opcode::PseudoVSPILL4_MF8,
23665 0 : 9823 => Opcode::PseudoVSPILL5_M1,
23666 0 : 9824 => Opcode::PseudoVSPILL5_MF2,
23667 0 : 9825 => Opcode::PseudoVSPILL5_MF4,
23668 0 : 9826 => Opcode::PseudoVSPILL5_MF8,
23669 0 : 9827 => Opcode::PseudoVSPILL6_M1,
23670 0 : 9828 => Opcode::PseudoVSPILL6_MF2,
23671 0 : 9829 => Opcode::PseudoVSPILL6_MF4,
23672 0 : 9830 => Opcode::PseudoVSPILL6_MF8,
23673 0 : 9831 => Opcode::PseudoVSPILL7_M1,
23674 0 : 9832 => Opcode::PseudoVSPILL7_MF2,
23675 0 : 9833 => Opcode::PseudoVSPILL7_MF4,
23676 0 : 9834 => Opcode::PseudoVSPILL7_MF8,
23677 0 : 9835 => Opcode::PseudoVSPILL8_M1,
23678 0 : 9836 => Opcode::PseudoVSPILL8_MF2,
23679 0 : 9837 => Opcode::PseudoVSPILL8_MF4,
23680 0 : 9838 => Opcode::PseudoVSPILL8_MF8,
23681 0 : 9839 => Opcode::PseudoVSRA_VI_M1,
23682 0 : 9840 => Opcode::PseudoVSRA_VI_M1_MASK,
23683 0 : 9841 => Opcode::PseudoVSRA_VI_M2,
23684 0 : 9842 => Opcode::PseudoVSRA_VI_M2_MASK,
23685 0 : 9843 => Opcode::PseudoVSRA_VI_M4,
23686 0 : 9844 => Opcode::PseudoVSRA_VI_M4_MASK,
23687 0 : 9845 => Opcode::PseudoVSRA_VI_M8,
23688 0 : 9846 => Opcode::PseudoVSRA_VI_M8_MASK,
23689 0 : 9847 => Opcode::PseudoVSRA_VI_MF2,
23690 0 : 9848 => Opcode::PseudoVSRA_VI_MF2_MASK,
23691 0 : 9849 => Opcode::PseudoVSRA_VI_MF4,
23692 0 : 9850 => Opcode::PseudoVSRA_VI_MF4_MASK,
23693 0 : 9851 => Opcode::PseudoVSRA_VI_MF8,
23694 0 : 9852 => Opcode::PseudoVSRA_VI_MF8_MASK,
23695 0 : 9853 => Opcode::PseudoVSRA_VV_M1,
23696 0 : 9854 => Opcode::PseudoVSRA_VV_M1_MASK,
23697 0 : 9855 => Opcode::PseudoVSRA_VV_M2,
23698 0 : 9856 => Opcode::PseudoVSRA_VV_M2_MASK,
23699 0 : 9857 => Opcode::PseudoVSRA_VV_M4,
23700 0 : 9858 => Opcode::PseudoVSRA_VV_M4_MASK,
23701 0 : 9859 => Opcode::PseudoVSRA_VV_M8,
23702 0 : 9860 => Opcode::PseudoVSRA_VV_M8_MASK,
23703 0 : 9861 => Opcode::PseudoVSRA_VV_MF2,
23704 0 : 9862 => Opcode::PseudoVSRA_VV_MF2_MASK,
23705 0 : 9863 => Opcode::PseudoVSRA_VV_MF4,
23706 0 : 9864 => Opcode::PseudoVSRA_VV_MF4_MASK,
23707 0 : 9865 => Opcode::PseudoVSRA_VV_MF8,
23708 0 : 9866 => Opcode::PseudoVSRA_VV_MF8_MASK,
23709 0 : 9867 => Opcode::PseudoVSRA_VX_M1,
23710 0 : 9868 => Opcode::PseudoVSRA_VX_M1_MASK,
23711 0 : 9869 => Opcode::PseudoVSRA_VX_M2,
23712 0 : 9870 => Opcode::PseudoVSRA_VX_M2_MASK,
23713 0 : 9871 => Opcode::PseudoVSRA_VX_M4,
23714 0 : 9872 => Opcode::PseudoVSRA_VX_M4_MASK,
23715 0 : 9873 => Opcode::PseudoVSRA_VX_M8,
23716 0 : 9874 => Opcode::PseudoVSRA_VX_M8_MASK,
23717 0 : 9875 => Opcode::PseudoVSRA_VX_MF2,
23718 0 : 9876 => Opcode::PseudoVSRA_VX_MF2_MASK,
23719 0 : 9877 => Opcode::PseudoVSRA_VX_MF4,
23720 0 : 9878 => Opcode::PseudoVSRA_VX_MF4_MASK,
23721 0 : 9879 => Opcode::PseudoVSRA_VX_MF8,
23722 0 : 9880 => Opcode::PseudoVSRA_VX_MF8_MASK,
23723 0 : 9881 => Opcode::PseudoVSRL_VI_M1,
23724 0 : 9882 => Opcode::PseudoVSRL_VI_M1_MASK,
23725 0 : 9883 => Opcode::PseudoVSRL_VI_M2,
23726 0 : 9884 => Opcode::PseudoVSRL_VI_M2_MASK,
23727 0 : 9885 => Opcode::PseudoVSRL_VI_M4,
23728 0 : 9886 => Opcode::PseudoVSRL_VI_M4_MASK,
23729 0 : 9887 => Opcode::PseudoVSRL_VI_M8,
23730 0 : 9888 => Opcode::PseudoVSRL_VI_M8_MASK,
23731 0 : 9889 => Opcode::PseudoVSRL_VI_MF2,
23732 0 : 9890 => Opcode::PseudoVSRL_VI_MF2_MASK,
23733 0 : 9891 => Opcode::PseudoVSRL_VI_MF4,
23734 0 : 9892 => Opcode::PseudoVSRL_VI_MF4_MASK,
23735 0 : 9893 => Opcode::PseudoVSRL_VI_MF8,
23736 0 : 9894 => Opcode::PseudoVSRL_VI_MF8_MASK,
23737 0 : 9895 => Opcode::PseudoVSRL_VV_M1,
23738 0 : 9896 => Opcode::PseudoVSRL_VV_M1_MASK,
23739 0 : 9897 => Opcode::PseudoVSRL_VV_M2,
23740 0 : 9898 => Opcode::PseudoVSRL_VV_M2_MASK,
23741 0 : 9899 => Opcode::PseudoVSRL_VV_M4,
23742 0 : 9900 => Opcode::PseudoVSRL_VV_M4_MASK,
23743 0 : 9901 => Opcode::PseudoVSRL_VV_M8,
23744 0 : 9902 => Opcode::PseudoVSRL_VV_M8_MASK,
23745 0 : 9903 => Opcode::PseudoVSRL_VV_MF2,
23746 0 : 9904 => Opcode::PseudoVSRL_VV_MF2_MASK,
23747 0 : 9905 => Opcode::PseudoVSRL_VV_MF4,
23748 0 : 9906 => Opcode::PseudoVSRL_VV_MF4_MASK,
23749 0 : 9907 => Opcode::PseudoVSRL_VV_MF8,
23750 0 : 9908 => Opcode::PseudoVSRL_VV_MF8_MASK,
23751 0 : 9909 => Opcode::PseudoVSRL_VX_M1,
23752 0 : 9910 => Opcode::PseudoVSRL_VX_M1_MASK,
23753 0 : 9911 => Opcode::PseudoVSRL_VX_M2,
23754 0 : 9912 => Opcode::PseudoVSRL_VX_M2_MASK,
23755 0 : 9913 => Opcode::PseudoVSRL_VX_M4,
23756 0 : 9914 => Opcode::PseudoVSRL_VX_M4_MASK,
23757 0 : 9915 => Opcode::PseudoVSRL_VX_M8,
23758 0 : 9916 => Opcode::PseudoVSRL_VX_M8_MASK,
23759 0 : 9917 => Opcode::PseudoVSRL_VX_MF2,
23760 0 : 9918 => Opcode::PseudoVSRL_VX_MF2_MASK,
23761 0 : 9919 => Opcode::PseudoVSRL_VX_MF4,
23762 0 : 9920 => Opcode::PseudoVSRL_VX_MF4_MASK,
23763 0 : 9921 => Opcode::PseudoVSRL_VX_MF8,
23764 0 : 9922 => Opcode::PseudoVSRL_VX_MF8_MASK,
23765 0 : 9923 => Opcode::PseudoVSSE16_V_M1,
23766 0 : 9924 => Opcode::PseudoVSSE16_V_M1_MASK,
23767 0 : 9925 => Opcode::PseudoVSSE16_V_M2,
23768 0 : 9926 => Opcode::PseudoVSSE16_V_M2_MASK,
23769 0 : 9927 => Opcode::PseudoVSSE16_V_M4,
23770 0 : 9928 => Opcode::PseudoVSSE16_V_M4_MASK,
23771 0 : 9929 => Opcode::PseudoVSSE16_V_M8,
23772 0 : 9930 => Opcode::PseudoVSSE16_V_M8_MASK,
23773 0 : 9931 => Opcode::PseudoVSSE16_V_MF2,
23774 0 : 9932 => Opcode::PseudoVSSE16_V_MF2_MASK,
23775 0 : 9933 => Opcode::PseudoVSSE16_V_MF4,
23776 0 : 9934 => Opcode::PseudoVSSE16_V_MF4_MASK,
23777 0 : 9935 => Opcode::PseudoVSSE32_V_M1,
23778 0 : 9936 => Opcode::PseudoVSSE32_V_M1_MASK,
23779 0 : 9937 => Opcode::PseudoVSSE32_V_M2,
23780 0 : 9938 => Opcode::PseudoVSSE32_V_M2_MASK,
23781 0 : 9939 => Opcode::PseudoVSSE32_V_M4,
23782 0 : 9940 => Opcode::PseudoVSSE32_V_M4_MASK,
23783 0 : 9941 => Opcode::PseudoVSSE32_V_M8,
23784 0 : 9942 => Opcode::PseudoVSSE32_V_M8_MASK,
23785 0 : 9943 => Opcode::PseudoVSSE32_V_MF2,
23786 0 : 9944 => Opcode::PseudoVSSE32_V_MF2_MASK,
23787 0 : 9945 => Opcode::PseudoVSSE64_V_M1,
23788 0 : 9946 => Opcode::PseudoVSSE64_V_M1_MASK,
23789 0 : 9947 => Opcode::PseudoVSSE64_V_M2,
23790 0 : 9948 => Opcode::PseudoVSSE64_V_M2_MASK,
23791 0 : 9949 => Opcode::PseudoVSSE64_V_M4,
23792 0 : 9950 => Opcode::PseudoVSSE64_V_M4_MASK,
23793 0 : 9951 => Opcode::PseudoVSSE64_V_M8,
23794 0 : 9952 => Opcode::PseudoVSSE64_V_M8_MASK,
23795 0 : 9953 => Opcode::PseudoVSSE8_V_M1,
23796 0 : 9954 => Opcode::PseudoVSSE8_V_M1_MASK,
23797 0 : 9955 => Opcode::PseudoVSSE8_V_M2,
23798 0 : 9956 => Opcode::PseudoVSSE8_V_M2_MASK,
23799 0 : 9957 => Opcode::PseudoVSSE8_V_M4,
23800 0 : 9958 => Opcode::PseudoVSSE8_V_M4_MASK,
23801 0 : 9959 => Opcode::PseudoVSSE8_V_M8,
23802 0 : 9960 => Opcode::PseudoVSSE8_V_M8_MASK,
23803 0 : 9961 => Opcode::PseudoVSSE8_V_MF2,
23804 0 : 9962 => Opcode::PseudoVSSE8_V_MF2_MASK,
23805 0 : 9963 => Opcode::PseudoVSSE8_V_MF4,
23806 0 : 9964 => Opcode::PseudoVSSE8_V_MF4_MASK,
23807 0 : 9965 => Opcode::PseudoVSSE8_V_MF8,
23808 0 : 9966 => Opcode::PseudoVSSE8_V_MF8_MASK,
23809 0 : 9967 => Opcode::PseudoVSSEG2E16_V_M1,
23810 0 : 9968 => Opcode::PseudoVSSEG2E16_V_M1_MASK,
23811 0 : 9969 => Opcode::PseudoVSSEG2E16_V_M2,
23812 0 : 9970 => Opcode::PseudoVSSEG2E16_V_M2_MASK,
23813 0 : 9971 => Opcode::PseudoVSSEG2E16_V_M4,
23814 0 : 9972 => Opcode::PseudoVSSEG2E16_V_M4_MASK,
23815 0 : 9973 => Opcode::PseudoVSSEG2E16_V_MF2,
23816 0 : 9974 => Opcode::PseudoVSSEG2E16_V_MF2_MASK,
23817 0 : 9975 => Opcode::PseudoVSSEG2E16_V_MF4,
23818 0 : 9976 => Opcode::PseudoVSSEG2E16_V_MF4_MASK,
23819 0 : 9977 => Opcode::PseudoVSSEG2E32_V_M1,
23820 0 : 9978 => Opcode::PseudoVSSEG2E32_V_M1_MASK,
23821 0 : 9979 => Opcode::PseudoVSSEG2E32_V_M2,
23822 0 : 9980 => Opcode::PseudoVSSEG2E32_V_M2_MASK,
23823 0 : 9981 => Opcode::PseudoVSSEG2E32_V_M4,
23824 0 : 9982 => Opcode::PseudoVSSEG2E32_V_M4_MASK,
23825 0 : 9983 => Opcode::PseudoVSSEG2E32_V_MF2,
23826 0 : 9984 => Opcode::PseudoVSSEG2E32_V_MF2_MASK,
23827 0 : 9985 => Opcode::PseudoVSSEG2E64_V_M1,
23828 0 : 9986 => Opcode::PseudoVSSEG2E64_V_M1_MASK,
23829 0 : 9987 => Opcode::PseudoVSSEG2E64_V_M2,
23830 0 : 9988 => Opcode::PseudoVSSEG2E64_V_M2_MASK,
23831 0 : 9989 => Opcode::PseudoVSSEG2E64_V_M4,
23832 0 : 9990 => Opcode::PseudoVSSEG2E64_V_M4_MASK,
23833 0 : 9991 => Opcode::PseudoVSSEG2E8_V_M1,
23834 0 : 9992 => Opcode::PseudoVSSEG2E8_V_M1_MASK,
23835 0 : 9993 => Opcode::PseudoVSSEG2E8_V_M2,
23836 0 : 9994 => Opcode::PseudoVSSEG2E8_V_M2_MASK,
23837 0 : 9995 => Opcode::PseudoVSSEG2E8_V_M4,
23838 0 : 9996 => Opcode::PseudoVSSEG2E8_V_M4_MASK,
23839 0 : 9997 => Opcode::PseudoVSSEG2E8_V_MF2,
23840 0 : 9998 => Opcode::PseudoVSSEG2E8_V_MF2_MASK,
23841 0 : 9999 => Opcode::PseudoVSSEG2E8_V_MF4,
23842 0 : 10000 => Opcode::PseudoVSSEG2E8_V_MF4_MASK,
23843 0 : 10001 => Opcode::PseudoVSSEG2E8_V_MF8,
23844 0 : 10002 => Opcode::PseudoVSSEG2E8_V_MF8_MASK,
23845 0 : 10003 => Opcode::PseudoVSSEG3E16_V_M1,
23846 0 : 10004 => Opcode::PseudoVSSEG3E16_V_M1_MASK,
23847 0 : 10005 => Opcode::PseudoVSSEG3E16_V_M2,
23848 0 : 10006 => Opcode::PseudoVSSEG3E16_V_M2_MASK,
23849 0 : 10007 => Opcode::PseudoVSSEG3E16_V_MF2,
23850 0 : 10008 => Opcode::PseudoVSSEG3E16_V_MF2_MASK,
23851 0 : 10009 => Opcode::PseudoVSSEG3E16_V_MF4,
23852 0 : 10010 => Opcode::PseudoVSSEG3E16_V_MF4_MASK,
23853 0 : 10011 => Opcode::PseudoVSSEG3E32_V_M1,
23854 0 : 10012 => Opcode::PseudoVSSEG3E32_V_M1_MASK,
23855 0 : 10013 => Opcode::PseudoVSSEG3E32_V_M2,
23856 0 : 10014 => Opcode::PseudoVSSEG3E32_V_M2_MASK,
23857 0 : 10015 => Opcode::PseudoVSSEG3E32_V_MF2,
23858 0 : 10016 => Opcode::PseudoVSSEG3E32_V_MF2_MASK,
23859 0 : 10017 => Opcode::PseudoVSSEG3E64_V_M1,
23860 0 : 10018 => Opcode::PseudoVSSEG3E64_V_M1_MASK,
23861 0 : 10019 => Opcode::PseudoVSSEG3E64_V_M2,
23862 0 : 10020 => Opcode::PseudoVSSEG3E64_V_M2_MASK,
23863 0 : 10021 => Opcode::PseudoVSSEG3E8_V_M1,
23864 0 : 10022 => Opcode::PseudoVSSEG3E8_V_M1_MASK,
23865 0 : 10023 => Opcode::PseudoVSSEG3E8_V_M2,
23866 0 : 10024 => Opcode::PseudoVSSEG3E8_V_M2_MASK,
23867 0 : 10025 => Opcode::PseudoVSSEG3E8_V_MF2,
23868 0 : 10026 => Opcode::PseudoVSSEG3E8_V_MF2_MASK,
23869 0 : 10027 => Opcode::PseudoVSSEG3E8_V_MF4,
23870 0 : 10028 => Opcode::PseudoVSSEG3E8_V_MF4_MASK,
23871 0 : 10029 => Opcode::PseudoVSSEG3E8_V_MF8,
23872 0 : 10030 => Opcode::PseudoVSSEG3E8_V_MF8_MASK,
23873 0 : 10031 => Opcode::PseudoVSSEG4E16_V_M1,
23874 0 : 10032 => Opcode::PseudoVSSEG4E16_V_M1_MASK,
23875 0 : 10033 => Opcode::PseudoVSSEG4E16_V_M2,
23876 0 : 10034 => Opcode::PseudoVSSEG4E16_V_M2_MASK,
23877 0 : 10035 => Opcode::PseudoVSSEG4E16_V_MF2,
23878 0 : 10036 => Opcode::PseudoVSSEG4E16_V_MF2_MASK,
23879 0 : 10037 => Opcode::PseudoVSSEG4E16_V_MF4,
23880 0 : 10038 => Opcode::PseudoVSSEG4E16_V_MF4_MASK,
23881 0 : 10039 => Opcode::PseudoVSSEG4E32_V_M1,
23882 0 : 10040 => Opcode::PseudoVSSEG4E32_V_M1_MASK,
23883 0 : 10041 => Opcode::PseudoVSSEG4E32_V_M2,
23884 0 : 10042 => Opcode::PseudoVSSEG4E32_V_M2_MASK,
23885 0 : 10043 => Opcode::PseudoVSSEG4E32_V_MF2,
23886 0 : 10044 => Opcode::PseudoVSSEG4E32_V_MF2_MASK,
23887 0 : 10045 => Opcode::PseudoVSSEG4E64_V_M1,
23888 0 : 10046 => Opcode::PseudoVSSEG4E64_V_M1_MASK,
23889 0 : 10047 => Opcode::PseudoVSSEG4E64_V_M2,
23890 0 : 10048 => Opcode::PseudoVSSEG4E64_V_M2_MASK,
23891 0 : 10049 => Opcode::PseudoVSSEG4E8_V_M1,
23892 0 : 10050 => Opcode::PseudoVSSEG4E8_V_M1_MASK,
23893 0 : 10051 => Opcode::PseudoVSSEG4E8_V_M2,
23894 0 : 10052 => Opcode::PseudoVSSEG4E8_V_M2_MASK,
23895 0 : 10053 => Opcode::PseudoVSSEG4E8_V_MF2,
23896 0 : 10054 => Opcode::PseudoVSSEG4E8_V_MF2_MASK,
23897 0 : 10055 => Opcode::PseudoVSSEG4E8_V_MF4,
23898 0 : 10056 => Opcode::PseudoVSSEG4E8_V_MF4_MASK,
23899 0 : 10057 => Opcode::PseudoVSSEG4E8_V_MF8,
23900 0 : 10058 => Opcode::PseudoVSSEG4E8_V_MF8_MASK,
23901 0 : 10059 => Opcode::PseudoVSSEG5E16_V_M1,
23902 0 : 10060 => Opcode::PseudoVSSEG5E16_V_M1_MASK,
23903 0 : 10061 => Opcode::PseudoVSSEG5E16_V_MF2,
23904 0 : 10062 => Opcode::PseudoVSSEG5E16_V_MF2_MASK,
23905 0 : 10063 => Opcode::PseudoVSSEG5E16_V_MF4,
23906 0 : 10064 => Opcode::PseudoVSSEG5E16_V_MF4_MASK,
23907 0 : 10065 => Opcode::PseudoVSSEG5E32_V_M1,
23908 0 : 10066 => Opcode::PseudoVSSEG5E32_V_M1_MASK,
23909 0 : 10067 => Opcode::PseudoVSSEG5E32_V_MF2,
23910 0 : 10068 => Opcode::PseudoVSSEG5E32_V_MF2_MASK,
23911 0 : 10069 => Opcode::PseudoVSSEG5E64_V_M1,
23912 0 : 10070 => Opcode::PseudoVSSEG5E64_V_M1_MASK,
23913 0 : 10071 => Opcode::PseudoVSSEG5E8_V_M1,
23914 0 : 10072 => Opcode::PseudoVSSEG5E8_V_M1_MASK,
23915 0 : 10073 => Opcode::PseudoVSSEG5E8_V_MF2,
23916 0 : 10074 => Opcode::PseudoVSSEG5E8_V_MF2_MASK,
23917 0 : 10075 => Opcode::PseudoVSSEG5E8_V_MF4,
23918 0 : 10076 => Opcode::PseudoVSSEG5E8_V_MF4_MASK,
23919 0 : 10077 => Opcode::PseudoVSSEG5E8_V_MF8,
23920 0 : 10078 => Opcode::PseudoVSSEG5E8_V_MF8_MASK,
23921 0 : 10079 => Opcode::PseudoVSSEG6E16_V_M1,
23922 0 : 10080 => Opcode::PseudoVSSEG6E16_V_M1_MASK,
23923 0 : 10081 => Opcode::PseudoVSSEG6E16_V_MF2,
23924 0 : 10082 => Opcode::PseudoVSSEG6E16_V_MF2_MASK,
23925 0 : 10083 => Opcode::PseudoVSSEG6E16_V_MF4,
23926 0 : 10084 => Opcode::PseudoVSSEG6E16_V_MF4_MASK,
23927 0 : 10085 => Opcode::PseudoVSSEG6E32_V_M1,
23928 0 : 10086 => Opcode::PseudoVSSEG6E32_V_M1_MASK,
23929 0 : 10087 => Opcode::PseudoVSSEG6E32_V_MF2,
23930 0 : 10088 => Opcode::PseudoVSSEG6E32_V_MF2_MASK,
23931 0 : 10089 => Opcode::PseudoVSSEG6E64_V_M1,
23932 0 : 10090 => Opcode::PseudoVSSEG6E64_V_M1_MASK,
23933 0 : 10091 => Opcode::PseudoVSSEG6E8_V_M1,
23934 0 : 10092 => Opcode::PseudoVSSEG6E8_V_M1_MASK,
23935 0 : 10093 => Opcode::PseudoVSSEG6E8_V_MF2,
23936 0 : 10094 => Opcode::PseudoVSSEG6E8_V_MF2_MASK,
23937 0 : 10095 => Opcode::PseudoVSSEG6E8_V_MF4,
23938 0 : 10096 => Opcode::PseudoVSSEG6E8_V_MF4_MASK,
23939 0 : 10097 => Opcode::PseudoVSSEG6E8_V_MF8,
23940 0 : 10098 => Opcode::PseudoVSSEG6E8_V_MF8_MASK,
23941 0 : 10099 => Opcode::PseudoVSSEG7E16_V_M1,
23942 0 : 10100 => Opcode::PseudoVSSEG7E16_V_M1_MASK,
23943 0 : 10101 => Opcode::PseudoVSSEG7E16_V_MF2,
23944 0 : 10102 => Opcode::PseudoVSSEG7E16_V_MF2_MASK,
23945 0 : 10103 => Opcode::PseudoVSSEG7E16_V_MF4,
23946 0 : 10104 => Opcode::PseudoVSSEG7E16_V_MF4_MASK,
23947 0 : 10105 => Opcode::PseudoVSSEG7E32_V_M1,
23948 0 : 10106 => Opcode::PseudoVSSEG7E32_V_M1_MASK,
23949 0 : 10107 => Opcode::PseudoVSSEG7E32_V_MF2,
23950 0 : 10108 => Opcode::PseudoVSSEG7E32_V_MF2_MASK,
23951 0 : 10109 => Opcode::PseudoVSSEG7E64_V_M1,
23952 0 : 10110 => Opcode::PseudoVSSEG7E64_V_M1_MASK,
23953 0 : 10111 => Opcode::PseudoVSSEG7E8_V_M1,
23954 0 : 10112 => Opcode::PseudoVSSEG7E8_V_M1_MASK,
23955 0 : 10113 => Opcode::PseudoVSSEG7E8_V_MF2,
23956 0 : 10114 => Opcode::PseudoVSSEG7E8_V_MF2_MASK,
23957 0 : 10115 => Opcode::PseudoVSSEG7E8_V_MF4,
23958 0 : 10116 => Opcode::PseudoVSSEG7E8_V_MF4_MASK,
23959 0 : 10117 => Opcode::PseudoVSSEG7E8_V_MF8,
23960 0 : 10118 => Opcode::PseudoVSSEG7E8_V_MF8_MASK,
23961 0 : 10119 => Opcode::PseudoVSSEG8E16_V_M1,
23962 0 : 10120 => Opcode::PseudoVSSEG8E16_V_M1_MASK,
23963 0 : 10121 => Opcode::PseudoVSSEG8E16_V_MF2,
23964 0 : 10122 => Opcode::PseudoVSSEG8E16_V_MF2_MASK,
23965 0 : 10123 => Opcode::PseudoVSSEG8E16_V_MF4,
23966 0 : 10124 => Opcode::PseudoVSSEG8E16_V_MF4_MASK,
23967 0 : 10125 => Opcode::PseudoVSSEG8E32_V_M1,
23968 0 : 10126 => Opcode::PseudoVSSEG8E32_V_M1_MASK,
23969 0 : 10127 => Opcode::PseudoVSSEG8E32_V_MF2,
23970 0 : 10128 => Opcode::PseudoVSSEG8E32_V_MF2_MASK,
23971 0 : 10129 => Opcode::PseudoVSSEG8E64_V_M1,
23972 0 : 10130 => Opcode::PseudoVSSEG8E64_V_M1_MASK,
23973 0 : 10131 => Opcode::PseudoVSSEG8E8_V_M1,
23974 0 : 10132 => Opcode::PseudoVSSEG8E8_V_M1_MASK,
23975 0 : 10133 => Opcode::PseudoVSSEG8E8_V_MF2,
23976 0 : 10134 => Opcode::PseudoVSSEG8E8_V_MF2_MASK,
23977 0 : 10135 => Opcode::PseudoVSSEG8E8_V_MF4,
23978 0 : 10136 => Opcode::PseudoVSSEG8E8_V_MF4_MASK,
23979 0 : 10137 => Opcode::PseudoVSSEG8E8_V_MF8,
23980 0 : 10138 => Opcode::PseudoVSSEG8E8_V_MF8_MASK,
23981 0 : 10139 => Opcode::PseudoVSSRA_VI_M1,
23982 0 : 10140 => Opcode::PseudoVSSRA_VI_M1_MASK,
23983 0 : 10141 => Opcode::PseudoVSSRA_VI_M2,
23984 0 : 10142 => Opcode::PseudoVSSRA_VI_M2_MASK,
23985 0 : 10143 => Opcode::PseudoVSSRA_VI_M4,
23986 0 : 10144 => Opcode::PseudoVSSRA_VI_M4_MASK,
23987 0 : 10145 => Opcode::PseudoVSSRA_VI_M8,
23988 0 : 10146 => Opcode::PseudoVSSRA_VI_M8_MASK,
23989 0 : 10147 => Opcode::PseudoVSSRA_VI_MF2,
23990 0 : 10148 => Opcode::PseudoVSSRA_VI_MF2_MASK,
23991 0 : 10149 => Opcode::PseudoVSSRA_VI_MF4,
23992 0 : 10150 => Opcode::PseudoVSSRA_VI_MF4_MASK,
23993 0 : 10151 => Opcode::PseudoVSSRA_VI_MF8,
23994 0 : 10152 => Opcode::PseudoVSSRA_VI_MF8_MASK,
23995 0 : 10153 => Opcode::PseudoVSSRA_VV_M1,
23996 0 : 10154 => Opcode::PseudoVSSRA_VV_M1_MASK,
23997 0 : 10155 => Opcode::PseudoVSSRA_VV_M2,
23998 0 : 10156 => Opcode::PseudoVSSRA_VV_M2_MASK,
23999 0 : 10157 => Opcode::PseudoVSSRA_VV_M4,
24000 0 : 10158 => Opcode::PseudoVSSRA_VV_M4_MASK,
24001 0 : 10159 => Opcode::PseudoVSSRA_VV_M8,
24002 0 : 10160 => Opcode::PseudoVSSRA_VV_M8_MASK,
24003 0 : 10161 => Opcode::PseudoVSSRA_VV_MF2,
24004 0 : 10162 => Opcode::PseudoVSSRA_VV_MF2_MASK,
24005 0 : 10163 => Opcode::PseudoVSSRA_VV_MF4,
24006 0 : 10164 => Opcode::PseudoVSSRA_VV_MF4_MASK,
24007 0 : 10165 => Opcode::PseudoVSSRA_VV_MF8,
24008 0 : 10166 => Opcode::PseudoVSSRA_VV_MF8_MASK,
24009 0 : 10167 => Opcode::PseudoVSSRA_VX_M1,
24010 0 : 10168 => Opcode::PseudoVSSRA_VX_M1_MASK,
24011 0 : 10169 => Opcode::PseudoVSSRA_VX_M2,
24012 0 : 10170 => Opcode::PseudoVSSRA_VX_M2_MASK,
24013 0 : 10171 => Opcode::PseudoVSSRA_VX_M4,
24014 0 : 10172 => Opcode::PseudoVSSRA_VX_M4_MASK,
24015 0 : 10173 => Opcode::PseudoVSSRA_VX_M8,
24016 0 : 10174 => Opcode::PseudoVSSRA_VX_M8_MASK,
24017 0 : 10175 => Opcode::PseudoVSSRA_VX_MF2,
24018 0 : 10176 => Opcode::PseudoVSSRA_VX_MF2_MASK,
24019 0 : 10177 => Opcode::PseudoVSSRA_VX_MF4,
24020 0 : 10178 => Opcode::PseudoVSSRA_VX_MF4_MASK,
24021 0 : 10179 => Opcode::PseudoVSSRA_VX_MF8,
24022 0 : 10180 => Opcode::PseudoVSSRA_VX_MF8_MASK,
24023 0 : 10181 => Opcode::PseudoVSSRL_VI_M1,
24024 0 : 10182 => Opcode::PseudoVSSRL_VI_M1_MASK,
24025 0 : 10183 => Opcode::PseudoVSSRL_VI_M2,
24026 0 : 10184 => Opcode::PseudoVSSRL_VI_M2_MASK,
24027 0 : 10185 => Opcode::PseudoVSSRL_VI_M4,
24028 0 : 10186 => Opcode::PseudoVSSRL_VI_M4_MASK,
24029 0 : 10187 => Opcode::PseudoVSSRL_VI_M8,
24030 0 : 10188 => Opcode::PseudoVSSRL_VI_M8_MASK,
24031 0 : 10189 => Opcode::PseudoVSSRL_VI_MF2,
24032 0 : 10190 => Opcode::PseudoVSSRL_VI_MF2_MASK,
24033 0 : 10191 => Opcode::PseudoVSSRL_VI_MF4,
24034 0 : 10192 => Opcode::PseudoVSSRL_VI_MF4_MASK,
24035 0 : 10193 => Opcode::PseudoVSSRL_VI_MF8,
24036 0 : 10194 => Opcode::PseudoVSSRL_VI_MF8_MASK,
24037 0 : 10195 => Opcode::PseudoVSSRL_VV_M1,
24038 0 : 10196 => Opcode::PseudoVSSRL_VV_M1_MASK,
24039 0 : 10197 => Opcode::PseudoVSSRL_VV_M2,
24040 0 : 10198 => Opcode::PseudoVSSRL_VV_M2_MASK,
24041 0 : 10199 => Opcode::PseudoVSSRL_VV_M4,
24042 0 : 10200 => Opcode::PseudoVSSRL_VV_M4_MASK,
24043 0 : 10201 => Opcode::PseudoVSSRL_VV_M8,
24044 0 : 10202 => Opcode::PseudoVSSRL_VV_M8_MASK,
24045 0 : 10203 => Opcode::PseudoVSSRL_VV_MF2,
24046 0 : 10204 => Opcode::PseudoVSSRL_VV_MF2_MASK,
24047 0 : 10205 => Opcode::PseudoVSSRL_VV_MF4,
24048 0 : 10206 => Opcode::PseudoVSSRL_VV_MF4_MASK,
24049 0 : 10207 => Opcode::PseudoVSSRL_VV_MF8,
24050 0 : 10208 => Opcode::PseudoVSSRL_VV_MF8_MASK,
24051 0 : 10209 => Opcode::PseudoVSSRL_VX_M1,
24052 0 : 10210 => Opcode::PseudoVSSRL_VX_M1_MASK,
24053 0 : 10211 => Opcode::PseudoVSSRL_VX_M2,
24054 0 : 10212 => Opcode::PseudoVSSRL_VX_M2_MASK,
24055 0 : 10213 => Opcode::PseudoVSSRL_VX_M4,
24056 0 : 10214 => Opcode::PseudoVSSRL_VX_M4_MASK,
24057 0 : 10215 => Opcode::PseudoVSSRL_VX_M8,
24058 0 : 10216 => Opcode::PseudoVSSRL_VX_M8_MASK,
24059 0 : 10217 => Opcode::PseudoVSSRL_VX_MF2,
24060 0 : 10218 => Opcode::PseudoVSSRL_VX_MF2_MASK,
24061 0 : 10219 => Opcode::PseudoVSSRL_VX_MF4,
24062 0 : 10220 => Opcode::PseudoVSSRL_VX_MF4_MASK,
24063 0 : 10221 => Opcode::PseudoVSSRL_VX_MF8,
24064 0 : 10222 => Opcode::PseudoVSSRL_VX_MF8_MASK,
24065 0 : 10223 => Opcode::PseudoVSSSEG2E16_V_M1,
24066 0 : 10224 => Opcode::PseudoVSSSEG2E16_V_M1_MASK,
24067 0 : 10225 => Opcode::PseudoVSSSEG2E16_V_M2,
24068 0 : 10226 => Opcode::PseudoVSSSEG2E16_V_M2_MASK,
24069 0 : 10227 => Opcode::PseudoVSSSEG2E16_V_M4,
24070 0 : 10228 => Opcode::PseudoVSSSEG2E16_V_M4_MASK,
24071 0 : 10229 => Opcode::PseudoVSSSEG2E16_V_MF2,
24072 0 : 10230 => Opcode::PseudoVSSSEG2E16_V_MF2_MASK,
24073 0 : 10231 => Opcode::PseudoVSSSEG2E16_V_MF4,
24074 0 : 10232 => Opcode::PseudoVSSSEG2E16_V_MF4_MASK,
24075 0 : 10233 => Opcode::PseudoVSSSEG2E32_V_M1,
24076 0 : 10234 => Opcode::PseudoVSSSEG2E32_V_M1_MASK,
24077 0 : 10235 => Opcode::PseudoVSSSEG2E32_V_M2,
24078 0 : 10236 => Opcode::PseudoVSSSEG2E32_V_M2_MASK,
24079 0 : 10237 => Opcode::PseudoVSSSEG2E32_V_M4,
24080 0 : 10238 => Opcode::PseudoVSSSEG2E32_V_M4_MASK,
24081 0 : 10239 => Opcode::PseudoVSSSEG2E32_V_MF2,
24082 0 : 10240 => Opcode::PseudoVSSSEG2E32_V_MF2_MASK,
24083 0 : 10241 => Opcode::PseudoVSSSEG2E64_V_M1,
24084 0 : 10242 => Opcode::PseudoVSSSEG2E64_V_M1_MASK,
24085 0 : 10243 => Opcode::PseudoVSSSEG2E64_V_M2,
24086 0 : 10244 => Opcode::PseudoVSSSEG2E64_V_M2_MASK,
24087 0 : 10245 => Opcode::PseudoVSSSEG2E64_V_M4,
24088 0 : 10246 => Opcode::PseudoVSSSEG2E64_V_M4_MASK,
24089 0 : 10247 => Opcode::PseudoVSSSEG2E8_V_M1,
24090 0 : 10248 => Opcode::PseudoVSSSEG2E8_V_M1_MASK,
24091 0 : 10249 => Opcode::PseudoVSSSEG2E8_V_M2,
24092 0 : 10250 => Opcode::PseudoVSSSEG2E8_V_M2_MASK,
24093 0 : 10251 => Opcode::PseudoVSSSEG2E8_V_M4,
24094 0 : 10252 => Opcode::PseudoVSSSEG2E8_V_M4_MASK,
24095 0 : 10253 => Opcode::PseudoVSSSEG2E8_V_MF2,
24096 0 : 10254 => Opcode::PseudoVSSSEG2E8_V_MF2_MASK,
24097 0 : 10255 => Opcode::PseudoVSSSEG2E8_V_MF4,
24098 0 : 10256 => Opcode::PseudoVSSSEG2E8_V_MF4_MASK,
24099 0 : 10257 => Opcode::PseudoVSSSEG2E8_V_MF8,
24100 0 : 10258 => Opcode::PseudoVSSSEG2E8_V_MF8_MASK,
24101 0 : 10259 => Opcode::PseudoVSSSEG3E16_V_M1,
24102 0 : 10260 => Opcode::PseudoVSSSEG3E16_V_M1_MASK,
24103 0 : 10261 => Opcode::PseudoVSSSEG3E16_V_M2,
24104 0 : 10262 => Opcode::PseudoVSSSEG3E16_V_M2_MASK,
24105 0 : 10263 => Opcode::PseudoVSSSEG3E16_V_MF2,
24106 0 : 10264 => Opcode::PseudoVSSSEG3E16_V_MF2_MASK,
24107 0 : 10265 => Opcode::PseudoVSSSEG3E16_V_MF4,
24108 0 : 10266 => Opcode::PseudoVSSSEG3E16_V_MF4_MASK,
24109 0 : 10267 => Opcode::PseudoVSSSEG3E32_V_M1,
24110 0 : 10268 => Opcode::PseudoVSSSEG3E32_V_M1_MASK,
24111 0 : 10269 => Opcode::PseudoVSSSEG3E32_V_M2,
24112 0 : 10270 => Opcode::PseudoVSSSEG3E32_V_M2_MASK,
24113 0 : 10271 => Opcode::PseudoVSSSEG3E32_V_MF2,
24114 0 : 10272 => Opcode::PseudoVSSSEG3E32_V_MF2_MASK,
24115 0 : 10273 => Opcode::PseudoVSSSEG3E64_V_M1,
24116 0 : 10274 => Opcode::PseudoVSSSEG3E64_V_M1_MASK,
24117 0 : 10275 => Opcode::PseudoVSSSEG3E64_V_M2,
24118 0 : 10276 => Opcode::PseudoVSSSEG3E64_V_M2_MASK,
24119 0 : 10277 => Opcode::PseudoVSSSEG3E8_V_M1,
24120 0 : 10278 => Opcode::PseudoVSSSEG3E8_V_M1_MASK,
24121 0 : 10279 => Opcode::PseudoVSSSEG3E8_V_M2,
24122 0 : 10280 => Opcode::PseudoVSSSEG3E8_V_M2_MASK,
24123 0 : 10281 => Opcode::PseudoVSSSEG3E8_V_MF2,
24124 0 : 10282 => Opcode::PseudoVSSSEG3E8_V_MF2_MASK,
24125 0 : 10283 => Opcode::PseudoVSSSEG3E8_V_MF4,
24126 0 : 10284 => Opcode::PseudoVSSSEG3E8_V_MF4_MASK,
24127 0 : 10285 => Opcode::PseudoVSSSEG3E8_V_MF8,
24128 0 : 10286 => Opcode::PseudoVSSSEG3E8_V_MF8_MASK,
24129 0 : 10287 => Opcode::PseudoVSSSEG4E16_V_M1,
24130 0 : 10288 => Opcode::PseudoVSSSEG4E16_V_M1_MASK,
24131 0 : 10289 => Opcode::PseudoVSSSEG4E16_V_M2,
24132 0 : 10290 => Opcode::PseudoVSSSEG4E16_V_M2_MASK,
24133 0 : 10291 => Opcode::PseudoVSSSEG4E16_V_MF2,
24134 0 : 10292 => Opcode::PseudoVSSSEG4E16_V_MF2_MASK,
24135 0 : 10293 => Opcode::PseudoVSSSEG4E16_V_MF4,
24136 0 : 10294 => Opcode::PseudoVSSSEG4E16_V_MF4_MASK,
24137 0 : 10295 => Opcode::PseudoVSSSEG4E32_V_M1,
24138 0 : 10296 => Opcode::PseudoVSSSEG4E32_V_M1_MASK,
24139 0 : 10297 => Opcode::PseudoVSSSEG4E32_V_M2,
24140 0 : 10298 => Opcode::PseudoVSSSEG4E32_V_M2_MASK,
24141 0 : 10299 => Opcode::PseudoVSSSEG4E32_V_MF2,
24142 0 : 10300 => Opcode::PseudoVSSSEG4E32_V_MF2_MASK,
24143 0 : 10301 => Opcode::PseudoVSSSEG4E64_V_M1,
24144 0 : 10302 => Opcode::PseudoVSSSEG4E64_V_M1_MASK,
24145 0 : 10303 => Opcode::PseudoVSSSEG4E64_V_M2,
24146 0 : 10304 => Opcode::PseudoVSSSEG4E64_V_M2_MASK,
24147 0 : 10305 => Opcode::PseudoVSSSEG4E8_V_M1,
24148 0 : 10306 => Opcode::PseudoVSSSEG4E8_V_M1_MASK,
24149 0 : 10307 => Opcode::PseudoVSSSEG4E8_V_M2,
24150 0 : 10308 => Opcode::PseudoVSSSEG4E8_V_M2_MASK,
24151 0 : 10309 => Opcode::PseudoVSSSEG4E8_V_MF2,
24152 0 : 10310 => Opcode::PseudoVSSSEG4E8_V_MF2_MASK,
24153 0 : 10311 => Opcode::PseudoVSSSEG4E8_V_MF4,
24154 0 : 10312 => Opcode::PseudoVSSSEG4E8_V_MF4_MASK,
24155 0 : 10313 => Opcode::PseudoVSSSEG4E8_V_MF8,
24156 0 : 10314 => Opcode::PseudoVSSSEG4E8_V_MF8_MASK,
24157 0 : 10315 => Opcode::PseudoVSSSEG5E16_V_M1,
24158 0 : 10316 => Opcode::PseudoVSSSEG5E16_V_M1_MASK,
24159 0 : 10317 => Opcode::PseudoVSSSEG5E16_V_MF2,
24160 0 : 10318 => Opcode::PseudoVSSSEG5E16_V_MF2_MASK,
24161 0 : 10319 => Opcode::PseudoVSSSEG5E16_V_MF4,
24162 0 : 10320 => Opcode::PseudoVSSSEG5E16_V_MF4_MASK,
24163 0 : 10321 => Opcode::PseudoVSSSEG5E32_V_M1,
24164 0 : 10322 => Opcode::PseudoVSSSEG5E32_V_M1_MASK,
24165 0 : 10323 => Opcode::PseudoVSSSEG5E32_V_MF2,
24166 0 : 10324 => Opcode::PseudoVSSSEG5E32_V_MF2_MASK,
24167 0 : 10325 => Opcode::PseudoVSSSEG5E64_V_M1,
24168 0 : 10326 => Opcode::PseudoVSSSEG5E64_V_M1_MASK,
24169 0 : 10327 => Opcode::PseudoVSSSEG5E8_V_M1,
24170 0 : 10328 => Opcode::PseudoVSSSEG5E8_V_M1_MASK,
24171 0 : 10329 => Opcode::PseudoVSSSEG5E8_V_MF2,
24172 0 : 10330 => Opcode::PseudoVSSSEG5E8_V_MF2_MASK,
24173 0 : 10331 => Opcode::PseudoVSSSEG5E8_V_MF4,
24174 0 : 10332 => Opcode::PseudoVSSSEG5E8_V_MF4_MASK,
24175 0 : 10333 => Opcode::PseudoVSSSEG5E8_V_MF8,
24176 0 : 10334 => Opcode::PseudoVSSSEG5E8_V_MF8_MASK,
24177 0 : 10335 => Opcode::PseudoVSSSEG6E16_V_M1,
24178 0 : 10336 => Opcode::PseudoVSSSEG6E16_V_M1_MASK,
24179 0 : 10337 => Opcode::PseudoVSSSEG6E16_V_MF2,
24180 0 : 10338 => Opcode::PseudoVSSSEG6E16_V_MF2_MASK,
24181 0 : 10339 => Opcode::PseudoVSSSEG6E16_V_MF4,
24182 0 : 10340 => Opcode::PseudoVSSSEG6E16_V_MF4_MASK,
24183 0 : 10341 => Opcode::PseudoVSSSEG6E32_V_M1,
24184 0 : 10342 => Opcode::PseudoVSSSEG6E32_V_M1_MASK,
24185 0 : 10343 => Opcode::PseudoVSSSEG6E32_V_MF2,
24186 0 : 10344 => Opcode::PseudoVSSSEG6E32_V_MF2_MASK,
24187 0 : 10345 => Opcode::PseudoVSSSEG6E64_V_M1,
24188 0 : 10346 => Opcode::PseudoVSSSEG6E64_V_M1_MASK,
24189 0 : 10347 => Opcode::PseudoVSSSEG6E8_V_M1,
24190 0 : 10348 => Opcode::PseudoVSSSEG6E8_V_M1_MASK,
24191 0 : 10349 => Opcode::PseudoVSSSEG6E8_V_MF2,
24192 0 : 10350 => Opcode::PseudoVSSSEG6E8_V_MF2_MASK,
24193 0 : 10351 => Opcode::PseudoVSSSEG6E8_V_MF4,
24194 0 : 10352 => Opcode::PseudoVSSSEG6E8_V_MF4_MASK,
24195 0 : 10353 => Opcode::PseudoVSSSEG6E8_V_MF8,
24196 0 : 10354 => Opcode::PseudoVSSSEG6E8_V_MF8_MASK,
24197 0 : 10355 => Opcode::PseudoVSSSEG7E16_V_M1,
24198 0 : 10356 => Opcode::PseudoVSSSEG7E16_V_M1_MASK,
24199 0 : 10357 => Opcode::PseudoVSSSEG7E16_V_MF2,
24200 0 : 10358 => Opcode::PseudoVSSSEG7E16_V_MF2_MASK,
24201 0 : 10359 => Opcode::PseudoVSSSEG7E16_V_MF4,
24202 0 : 10360 => Opcode::PseudoVSSSEG7E16_V_MF4_MASK,
24203 0 : 10361 => Opcode::PseudoVSSSEG7E32_V_M1,
24204 0 : 10362 => Opcode::PseudoVSSSEG7E32_V_M1_MASK,
24205 0 : 10363 => Opcode::PseudoVSSSEG7E32_V_MF2,
24206 0 : 10364 => Opcode::PseudoVSSSEG7E32_V_MF2_MASK,
24207 0 : 10365 => Opcode::PseudoVSSSEG7E64_V_M1,
24208 0 : 10366 => Opcode::PseudoVSSSEG7E64_V_M1_MASK,
24209 0 : 10367 => Opcode::PseudoVSSSEG7E8_V_M1,
24210 0 : 10368 => Opcode::PseudoVSSSEG7E8_V_M1_MASK,
24211 0 : 10369 => Opcode::PseudoVSSSEG7E8_V_MF2,
24212 0 : 10370 => Opcode::PseudoVSSSEG7E8_V_MF2_MASK,
24213 0 : 10371 => Opcode::PseudoVSSSEG7E8_V_MF4,
24214 0 : 10372 => Opcode::PseudoVSSSEG7E8_V_MF4_MASK,
24215 0 : 10373 => Opcode::PseudoVSSSEG7E8_V_MF8,
24216 0 : 10374 => Opcode::PseudoVSSSEG7E8_V_MF8_MASK,
24217 0 : 10375 => Opcode::PseudoVSSSEG8E16_V_M1,
24218 0 : 10376 => Opcode::PseudoVSSSEG8E16_V_M1_MASK,
24219 0 : 10377 => Opcode::PseudoVSSSEG8E16_V_MF2,
24220 0 : 10378 => Opcode::PseudoVSSSEG8E16_V_MF2_MASK,
24221 0 : 10379 => Opcode::PseudoVSSSEG8E16_V_MF4,
24222 0 : 10380 => Opcode::PseudoVSSSEG8E16_V_MF4_MASK,
24223 0 : 10381 => Opcode::PseudoVSSSEG8E32_V_M1,
24224 0 : 10382 => Opcode::PseudoVSSSEG8E32_V_M1_MASK,
24225 0 : 10383 => Opcode::PseudoVSSSEG8E32_V_MF2,
24226 0 : 10384 => Opcode::PseudoVSSSEG8E32_V_MF2_MASK,
24227 0 : 10385 => Opcode::PseudoVSSSEG8E64_V_M1,
24228 0 : 10386 => Opcode::PseudoVSSSEG8E64_V_M1_MASK,
24229 0 : 10387 => Opcode::PseudoVSSSEG8E8_V_M1,
24230 0 : 10388 => Opcode::PseudoVSSSEG8E8_V_M1_MASK,
24231 0 : 10389 => Opcode::PseudoVSSSEG8E8_V_MF2,
24232 0 : 10390 => Opcode::PseudoVSSSEG8E8_V_MF2_MASK,
24233 0 : 10391 => Opcode::PseudoVSSSEG8E8_V_MF4,
24234 0 : 10392 => Opcode::PseudoVSSSEG8E8_V_MF4_MASK,
24235 0 : 10393 => Opcode::PseudoVSSSEG8E8_V_MF8,
24236 0 : 10394 => Opcode::PseudoVSSSEG8E8_V_MF8_MASK,
24237 0 : 10395 => Opcode::PseudoVSSUBU_VV_M1,
24238 0 : 10396 => Opcode::PseudoVSSUBU_VV_M1_MASK,
24239 0 : 10397 => Opcode::PseudoVSSUBU_VV_M2,
24240 0 : 10398 => Opcode::PseudoVSSUBU_VV_M2_MASK,
24241 0 : 10399 => Opcode::PseudoVSSUBU_VV_M4,
24242 0 : 10400 => Opcode::PseudoVSSUBU_VV_M4_MASK,
24243 0 : 10401 => Opcode::PseudoVSSUBU_VV_M8,
24244 0 : 10402 => Opcode::PseudoVSSUBU_VV_M8_MASK,
24245 0 : 10403 => Opcode::PseudoVSSUBU_VV_MF2,
24246 0 : 10404 => Opcode::PseudoVSSUBU_VV_MF2_MASK,
24247 0 : 10405 => Opcode::PseudoVSSUBU_VV_MF4,
24248 0 : 10406 => Opcode::PseudoVSSUBU_VV_MF4_MASK,
24249 0 : 10407 => Opcode::PseudoVSSUBU_VV_MF8,
24250 0 : 10408 => Opcode::PseudoVSSUBU_VV_MF8_MASK,
24251 0 : 10409 => Opcode::PseudoVSSUBU_VX_M1,
24252 0 : 10410 => Opcode::PseudoVSSUBU_VX_M1_MASK,
24253 0 : 10411 => Opcode::PseudoVSSUBU_VX_M2,
24254 0 : 10412 => Opcode::PseudoVSSUBU_VX_M2_MASK,
24255 0 : 10413 => Opcode::PseudoVSSUBU_VX_M4,
24256 0 : 10414 => Opcode::PseudoVSSUBU_VX_M4_MASK,
24257 0 : 10415 => Opcode::PseudoVSSUBU_VX_M8,
24258 0 : 10416 => Opcode::PseudoVSSUBU_VX_M8_MASK,
24259 0 : 10417 => Opcode::PseudoVSSUBU_VX_MF2,
24260 0 : 10418 => Opcode::PseudoVSSUBU_VX_MF2_MASK,
24261 0 : 10419 => Opcode::PseudoVSSUBU_VX_MF4,
24262 0 : 10420 => Opcode::PseudoVSSUBU_VX_MF4_MASK,
24263 0 : 10421 => Opcode::PseudoVSSUBU_VX_MF8,
24264 0 : 10422 => Opcode::PseudoVSSUBU_VX_MF8_MASK,
24265 0 : 10423 => Opcode::PseudoVSSUB_VV_M1,
24266 0 : 10424 => Opcode::PseudoVSSUB_VV_M1_MASK,
24267 0 : 10425 => Opcode::PseudoVSSUB_VV_M2,
24268 0 : 10426 => Opcode::PseudoVSSUB_VV_M2_MASK,
24269 0 : 10427 => Opcode::PseudoVSSUB_VV_M4,
24270 0 : 10428 => Opcode::PseudoVSSUB_VV_M4_MASK,
24271 0 : 10429 => Opcode::PseudoVSSUB_VV_M8,
24272 0 : 10430 => Opcode::PseudoVSSUB_VV_M8_MASK,
24273 0 : 10431 => Opcode::PseudoVSSUB_VV_MF2,
24274 0 : 10432 => Opcode::PseudoVSSUB_VV_MF2_MASK,
24275 0 : 10433 => Opcode::PseudoVSSUB_VV_MF4,
24276 0 : 10434 => Opcode::PseudoVSSUB_VV_MF4_MASK,
24277 0 : 10435 => Opcode::PseudoVSSUB_VV_MF8,
24278 0 : 10436 => Opcode::PseudoVSSUB_VV_MF8_MASK,
24279 0 : 10437 => Opcode::PseudoVSSUB_VX_M1,
24280 0 : 10438 => Opcode::PseudoVSSUB_VX_M1_MASK,
24281 0 : 10439 => Opcode::PseudoVSSUB_VX_M2,
24282 0 : 10440 => Opcode::PseudoVSSUB_VX_M2_MASK,
24283 0 : 10441 => Opcode::PseudoVSSUB_VX_M4,
24284 0 : 10442 => Opcode::PseudoVSSUB_VX_M4_MASK,
24285 0 : 10443 => Opcode::PseudoVSSUB_VX_M8,
24286 0 : 10444 => Opcode::PseudoVSSUB_VX_M8_MASK,
24287 0 : 10445 => Opcode::PseudoVSSUB_VX_MF2,
24288 0 : 10446 => Opcode::PseudoVSSUB_VX_MF2_MASK,
24289 0 : 10447 => Opcode::PseudoVSSUB_VX_MF4,
24290 0 : 10448 => Opcode::PseudoVSSUB_VX_MF4_MASK,
24291 0 : 10449 => Opcode::PseudoVSSUB_VX_MF8,
24292 0 : 10450 => Opcode::PseudoVSSUB_VX_MF8_MASK,
24293 0 : 10451 => Opcode::PseudoVSUB_VV_M1,
24294 0 : 10452 => Opcode::PseudoVSUB_VV_M1_MASK,
24295 0 : 10453 => Opcode::PseudoVSUB_VV_M2,
24296 0 : 10454 => Opcode::PseudoVSUB_VV_M2_MASK,
24297 0 : 10455 => Opcode::PseudoVSUB_VV_M4,
24298 0 : 10456 => Opcode::PseudoVSUB_VV_M4_MASK,
24299 0 : 10457 => Opcode::PseudoVSUB_VV_M8,
24300 0 : 10458 => Opcode::PseudoVSUB_VV_M8_MASK,
24301 0 : 10459 => Opcode::PseudoVSUB_VV_MF2,
24302 0 : 10460 => Opcode::PseudoVSUB_VV_MF2_MASK,
24303 0 : 10461 => Opcode::PseudoVSUB_VV_MF4,
24304 0 : 10462 => Opcode::PseudoVSUB_VV_MF4_MASK,
24305 0 : 10463 => Opcode::PseudoVSUB_VV_MF8,
24306 0 : 10464 => Opcode::PseudoVSUB_VV_MF8_MASK,
24307 0 : 10465 => Opcode::PseudoVSUB_VX_M1,
24308 0 : 10466 => Opcode::PseudoVSUB_VX_M1_MASK,
24309 0 : 10467 => Opcode::PseudoVSUB_VX_M2,
24310 0 : 10468 => Opcode::PseudoVSUB_VX_M2_MASK,
24311 0 : 10469 => Opcode::PseudoVSUB_VX_M4,
24312 0 : 10470 => Opcode::PseudoVSUB_VX_M4_MASK,
24313 0 : 10471 => Opcode::PseudoVSUB_VX_M8,
24314 0 : 10472 => Opcode::PseudoVSUB_VX_M8_MASK,
24315 0 : 10473 => Opcode::PseudoVSUB_VX_MF2,
24316 0 : 10474 => Opcode::PseudoVSUB_VX_MF2_MASK,
24317 0 : 10475 => Opcode::PseudoVSUB_VX_MF4,
24318 0 : 10476 => Opcode::PseudoVSUB_VX_MF4_MASK,
24319 0 : 10477 => Opcode::PseudoVSUB_VX_MF8,
24320 0 : 10478 => Opcode::PseudoVSUB_VX_MF8_MASK,
24321 0 : 10479 => Opcode::PseudoVSUXEI16_V_M1_M1,
24322 0 : 10480 => Opcode::PseudoVSUXEI16_V_M1_M1_MASK,
24323 0 : 10481 => Opcode::PseudoVSUXEI16_V_M1_M2,
24324 0 : 10482 => Opcode::PseudoVSUXEI16_V_M1_M2_MASK,
24325 0 : 10483 => Opcode::PseudoVSUXEI16_V_M1_M4,
24326 0 : 10484 => Opcode::PseudoVSUXEI16_V_M1_M4_MASK,
24327 0 : 10485 => Opcode::PseudoVSUXEI16_V_M1_MF2,
24328 0 : 10486 => Opcode::PseudoVSUXEI16_V_M1_MF2_MASK,
24329 0 : 10487 => Opcode::PseudoVSUXEI16_V_M2_M1,
24330 0 : 10488 => Opcode::PseudoVSUXEI16_V_M2_M1_MASK,
24331 0 : 10489 => Opcode::PseudoVSUXEI16_V_M2_M2,
24332 0 : 10490 => Opcode::PseudoVSUXEI16_V_M2_M2_MASK,
24333 0 : 10491 => Opcode::PseudoVSUXEI16_V_M2_M4,
24334 0 : 10492 => Opcode::PseudoVSUXEI16_V_M2_M4_MASK,
24335 0 : 10493 => Opcode::PseudoVSUXEI16_V_M2_M8,
24336 0 : 10494 => Opcode::PseudoVSUXEI16_V_M2_M8_MASK,
24337 0 : 10495 => Opcode::PseudoVSUXEI16_V_M4_M2,
24338 0 : 10496 => Opcode::PseudoVSUXEI16_V_M4_M2_MASK,
24339 0 : 10497 => Opcode::PseudoVSUXEI16_V_M4_M4,
24340 0 : 10498 => Opcode::PseudoVSUXEI16_V_M4_M4_MASK,
24341 0 : 10499 => Opcode::PseudoVSUXEI16_V_M4_M8,
24342 0 : 10500 => Opcode::PseudoVSUXEI16_V_M4_M8_MASK,
24343 0 : 10501 => Opcode::PseudoVSUXEI16_V_M8_M4,
24344 0 : 10502 => Opcode::PseudoVSUXEI16_V_M8_M4_MASK,
24345 0 : 10503 => Opcode::PseudoVSUXEI16_V_M8_M8,
24346 0 : 10504 => Opcode::PseudoVSUXEI16_V_M8_M8_MASK,
24347 0 : 10505 => Opcode::PseudoVSUXEI16_V_MF2_M1,
24348 0 : 10506 => Opcode::PseudoVSUXEI16_V_MF2_M1_MASK,
24349 0 : 10507 => Opcode::PseudoVSUXEI16_V_MF2_M2,
24350 0 : 10508 => Opcode::PseudoVSUXEI16_V_MF2_M2_MASK,
24351 0 : 10509 => Opcode::PseudoVSUXEI16_V_MF2_MF2,
24352 0 : 10510 => Opcode::PseudoVSUXEI16_V_MF2_MF2_MASK,
24353 0 : 10511 => Opcode::PseudoVSUXEI16_V_MF2_MF4,
24354 0 : 10512 => Opcode::PseudoVSUXEI16_V_MF2_MF4_MASK,
24355 0 : 10513 => Opcode::PseudoVSUXEI16_V_MF4_M1,
24356 0 : 10514 => Opcode::PseudoVSUXEI16_V_MF4_M1_MASK,
24357 0 : 10515 => Opcode::PseudoVSUXEI16_V_MF4_MF2,
24358 0 : 10516 => Opcode::PseudoVSUXEI16_V_MF4_MF2_MASK,
24359 0 : 10517 => Opcode::PseudoVSUXEI16_V_MF4_MF4,
24360 0 : 10518 => Opcode::PseudoVSUXEI16_V_MF4_MF4_MASK,
24361 0 : 10519 => Opcode::PseudoVSUXEI16_V_MF4_MF8,
24362 0 : 10520 => Opcode::PseudoVSUXEI16_V_MF4_MF8_MASK,
24363 0 : 10521 => Opcode::PseudoVSUXEI32_V_M1_M1,
24364 0 : 10522 => Opcode::PseudoVSUXEI32_V_M1_M1_MASK,
24365 0 : 10523 => Opcode::PseudoVSUXEI32_V_M1_M2,
24366 0 : 10524 => Opcode::PseudoVSUXEI32_V_M1_M2_MASK,
24367 0 : 10525 => Opcode::PseudoVSUXEI32_V_M1_MF2,
24368 0 : 10526 => Opcode::PseudoVSUXEI32_V_M1_MF2_MASK,
24369 0 : 10527 => Opcode::PseudoVSUXEI32_V_M1_MF4,
24370 0 : 10528 => Opcode::PseudoVSUXEI32_V_M1_MF4_MASK,
24371 0 : 10529 => Opcode::PseudoVSUXEI32_V_M2_M1,
24372 0 : 10530 => Opcode::PseudoVSUXEI32_V_M2_M1_MASK,
24373 0 : 10531 => Opcode::PseudoVSUXEI32_V_M2_M2,
24374 0 : 10532 => Opcode::PseudoVSUXEI32_V_M2_M2_MASK,
24375 0 : 10533 => Opcode::PseudoVSUXEI32_V_M2_M4,
24376 0 : 10534 => Opcode::PseudoVSUXEI32_V_M2_M4_MASK,
24377 0 : 10535 => Opcode::PseudoVSUXEI32_V_M2_MF2,
24378 0 : 10536 => Opcode::PseudoVSUXEI32_V_M2_MF2_MASK,
24379 0 : 10537 => Opcode::PseudoVSUXEI32_V_M4_M1,
24380 0 : 10538 => Opcode::PseudoVSUXEI32_V_M4_M1_MASK,
24381 0 : 10539 => Opcode::PseudoVSUXEI32_V_M4_M2,
24382 0 : 10540 => Opcode::PseudoVSUXEI32_V_M4_M2_MASK,
24383 0 : 10541 => Opcode::PseudoVSUXEI32_V_M4_M4,
24384 0 : 10542 => Opcode::PseudoVSUXEI32_V_M4_M4_MASK,
24385 0 : 10543 => Opcode::PseudoVSUXEI32_V_M4_M8,
24386 0 : 10544 => Opcode::PseudoVSUXEI32_V_M4_M8_MASK,
24387 0 : 10545 => Opcode::PseudoVSUXEI32_V_M8_M2,
24388 0 : 10546 => Opcode::PseudoVSUXEI32_V_M8_M2_MASK,
24389 0 : 10547 => Opcode::PseudoVSUXEI32_V_M8_M4,
24390 0 : 10548 => Opcode::PseudoVSUXEI32_V_M8_M4_MASK,
24391 0 : 10549 => Opcode::PseudoVSUXEI32_V_M8_M8,
24392 0 : 10550 => Opcode::PseudoVSUXEI32_V_M8_M8_MASK,
24393 0 : 10551 => Opcode::PseudoVSUXEI32_V_MF2_M1,
24394 0 : 10552 => Opcode::PseudoVSUXEI32_V_MF2_M1_MASK,
24395 0 : 10553 => Opcode::PseudoVSUXEI32_V_MF2_MF2,
24396 0 : 10554 => Opcode::PseudoVSUXEI32_V_MF2_MF2_MASK,
24397 0 : 10555 => Opcode::PseudoVSUXEI32_V_MF2_MF4,
24398 0 : 10556 => Opcode::PseudoVSUXEI32_V_MF2_MF4_MASK,
24399 0 : 10557 => Opcode::PseudoVSUXEI32_V_MF2_MF8,
24400 0 : 10558 => Opcode::PseudoVSUXEI32_V_MF2_MF8_MASK,
24401 0 : 10559 => Opcode::PseudoVSUXEI64_V_M1_M1,
24402 0 : 10560 => Opcode::PseudoVSUXEI64_V_M1_M1_MASK,
24403 0 : 10561 => Opcode::PseudoVSUXEI64_V_M1_MF2,
24404 0 : 10562 => Opcode::PseudoVSUXEI64_V_M1_MF2_MASK,
24405 0 : 10563 => Opcode::PseudoVSUXEI64_V_M1_MF4,
24406 0 : 10564 => Opcode::PseudoVSUXEI64_V_M1_MF4_MASK,
24407 0 : 10565 => Opcode::PseudoVSUXEI64_V_M1_MF8,
24408 0 : 10566 => Opcode::PseudoVSUXEI64_V_M1_MF8_MASK,
24409 0 : 10567 => Opcode::PseudoVSUXEI64_V_M2_M1,
24410 0 : 10568 => Opcode::PseudoVSUXEI64_V_M2_M1_MASK,
24411 0 : 10569 => Opcode::PseudoVSUXEI64_V_M2_M2,
24412 0 : 10570 => Opcode::PseudoVSUXEI64_V_M2_M2_MASK,
24413 0 : 10571 => Opcode::PseudoVSUXEI64_V_M2_MF2,
24414 0 : 10572 => Opcode::PseudoVSUXEI64_V_M2_MF2_MASK,
24415 0 : 10573 => Opcode::PseudoVSUXEI64_V_M2_MF4,
24416 0 : 10574 => Opcode::PseudoVSUXEI64_V_M2_MF4_MASK,
24417 0 : 10575 => Opcode::PseudoVSUXEI64_V_M4_M1,
24418 0 : 10576 => Opcode::PseudoVSUXEI64_V_M4_M1_MASK,
24419 0 : 10577 => Opcode::PseudoVSUXEI64_V_M4_M2,
24420 0 : 10578 => Opcode::PseudoVSUXEI64_V_M4_M2_MASK,
24421 0 : 10579 => Opcode::PseudoVSUXEI64_V_M4_M4,
24422 0 : 10580 => Opcode::PseudoVSUXEI64_V_M4_M4_MASK,
24423 0 : 10581 => Opcode::PseudoVSUXEI64_V_M4_MF2,
24424 0 : 10582 => Opcode::PseudoVSUXEI64_V_M4_MF2_MASK,
24425 0 : 10583 => Opcode::PseudoVSUXEI64_V_M8_M1,
24426 0 : 10584 => Opcode::PseudoVSUXEI64_V_M8_M1_MASK,
24427 0 : 10585 => Opcode::PseudoVSUXEI64_V_M8_M2,
24428 0 : 10586 => Opcode::PseudoVSUXEI64_V_M8_M2_MASK,
24429 0 : 10587 => Opcode::PseudoVSUXEI64_V_M8_M4,
24430 0 : 10588 => Opcode::PseudoVSUXEI64_V_M8_M4_MASK,
24431 0 : 10589 => Opcode::PseudoVSUXEI64_V_M8_M8,
24432 0 : 10590 => Opcode::PseudoVSUXEI64_V_M8_M8_MASK,
24433 0 : 10591 => Opcode::PseudoVSUXEI8_V_M1_M1,
24434 0 : 10592 => Opcode::PseudoVSUXEI8_V_M1_M1_MASK,
24435 0 : 10593 => Opcode::PseudoVSUXEI8_V_M1_M2,
24436 0 : 10594 => Opcode::PseudoVSUXEI8_V_M1_M2_MASK,
24437 0 : 10595 => Opcode::PseudoVSUXEI8_V_M1_M4,
24438 0 : 10596 => Opcode::PseudoVSUXEI8_V_M1_M4_MASK,
24439 0 : 10597 => Opcode::PseudoVSUXEI8_V_M1_M8,
24440 0 : 10598 => Opcode::PseudoVSUXEI8_V_M1_M8_MASK,
24441 0 : 10599 => Opcode::PseudoVSUXEI8_V_M2_M2,
24442 0 : 10600 => Opcode::PseudoVSUXEI8_V_M2_M2_MASK,
24443 0 : 10601 => Opcode::PseudoVSUXEI8_V_M2_M4,
24444 0 : 10602 => Opcode::PseudoVSUXEI8_V_M2_M4_MASK,
24445 0 : 10603 => Opcode::PseudoVSUXEI8_V_M2_M8,
24446 0 : 10604 => Opcode::PseudoVSUXEI8_V_M2_M8_MASK,
24447 0 : 10605 => Opcode::PseudoVSUXEI8_V_M4_M4,
24448 0 : 10606 => Opcode::PseudoVSUXEI8_V_M4_M4_MASK,
24449 0 : 10607 => Opcode::PseudoVSUXEI8_V_M4_M8,
24450 0 : 10608 => Opcode::PseudoVSUXEI8_V_M4_M8_MASK,
24451 0 : 10609 => Opcode::PseudoVSUXEI8_V_M8_M8,
24452 0 : 10610 => Opcode::PseudoVSUXEI8_V_M8_M8_MASK,
24453 0 : 10611 => Opcode::PseudoVSUXEI8_V_MF2_M1,
24454 0 : 10612 => Opcode::PseudoVSUXEI8_V_MF2_M1_MASK,
24455 0 : 10613 => Opcode::PseudoVSUXEI8_V_MF2_M2,
24456 0 : 10614 => Opcode::PseudoVSUXEI8_V_MF2_M2_MASK,
24457 0 : 10615 => Opcode::PseudoVSUXEI8_V_MF2_M4,
24458 0 : 10616 => Opcode::PseudoVSUXEI8_V_MF2_M4_MASK,
24459 0 : 10617 => Opcode::PseudoVSUXEI8_V_MF2_MF2,
24460 0 : 10618 => Opcode::PseudoVSUXEI8_V_MF2_MF2_MASK,
24461 0 : 10619 => Opcode::PseudoVSUXEI8_V_MF4_M1,
24462 0 : 10620 => Opcode::PseudoVSUXEI8_V_MF4_M1_MASK,
24463 0 : 10621 => Opcode::PseudoVSUXEI8_V_MF4_M2,
24464 0 : 10622 => Opcode::PseudoVSUXEI8_V_MF4_M2_MASK,
24465 0 : 10623 => Opcode::PseudoVSUXEI8_V_MF4_MF2,
24466 0 : 10624 => Opcode::PseudoVSUXEI8_V_MF4_MF2_MASK,
24467 0 : 10625 => Opcode::PseudoVSUXEI8_V_MF4_MF4,
24468 0 : 10626 => Opcode::PseudoVSUXEI8_V_MF4_MF4_MASK,
24469 0 : 10627 => Opcode::PseudoVSUXEI8_V_MF8_M1,
24470 0 : 10628 => Opcode::PseudoVSUXEI8_V_MF8_M1_MASK,
24471 0 : 10629 => Opcode::PseudoVSUXEI8_V_MF8_MF2,
24472 0 : 10630 => Opcode::PseudoVSUXEI8_V_MF8_MF2_MASK,
24473 0 : 10631 => Opcode::PseudoVSUXEI8_V_MF8_MF4,
24474 0 : 10632 => Opcode::PseudoVSUXEI8_V_MF8_MF4_MASK,
24475 0 : 10633 => Opcode::PseudoVSUXEI8_V_MF8_MF8,
24476 0 : 10634 => Opcode::PseudoVSUXEI8_V_MF8_MF8_MASK,
24477 0 : 10635 => Opcode::PseudoVSUXSEG2EI16_V_M1_M1,
24478 0 : 10636 => Opcode::PseudoVSUXSEG2EI16_V_M1_M1_MASK,
24479 0 : 10637 => Opcode::PseudoVSUXSEG2EI16_V_M1_M2,
24480 0 : 10638 => Opcode::PseudoVSUXSEG2EI16_V_M1_M2_MASK,
24481 0 : 10639 => Opcode::PseudoVSUXSEG2EI16_V_M1_M4,
24482 0 : 10640 => Opcode::PseudoVSUXSEG2EI16_V_M1_M4_MASK,
24483 0 : 10641 => Opcode::PseudoVSUXSEG2EI16_V_M1_MF2,
24484 0 : 10642 => Opcode::PseudoVSUXSEG2EI16_V_M1_MF2_MASK,
24485 0 : 10643 => Opcode::PseudoVSUXSEG2EI16_V_M2_M1,
24486 0 : 10644 => Opcode::PseudoVSUXSEG2EI16_V_M2_M1_MASK,
24487 0 : 10645 => Opcode::PseudoVSUXSEG2EI16_V_M2_M2,
24488 0 : 10646 => Opcode::PseudoVSUXSEG2EI16_V_M2_M2_MASK,
24489 0 : 10647 => Opcode::PseudoVSUXSEG2EI16_V_M2_M4,
24490 0 : 10648 => Opcode::PseudoVSUXSEG2EI16_V_M2_M4_MASK,
24491 0 : 10649 => Opcode::PseudoVSUXSEG2EI16_V_M4_M2,
24492 0 : 10650 => Opcode::PseudoVSUXSEG2EI16_V_M4_M2_MASK,
24493 0 : 10651 => Opcode::PseudoVSUXSEG2EI16_V_M4_M4,
24494 0 : 10652 => Opcode::PseudoVSUXSEG2EI16_V_M4_M4_MASK,
24495 0 : 10653 => Opcode::PseudoVSUXSEG2EI16_V_M8_M4,
24496 0 : 10654 => Opcode::PseudoVSUXSEG2EI16_V_M8_M4_MASK,
24497 0 : 10655 => Opcode::PseudoVSUXSEG2EI16_V_MF2_M1,
24498 0 : 10656 => Opcode::PseudoVSUXSEG2EI16_V_MF2_M1_MASK,
24499 0 : 10657 => Opcode::PseudoVSUXSEG2EI16_V_MF2_M2,
24500 0 : 10658 => Opcode::PseudoVSUXSEG2EI16_V_MF2_M2_MASK,
24501 0 : 10659 => Opcode::PseudoVSUXSEG2EI16_V_MF2_MF2,
24502 0 : 10660 => Opcode::PseudoVSUXSEG2EI16_V_MF2_MF2_MASK,
24503 0 : 10661 => Opcode::PseudoVSUXSEG2EI16_V_MF2_MF4,
24504 0 : 10662 => Opcode::PseudoVSUXSEG2EI16_V_MF2_MF4_MASK,
24505 0 : 10663 => Opcode::PseudoVSUXSEG2EI16_V_MF4_M1,
24506 0 : 10664 => Opcode::PseudoVSUXSEG2EI16_V_MF4_M1_MASK,
24507 0 : 10665 => Opcode::PseudoVSUXSEG2EI16_V_MF4_MF2,
24508 0 : 10666 => Opcode::PseudoVSUXSEG2EI16_V_MF4_MF2_MASK,
24509 0 : 10667 => Opcode::PseudoVSUXSEG2EI16_V_MF4_MF4,
24510 0 : 10668 => Opcode::PseudoVSUXSEG2EI16_V_MF4_MF4_MASK,
24511 0 : 10669 => Opcode::PseudoVSUXSEG2EI16_V_MF4_MF8,
24512 0 : 10670 => Opcode::PseudoVSUXSEG2EI16_V_MF4_MF8_MASK,
24513 0 : 10671 => Opcode::PseudoVSUXSEG2EI32_V_M1_M1,
24514 0 : 10672 => Opcode::PseudoVSUXSEG2EI32_V_M1_M1_MASK,
24515 0 : 10673 => Opcode::PseudoVSUXSEG2EI32_V_M1_M2,
24516 0 : 10674 => Opcode::PseudoVSUXSEG2EI32_V_M1_M2_MASK,
24517 0 : 10675 => Opcode::PseudoVSUXSEG2EI32_V_M1_MF2,
24518 0 : 10676 => Opcode::PseudoVSUXSEG2EI32_V_M1_MF2_MASK,
24519 0 : 10677 => Opcode::PseudoVSUXSEG2EI32_V_M1_MF4,
24520 0 : 10678 => Opcode::PseudoVSUXSEG2EI32_V_M1_MF4_MASK,
24521 0 : 10679 => Opcode::PseudoVSUXSEG2EI32_V_M2_M1,
24522 0 : 10680 => Opcode::PseudoVSUXSEG2EI32_V_M2_M1_MASK,
24523 0 : 10681 => Opcode::PseudoVSUXSEG2EI32_V_M2_M2,
24524 0 : 10682 => Opcode::PseudoVSUXSEG2EI32_V_M2_M2_MASK,
24525 0 : 10683 => Opcode::PseudoVSUXSEG2EI32_V_M2_M4,
24526 0 : 10684 => Opcode::PseudoVSUXSEG2EI32_V_M2_M4_MASK,
24527 0 : 10685 => Opcode::PseudoVSUXSEG2EI32_V_M2_MF2,
24528 0 : 10686 => Opcode::PseudoVSUXSEG2EI32_V_M2_MF2_MASK,
24529 0 : 10687 => Opcode::PseudoVSUXSEG2EI32_V_M4_M1,
24530 0 : 10688 => Opcode::PseudoVSUXSEG2EI32_V_M4_M1_MASK,
24531 0 : 10689 => Opcode::PseudoVSUXSEG2EI32_V_M4_M2,
24532 0 : 10690 => Opcode::PseudoVSUXSEG2EI32_V_M4_M2_MASK,
24533 0 : 10691 => Opcode::PseudoVSUXSEG2EI32_V_M4_M4,
24534 0 : 10692 => Opcode::PseudoVSUXSEG2EI32_V_M4_M4_MASK,
24535 0 : 10693 => Opcode::PseudoVSUXSEG2EI32_V_M8_M2,
24536 0 : 10694 => Opcode::PseudoVSUXSEG2EI32_V_M8_M2_MASK,
24537 0 : 10695 => Opcode::PseudoVSUXSEG2EI32_V_M8_M4,
24538 0 : 10696 => Opcode::PseudoVSUXSEG2EI32_V_M8_M4_MASK,
24539 0 : 10697 => Opcode::PseudoVSUXSEG2EI32_V_MF2_M1,
24540 0 : 10698 => Opcode::PseudoVSUXSEG2EI32_V_MF2_M1_MASK,
24541 0 : 10699 => Opcode::PseudoVSUXSEG2EI32_V_MF2_MF2,
24542 0 : 10700 => Opcode::PseudoVSUXSEG2EI32_V_MF2_MF2_MASK,
24543 0 : 10701 => Opcode::PseudoVSUXSEG2EI32_V_MF2_MF4,
24544 0 : 10702 => Opcode::PseudoVSUXSEG2EI32_V_MF2_MF4_MASK,
24545 0 : 10703 => Opcode::PseudoVSUXSEG2EI32_V_MF2_MF8,
24546 0 : 10704 => Opcode::PseudoVSUXSEG2EI32_V_MF2_MF8_MASK,
24547 0 : 10705 => Opcode::PseudoVSUXSEG2EI64_V_M1_M1,
24548 0 : 10706 => Opcode::PseudoVSUXSEG2EI64_V_M1_M1_MASK,
24549 0 : 10707 => Opcode::PseudoVSUXSEG2EI64_V_M1_MF2,
24550 0 : 10708 => Opcode::PseudoVSUXSEG2EI64_V_M1_MF2_MASK,
24551 0 : 10709 => Opcode::PseudoVSUXSEG2EI64_V_M1_MF4,
24552 0 : 10710 => Opcode::PseudoVSUXSEG2EI64_V_M1_MF4_MASK,
24553 0 : 10711 => Opcode::PseudoVSUXSEG2EI64_V_M1_MF8,
24554 0 : 10712 => Opcode::PseudoVSUXSEG2EI64_V_M1_MF8_MASK,
24555 0 : 10713 => Opcode::PseudoVSUXSEG2EI64_V_M2_M1,
24556 0 : 10714 => Opcode::PseudoVSUXSEG2EI64_V_M2_M1_MASK,
24557 0 : 10715 => Opcode::PseudoVSUXSEG2EI64_V_M2_M2,
24558 0 : 10716 => Opcode::PseudoVSUXSEG2EI64_V_M2_M2_MASK,
24559 0 : 10717 => Opcode::PseudoVSUXSEG2EI64_V_M2_MF2,
24560 0 : 10718 => Opcode::PseudoVSUXSEG2EI64_V_M2_MF2_MASK,
24561 0 : 10719 => Opcode::PseudoVSUXSEG2EI64_V_M2_MF4,
24562 0 : 10720 => Opcode::PseudoVSUXSEG2EI64_V_M2_MF4_MASK,
24563 0 : 10721 => Opcode::PseudoVSUXSEG2EI64_V_M4_M1,
24564 0 : 10722 => Opcode::PseudoVSUXSEG2EI64_V_M4_M1_MASK,
24565 0 : 10723 => Opcode::PseudoVSUXSEG2EI64_V_M4_M2,
24566 0 : 10724 => Opcode::PseudoVSUXSEG2EI64_V_M4_M2_MASK,
24567 0 : 10725 => Opcode::PseudoVSUXSEG2EI64_V_M4_M4,
24568 0 : 10726 => Opcode::PseudoVSUXSEG2EI64_V_M4_M4_MASK,
24569 0 : 10727 => Opcode::PseudoVSUXSEG2EI64_V_M4_MF2,
24570 0 : 10728 => Opcode::PseudoVSUXSEG2EI64_V_M4_MF2_MASK,
24571 0 : 10729 => Opcode::PseudoVSUXSEG2EI64_V_M8_M1,
24572 0 : 10730 => Opcode::PseudoVSUXSEG2EI64_V_M8_M1_MASK,
24573 0 : 10731 => Opcode::PseudoVSUXSEG2EI64_V_M8_M2,
24574 0 : 10732 => Opcode::PseudoVSUXSEG2EI64_V_M8_M2_MASK,
24575 0 : 10733 => Opcode::PseudoVSUXSEG2EI64_V_M8_M4,
24576 0 : 10734 => Opcode::PseudoVSUXSEG2EI64_V_M8_M4_MASK,
24577 0 : 10735 => Opcode::PseudoVSUXSEG2EI8_V_M1_M1,
24578 0 : 10736 => Opcode::PseudoVSUXSEG2EI8_V_M1_M1_MASK,
24579 0 : 10737 => Opcode::PseudoVSUXSEG2EI8_V_M1_M2,
24580 0 : 10738 => Opcode::PseudoVSUXSEG2EI8_V_M1_M2_MASK,
24581 0 : 10739 => Opcode::PseudoVSUXSEG2EI8_V_M1_M4,
24582 0 : 10740 => Opcode::PseudoVSUXSEG2EI8_V_M1_M4_MASK,
24583 0 : 10741 => Opcode::PseudoVSUXSEG2EI8_V_M2_M2,
24584 0 : 10742 => Opcode::PseudoVSUXSEG2EI8_V_M2_M2_MASK,
24585 0 : 10743 => Opcode::PseudoVSUXSEG2EI8_V_M2_M4,
24586 0 : 10744 => Opcode::PseudoVSUXSEG2EI8_V_M2_M4_MASK,
24587 0 : 10745 => Opcode::PseudoVSUXSEG2EI8_V_M4_M4,
24588 0 : 10746 => Opcode::PseudoVSUXSEG2EI8_V_M4_M4_MASK,
24589 0 : 10747 => Opcode::PseudoVSUXSEG2EI8_V_MF2_M1,
24590 0 : 10748 => Opcode::PseudoVSUXSEG2EI8_V_MF2_M1_MASK,
24591 0 : 10749 => Opcode::PseudoVSUXSEG2EI8_V_MF2_M2,
24592 0 : 10750 => Opcode::PseudoVSUXSEG2EI8_V_MF2_M2_MASK,
24593 0 : 10751 => Opcode::PseudoVSUXSEG2EI8_V_MF2_M4,
24594 0 : 10752 => Opcode::PseudoVSUXSEG2EI8_V_MF2_M4_MASK,
24595 0 : 10753 => Opcode::PseudoVSUXSEG2EI8_V_MF2_MF2,
24596 0 : 10754 => Opcode::PseudoVSUXSEG2EI8_V_MF2_MF2_MASK,
24597 0 : 10755 => Opcode::PseudoVSUXSEG2EI8_V_MF4_M1,
24598 0 : 10756 => Opcode::PseudoVSUXSEG2EI8_V_MF4_M1_MASK,
24599 0 : 10757 => Opcode::PseudoVSUXSEG2EI8_V_MF4_M2,
24600 0 : 10758 => Opcode::PseudoVSUXSEG2EI8_V_MF4_M2_MASK,
24601 0 : 10759 => Opcode::PseudoVSUXSEG2EI8_V_MF4_MF2,
24602 0 : 10760 => Opcode::PseudoVSUXSEG2EI8_V_MF4_MF2_MASK,
24603 0 : 10761 => Opcode::PseudoVSUXSEG2EI8_V_MF4_MF4,
24604 0 : 10762 => Opcode::PseudoVSUXSEG2EI8_V_MF4_MF4_MASK,
24605 0 : 10763 => Opcode::PseudoVSUXSEG2EI8_V_MF8_M1,
24606 0 : 10764 => Opcode::PseudoVSUXSEG2EI8_V_MF8_M1_MASK,
24607 0 : 10765 => Opcode::PseudoVSUXSEG2EI8_V_MF8_MF2,
24608 0 : 10766 => Opcode::PseudoVSUXSEG2EI8_V_MF8_MF2_MASK,
24609 0 : 10767 => Opcode::PseudoVSUXSEG2EI8_V_MF8_MF4,
24610 0 : 10768 => Opcode::PseudoVSUXSEG2EI8_V_MF8_MF4_MASK,
24611 0 : 10769 => Opcode::PseudoVSUXSEG2EI8_V_MF8_MF8,
24612 0 : 10770 => Opcode::PseudoVSUXSEG2EI8_V_MF8_MF8_MASK,
24613 0 : 10771 => Opcode::PseudoVSUXSEG3EI16_V_M1_M1,
24614 0 : 10772 => Opcode::PseudoVSUXSEG3EI16_V_M1_M1_MASK,
24615 0 : 10773 => Opcode::PseudoVSUXSEG3EI16_V_M1_M2,
24616 0 : 10774 => Opcode::PseudoVSUXSEG3EI16_V_M1_M2_MASK,
24617 0 : 10775 => Opcode::PseudoVSUXSEG3EI16_V_M1_MF2,
24618 0 : 10776 => Opcode::PseudoVSUXSEG3EI16_V_M1_MF2_MASK,
24619 0 : 10777 => Opcode::PseudoVSUXSEG3EI16_V_M2_M1,
24620 0 : 10778 => Opcode::PseudoVSUXSEG3EI16_V_M2_M1_MASK,
24621 0 : 10779 => Opcode::PseudoVSUXSEG3EI16_V_M2_M2,
24622 0 : 10780 => Opcode::PseudoVSUXSEG3EI16_V_M2_M2_MASK,
24623 0 : 10781 => Opcode::PseudoVSUXSEG3EI16_V_M4_M2,
24624 0 : 10782 => Opcode::PseudoVSUXSEG3EI16_V_M4_M2_MASK,
24625 0 : 10783 => Opcode::PseudoVSUXSEG3EI16_V_MF2_M1,
24626 0 : 10784 => Opcode::PseudoVSUXSEG3EI16_V_MF2_M1_MASK,
24627 0 : 10785 => Opcode::PseudoVSUXSEG3EI16_V_MF2_M2,
24628 0 : 10786 => Opcode::PseudoVSUXSEG3EI16_V_MF2_M2_MASK,
24629 0 : 10787 => Opcode::PseudoVSUXSEG3EI16_V_MF2_MF2,
24630 0 : 10788 => Opcode::PseudoVSUXSEG3EI16_V_MF2_MF2_MASK,
24631 0 : 10789 => Opcode::PseudoVSUXSEG3EI16_V_MF2_MF4,
24632 0 : 10790 => Opcode::PseudoVSUXSEG3EI16_V_MF2_MF4_MASK,
24633 0 : 10791 => Opcode::PseudoVSUXSEG3EI16_V_MF4_M1,
24634 0 : 10792 => Opcode::PseudoVSUXSEG3EI16_V_MF4_M1_MASK,
24635 0 : 10793 => Opcode::PseudoVSUXSEG3EI16_V_MF4_MF2,
24636 0 : 10794 => Opcode::PseudoVSUXSEG3EI16_V_MF4_MF2_MASK,
24637 0 : 10795 => Opcode::PseudoVSUXSEG3EI16_V_MF4_MF4,
24638 0 : 10796 => Opcode::PseudoVSUXSEG3EI16_V_MF4_MF4_MASK,
24639 0 : 10797 => Opcode::PseudoVSUXSEG3EI16_V_MF4_MF8,
24640 0 : 10798 => Opcode::PseudoVSUXSEG3EI16_V_MF4_MF8_MASK,
24641 0 : 10799 => Opcode::PseudoVSUXSEG3EI32_V_M1_M1,
24642 0 : 10800 => Opcode::PseudoVSUXSEG3EI32_V_M1_M1_MASK,
24643 0 : 10801 => Opcode::PseudoVSUXSEG3EI32_V_M1_M2,
24644 0 : 10802 => Opcode::PseudoVSUXSEG3EI32_V_M1_M2_MASK,
24645 0 : 10803 => Opcode::PseudoVSUXSEG3EI32_V_M1_MF2,
24646 0 : 10804 => Opcode::PseudoVSUXSEG3EI32_V_M1_MF2_MASK,
24647 0 : 10805 => Opcode::PseudoVSUXSEG3EI32_V_M1_MF4,
24648 0 : 10806 => Opcode::PseudoVSUXSEG3EI32_V_M1_MF4_MASK,
24649 0 : 10807 => Opcode::PseudoVSUXSEG3EI32_V_M2_M1,
24650 0 : 10808 => Opcode::PseudoVSUXSEG3EI32_V_M2_M1_MASK,
24651 0 : 10809 => Opcode::PseudoVSUXSEG3EI32_V_M2_M2,
24652 0 : 10810 => Opcode::PseudoVSUXSEG3EI32_V_M2_M2_MASK,
24653 0 : 10811 => Opcode::PseudoVSUXSEG3EI32_V_M2_MF2,
24654 0 : 10812 => Opcode::PseudoVSUXSEG3EI32_V_M2_MF2_MASK,
24655 0 : 10813 => Opcode::PseudoVSUXSEG3EI32_V_M4_M1,
24656 0 : 10814 => Opcode::PseudoVSUXSEG3EI32_V_M4_M1_MASK,
24657 0 : 10815 => Opcode::PseudoVSUXSEG3EI32_V_M4_M2,
24658 0 : 10816 => Opcode::PseudoVSUXSEG3EI32_V_M4_M2_MASK,
24659 0 : 10817 => Opcode::PseudoVSUXSEG3EI32_V_M8_M2,
24660 0 : 10818 => Opcode::PseudoVSUXSEG3EI32_V_M8_M2_MASK,
24661 0 : 10819 => Opcode::PseudoVSUXSEG3EI32_V_MF2_M1,
24662 0 : 10820 => Opcode::PseudoVSUXSEG3EI32_V_MF2_M1_MASK,
24663 0 : 10821 => Opcode::PseudoVSUXSEG3EI32_V_MF2_MF2,
24664 0 : 10822 => Opcode::PseudoVSUXSEG3EI32_V_MF2_MF2_MASK,
24665 0 : 10823 => Opcode::PseudoVSUXSEG3EI32_V_MF2_MF4,
24666 0 : 10824 => Opcode::PseudoVSUXSEG3EI32_V_MF2_MF4_MASK,
24667 0 : 10825 => Opcode::PseudoVSUXSEG3EI32_V_MF2_MF8,
24668 0 : 10826 => Opcode::PseudoVSUXSEG3EI32_V_MF2_MF8_MASK,
24669 0 : 10827 => Opcode::PseudoVSUXSEG3EI64_V_M1_M1,
24670 0 : 10828 => Opcode::PseudoVSUXSEG3EI64_V_M1_M1_MASK,
24671 0 : 10829 => Opcode::PseudoVSUXSEG3EI64_V_M1_MF2,
24672 0 : 10830 => Opcode::PseudoVSUXSEG3EI64_V_M1_MF2_MASK,
24673 0 : 10831 => Opcode::PseudoVSUXSEG3EI64_V_M1_MF4,
24674 0 : 10832 => Opcode::PseudoVSUXSEG3EI64_V_M1_MF4_MASK,
24675 0 : 10833 => Opcode::PseudoVSUXSEG3EI64_V_M1_MF8,
24676 0 : 10834 => Opcode::PseudoVSUXSEG3EI64_V_M1_MF8_MASK,
24677 0 : 10835 => Opcode::PseudoVSUXSEG3EI64_V_M2_M1,
24678 0 : 10836 => Opcode::PseudoVSUXSEG3EI64_V_M2_M1_MASK,
24679 0 : 10837 => Opcode::PseudoVSUXSEG3EI64_V_M2_M2,
24680 0 : 10838 => Opcode::PseudoVSUXSEG3EI64_V_M2_M2_MASK,
24681 0 : 10839 => Opcode::PseudoVSUXSEG3EI64_V_M2_MF2,
24682 0 : 10840 => Opcode::PseudoVSUXSEG3EI64_V_M2_MF2_MASK,
24683 0 : 10841 => Opcode::PseudoVSUXSEG3EI64_V_M2_MF4,
24684 0 : 10842 => Opcode::PseudoVSUXSEG3EI64_V_M2_MF4_MASK,
24685 0 : 10843 => Opcode::PseudoVSUXSEG3EI64_V_M4_M1,
24686 0 : 10844 => Opcode::PseudoVSUXSEG3EI64_V_M4_M1_MASK,
24687 0 : 10845 => Opcode::PseudoVSUXSEG3EI64_V_M4_M2,
24688 0 : 10846 => Opcode::PseudoVSUXSEG3EI64_V_M4_M2_MASK,
24689 0 : 10847 => Opcode::PseudoVSUXSEG3EI64_V_M4_MF2,
24690 0 : 10848 => Opcode::PseudoVSUXSEG3EI64_V_M4_MF2_MASK,
24691 0 : 10849 => Opcode::PseudoVSUXSEG3EI64_V_M8_M1,
24692 0 : 10850 => Opcode::PseudoVSUXSEG3EI64_V_M8_M1_MASK,
24693 0 : 10851 => Opcode::PseudoVSUXSEG3EI64_V_M8_M2,
24694 0 : 10852 => Opcode::PseudoVSUXSEG3EI64_V_M8_M2_MASK,
24695 0 : 10853 => Opcode::PseudoVSUXSEG3EI8_V_M1_M1,
24696 0 : 10854 => Opcode::PseudoVSUXSEG3EI8_V_M1_M1_MASK,
24697 0 : 10855 => Opcode::PseudoVSUXSEG3EI8_V_M1_M2,
24698 0 : 10856 => Opcode::PseudoVSUXSEG3EI8_V_M1_M2_MASK,
24699 0 : 10857 => Opcode::PseudoVSUXSEG3EI8_V_M2_M2,
24700 0 : 10858 => Opcode::PseudoVSUXSEG3EI8_V_M2_M2_MASK,
24701 0 : 10859 => Opcode::PseudoVSUXSEG3EI8_V_MF2_M1,
24702 0 : 10860 => Opcode::PseudoVSUXSEG3EI8_V_MF2_M1_MASK,
24703 0 : 10861 => Opcode::PseudoVSUXSEG3EI8_V_MF2_M2,
24704 0 : 10862 => Opcode::PseudoVSUXSEG3EI8_V_MF2_M2_MASK,
24705 0 : 10863 => Opcode::PseudoVSUXSEG3EI8_V_MF2_MF2,
24706 0 : 10864 => Opcode::PseudoVSUXSEG3EI8_V_MF2_MF2_MASK,
24707 0 : 10865 => Opcode::PseudoVSUXSEG3EI8_V_MF4_M1,
24708 0 : 10866 => Opcode::PseudoVSUXSEG3EI8_V_MF4_M1_MASK,
24709 0 : 10867 => Opcode::PseudoVSUXSEG3EI8_V_MF4_M2,
24710 0 : 10868 => Opcode::PseudoVSUXSEG3EI8_V_MF4_M2_MASK,
24711 0 : 10869 => Opcode::PseudoVSUXSEG3EI8_V_MF4_MF2,
24712 0 : 10870 => Opcode::PseudoVSUXSEG3EI8_V_MF4_MF2_MASK,
24713 0 : 10871 => Opcode::PseudoVSUXSEG3EI8_V_MF4_MF4,
24714 0 : 10872 => Opcode::PseudoVSUXSEG3EI8_V_MF4_MF4_MASK,
24715 0 : 10873 => Opcode::PseudoVSUXSEG3EI8_V_MF8_M1,
24716 0 : 10874 => Opcode::PseudoVSUXSEG3EI8_V_MF8_M1_MASK,
24717 0 : 10875 => Opcode::PseudoVSUXSEG3EI8_V_MF8_MF2,
24718 0 : 10876 => Opcode::PseudoVSUXSEG3EI8_V_MF8_MF2_MASK,
24719 0 : 10877 => Opcode::PseudoVSUXSEG3EI8_V_MF8_MF4,
24720 0 : 10878 => Opcode::PseudoVSUXSEG3EI8_V_MF8_MF4_MASK,
24721 0 : 10879 => Opcode::PseudoVSUXSEG3EI8_V_MF8_MF8,
24722 0 : 10880 => Opcode::PseudoVSUXSEG3EI8_V_MF8_MF8_MASK,
24723 0 : 10881 => Opcode::PseudoVSUXSEG4EI16_V_M1_M1,
24724 0 : 10882 => Opcode::PseudoVSUXSEG4EI16_V_M1_M1_MASK,
24725 0 : 10883 => Opcode::PseudoVSUXSEG4EI16_V_M1_M2,
24726 0 : 10884 => Opcode::PseudoVSUXSEG4EI16_V_M1_M2_MASK,
24727 0 : 10885 => Opcode::PseudoVSUXSEG4EI16_V_M1_MF2,
24728 0 : 10886 => Opcode::PseudoVSUXSEG4EI16_V_M1_MF2_MASK,
24729 0 : 10887 => Opcode::PseudoVSUXSEG4EI16_V_M2_M1,
24730 0 : 10888 => Opcode::PseudoVSUXSEG4EI16_V_M2_M1_MASK,
24731 0 : 10889 => Opcode::PseudoVSUXSEG4EI16_V_M2_M2,
24732 0 : 10890 => Opcode::PseudoVSUXSEG4EI16_V_M2_M2_MASK,
24733 0 : 10891 => Opcode::PseudoVSUXSEG4EI16_V_M4_M2,
24734 0 : 10892 => Opcode::PseudoVSUXSEG4EI16_V_M4_M2_MASK,
24735 0 : 10893 => Opcode::PseudoVSUXSEG4EI16_V_MF2_M1,
24736 0 : 10894 => Opcode::PseudoVSUXSEG4EI16_V_MF2_M1_MASK,
24737 0 : 10895 => Opcode::PseudoVSUXSEG4EI16_V_MF2_M2,
24738 0 : 10896 => Opcode::PseudoVSUXSEG4EI16_V_MF2_M2_MASK,
24739 0 : 10897 => Opcode::PseudoVSUXSEG4EI16_V_MF2_MF2,
24740 0 : 10898 => Opcode::PseudoVSUXSEG4EI16_V_MF2_MF2_MASK,
24741 0 : 10899 => Opcode::PseudoVSUXSEG4EI16_V_MF2_MF4,
24742 0 : 10900 => Opcode::PseudoVSUXSEG4EI16_V_MF2_MF4_MASK,
24743 0 : 10901 => Opcode::PseudoVSUXSEG4EI16_V_MF4_M1,
24744 0 : 10902 => Opcode::PseudoVSUXSEG4EI16_V_MF4_M1_MASK,
24745 0 : 10903 => Opcode::PseudoVSUXSEG4EI16_V_MF4_MF2,
24746 0 : 10904 => Opcode::PseudoVSUXSEG4EI16_V_MF4_MF2_MASK,
24747 0 : 10905 => Opcode::PseudoVSUXSEG4EI16_V_MF4_MF4,
24748 0 : 10906 => Opcode::PseudoVSUXSEG4EI16_V_MF4_MF4_MASK,
24749 0 : 10907 => Opcode::PseudoVSUXSEG4EI16_V_MF4_MF8,
24750 0 : 10908 => Opcode::PseudoVSUXSEG4EI16_V_MF4_MF8_MASK,
24751 0 : 10909 => Opcode::PseudoVSUXSEG4EI32_V_M1_M1,
24752 0 : 10910 => Opcode::PseudoVSUXSEG4EI32_V_M1_M1_MASK,
24753 0 : 10911 => Opcode::PseudoVSUXSEG4EI32_V_M1_M2,
24754 0 : 10912 => Opcode::PseudoVSUXSEG4EI32_V_M1_M2_MASK,
24755 0 : 10913 => Opcode::PseudoVSUXSEG4EI32_V_M1_MF2,
24756 0 : 10914 => Opcode::PseudoVSUXSEG4EI32_V_M1_MF2_MASK,
24757 0 : 10915 => Opcode::PseudoVSUXSEG4EI32_V_M1_MF4,
24758 0 : 10916 => Opcode::PseudoVSUXSEG4EI32_V_M1_MF4_MASK,
24759 0 : 10917 => Opcode::PseudoVSUXSEG4EI32_V_M2_M1,
24760 0 : 10918 => Opcode::PseudoVSUXSEG4EI32_V_M2_M1_MASK,
24761 0 : 10919 => Opcode::PseudoVSUXSEG4EI32_V_M2_M2,
24762 0 : 10920 => Opcode::PseudoVSUXSEG4EI32_V_M2_M2_MASK,
24763 0 : 10921 => Opcode::PseudoVSUXSEG4EI32_V_M2_MF2,
24764 0 : 10922 => Opcode::PseudoVSUXSEG4EI32_V_M2_MF2_MASK,
24765 0 : 10923 => Opcode::PseudoVSUXSEG4EI32_V_M4_M1,
24766 0 : 10924 => Opcode::PseudoVSUXSEG4EI32_V_M4_M1_MASK,
24767 0 : 10925 => Opcode::PseudoVSUXSEG4EI32_V_M4_M2,
24768 0 : 10926 => Opcode::PseudoVSUXSEG4EI32_V_M4_M2_MASK,
24769 0 : 10927 => Opcode::PseudoVSUXSEG4EI32_V_M8_M2,
24770 0 : 10928 => Opcode::PseudoVSUXSEG4EI32_V_M8_M2_MASK,
24771 0 : 10929 => Opcode::PseudoVSUXSEG4EI32_V_MF2_M1,
24772 0 : 10930 => Opcode::PseudoVSUXSEG4EI32_V_MF2_M1_MASK,
24773 0 : 10931 => Opcode::PseudoVSUXSEG4EI32_V_MF2_MF2,
24774 0 : 10932 => Opcode::PseudoVSUXSEG4EI32_V_MF2_MF2_MASK,
24775 0 : 10933 => Opcode::PseudoVSUXSEG4EI32_V_MF2_MF4,
24776 0 : 10934 => Opcode::PseudoVSUXSEG4EI32_V_MF2_MF4_MASK,
24777 0 : 10935 => Opcode::PseudoVSUXSEG4EI32_V_MF2_MF8,
24778 0 : 10936 => Opcode::PseudoVSUXSEG4EI32_V_MF2_MF8_MASK,
24779 0 : 10937 => Opcode::PseudoVSUXSEG4EI64_V_M1_M1,
24780 0 : 10938 => Opcode::PseudoVSUXSEG4EI64_V_M1_M1_MASK,
24781 0 : 10939 => Opcode::PseudoVSUXSEG4EI64_V_M1_MF2,
24782 0 : 10940 => Opcode::PseudoVSUXSEG4EI64_V_M1_MF2_MASK,
24783 0 : 10941 => Opcode::PseudoVSUXSEG4EI64_V_M1_MF4,
24784 0 : 10942 => Opcode::PseudoVSUXSEG4EI64_V_M1_MF4_MASK,
24785 0 : 10943 => Opcode::PseudoVSUXSEG4EI64_V_M1_MF8,
24786 0 : 10944 => Opcode::PseudoVSUXSEG4EI64_V_M1_MF8_MASK,
24787 0 : 10945 => Opcode::PseudoVSUXSEG4EI64_V_M2_M1,
24788 0 : 10946 => Opcode::PseudoVSUXSEG4EI64_V_M2_M1_MASK,
24789 0 : 10947 => Opcode::PseudoVSUXSEG4EI64_V_M2_M2,
24790 0 : 10948 => Opcode::PseudoVSUXSEG4EI64_V_M2_M2_MASK,
24791 0 : 10949 => Opcode::PseudoVSUXSEG4EI64_V_M2_MF2,
24792 0 : 10950 => Opcode::PseudoVSUXSEG4EI64_V_M2_MF2_MASK,
24793 0 : 10951 => Opcode::PseudoVSUXSEG4EI64_V_M2_MF4,
24794 0 : 10952 => Opcode::PseudoVSUXSEG4EI64_V_M2_MF4_MASK,
24795 0 : 10953 => Opcode::PseudoVSUXSEG4EI64_V_M4_M1,
24796 0 : 10954 => Opcode::PseudoVSUXSEG4EI64_V_M4_M1_MASK,
24797 0 : 10955 => Opcode::PseudoVSUXSEG4EI64_V_M4_M2,
24798 0 : 10956 => Opcode::PseudoVSUXSEG4EI64_V_M4_M2_MASK,
24799 0 : 10957 => Opcode::PseudoVSUXSEG4EI64_V_M4_MF2,
24800 0 : 10958 => Opcode::PseudoVSUXSEG4EI64_V_M4_MF2_MASK,
24801 0 : 10959 => Opcode::PseudoVSUXSEG4EI64_V_M8_M1,
24802 0 : 10960 => Opcode::PseudoVSUXSEG4EI64_V_M8_M1_MASK,
24803 0 : 10961 => Opcode::PseudoVSUXSEG4EI64_V_M8_M2,
24804 0 : 10962 => Opcode::PseudoVSUXSEG4EI64_V_M8_M2_MASK,
24805 0 : 10963 => Opcode::PseudoVSUXSEG4EI8_V_M1_M1,
24806 0 : 10964 => Opcode::PseudoVSUXSEG4EI8_V_M1_M1_MASK,
24807 0 : 10965 => Opcode::PseudoVSUXSEG4EI8_V_M1_M2,
24808 0 : 10966 => Opcode::PseudoVSUXSEG4EI8_V_M1_M2_MASK,
24809 0 : 10967 => Opcode::PseudoVSUXSEG4EI8_V_M2_M2,
24810 0 : 10968 => Opcode::PseudoVSUXSEG4EI8_V_M2_M2_MASK,
24811 0 : 10969 => Opcode::PseudoVSUXSEG4EI8_V_MF2_M1,
24812 0 : 10970 => Opcode::PseudoVSUXSEG4EI8_V_MF2_M1_MASK,
24813 0 : 10971 => Opcode::PseudoVSUXSEG4EI8_V_MF2_M2,
24814 0 : 10972 => Opcode::PseudoVSUXSEG4EI8_V_MF2_M2_MASK,
24815 0 : 10973 => Opcode::PseudoVSUXSEG4EI8_V_MF2_MF2,
24816 0 : 10974 => Opcode::PseudoVSUXSEG4EI8_V_MF2_MF2_MASK,
24817 0 : 10975 => Opcode::PseudoVSUXSEG4EI8_V_MF4_M1,
24818 0 : 10976 => Opcode::PseudoVSUXSEG4EI8_V_MF4_M1_MASK,
24819 0 : 10977 => Opcode::PseudoVSUXSEG4EI8_V_MF4_M2,
24820 0 : 10978 => Opcode::PseudoVSUXSEG4EI8_V_MF4_M2_MASK,
24821 0 : 10979 => Opcode::PseudoVSUXSEG4EI8_V_MF4_MF2,
24822 0 : 10980 => Opcode::PseudoVSUXSEG4EI8_V_MF4_MF2_MASK,
24823 0 : 10981 => Opcode::PseudoVSUXSEG4EI8_V_MF4_MF4,
24824 0 : 10982 => Opcode::PseudoVSUXSEG4EI8_V_MF4_MF4_MASK,
24825 0 : 10983 => Opcode::PseudoVSUXSEG4EI8_V_MF8_M1,
24826 0 : 10984 => Opcode::PseudoVSUXSEG4EI8_V_MF8_M1_MASK,
24827 0 : 10985 => Opcode::PseudoVSUXSEG4EI8_V_MF8_MF2,
24828 0 : 10986 => Opcode::PseudoVSUXSEG4EI8_V_MF8_MF2_MASK,
24829 0 : 10987 => Opcode::PseudoVSUXSEG4EI8_V_MF8_MF4,
24830 0 : 10988 => Opcode::PseudoVSUXSEG4EI8_V_MF8_MF4_MASK,
24831 0 : 10989 => Opcode::PseudoVSUXSEG4EI8_V_MF8_MF8,
24832 0 : 10990 => Opcode::PseudoVSUXSEG4EI8_V_MF8_MF8_MASK,
24833 0 : 10991 => Opcode::PseudoVSUXSEG5EI16_V_M1_M1,
24834 0 : 10992 => Opcode::PseudoVSUXSEG5EI16_V_M1_M1_MASK,
24835 0 : 10993 => Opcode::PseudoVSUXSEG5EI16_V_M1_MF2,
24836 0 : 10994 => Opcode::PseudoVSUXSEG5EI16_V_M1_MF2_MASK,
24837 0 : 10995 => Opcode::PseudoVSUXSEG5EI16_V_M2_M1,
24838 0 : 10996 => Opcode::PseudoVSUXSEG5EI16_V_M2_M1_MASK,
24839 0 : 10997 => Opcode::PseudoVSUXSEG5EI16_V_MF2_M1,
24840 0 : 10998 => Opcode::PseudoVSUXSEG5EI16_V_MF2_M1_MASK,
24841 0 : 10999 => Opcode::PseudoVSUXSEG5EI16_V_MF2_MF2,
24842 0 : 11000 => Opcode::PseudoVSUXSEG5EI16_V_MF2_MF2_MASK,
24843 0 : 11001 => Opcode::PseudoVSUXSEG5EI16_V_MF2_MF4,
24844 0 : 11002 => Opcode::PseudoVSUXSEG5EI16_V_MF2_MF4_MASK,
24845 0 : 11003 => Opcode::PseudoVSUXSEG5EI16_V_MF4_M1,
24846 0 : 11004 => Opcode::PseudoVSUXSEG5EI16_V_MF4_M1_MASK,
24847 0 : 11005 => Opcode::PseudoVSUXSEG5EI16_V_MF4_MF2,
24848 0 : 11006 => Opcode::PseudoVSUXSEG5EI16_V_MF4_MF2_MASK,
24849 0 : 11007 => Opcode::PseudoVSUXSEG5EI16_V_MF4_MF4,
24850 0 : 11008 => Opcode::PseudoVSUXSEG5EI16_V_MF4_MF4_MASK,
24851 0 : 11009 => Opcode::PseudoVSUXSEG5EI16_V_MF4_MF8,
24852 0 : 11010 => Opcode::PseudoVSUXSEG5EI16_V_MF4_MF8_MASK,
24853 0 : 11011 => Opcode::PseudoVSUXSEG5EI32_V_M1_M1,
24854 0 : 11012 => Opcode::PseudoVSUXSEG5EI32_V_M1_M1_MASK,
24855 0 : 11013 => Opcode::PseudoVSUXSEG5EI32_V_M1_MF2,
24856 0 : 11014 => Opcode::PseudoVSUXSEG5EI32_V_M1_MF2_MASK,
24857 0 : 11015 => Opcode::PseudoVSUXSEG5EI32_V_M1_MF4,
24858 0 : 11016 => Opcode::PseudoVSUXSEG5EI32_V_M1_MF4_MASK,
24859 0 : 11017 => Opcode::PseudoVSUXSEG5EI32_V_M2_M1,
24860 0 : 11018 => Opcode::PseudoVSUXSEG5EI32_V_M2_M1_MASK,
24861 0 : 11019 => Opcode::PseudoVSUXSEG5EI32_V_M2_MF2,
24862 0 : 11020 => Opcode::PseudoVSUXSEG5EI32_V_M2_MF2_MASK,
24863 0 : 11021 => Opcode::PseudoVSUXSEG5EI32_V_M4_M1,
24864 0 : 11022 => Opcode::PseudoVSUXSEG5EI32_V_M4_M1_MASK,
24865 0 : 11023 => Opcode::PseudoVSUXSEG5EI32_V_MF2_M1,
24866 0 : 11024 => Opcode::PseudoVSUXSEG5EI32_V_MF2_M1_MASK,
24867 0 : 11025 => Opcode::PseudoVSUXSEG5EI32_V_MF2_MF2,
24868 0 : 11026 => Opcode::PseudoVSUXSEG5EI32_V_MF2_MF2_MASK,
24869 0 : 11027 => Opcode::PseudoVSUXSEG5EI32_V_MF2_MF4,
24870 0 : 11028 => Opcode::PseudoVSUXSEG5EI32_V_MF2_MF4_MASK,
24871 0 : 11029 => Opcode::PseudoVSUXSEG5EI32_V_MF2_MF8,
24872 0 : 11030 => Opcode::PseudoVSUXSEG5EI32_V_MF2_MF8_MASK,
24873 0 : 11031 => Opcode::PseudoVSUXSEG5EI64_V_M1_M1,
24874 0 : 11032 => Opcode::PseudoVSUXSEG5EI64_V_M1_M1_MASK,
24875 0 : 11033 => Opcode::PseudoVSUXSEG5EI64_V_M1_MF2,
24876 0 : 11034 => Opcode::PseudoVSUXSEG5EI64_V_M1_MF2_MASK,
24877 0 : 11035 => Opcode::PseudoVSUXSEG5EI64_V_M1_MF4,
24878 0 : 11036 => Opcode::PseudoVSUXSEG5EI64_V_M1_MF4_MASK,
24879 0 : 11037 => Opcode::PseudoVSUXSEG5EI64_V_M1_MF8,
24880 0 : 11038 => Opcode::PseudoVSUXSEG5EI64_V_M1_MF8_MASK,
24881 0 : 11039 => Opcode::PseudoVSUXSEG5EI64_V_M2_M1,
24882 0 : 11040 => Opcode::PseudoVSUXSEG5EI64_V_M2_M1_MASK,
24883 0 : 11041 => Opcode::PseudoVSUXSEG5EI64_V_M2_MF2,
24884 0 : 11042 => Opcode::PseudoVSUXSEG5EI64_V_M2_MF2_MASK,
24885 0 : 11043 => Opcode::PseudoVSUXSEG5EI64_V_M2_MF4,
24886 0 : 11044 => Opcode::PseudoVSUXSEG5EI64_V_M2_MF4_MASK,
24887 0 : 11045 => Opcode::PseudoVSUXSEG5EI64_V_M4_M1,
24888 0 : 11046 => Opcode::PseudoVSUXSEG5EI64_V_M4_M1_MASK,
24889 0 : 11047 => Opcode::PseudoVSUXSEG5EI64_V_M4_MF2,
24890 0 : 11048 => Opcode::PseudoVSUXSEG5EI64_V_M4_MF2_MASK,
24891 0 : 11049 => Opcode::PseudoVSUXSEG5EI64_V_M8_M1,
24892 0 : 11050 => Opcode::PseudoVSUXSEG5EI64_V_M8_M1_MASK,
24893 0 : 11051 => Opcode::PseudoVSUXSEG5EI8_V_M1_M1,
24894 0 : 11052 => Opcode::PseudoVSUXSEG5EI8_V_M1_M1_MASK,
24895 0 : 11053 => Opcode::PseudoVSUXSEG5EI8_V_MF2_M1,
24896 0 : 11054 => Opcode::PseudoVSUXSEG5EI8_V_MF2_M1_MASK,
24897 0 : 11055 => Opcode::PseudoVSUXSEG5EI8_V_MF2_MF2,
24898 0 : 11056 => Opcode::PseudoVSUXSEG5EI8_V_MF2_MF2_MASK,
24899 0 : 11057 => Opcode::PseudoVSUXSEG5EI8_V_MF4_M1,
24900 0 : 11058 => Opcode::PseudoVSUXSEG5EI8_V_MF4_M1_MASK,
24901 0 : 11059 => Opcode::PseudoVSUXSEG5EI8_V_MF4_MF2,
24902 0 : 11060 => Opcode::PseudoVSUXSEG5EI8_V_MF4_MF2_MASK,
24903 0 : 11061 => Opcode::PseudoVSUXSEG5EI8_V_MF4_MF4,
24904 0 : 11062 => Opcode::PseudoVSUXSEG5EI8_V_MF4_MF4_MASK,
24905 0 : 11063 => Opcode::PseudoVSUXSEG5EI8_V_MF8_M1,
24906 0 : 11064 => Opcode::PseudoVSUXSEG5EI8_V_MF8_M1_MASK,
24907 0 : 11065 => Opcode::PseudoVSUXSEG5EI8_V_MF8_MF2,
24908 0 : 11066 => Opcode::PseudoVSUXSEG5EI8_V_MF8_MF2_MASK,
24909 0 : 11067 => Opcode::PseudoVSUXSEG5EI8_V_MF8_MF4,
24910 0 : 11068 => Opcode::PseudoVSUXSEG5EI8_V_MF8_MF4_MASK,
24911 0 : 11069 => Opcode::PseudoVSUXSEG5EI8_V_MF8_MF8,
24912 0 : 11070 => Opcode::PseudoVSUXSEG5EI8_V_MF8_MF8_MASK,
24913 0 : 11071 => Opcode::PseudoVSUXSEG6EI16_V_M1_M1,
24914 0 : 11072 => Opcode::PseudoVSUXSEG6EI16_V_M1_M1_MASK,
24915 0 : 11073 => Opcode::PseudoVSUXSEG6EI16_V_M1_MF2,
24916 0 : 11074 => Opcode::PseudoVSUXSEG6EI16_V_M1_MF2_MASK,
24917 0 : 11075 => Opcode::PseudoVSUXSEG6EI16_V_M2_M1,
24918 0 : 11076 => Opcode::PseudoVSUXSEG6EI16_V_M2_M1_MASK,
24919 0 : 11077 => Opcode::PseudoVSUXSEG6EI16_V_MF2_M1,
24920 0 : 11078 => Opcode::PseudoVSUXSEG6EI16_V_MF2_M1_MASK,
24921 0 : 11079 => Opcode::PseudoVSUXSEG6EI16_V_MF2_MF2,
24922 0 : 11080 => Opcode::PseudoVSUXSEG6EI16_V_MF2_MF2_MASK,
24923 0 : 11081 => Opcode::PseudoVSUXSEG6EI16_V_MF2_MF4,
24924 0 : 11082 => Opcode::PseudoVSUXSEG6EI16_V_MF2_MF4_MASK,
24925 0 : 11083 => Opcode::PseudoVSUXSEG6EI16_V_MF4_M1,
24926 0 : 11084 => Opcode::PseudoVSUXSEG6EI16_V_MF4_M1_MASK,
24927 0 : 11085 => Opcode::PseudoVSUXSEG6EI16_V_MF4_MF2,
24928 0 : 11086 => Opcode::PseudoVSUXSEG6EI16_V_MF4_MF2_MASK,
24929 0 : 11087 => Opcode::PseudoVSUXSEG6EI16_V_MF4_MF4,
24930 0 : 11088 => Opcode::PseudoVSUXSEG6EI16_V_MF4_MF4_MASK,
24931 0 : 11089 => Opcode::PseudoVSUXSEG6EI16_V_MF4_MF8,
24932 0 : 11090 => Opcode::PseudoVSUXSEG6EI16_V_MF4_MF8_MASK,
24933 0 : 11091 => Opcode::PseudoVSUXSEG6EI32_V_M1_M1,
24934 0 : 11092 => Opcode::PseudoVSUXSEG6EI32_V_M1_M1_MASK,
24935 0 : 11093 => Opcode::PseudoVSUXSEG6EI32_V_M1_MF2,
24936 0 : 11094 => Opcode::PseudoVSUXSEG6EI32_V_M1_MF2_MASK,
24937 0 : 11095 => Opcode::PseudoVSUXSEG6EI32_V_M1_MF4,
24938 0 : 11096 => Opcode::PseudoVSUXSEG6EI32_V_M1_MF4_MASK,
24939 0 : 11097 => Opcode::PseudoVSUXSEG6EI32_V_M2_M1,
24940 0 : 11098 => Opcode::PseudoVSUXSEG6EI32_V_M2_M1_MASK,
24941 0 : 11099 => Opcode::PseudoVSUXSEG6EI32_V_M2_MF2,
24942 0 : 11100 => Opcode::PseudoVSUXSEG6EI32_V_M2_MF2_MASK,
24943 0 : 11101 => Opcode::PseudoVSUXSEG6EI32_V_M4_M1,
24944 0 : 11102 => Opcode::PseudoVSUXSEG6EI32_V_M4_M1_MASK,
24945 0 : 11103 => Opcode::PseudoVSUXSEG6EI32_V_MF2_M1,
24946 0 : 11104 => Opcode::PseudoVSUXSEG6EI32_V_MF2_M1_MASK,
24947 0 : 11105 => Opcode::PseudoVSUXSEG6EI32_V_MF2_MF2,
24948 0 : 11106 => Opcode::PseudoVSUXSEG6EI32_V_MF2_MF2_MASK,
24949 0 : 11107 => Opcode::PseudoVSUXSEG6EI32_V_MF2_MF4,
24950 0 : 11108 => Opcode::PseudoVSUXSEG6EI32_V_MF2_MF4_MASK,
24951 0 : 11109 => Opcode::PseudoVSUXSEG6EI32_V_MF2_MF8,
24952 0 : 11110 => Opcode::PseudoVSUXSEG6EI32_V_MF2_MF8_MASK,
24953 0 : 11111 => Opcode::PseudoVSUXSEG6EI64_V_M1_M1,
24954 0 : 11112 => Opcode::PseudoVSUXSEG6EI64_V_M1_M1_MASK,
24955 0 : 11113 => Opcode::PseudoVSUXSEG6EI64_V_M1_MF2,
24956 0 : 11114 => Opcode::PseudoVSUXSEG6EI64_V_M1_MF2_MASK,
24957 0 : 11115 => Opcode::PseudoVSUXSEG6EI64_V_M1_MF4,
24958 0 : 11116 => Opcode::PseudoVSUXSEG6EI64_V_M1_MF4_MASK,
24959 0 : 11117 => Opcode::PseudoVSUXSEG6EI64_V_M1_MF8,
24960 0 : 11118 => Opcode::PseudoVSUXSEG6EI64_V_M1_MF8_MASK,
24961 0 : 11119 => Opcode::PseudoVSUXSEG6EI64_V_M2_M1,
24962 0 : 11120 => Opcode::PseudoVSUXSEG6EI64_V_M2_M1_MASK,
24963 0 : 11121 => Opcode::PseudoVSUXSEG6EI64_V_M2_MF2,
24964 0 : 11122 => Opcode::PseudoVSUXSEG6EI64_V_M2_MF2_MASK,
24965 0 : 11123 => Opcode::PseudoVSUXSEG6EI64_V_M2_MF4,
24966 0 : 11124 => Opcode::PseudoVSUXSEG6EI64_V_M2_MF4_MASK,
24967 0 : 11125 => Opcode::PseudoVSUXSEG6EI64_V_M4_M1,
24968 0 : 11126 => Opcode::PseudoVSUXSEG6EI64_V_M4_M1_MASK,
24969 0 : 11127 => Opcode::PseudoVSUXSEG6EI64_V_M4_MF2,
24970 0 : 11128 => Opcode::PseudoVSUXSEG6EI64_V_M4_MF2_MASK,
24971 0 : 11129 => Opcode::PseudoVSUXSEG6EI64_V_M8_M1,
24972 0 : 11130 => Opcode::PseudoVSUXSEG6EI64_V_M8_M1_MASK,
24973 0 : 11131 => Opcode::PseudoVSUXSEG6EI8_V_M1_M1,
24974 0 : 11132 => Opcode::PseudoVSUXSEG6EI8_V_M1_M1_MASK,
24975 0 : 11133 => Opcode::PseudoVSUXSEG6EI8_V_MF2_M1,
24976 0 : 11134 => Opcode::PseudoVSUXSEG6EI8_V_MF2_M1_MASK,
24977 0 : 11135 => Opcode::PseudoVSUXSEG6EI8_V_MF2_MF2,
24978 0 : 11136 => Opcode::PseudoVSUXSEG6EI8_V_MF2_MF2_MASK,
24979 0 : 11137 => Opcode::PseudoVSUXSEG6EI8_V_MF4_M1,
24980 0 : 11138 => Opcode::PseudoVSUXSEG6EI8_V_MF4_M1_MASK,
24981 0 : 11139 => Opcode::PseudoVSUXSEG6EI8_V_MF4_MF2,
24982 0 : 11140 => Opcode::PseudoVSUXSEG6EI8_V_MF4_MF2_MASK,
24983 0 : 11141 => Opcode::PseudoVSUXSEG6EI8_V_MF4_MF4,
24984 0 : 11142 => Opcode::PseudoVSUXSEG6EI8_V_MF4_MF4_MASK,
24985 0 : 11143 => Opcode::PseudoVSUXSEG6EI8_V_MF8_M1,
24986 0 : 11144 => Opcode::PseudoVSUXSEG6EI8_V_MF8_M1_MASK,
24987 0 : 11145 => Opcode::PseudoVSUXSEG6EI8_V_MF8_MF2,
24988 0 : 11146 => Opcode::PseudoVSUXSEG6EI8_V_MF8_MF2_MASK,
24989 0 : 11147 => Opcode::PseudoVSUXSEG6EI8_V_MF8_MF4,
24990 0 : 11148 => Opcode::PseudoVSUXSEG6EI8_V_MF8_MF4_MASK,
24991 0 : 11149 => Opcode::PseudoVSUXSEG6EI8_V_MF8_MF8,
24992 0 : 11150 => Opcode::PseudoVSUXSEG6EI8_V_MF8_MF8_MASK,
24993 0 : 11151 => Opcode::PseudoVSUXSEG7EI16_V_M1_M1,
24994 0 : 11152 => Opcode::PseudoVSUXSEG7EI16_V_M1_M1_MASK,
24995 0 : 11153 => Opcode::PseudoVSUXSEG7EI16_V_M1_MF2,
24996 0 : 11154 => Opcode::PseudoVSUXSEG7EI16_V_M1_MF2_MASK,
24997 0 : 11155 => Opcode::PseudoVSUXSEG7EI16_V_M2_M1,
24998 0 : 11156 => Opcode::PseudoVSUXSEG7EI16_V_M2_M1_MASK,
24999 0 : 11157 => Opcode::PseudoVSUXSEG7EI16_V_MF2_M1,
25000 0 : 11158 => Opcode::PseudoVSUXSEG7EI16_V_MF2_M1_MASK,
25001 0 : 11159 => Opcode::PseudoVSUXSEG7EI16_V_MF2_MF2,
25002 0 : 11160 => Opcode::PseudoVSUXSEG7EI16_V_MF2_MF2_MASK,
25003 0 : 11161 => Opcode::PseudoVSUXSEG7EI16_V_MF2_MF4,
25004 0 : 11162 => Opcode::PseudoVSUXSEG7EI16_V_MF2_MF4_MASK,
25005 0 : 11163 => Opcode::PseudoVSUXSEG7EI16_V_MF4_M1,
25006 0 : 11164 => Opcode::PseudoVSUXSEG7EI16_V_MF4_M1_MASK,
25007 0 : 11165 => Opcode::PseudoVSUXSEG7EI16_V_MF4_MF2,
25008 0 : 11166 => Opcode::PseudoVSUXSEG7EI16_V_MF4_MF2_MASK,
25009 0 : 11167 => Opcode::PseudoVSUXSEG7EI16_V_MF4_MF4,
25010 0 : 11168 => Opcode::PseudoVSUXSEG7EI16_V_MF4_MF4_MASK,
25011 0 : 11169 => Opcode::PseudoVSUXSEG7EI16_V_MF4_MF8,
25012 0 : 11170 => Opcode::PseudoVSUXSEG7EI16_V_MF4_MF8_MASK,
25013 0 : 11171 => Opcode::PseudoVSUXSEG7EI32_V_M1_M1,
25014 0 : 11172 => Opcode::PseudoVSUXSEG7EI32_V_M1_M1_MASK,
25015 0 : 11173 => Opcode::PseudoVSUXSEG7EI32_V_M1_MF2,
25016 0 : 11174 => Opcode::PseudoVSUXSEG7EI32_V_M1_MF2_MASK,
25017 0 : 11175 => Opcode::PseudoVSUXSEG7EI32_V_M1_MF4,
25018 0 : 11176 => Opcode::PseudoVSUXSEG7EI32_V_M1_MF4_MASK,
25019 0 : 11177 => Opcode::PseudoVSUXSEG7EI32_V_M2_M1,
25020 0 : 11178 => Opcode::PseudoVSUXSEG7EI32_V_M2_M1_MASK,
25021 0 : 11179 => Opcode::PseudoVSUXSEG7EI32_V_M2_MF2,
25022 0 : 11180 => Opcode::PseudoVSUXSEG7EI32_V_M2_MF2_MASK,
25023 0 : 11181 => Opcode::PseudoVSUXSEG7EI32_V_M4_M1,
25024 0 : 11182 => Opcode::PseudoVSUXSEG7EI32_V_M4_M1_MASK,
25025 0 : 11183 => Opcode::PseudoVSUXSEG7EI32_V_MF2_M1,
25026 0 : 11184 => Opcode::PseudoVSUXSEG7EI32_V_MF2_M1_MASK,
25027 0 : 11185 => Opcode::PseudoVSUXSEG7EI32_V_MF2_MF2,
25028 0 : 11186 => Opcode::PseudoVSUXSEG7EI32_V_MF2_MF2_MASK,
25029 0 : 11187 => Opcode::PseudoVSUXSEG7EI32_V_MF2_MF4,
25030 0 : 11188 => Opcode::PseudoVSUXSEG7EI32_V_MF2_MF4_MASK,
25031 0 : 11189 => Opcode::PseudoVSUXSEG7EI32_V_MF2_MF8,
25032 0 : 11190 => Opcode::PseudoVSUXSEG7EI32_V_MF2_MF8_MASK,
25033 0 : 11191 => Opcode::PseudoVSUXSEG7EI64_V_M1_M1,
25034 0 : 11192 => Opcode::PseudoVSUXSEG7EI64_V_M1_M1_MASK,
25035 0 : 11193 => Opcode::PseudoVSUXSEG7EI64_V_M1_MF2,
25036 0 : 11194 => Opcode::PseudoVSUXSEG7EI64_V_M1_MF2_MASK,
25037 0 : 11195 => Opcode::PseudoVSUXSEG7EI64_V_M1_MF4,
25038 0 : 11196 => Opcode::PseudoVSUXSEG7EI64_V_M1_MF4_MASK,
25039 0 : 11197 => Opcode::PseudoVSUXSEG7EI64_V_M1_MF8,
25040 0 : 11198 => Opcode::PseudoVSUXSEG7EI64_V_M1_MF8_MASK,
25041 0 : 11199 => Opcode::PseudoVSUXSEG7EI64_V_M2_M1,
25042 0 : 11200 => Opcode::PseudoVSUXSEG7EI64_V_M2_M1_MASK,
25043 0 : 11201 => Opcode::PseudoVSUXSEG7EI64_V_M2_MF2,
25044 0 : 11202 => Opcode::PseudoVSUXSEG7EI64_V_M2_MF2_MASK,
25045 0 : 11203 => Opcode::PseudoVSUXSEG7EI64_V_M2_MF4,
25046 0 : 11204 => Opcode::PseudoVSUXSEG7EI64_V_M2_MF4_MASK,
25047 0 : 11205 => Opcode::PseudoVSUXSEG7EI64_V_M4_M1,
25048 0 : 11206 => Opcode::PseudoVSUXSEG7EI64_V_M4_M1_MASK,
25049 0 : 11207 => Opcode::PseudoVSUXSEG7EI64_V_M4_MF2,
25050 0 : 11208 => Opcode::PseudoVSUXSEG7EI64_V_M4_MF2_MASK,
25051 0 : 11209 => Opcode::PseudoVSUXSEG7EI64_V_M8_M1,
25052 0 : 11210 => Opcode::PseudoVSUXSEG7EI64_V_M8_M1_MASK,
25053 0 : 11211 => Opcode::PseudoVSUXSEG7EI8_V_M1_M1,
25054 0 : 11212 => Opcode::PseudoVSUXSEG7EI8_V_M1_M1_MASK,
25055 0 : 11213 => Opcode::PseudoVSUXSEG7EI8_V_MF2_M1,
25056 0 : 11214 => Opcode::PseudoVSUXSEG7EI8_V_MF2_M1_MASK,
25057 0 : 11215 => Opcode::PseudoVSUXSEG7EI8_V_MF2_MF2,
25058 0 : 11216 => Opcode::PseudoVSUXSEG7EI8_V_MF2_MF2_MASK,
25059 0 : 11217 => Opcode::PseudoVSUXSEG7EI8_V_MF4_M1,
25060 0 : 11218 => Opcode::PseudoVSUXSEG7EI8_V_MF4_M1_MASK,
25061 0 : 11219 => Opcode::PseudoVSUXSEG7EI8_V_MF4_MF2,
25062 0 : 11220 => Opcode::PseudoVSUXSEG7EI8_V_MF4_MF2_MASK,
25063 0 : 11221 => Opcode::PseudoVSUXSEG7EI8_V_MF4_MF4,
25064 0 : 11222 => Opcode::PseudoVSUXSEG7EI8_V_MF4_MF4_MASK,
25065 0 : 11223 => Opcode::PseudoVSUXSEG7EI8_V_MF8_M1,
25066 0 : 11224 => Opcode::PseudoVSUXSEG7EI8_V_MF8_M1_MASK,
25067 0 : 11225 => Opcode::PseudoVSUXSEG7EI8_V_MF8_MF2,
25068 0 : 11226 => Opcode::PseudoVSUXSEG7EI8_V_MF8_MF2_MASK,
25069 0 : 11227 => Opcode::PseudoVSUXSEG7EI8_V_MF8_MF4,
25070 0 : 11228 => Opcode::PseudoVSUXSEG7EI8_V_MF8_MF4_MASK,
25071 0 : 11229 => Opcode::PseudoVSUXSEG7EI8_V_MF8_MF8,
25072 0 : 11230 => Opcode::PseudoVSUXSEG7EI8_V_MF8_MF8_MASK,
25073 0 : 11231 => Opcode::PseudoVSUXSEG8EI16_V_M1_M1,
25074 0 : 11232 => Opcode::PseudoVSUXSEG8EI16_V_M1_M1_MASK,
25075 0 : 11233 => Opcode::PseudoVSUXSEG8EI16_V_M1_MF2,
25076 0 : 11234 => Opcode::PseudoVSUXSEG8EI16_V_M1_MF2_MASK,
25077 0 : 11235 => Opcode::PseudoVSUXSEG8EI16_V_M2_M1,
25078 0 : 11236 => Opcode::PseudoVSUXSEG8EI16_V_M2_M1_MASK,
25079 0 : 11237 => Opcode::PseudoVSUXSEG8EI16_V_MF2_M1,
25080 0 : 11238 => Opcode::PseudoVSUXSEG8EI16_V_MF2_M1_MASK,
25081 0 : 11239 => Opcode::PseudoVSUXSEG8EI16_V_MF2_MF2,
25082 0 : 11240 => Opcode::PseudoVSUXSEG8EI16_V_MF2_MF2_MASK,
25083 0 : 11241 => Opcode::PseudoVSUXSEG8EI16_V_MF2_MF4,
25084 0 : 11242 => Opcode::PseudoVSUXSEG8EI16_V_MF2_MF4_MASK,
25085 0 : 11243 => Opcode::PseudoVSUXSEG8EI16_V_MF4_M1,
25086 0 : 11244 => Opcode::PseudoVSUXSEG8EI16_V_MF4_M1_MASK,
25087 0 : 11245 => Opcode::PseudoVSUXSEG8EI16_V_MF4_MF2,
25088 0 : 11246 => Opcode::PseudoVSUXSEG8EI16_V_MF4_MF2_MASK,
25089 0 : 11247 => Opcode::PseudoVSUXSEG8EI16_V_MF4_MF4,
25090 0 : 11248 => Opcode::PseudoVSUXSEG8EI16_V_MF4_MF4_MASK,
25091 0 : 11249 => Opcode::PseudoVSUXSEG8EI16_V_MF4_MF8,
25092 0 : 11250 => Opcode::PseudoVSUXSEG8EI16_V_MF4_MF8_MASK,
25093 0 : 11251 => Opcode::PseudoVSUXSEG8EI32_V_M1_M1,
25094 0 : 11252 => Opcode::PseudoVSUXSEG8EI32_V_M1_M1_MASK,
25095 0 : 11253 => Opcode::PseudoVSUXSEG8EI32_V_M1_MF2,
25096 0 : 11254 => Opcode::PseudoVSUXSEG8EI32_V_M1_MF2_MASK,
25097 0 : 11255 => Opcode::PseudoVSUXSEG8EI32_V_M1_MF4,
25098 0 : 11256 => Opcode::PseudoVSUXSEG8EI32_V_M1_MF4_MASK,
25099 0 : 11257 => Opcode::PseudoVSUXSEG8EI32_V_M2_M1,
25100 0 : 11258 => Opcode::PseudoVSUXSEG8EI32_V_M2_M1_MASK,
25101 0 : 11259 => Opcode::PseudoVSUXSEG8EI32_V_M2_MF2,
25102 0 : 11260 => Opcode::PseudoVSUXSEG8EI32_V_M2_MF2_MASK,
25103 0 : 11261 => Opcode::PseudoVSUXSEG8EI32_V_M4_M1,
25104 0 : 11262 => Opcode::PseudoVSUXSEG8EI32_V_M4_M1_MASK,
25105 0 : 11263 => Opcode::PseudoVSUXSEG8EI32_V_MF2_M1,
25106 0 : 11264 => Opcode::PseudoVSUXSEG8EI32_V_MF2_M1_MASK,
25107 0 : 11265 => Opcode::PseudoVSUXSEG8EI32_V_MF2_MF2,
25108 0 : 11266 => Opcode::PseudoVSUXSEG8EI32_V_MF2_MF2_MASK,
25109 0 : 11267 => Opcode::PseudoVSUXSEG8EI32_V_MF2_MF4,
25110 0 : 11268 => Opcode::PseudoVSUXSEG8EI32_V_MF2_MF4_MASK,
25111 0 : 11269 => Opcode::PseudoVSUXSEG8EI32_V_MF2_MF8,
25112 0 : 11270 => Opcode::PseudoVSUXSEG8EI32_V_MF2_MF8_MASK,
25113 0 : 11271 => Opcode::PseudoVSUXSEG8EI64_V_M1_M1,
25114 0 : 11272 => Opcode::PseudoVSUXSEG8EI64_V_M1_M1_MASK,
25115 0 : 11273 => Opcode::PseudoVSUXSEG8EI64_V_M1_MF2,
25116 0 : 11274 => Opcode::PseudoVSUXSEG8EI64_V_M1_MF2_MASK,
25117 0 : 11275 => Opcode::PseudoVSUXSEG8EI64_V_M1_MF4,
25118 0 : 11276 => Opcode::PseudoVSUXSEG8EI64_V_M1_MF4_MASK,
25119 0 : 11277 => Opcode::PseudoVSUXSEG8EI64_V_M1_MF8,
25120 0 : 11278 => Opcode::PseudoVSUXSEG8EI64_V_M1_MF8_MASK,
25121 0 : 11279 => Opcode::PseudoVSUXSEG8EI64_V_M2_M1,
25122 0 : 11280 => Opcode::PseudoVSUXSEG8EI64_V_M2_M1_MASK,
25123 0 : 11281 => Opcode::PseudoVSUXSEG8EI64_V_M2_MF2,
25124 0 : 11282 => Opcode::PseudoVSUXSEG8EI64_V_M2_MF2_MASK,
25125 0 : 11283 => Opcode::PseudoVSUXSEG8EI64_V_M2_MF4,
25126 0 : 11284 => Opcode::PseudoVSUXSEG8EI64_V_M2_MF4_MASK,
25127 0 : 11285 => Opcode::PseudoVSUXSEG8EI64_V_M4_M1,
25128 0 : 11286 => Opcode::PseudoVSUXSEG8EI64_V_M4_M1_MASK,
25129 0 : 11287 => Opcode::PseudoVSUXSEG8EI64_V_M4_MF2,
25130 0 : 11288 => Opcode::PseudoVSUXSEG8EI64_V_M4_MF2_MASK,
25131 0 : 11289 => Opcode::PseudoVSUXSEG8EI64_V_M8_M1,
25132 0 : 11290 => Opcode::PseudoVSUXSEG8EI64_V_M8_M1_MASK,
25133 0 : 11291 => Opcode::PseudoVSUXSEG8EI8_V_M1_M1,
25134 0 : 11292 => Opcode::PseudoVSUXSEG8EI8_V_M1_M1_MASK,
25135 0 : 11293 => Opcode::PseudoVSUXSEG8EI8_V_MF2_M1,
25136 0 : 11294 => Opcode::PseudoVSUXSEG8EI8_V_MF2_M1_MASK,
25137 0 : 11295 => Opcode::PseudoVSUXSEG8EI8_V_MF2_MF2,
25138 0 : 11296 => Opcode::PseudoVSUXSEG8EI8_V_MF2_MF2_MASK,
25139 0 : 11297 => Opcode::PseudoVSUXSEG8EI8_V_MF4_M1,
25140 0 : 11298 => Opcode::PseudoVSUXSEG8EI8_V_MF4_M1_MASK,
25141 0 : 11299 => Opcode::PseudoVSUXSEG8EI8_V_MF4_MF2,
25142 0 : 11300 => Opcode::PseudoVSUXSEG8EI8_V_MF4_MF2_MASK,
25143 0 : 11301 => Opcode::PseudoVSUXSEG8EI8_V_MF4_MF4,
25144 0 : 11302 => Opcode::PseudoVSUXSEG8EI8_V_MF4_MF4_MASK,
25145 0 : 11303 => Opcode::PseudoVSUXSEG8EI8_V_MF8_M1,
25146 0 : 11304 => Opcode::PseudoVSUXSEG8EI8_V_MF8_M1_MASK,
25147 0 : 11305 => Opcode::PseudoVSUXSEG8EI8_V_MF8_MF2,
25148 0 : 11306 => Opcode::PseudoVSUXSEG8EI8_V_MF8_MF2_MASK,
25149 0 : 11307 => Opcode::PseudoVSUXSEG8EI8_V_MF8_MF4,
25150 0 : 11308 => Opcode::PseudoVSUXSEG8EI8_V_MF8_MF4_MASK,
25151 0 : 11309 => Opcode::PseudoVSUXSEG8EI8_V_MF8_MF8,
25152 0 : 11310 => Opcode::PseudoVSUXSEG8EI8_V_MF8_MF8_MASK,
25153 0 : 11311 => Opcode::PseudoVWADDU_VV_M1,
25154 0 : 11312 => Opcode::PseudoVWADDU_VV_M1_MASK,
25155 0 : 11313 => Opcode::PseudoVWADDU_VV_M2,
25156 0 : 11314 => Opcode::PseudoVWADDU_VV_M2_MASK,
25157 0 : 11315 => Opcode::PseudoVWADDU_VV_M4,
25158 0 : 11316 => Opcode::PseudoVWADDU_VV_M4_MASK,
25159 0 : 11317 => Opcode::PseudoVWADDU_VV_MF2,
25160 0 : 11318 => Opcode::PseudoVWADDU_VV_MF2_MASK,
25161 0 : 11319 => Opcode::PseudoVWADDU_VV_MF4,
25162 0 : 11320 => Opcode::PseudoVWADDU_VV_MF4_MASK,
25163 0 : 11321 => Opcode::PseudoVWADDU_VV_MF8,
25164 0 : 11322 => Opcode::PseudoVWADDU_VV_MF8_MASK,
25165 0 : 11323 => Opcode::PseudoVWADDU_VX_M1,
25166 0 : 11324 => Opcode::PseudoVWADDU_VX_M1_MASK,
25167 0 : 11325 => Opcode::PseudoVWADDU_VX_M2,
25168 0 : 11326 => Opcode::PseudoVWADDU_VX_M2_MASK,
25169 0 : 11327 => Opcode::PseudoVWADDU_VX_M4,
25170 0 : 11328 => Opcode::PseudoVWADDU_VX_M4_MASK,
25171 0 : 11329 => Opcode::PseudoVWADDU_VX_MF2,
25172 0 : 11330 => Opcode::PseudoVWADDU_VX_MF2_MASK,
25173 0 : 11331 => Opcode::PseudoVWADDU_VX_MF4,
25174 0 : 11332 => Opcode::PseudoVWADDU_VX_MF4_MASK,
25175 0 : 11333 => Opcode::PseudoVWADDU_VX_MF8,
25176 0 : 11334 => Opcode::PseudoVWADDU_VX_MF8_MASK,
25177 0 : 11335 => Opcode::PseudoVWADDU_WV_M1,
25178 0 : 11336 => Opcode::PseudoVWADDU_WV_M1_MASK,
25179 0 : 11337 => Opcode::PseudoVWADDU_WV_M1_MASK_TIED,
25180 0 : 11338 => Opcode::PseudoVWADDU_WV_M1_TIED,
25181 0 : 11339 => Opcode::PseudoVWADDU_WV_M2,
25182 0 : 11340 => Opcode::PseudoVWADDU_WV_M2_MASK,
25183 0 : 11341 => Opcode::PseudoVWADDU_WV_M2_MASK_TIED,
25184 0 : 11342 => Opcode::PseudoVWADDU_WV_M2_TIED,
25185 0 : 11343 => Opcode::PseudoVWADDU_WV_M4,
25186 0 : 11344 => Opcode::PseudoVWADDU_WV_M4_MASK,
25187 0 : 11345 => Opcode::PseudoVWADDU_WV_M4_MASK_TIED,
25188 0 : 11346 => Opcode::PseudoVWADDU_WV_M4_TIED,
25189 0 : 11347 => Opcode::PseudoVWADDU_WV_MF2,
25190 0 : 11348 => Opcode::PseudoVWADDU_WV_MF2_MASK,
25191 0 : 11349 => Opcode::PseudoVWADDU_WV_MF2_MASK_TIED,
25192 0 : 11350 => Opcode::PseudoVWADDU_WV_MF2_TIED,
25193 0 : 11351 => Opcode::PseudoVWADDU_WV_MF4,
25194 0 : 11352 => Opcode::PseudoVWADDU_WV_MF4_MASK,
25195 0 : 11353 => Opcode::PseudoVWADDU_WV_MF4_MASK_TIED,
25196 0 : 11354 => Opcode::PseudoVWADDU_WV_MF4_TIED,
25197 0 : 11355 => Opcode::PseudoVWADDU_WV_MF8,
25198 0 : 11356 => Opcode::PseudoVWADDU_WV_MF8_MASK,
25199 0 : 11357 => Opcode::PseudoVWADDU_WV_MF8_MASK_TIED,
25200 0 : 11358 => Opcode::PseudoVWADDU_WV_MF8_TIED,
25201 0 : 11359 => Opcode::PseudoVWADDU_WX_M1,
25202 0 : 11360 => Opcode::PseudoVWADDU_WX_M1_MASK,
25203 0 : 11361 => Opcode::PseudoVWADDU_WX_M2,
25204 0 : 11362 => Opcode::PseudoVWADDU_WX_M2_MASK,
25205 0 : 11363 => Opcode::PseudoVWADDU_WX_M4,
25206 0 : 11364 => Opcode::PseudoVWADDU_WX_M4_MASK,
25207 0 : 11365 => Opcode::PseudoVWADDU_WX_MF2,
25208 0 : 11366 => Opcode::PseudoVWADDU_WX_MF2_MASK,
25209 0 : 11367 => Opcode::PseudoVWADDU_WX_MF4,
25210 0 : 11368 => Opcode::PseudoVWADDU_WX_MF4_MASK,
25211 0 : 11369 => Opcode::PseudoVWADDU_WX_MF8,
25212 0 : 11370 => Opcode::PseudoVWADDU_WX_MF8_MASK,
25213 0 : 11371 => Opcode::PseudoVWADD_VV_M1,
25214 0 : 11372 => Opcode::PseudoVWADD_VV_M1_MASK,
25215 0 : 11373 => Opcode::PseudoVWADD_VV_M2,
25216 0 : 11374 => Opcode::PseudoVWADD_VV_M2_MASK,
25217 0 : 11375 => Opcode::PseudoVWADD_VV_M4,
25218 0 : 11376 => Opcode::PseudoVWADD_VV_M4_MASK,
25219 0 : 11377 => Opcode::PseudoVWADD_VV_MF2,
25220 0 : 11378 => Opcode::PseudoVWADD_VV_MF2_MASK,
25221 0 : 11379 => Opcode::PseudoVWADD_VV_MF4,
25222 0 : 11380 => Opcode::PseudoVWADD_VV_MF4_MASK,
25223 0 : 11381 => Opcode::PseudoVWADD_VV_MF8,
25224 0 : 11382 => Opcode::PseudoVWADD_VV_MF8_MASK,
25225 0 : 11383 => Opcode::PseudoVWADD_VX_M1,
25226 0 : 11384 => Opcode::PseudoVWADD_VX_M1_MASK,
25227 0 : 11385 => Opcode::PseudoVWADD_VX_M2,
25228 0 : 11386 => Opcode::PseudoVWADD_VX_M2_MASK,
25229 0 : 11387 => Opcode::PseudoVWADD_VX_M4,
25230 0 : 11388 => Opcode::PseudoVWADD_VX_M4_MASK,
25231 0 : 11389 => Opcode::PseudoVWADD_VX_MF2,
25232 0 : 11390 => Opcode::PseudoVWADD_VX_MF2_MASK,
25233 0 : 11391 => Opcode::PseudoVWADD_VX_MF4,
25234 0 : 11392 => Opcode::PseudoVWADD_VX_MF4_MASK,
25235 0 : 11393 => Opcode::PseudoVWADD_VX_MF8,
25236 0 : 11394 => Opcode::PseudoVWADD_VX_MF8_MASK,
25237 0 : 11395 => Opcode::PseudoVWADD_WV_M1,
25238 0 : 11396 => Opcode::PseudoVWADD_WV_M1_MASK,
25239 0 : 11397 => Opcode::PseudoVWADD_WV_M1_MASK_TIED,
25240 0 : 11398 => Opcode::PseudoVWADD_WV_M1_TIED,
25241 0 : 11399 => Opcode::PseudoVWADD_WV_M2,
25242 0 : 11400 => Opcode::PseudoVWADD_WV_M2_MASK,
25243 0 : 11401 => Opcode::PseudoVWADD_WV_M2_MASK_TIED,
25244 0 : 11402 => Opcode::PseudoVWADD_WV_M2_TIED,
25245 0 : 11403 => Opcode::PseudoVWADD_WV_M4,
25246 0 : 11404 => Opcode::PseudoVWADD_WV_M4_MASK,
25247 0 : 11405 => Opcode::PseudoVWADD_WV_M4_MASK_TIED,
25248 0 : 11406 => Opcode::PseudoVWADD_WV_M4_TIED,
25249 0 : 11407 => Opcode::PseudoVWADD_WV_MF2,
25250 0 : 11408 => Opcode::PseudoVWADD_WV_MF2_MASK,
25251 0 : 11409 => Opcode::PseudoVWADD_WV_MF2_MASK_TIED,
25252 0 : 11410 => Opcode::PseudoVWADD_WV_MF2_TIED,
25253 0 : 11411 => Opcode::PseudoVWADD_WV_MF4,
25254 0 : 11412 => Opcode::PseudoVWADD_WV_MF4_MASK,
25255 0 : 11413 => Opcode::PseudoVWADD_WV_MF4_MASK_TIED,
25256 0 : 11414 => Opcode::PseudoVWADD_WV_MF4_TIED,
25257 0 : 11415 => Opcode::PseudoVWADD_WV_MF8,
25258 0 : 11416 => Opcode::PseudoVWADD_WV_MF8_MASK,
25259 0 : 11417 => Opcode::PseudoVWADD_WV_MF8_MASK_TIED,
25260 0 : 11418 => Opcode::PseudoVWADD_WV_MF8_TIED,
25261 0 : 11419 => Opcode::PseudoVWADD_WX_M1,
25262 0 : 11420 => Opcode::PseudoVWADD_WX_M1_MASK,
25263 0 : 11421 => Opcode::PseudoVWADD_WX_M2,
25264 0 : 11422 => Opcode::PseudoVWADD_WX_M2_MASK,
25265 0 : 11423 => Opcode::PseudoVWADD_WX_M4,
25266 0 : 11424 => Opcode::PseudoVWADD_WX_M4_MASK,
25267 0 : 11425 => Opcode::PseudoVWADD_WX_MF2,
25268 0 : 11426 => Opcode::PseudoVWADD_WX_MF2_MASK,
25269 0 : 11427 => Opcode::PseudoVWADD_WX_MF4,
25270 0 : 11428 => Opcode::PseudoVWADD_WX_MF4_MASK,
25271 0 : 11429 => Opcode::PseudoVWADD_WX_MF8,
25272 0 : 11430 => Opcode::PseudoVWADD_WX_MF8_MASK,
25273 0 : 11431 => Opcode::PseudoVWMACCSU_VV_M1,
25274 0 : 11432 => Opcode::PseudoVWMACCSU_VV_M1_MASK,
25275 0 : 11433 => Opcode::PseudoVWMACCSU_VV_M2,
25276 0 : 11434 => Opcode::PseudoVWMACCSU_VV_M2_MASK,
25277 0 : 11435 => Opcode::PseudoVWMACCSU_VV_M4,
25278 0 : 11436 => Opcode::PseudoVWMACCSU_VV_M4_MASK,
25279 0 : 11437 => Opcode::PseudoVWMACCSU_VV_MF2,
25280 0 : 11438 => Opcode::PseudoVWMACCSU_VV_MF2_MASK,
25281 0 : 11439 => Opcode::PseudoVWMACCSU_VV_MF4,
25282 0 : 11440 => Opcode::PseudoVWMACCSU_VV_MF4_MASK,
25283 0 : 11441 => Opcode::PseudoVWMACCSU_VV_MF8,
25284 0 : 11442 => Opcode::PseudoVWMACCSU_VV_MF8_MASK,
25285 0 : 11443 => Opcode::PseudoVWMACCSU_VX_M1,
25286 0 : 11444 => Opcode::PseudoVWMACCSU_VX_M1_MASK,
25287 0 : 11445 => Opcode::PseudoVWMACCSU_VX_M2,
25288 0 : 11446 => Opcode::PseudoVWMACCSU_VX_M2_MASK,
25289 0 : 11447 => Opcode::PseudoVWMACCSU_VX_M4,
25290 0 : 11448 => Opcode::PseudoVWMACCSU_VX_M4_MASK,
25291 0 : 11449 => Opcode::PseudoVWMACCSU_VX_MF2,
25292 0 : 11450 => Opcode::PseudoVWMACCSU_VX_MF2_MASK,
25293 0 : 11451 => Opcode::PseudoVWMACCSU_VX_MF4,
25294 0 : 11452 => Opcode::PseudoVWMACCSU_VX_MF4_MASK,
25295 0 : 11453 => Opcode::PseudoVWMACCSU_VX_MF8,
25296 0 : 11454 => Opcode::PseudoVWMACCSU_VX_MF8_MASK,
25297 0 : 11455 => Opcode::PseudoVWMACCUS_VX_M1,
25298 0 : 11456 => Opcode::PseudoVWMACCUS_VX_M1_MASK,
25299 0 : 11457 => Opcode::PseudoVWMACCUS_VX_M2,
25300 0 : 11458 => Opcode::PseudoVWMACCUS_VX_M2_MASK,
25301 0 : 11459 => Opcode::PseudoVWMACCUS_VX_M4,
25302 0 : 11460 => Opcode::PseudoVWMACCUS_VX_M4_MASK,
25303 0 : 11461 => Opcode::PseudoVWMACCUS_VX_MF2,
25304 0 : 11462 => Opcode::PseudoVWMACCUS_VX_MF2_MASK,
25305 0 : 11463 => Opcode::PseudoVWMACCUS_VX_MF4,
25306 0 : 11464 => Opcode::PseudoVWMACCUS_VX_MF4_MASK,
25307 0 : 11465 => Opcode::PseudoVWMACCUS_VX_MF8,
25308 0 : 11466 => Opcode::PseudoVWMACCUS_VX_MF8_MASK,
25309 0 : 11467 => Opcode::PseudoVWMACCU_VV_M1,
25310 0 : 11468 => Opcode::PseudoVWMACCU_VV_M1_MASK,
25311 0 : 11469 => Opcode::PseudoVWMACCU_VV_M2,
25312 0 : 11470 => Opcode::PseudoVWMACCU_VV_M2_MASK,
25313 0 : 11471 => Opcode::PseudoVWMACCU_VV_M4,
25314 0 : 11472 => Opcode::PseudoVWMACCU_VV_M4_MASK,
25315 0 : 11473 => Opcode::PseudoVWMACCU_VV_MF2,
25316 0 : 11474 => Opcode::PseudoVWMACCU_VV_MF2_MASK,
25317 0 : 11475 => Opcode::PseudoVWMACCU_VV_MF4,
25318 0 : 11476 => Opcode::PseudoVWMACCU_VV_MF4_MASK,
25319 0 : 11477 => Opcode::PseudoVWMACCU_VV_MF8,
25320 0 : 11478 => Opcode::PseudoVWMACCU_VV_MF8_MASK,
25321 0 : 11479 => Opcode::PseudoVWMACCU_VX_M1,
25322 0 : 11480 => Opcode::PseudoVWMACCU_VX_M1_MASK,
25323 0 : 11481 => Opcode::PseudoVWMACCU_VX_M2,
25324 0 : 11482 => Opcode::PseudoVWMACCU_VX_M2_MASK,
25325 0 : 11483 => Opcode::PseudoVWMACCU_VX_M4,
25326 0 : 11484 => Opcode::PseudoVWMACCU_VX_M4_MASK,
25327 0 : 11485 => Opcode::PseudoVWMACCU_VX_MF2,
25328 0 : 11486 => Opcode::PseudoVWMACCU_VX_MF2_MASK,
25329 0 : 11487 => Opcode::PseudoVWMACCU_VX_MF4,
25330 0 : 11488 => Opcode::PseudoVWMACCU_VX_MF4_MASK,
25331 0 : 11489 => Opcode::PseudoVWMACCU_VX_MF8,
25332 0 : 11490 => Opcode::PseudoVWMACCU_VX_MF8_MASK,
25333 0 : 11491 => Opcode::PseudoVWMACC_VV_M1,
25334 0 : 11492 => Opcode::PseudoVWMACC_VV_M1_MASK,
25335 0 : 11493 => Opcode::PseudoVWMACC_VV_M2,
25336 0 : 11494 => Opcode::PseudoVWMACC_VV_M2_MASK,
25337 0 : 11495 => Opcode::PseudoVWMACC_VV_M4,
25338 0 : 11496 => Opcode::PseudoVWMACC_VV_M4_MASK,
25339 0 : 11497 => Opcode::PseudoVWMACC_VV_MF2,
25340 0 : 11498 => Opcode::PseudoVWMACC_VV_MF2_MASK,
25341 0 : 11499 => Opcode::PseudoVWMACC_VV_MF4,
25342 0 : 11500 => Opcode::PseudoVWMACC_VV_MF4_MASK,
25343 0 : 11501 => Opcode::PseudoVWMACC_VV_MF8,
25344 0 : 11502 => Opcode::PseudoVWMACC_VV_MF8_MASK,
25345 0 : 11503 => Opcode::PseudoVWMACC_VX_M1,
25346 0 : 11504 => Opcode::PseudoVWMACC_VX_M1_MASK,
25347 0 : 11505 => Opcode::PseudoVWMACC_VX_M2,
25348 0 : 11506 => Opcode::PseudoVWMACC_VX_M2_MASK,
25349 0 : 11507 => Opcode::PseudoVWMACC_VX_M4,
25350 0 : 11508 => Opcode::PseudoVWMACC_VX_M4_MASK,
25351 0 : 11509 => Opcode::PseudoVWMACC_VX_MF2,
25352 0 : 11510 => Opcode::PseudoVWMACC_VX_MF2_MASK,
25353 0 : 11511 => Opcode::PseudoVWMACC_VX_MF4,
25354 0 : 11512 => Opcode::PseudoVWMACC_VX_MF4_MASK,
25355 0 : 11513 => Opcode::PseudoVWMACC_VX_MF8,
25356 0 : 11514 => Opcode::PseudoVWMACC_VX_MF8_MASK,
25357 0 : 11515 => Opcode::PseudoVWMULSU_VV_M1,
25358 0 : 11516 => Opcode::PseudoVWMULSU_VV_M1_MASK,
25359 0 : 11517 => Opcode::PseudoVWMULSU_VV_M2,
25360 0 : 11518 => Opcode::PseudoVWMULSU_VV_M2_MASK,
25361 0 : 11519 => Opcode::PseudoVWMULSU_VV_M4,
25362 0 : 11520 => Opcode::PseudoVWMULSU_VV_M4_MASK,
25363 0 : 11521 => Opcode::PseudoVWMULSU_VV_MF2,
25364 0 : 11522 => Opcode::PseudoVWMULSU_VV_MF2_MASK,
25365 0 : 11523 => Opcode::PseudoVWMULSU_VV_MF4,
25366 0 : 11524 => Opcode::PseudoVWMULSU_VV_MF4_MASK,
25367 0 : 11525 => Opcode::PseudoVWMULSU_VV_MF8,
25368 0 : 11526 => Opcode::PseudoVWMULSU_VV_MF8_MASK,
25369 0 : 11527 => Opcode::PseudoVWMULSU_VX_M1,
25370 0 : 11528 => Opcode::PseudoVWMULSU_VX_M1_MASK,
25371 0 : 11529 => Opcode::PseudoVWMULSU_VX_M2,
25372 0 : 11530 => Opcode::PseudoVWMULSU_VX_M2_MASK,
25373 0 : 11531 => Opcode::PseudoVWMULSU_VX_M4,
25374 0 : 11532 => Opcode::PseudoVWMULSU_VX_M4_MASK,
25375 0 : 11533 => Opcode::PseudoVWMULSU_VX_MF2,
25376 0 : 11534 => Opcode::PseudoVWMULSU_VX_MF2_MASK,
25377 0 : 11535 => Opcode::PseudoVWMULSU_VX_MF4,
25378 0 : 11536 => Opcode::PseudoVWMULSU_VX_MF4_MASK,
25379 0 : 11537 => Opcode::PseudoVWMULSU_VX_MF8,
25380 0 : 11538 => Opcode::PseudoVWMULSU_VX_MF8_MASK,
25381 0 : 11539 => Opcode::PseudoVWMULU_VV_M1,
25382 0 : 11540 => Opcode::PseudoVWMULU_VV_M1_MASK,
25383 0 : 11541 => Opcode::PseudoVWMULU_VV_M2,
25384 0 : 11542 => Opcode::PseudoVWMULU_VV_M2_MASK,
25385 0 : 11543 => Opcode::PseudoVWMULU_VV_M4,
25386 0 : 11544 => Opcode::PseudoVWMULU_VV_M4_MASK,
25387 0 : 11545 => Opcode::PseudoVWMULU_VV_MF2,
25388 0 : 11546 => Opcode::PseudoVWMULU_VV_MF2_MASK,
25389 0 : 11547 => Opcode::PseudoVWMULU_VV_MF4,
25390 0 : 11548 => Opcode::PseudoVWMULU_VV_MF4_MASK,
25391 0 : 11549 => Opcode::PseudoVWMULU_VV_MF8,
25392 0 : 11550 => Opcode::PseudoVWMULU_VV_MF8_MASK,
25393 0 : 11551 => Opcode::PseudoVWMULU_VX_M1,
25394 0 : 11552 => Opcode::PseudoVWMULU_VX_M1_MASK,
25395 0 : 11553 => Opcode::PseudoVWMULU_VX_M2,
25396 0 : 11554 => Opcode::PseudoVWMULU_VX_M2_MASK,
25397 0 : 11555 => Opcode::PseudoVWMULU_VX_M4,
25398 0 : 11556 => Opcode::PseudoVWMULU_VX_M4_MASK,
25399 0 : 11557 => Opcode::PseudoVWMULU_VX_MF2,
25400 0 : 11558 => Opcode::PseudoVWMULU_VX_MF2_MASK,
25401 0 : 11559 => Opcode::PseudoVWMULU_VX_MF4,
25402 0 : 11560 => Opcode::PseudoVWMULU_VX_MF4_MASK,
25403 0 : 11561 => Opcode::PseudoVWMULU_VX_MF8,
25404 0 : 11562 => Opcode::PseudoVWMULU_VX_MF8_MASK,
25405 0 : 11563 => Opcode::PseudoVWMUL_VV_M1,
25406 0 : 11564 => Opcode::PseudoVWMUL_VV_M1_MASK,
25407 0 : 11565 => Opcode::PseudoVWMUL_VV_M2,
25408 0 : 11566 => Opcode::PseudoVWMUL_VV_M2_MASK,
25409 0 : 11567 => Opcode::PseudoVWMUL_VV_M4,
25410 0 : 11568 => Opcode::PseudoVWMUL_VV_M4_MASK,
25411 0 : 11569 => Opcode::PseudoVWMUL_VV_MF2,
25412 0 : 11570 => Opcode::PseudoVWMUL_VV_MF2_MASK,
25413 0 : 11571 => Opcode::PseudoVWMUL_VV_MF4,
25414 0 : 11572 => Opcode::PseudoVWMUL_VV_MF4_MASK,
25415 0 : 11573 => Opcode::PseudoVWMUL_VV_MF8,
25416 0 : 11574 => Opcode::PseudoVWMUL_VV_MF8_MASK,
25417 0 : 11575 => Opcode::PseudoVWMUL_VX_M1,
25418 0 : 11576 => Opcode::PseudoVWMUL_VX_M1_MASK,
25419 0 : 11577 => Opcode::PseudoVWMUL_VX_M2,
25420 0 : 11578 => Opcode::PseudoVWMUL_VX_M2_MASK,
25421 0 : 11579 => Opcode::PseudoVWMUL_VX_M4,
25422 0 : 11580 => Opcode::PseudoVWMUL_VX_M4_MASK,
25423 0 : 11581 => Opcode::PseudoVWMUL_VX_MF2,
25424 0 : 11582 => Opcode::PseudoVWMUL_VX_MF2_MASK,
25425 0 : 11583 => Opcode::PseudoVWMUL_VX_MF4,
25426 0 : 11584 => Opcode::PseudoVWMUL_VX_MF4_MASK,
25427 0 : 11585 => Opcode::PseudoVWMUL_VX_MF8,
25428 0 : 11586 => Opcode::PseudoVWMUL_VX_MF8_MASK,
25429 0 : 11587 => Opcode::PseudoVWREDSUMU_VS_M1_E16,
25430 0 : 11588 => Opcode::PseudoVWREDSUMU_VS_M1_E16_MASK,
25431 0 : 11589 => Opcode::PseudoVWREDSUMU_VS_M1_E32,
25432 0 : 11590 => Opcode::PseudoVWREDSUMU_VS_M1_E32_MASK,
25433 0 : 11591 => Opcode::PseudoVWREDSUMU_VS_M1_E8,
25434 0 : 11592 => Opcode::PseudoVWREDSUMU_VS_M1_E8_MASK,
25435 0 : 11593 => Opcode::PseudoVWREDSUMU_VS_M2_E16,
25436 0 : 11594 => Opcode::PseudoVWREDSUMU_VS_M2_E16_MASK,
25437 0 : 11595 => Opcode::PseudoVWREDSUMU_VS_M2_E32,
25438 0 : 11596 => Opcode::PseudoVWREDSUMU_VS_M2_E32_MASK,
25439 0 : 11597 => Opcode::PseudoVWREDSUMU_VS_M2_E8,
25440 0 : 11598 => Opcode::PseudoVWREDSUMU_VS_M2_E8_MASK,
25441 0 : 11599 => Opcode::PseudoVWREDSUMU_VS_M4_E16,
25442 0 : 11600 => Opcode::PseudoVWREDSUMU_VS_M4_E16_MASK,
25443 0 : 11601 => Opcode::PseudoVWREDSUMU_VS_M4_E32,
25444 0 : 11602 => Opcode::PseudoVWREDSUMU_VS_M4_E32_MASK,
25445 0 : 11603 => Opcode::PseudoVWREDSUMU_VS_M4_E8,
25446 0 : 11604 => Opcode::PseudoVWREDSUMU_VS_M4_E8_MASK,
25447 0 : 11605 => Opcode::PseudoVWREDSUMU_VS_M8_E16,
25448 0 : 11606 => Opcode::PseudoVWREDSUMU_VS_M8_E16_MASK,
25449 0 : 11607 => Opcode::PseudoVWREDSUMU_VS_M8_E32,
25450 0 : 11608 => Opcode::PseudoVWREDSUMU_VS_M8_E32_MASK,
25451 0 : 11609 => Opcode::PseudoVWREDSUMU_VS_M8_E8,
25452 0 : 11610 => Opcode::PseudoVWREDSUMU_VS_M8_E8_MASK,
25453 0 : 11611 => Opcode::PseudoVWREDSUMU_VS_MF2_E16,
25454 0 : 11612 => Opcode::PseudoVWREDSUMU_VS_MF2_E16_MASK,
25455 0 : 11613 => Opcode::PseudoVWREDSUMU_VS_MF2_E32,
25456 0 : 11614 => Opcode::PseudoVWREDSUMU_VS_MF2_E32_MASK,
25457 0 : 11615 => Opcode::PseudoVWREDSUMU_VS_MF2_E8,
25458 0 : 11616 => Opcode::PseudoVWREDSUMU_VS_MF2_E8_MASK,
25459 0 : 11617 => Opcode::PseudoVWREDSUMU_VS_MF4_E16,
25460 0 : 11618 => Opcode::PseudoVWREDSUMU_VS_MF4_E16_MASK,
25461 0 : 11619 => Opcode::PseudoVWREDSUMU_VS_MF4_E8,
25462 0 : 11620 => Opcode::PseudoVWREDSUMU_VS_MF4_E8_MASK,
25463 0 : 11621 => Opcode::PseudoVWREDSUMU_VS_MF8_E8,
25464 0 : 11622 => Opcode::PseudoVWREDSUMU_VS_MF8_E8_MASK,
25465 0 : 11623 => Opcode::PseudoVWREDSUM_VS_M1_E16,
25466 0 : 11624 => Opcode::PseudoVWREDSUM_VS_M1_E16_MASK,
25467 0 : 11625 => Opcode::PseudoVWREDSUM_VS_M1_E32,
25468 0 : 11626 => Opcode::PseudoVWREDSUM_VS_M1_E32_MASK,
25469 0 : 11627 => Opcode::PseudoVWREDSUM_VS_M1_E8,
25470 0 : 11628 => Opcode::PseudoVWREDSUM_VS_M1_E8_MASK,
25471 0 : 11629 => Opcode::PseudoVWREDSUM_VS_M2_E16,
25472 0 : 11630 => Opcode::PseudoVWREDSUM_VS_M2_E16_MASK,
25473 0 : 11631 => Opcode::PseudoVWREDSUM_VS_M2_E32,
25474 0 : 11632 => Opcode::PseudoVWREDSUM_VS_M2_E32_MASK,
25475 0 : 11633 => Opcode::PseudoVWREDSUM_VS_M2_E8,
25476 0 : 11634 => Opcode::PseudoVWREDSUM_VS_M2_E8_MASK,
25477 0 : 11635 => Opcode::PseudoVWREDSUM_VS_M4_E16,
25478 0 : 11636 => Opcode::PseudoVWREDSUM_VS_M4_E16_MASK,
25479 0 : 11637 => Opcode::PseudoVWREDSUM_VS_M4_E32,
25480 0 : 11638 => Opcode::PseudoVWREDSUM_VS_M4_E32_MASK,
25481 0 : 11639 => Opcode::PseudoVWREDSUM_VS_M4_E8,
25482 0 : 11640 => Opcode::PseudoVWREDSUM_VS_M4_E8_MASK,
25483 0 : 11641 => Opcode::PseudoVWREDSUM_VS_M8_E16,
25484 0 : 11642 => Opcode::PseudoVWREDSUM_VS_M8_E16_MASK,
25485 0 : 11643 => Opcode::PseudoVWREDSUM_VS_M8_E32,
25486 0 : 11644 => Opcode::PseudoVWREDSUM_VS_M8_E32_MASK,
25487 0 : 11645 => Opcode::PseudoVWREDSUM_VS_M8_E8,
25488 0 : 11646 => Opcode::PseudoVWREDSUM_VS_M8_E8_MASK,
25489 0 : 11647 => Opcode::PseudoVWREDSUM_VS_MF2_E16,
25490 0 : 11648 => Opcode::PseudoVWREDSUM_VS_MF2_E16_MASK,
25491 0 : 11649 => Opcode::PseudoVWREDSUM_VS_MF2_E32,
25492 0 : 11650 => Opcode::PseudoVWREDSUM_VS_MF2_E32_MASK,
25493 0 : 11651 => Opcode::PseudoVWREDSUM_VS_MF2_E8,
25494 0 : 11652 => Opcode::PseudoVWREDSUM_VS_MF2_E8_MASK,
25495 0 : 11653 => Opcode::PseudoVWREDSUM_VS_MF4_E16,
25496 0 : 11654 => Opcode::PseudoVWREDSUM_VS_MF4_E16_MASK,
25497 0 : 11655 => Opcode::PseudoVWREDSUM_VS_MF4_E8,
25498 0 : 11656 => Opcode::PseudoVWREDSUM_VS_MF4_E8_MASK,
25499 0 : 11657 => Opcode::PseudoVWREDSUM_VS_MF8_E8,
25500 0 : 11658 => Opcode::PseudoVWREDSUM_VS_MF8_E8_MASK,
25501 0 : 11659 => Opcode::PseudoVWSLL_VI_M1,
25502 0 : 11660 => Opcode::PseudoVWSLL_VI_M1_MASK,
25503 0 : 11661 => Opcode::PseudoVWSLL_VI_M2,
25504 0 : 11662 => Opcode::PseudoVWSLL_VI_M2_MASK,
25505 0 : 11663 => Opcode::PseudoVWSLL_VI_M4,
25506 0 : 11664 => Opcode::PseudoVWSLL_VI_M4_MASK,
25507 0 : 11665 => Opcode::PseudoVWSLL_VI_MF2,
25508 0 : 11666 => Opcode::PseudoVWSLL_VI_MF2_MASK,
25509 0 : 11667 => Opcode::PseudoVWSLL_VI_MF4,
25510 0 : 11668 => Opcode::PseudoVWSLL_VI_MF4_MASK,
25511 0 : 11669 => Opcode::PseudoVWSLL_VI_MF8,
25512 0 : 11670 => Opcode::PseudoVWSLL_VI_MF8_MASK,
25513 0 : 11671 => Opcode::PseudoVWSLL_VV_M1,
25514 0 : 11672 => Opcode::PseudoVWSLL_VV_M1_MASK,
25515 0 : 11673 => Opcode::PseudoVWSLL_VV_M2,
25516 0 : 11674 => Opcode::PseudoVWSLL_VV_M2_MASK,
25517 0 : 11675 => Opcode::PseudoVWSLL_VV_M4,
25518 0 : 11676 => Opcode::PseudoVWSLL_VV_M4_MASK,
25519 0 : 11677 => Opcode::PseudoVWSLL_VV_MF2,
25520 0 : 11678 => Opcode::PseudoVWSLL_VV_MF2_MASK,
25521 0 : 11679 => Opcode::PseudoVWSLL_VV_MF4,
25522 0 : 11680 => Opcode::PseudoVWSLL_VV_MF4_MASK,
25523 0 : 11681 => Opcode::PseudoVWSLL_VV_MF8,
25524 0 : 11682 => Opcode::PseudoVWSLL_VV_MF8_MASK,
25525 0 : 11683 => Opcode::PseudoVWSLL_VX_M1,
25526 0 : 11684 => Opcode::PseudoVWSLL_VX_M1_MASK,
25527 0 : 11685 => Opcode::PseudoVWSLL_VX_M2,
25528 0 : 11686 => Opcode::PseudoVWSLL_VX_M2_MASK,
25529 0 : 11687 => Opcode::PseudoVWSLL_VX_M4,
25530 0 : 11688 => Opcode::PseudoVWSLL_VX_M4_MASK,
25531 0 : 11689 => Opcode::PseudoVWSLL_VX_MF2,
25532 0 : 11690 => Opcode::PseudoVWSLL_VX_MF2_MASK,
25533 0 : 11691 => Opcode::PseudoVWSLL_VX_MF4,
25534 0 : 11692 => Opcode::PseudoVWSLL_VX_MF4_MASK,
25535 0 : 11693 => Opcode::PseudoVWSLL_VX_MF8,
25536 0 : 11694 => Opcode::PseudoVWSLL_VX_MF8_MASK,
25537 0 : 11695 => Opcode::PseudoVWSUBU_VV_M1,
25538 0 : 11696 => Opcode::PseudoVWSUBU_VV_M1_MASK,
25539 0 : 11697 => Opcode::PseudoVWSUBU_VV_M2,
25540 0 : 11698 => Opcode::PseudoVWSUBU_VV_M2_MASK,
25541 0 : 11699 => Opcode::PseudoVWSUBU_VV_M4,
25542 0 : 11700 => Opcode::PseudoVWSUBU_VV_M4_MASK,
25543 0 : 11701 => Opcode::PseudoVWSUBU_VV_MF2,
25544 0 : 11702 => Opcode::PseudoVWSUBU_VV_MF2_MASK,
25545 0 : 11703 => Opcode::PseudoVWSUBU_VV_MF4,
25546 0 : 11704 => Opcode::PseudoVWSUBU_VV_MF4_MASK,
25547 0 : 11705 => Opcode::PseudoVWSUBU_VV_MF8,
25548 0 : 11706 => Opcode::PseudoVWSUBU_VV_MF8_MASK,
25549 0 : 11707 => Opcode::PseudoVWSUBU_VX_M1,
25550 0 : 11708 => Opcode::PseudoVWSUBU_VX_M1_MASK,
25551 0 : 11709 => Opcode::PseudoVWSUBU_VX_M2,
25552 0 : 11710 => Opcode::PseudoVWSUBU_VX_M2_MASK,
25553 0 : 11711 => Opcode::PseudoVWSUBU_VX_M4,
25554 0 : 11712 => Opcode::PseudoVWSUBU_VX_M4_MASK,
25555 0 : 11713 => Opcode::PseudoVWSUBU_VX_MF2,
25556 0 : 11714 => Opcode::PseudoVWSUBU_VX_MF2_MASK,
25557 0 : 11715 => Opcode::PseudoVWSUBU_VX_MF4,
25558 0 : 11716 => Opcode::PseudoVWSUBU_VX_MF4_MASK,
25559 0 : 11717 => Opcode::PseudoVWSUBU_VX_MF8,
25560 0 : 11718 => Opcode::PseudoVWSUBU_VX_MF8_MASK,
25561 0 : 11719 => Opcode::PseudoVWSUBU_WV_M1,
25562 0 : 11720 => Opcode::PseudoVWSUBU_WV_M1_MASK,
25563 0 : 11721 => Opcode::PseudoVWSUBU_WV_M1_MASK_TIED,
25564 0 : 11722 => Opcode::PseudoVWSUBU_WV_M1_TIED,
25565 0 : 11723 => Opcode::PseudoVWSUBU_WV_M2,
25566 0 : 11724 => Opcode::PseudoVWSUBU_WV_M2_MASK,
25567 0 : 11725 => Opcode::PseudoVWSUBU_WV_M2_MASK_TIED,
25568 0 : 11726 => Opcode::PseudoVWSUBU_WV_M2_TIED,
25569 0 : 11727 => Opcode::PseudoVWSUBU_WV_M4,
25570 0 : 11728 => Opcode::PseudoVWSUBU_WV_M4_MASK,
25571 0 : 11729 => Opcode::PseudoVWSUBU_WV_M4_MASK_TIED,
25572 0 : 11730 => Opcode::PseudoVWSUBU_WV_M4_TIED,
25573 0 : 11731 => Opcode::PseudoVWSUBU_WV_MF2,
25574 0 : 11732 => Opcode::PseudoVWSUBU_WV_MF2_MASK,
25575 0 : 11733 => Opcode::PseudoVWSUBU_WV_MF2_MASK_TIED,
25576 0 : 11734 => Opcode::PseudoVWSUBU_WV_MF2_TIED,
25577 0 : 11735 => Opcode::PseudoVWSUBU_WV_MF4,
25578 0 : 11736 => Opcode::PseudoVWSUBU_WV_MF4_MASK,
25579 0 : 11737 => Opcode::PseudoVWSUBU_WV_MF4_MASK_TIED,
25580 0 : 11738 => Opcode::PseudoVWSUBU_WV_MF4_TIED,
25581 0 : 11739 => Opcode::PseudoVWSUBU_WV_MF8,
25582 0 : 11740 => Opcode::PseudoVWSUBU_WV_MF8_MASK,
25583 0 : 11741 => Opcode::PseudoVWSUBU_WV_MF8_MASK_TIED,
25584 0 : 11742 => Opcode::PseudoVWSUBU_WV_MF8_TIED,
25585 0 : 11743 => Opcode::PseudoVWSUBU_WX_M1,
25586 0 : 11744 => Opcode::PseudoVWSUBU_WX_M1_MASK,
25587 0 : 11745 => Opcode::PseudoVWSUBU_WX_M2,
25588 0 : 11746 => Opcode::PseudoVWSUBU_WX_M2_MASK,
25589 0 : 11747 => Opcode::PseudoVWSUBU_WX_M4,
25590 0 : 11748 => Opcode::PseudoVWSUBU_WX_M4_MASK,
25591 0 : 11749 => Opcode::PseudoVWSUBU_WX_MF2,
25592 0 : 11750 => Opcode::PseudoVWSUBU_WX_MF2_MASK,
25593 0 : 11751 => Opcode::PseudoVWSUBU_WX_MF4,
25594 0 : 11752 => Opcode::PseudoVWSUBU_WX_MF4_MASK,
25595 0 : 11753 => Opcode::PseudoVWSUBU_WX_MF8,
25596 0 : 11754 => Opcode::PseudoVWSUBU_WX_MF8_MASK,
25597 0 : 11755 => Opcode::PseudoVWSUB_VV_M1,
25598 0 : 11756 => Opcode::PseudoVWSUB_VV_M1_MASK,
25599 0 : 11757 => Opcode::PseudoVWSUB_VV_M2,
25600 0 : 11758 => Opcode::PseudoVWSUB_VV_M2_MASK,
25601 0 : 11759 => Opcode::PseudoVWSUB_VV_M4,
25602 0 : 11760 => Opcode::PseudoVWSUB_VV_M4_MASK,
25603 0 : 11761 => Opcode::PseudoVWSUB_VV_MF2,
25604 0 : 11762 => Opcode::PseudoVWSUB_VV_MF2_MASK,
25605 0 : 11763 => Opcode::PseudoVWSUB_VV_MF4,
25606 0 : 11764 => Opcode::PseudoVWSUB_VV_MF4_MASK,
25607 0 : 11765 => Opcode::PseudoVWSUB_VV_MF8,
25608 0 : 11766 => Opcode::PseudoVWSUB_VV_MF8_MASK,
25609 0 : 11767 => Opcode::PseudoVWSUB_VX_M1,
25610 0 : 11768 => Opcode::PseudoVWSUB_VX_M1_MASK,
25611 0 : 11769 => Opcode::PseudoVWSUB_VX_M2,
25612 0 : 11770 => Opcode::PseudoVWSUB_VX_M2_MASK,
25613 0 : 11771 => Opcode::PseudoVWSUB_VX_M4,
25614 0 : 11772 => Opcode::PseudoVWSUB_VX_M4_MASK,
25615 0 : 11773 => Opcode::PseudoVWSUB_VX_MF2,
25616 0 : 11774 => Opcode::PseudoVWSUB_VX_MF2_MASK,
25617 0 : 11775 => Opcode::PseudoVWSUB_VX_MF4,
25618 0 : 11776 => Opcode::PseudoVWSUB_VX_MF4_MASK,
25619 0 : 11777 => Opcode::PseudoVWSUB_VX_MF8,
25620 0 : 11778 => Opcode::PseudoVWSUB_VX_MF8_MASK,
25621 0 : 11779 => Opcode::PseudoVWSUB_WV_M1,
25622 0 : 11780 => Opcode::PseudoVWSUB_WV_M1_MASK,
25623 0 : 11781 => Opcode::PseudoVWSUB_WV_M1_MASK_TIED,
25624 0 : 11782 => Opcode::PseudoVWSUB_WV_M1_TIED,
25625 0 : 11783 => Opcode::PseudoVWSUB_WV_M2,
25626 0 : 11784 => Opcode::PseudoVWSUB_WV_M2_MASK,
25627 0 : 11785 => Opcode::PseudoVWSUB_WV_M2_MASK_TIED,
25628 0 : 11786 => Opcode::PseudoVWSUB_WV_M2_TIED,
25629 0 : 11787 => Opcode::PseudoVWSUB_WV_M4,
25630 0 : 11788 => Opcode::PseudoVWSUB_WV_M4_MASK,
25631 0 : 11789 => Opcode::PseudoVWSUB_WV_M4_MASK_TIED,
25632 0 : 11790 => Opcode::PseudoVWSUB_WV_M4_TIED,
25633 0 : 11791 => Opcode::PseudoVWSUB_WV_MF2,
25634 0 : 11792 => Opcode::PseudoVWSUB_WV_MF2_MASK,
25635 0 : 11793 => Opcode::PseudoVWSUB_WV_MF2_MASK_TIED,
25636 0 : 11794 => Opcode::PseudoVWSUB_WV_MF2_TIED,
25637 0 : 11795 => Opcode::PseudoVWSUB_WV_MF4,
25638 0 : 11796 => Opcode::PseudoVWSUB_WV_MF4_MASK,
25639 0 : 11797 => Opcode::PseudoVWSUB_WV_MF4_MASK_TIED,
25640 0 : 11798 => Opcode::PseudoVWSUB_WV_MF4_TIED,
25641 0 : 11799 => Opcode::PseudoVWSUB_WV_MF8,
25642 0 : 11800 => Opcode::PseudoVWSUB_WV_MF8_MASK,
25643 0 : 11801 => Opcode::PseudoVWSUB_WV_MF8_MASK_TIED,
25644 0 : 11802 => Opcode::PseudoVWSUB_WV_MF8_TIED,
25645 0 : 11803 => Opcode::PseudoVWSUB_WX_M1,
25646 0 : 11804 => Opcode::PseudoVWSUB_WX_M1_MASK,
25647 0 : 11805 => Opcode::PseudoVWSUB_WX_M2,
25648 0 : 11806 => Opcode::PseudoVWSUB_WX_M2_MASK,
25649 0 : 11807 => Opcode::PseudoVWSUB_WX_M4,
25650 0 : 11808 => Opcode::PseudoVWSUB_WX_M4_MASK,
25651 0 : 11809 => Opcode::PseudoVWSUB_WX_MF2,
25652 0 : 11810 => Opcode::PseudoVWSUB_WX_MF2_MASK,
25653 0 : 11811 => Opcode::PseudoVWSUB_WX_MF4,
25654 0 : 11812 => Opcode::PseudoVWSUB_WX_MF4_MASK,
25655 0 : 11813 => Opcode::PseudoVWSUB_WX_MF8,
25656 0 : 11814 => Opcode::PseudoVWSUB_WX_MF8_MASK,
25657 0 : 11815 => Opcode::PseudoVXOR_VI_M1,
25658 0 : 11816 => Opcode::PseudoVXOR_VI_M1_MASK,
25659 0 : 11817 => Opcode::PseudoVXOR_VI_M2,
25660 0 : 11818 => Opcode::PseudoVXOR_VI_M2_MASK,
25661 0 : 11819 => Opcode::PseudoVXOR_VI_M4,
25662 0 : 11820 => Opcode::PseudoVXOR_VI_M4_MASK,
25663 0 : 11821 => Opcode::PseudoVXOR_VI_M8,
25664 0 : 11822 => Opcode::PseudoVXOR_VI_M8_MASK,
25665 0 : 11823 => Opcode::PseudoVXOR_VI_MF2,
25666 0 : 11824 => Opcode::PseudoVXOR_VI_MF2_MASK,
25667 0 : 11825 => Opcode::PseudoVXOR_VI_MF4,
25668 0 : 11826 => Opcode::PseudoVXOR_VI_MF4_MASK,
25669 0 : 11827 => Opcode::PseudoVXOR_VI_MF8,
25670 0 : 11828 => Opcode::PseudoVXOR_VI_MF8_MASK,
25671 0 : 11829 => Opcode::PseudoVXOR_VV_M1,
25672 0 : 11830 => Opcode::PseudoVXOR_VV_M1_MASK,
25673 0 : 11831 => Opcode::PseudoVXOR_VV_M2,
25674 0 : 11832 => Opcode::PseudoVXOR_VV_M2_MASK,
25675 0 : 11833 => Opcode::PseudoVXOR_VV_M4,
25676 0 : 11834 => Opcode::PseudoVXOR_VV_M4_MASK,
25677 0 : 11835 => Opcode::PseudoVXOR_VV_M8,
25678 0 : 11836 => Opcode::PseudoVXOR_VV_M8_MASK,
25679 0 : 11837 => Opcode::PseudoVXOR_VV_MF2,
25680 0 : 11838 => Opcode::PseudoVXOR_VV_MF2_MASK,
25681 0 : 11839 => Opcode::PseudoVXOR_VV_MF4,
25682 0 : 11840 => Opcode::PseudoVXOR_VV_MF4_MASK,
25683 0 : 11841 => Opcode::PseudoVXOR_VV_MF8,
25684 0 : 11842 => Opcode::PseudoVXOR_VV_MF8_MASK,
25685 0 : 11843 => Opcode::PseudoVXOR_VX_M1,
25686 0 : 11844 => Opcode::PseudoVXOR_VX_M1_MASK,
25687 0 : 11845 => Opcode::PseudoVXOR_VX_M2,
25688 0 : 11846 => Opcode::PseudoVXOR_VX_M2_MASK,
25689 0 : 11847 => Opcode::PseudoVXOR_VX_M4,
25690 0 : 11848 => Opcode::PseudoVXOR_VX_M4_MASK,
25691 0 : 11849 => Opcode::PseudoVXOR_VX_M8,
25692 0 : 11850 => Opcode::PseudoVXOR_VX_M8_MASK,
25693 0 : 11851 => Opcode::PseudoVXOR_VX_MF2,
25694 0 : 11852 => Opcode::PseudoVXOR_VX_MF2_MASK,
25695 0 : 11853 => Opcode::PseudoVXOR_VX_MF4,
25696 0 : 11854 => Opcode::PseudoVXOR_VX_MF4_MASK,
25697 0 : 11855 => Opcode::PseudoVXOR_VX_MF8,
25698 0 : 11856 => Opcode::PseudoVXOR_VX_MF8_MASK,
25699 0 : 11857 => Opcode::PseudoVZEXT_VF2_M1,
25700 0 : 11858 => Opcode::PseudoVZEXT_VF2_M1_MASK,
25701 0 : 11859 => Opcode::PseudoVZEXT_VF2_M2,
25702 0 : 11860 => Opcode::PseudoVZEXT_VF2_M2_MASK,
25703 0 : 11861 => Opcode::PseudoVZEXT_VF2_M4,
25704 0 : 11862 => Opcode::PseudoVZEXT_VF2_M4_MASK,
25705 0 : 11863 => Opcode::PseudoVZEXT_VF2_M8,
25706 0 : 11864 => Opcode::PseudoVZEXT_VF2_M8_MASK,
25707 0 : 11865 => Opcode::PseudoVZEXT_VF2_MF2,
25708 0 : 11866 => Opcode::PseudoVZEXT_VF2_MF2_MASK,
25709 0 : 11867 => Opcode::PseudoVZEXT_VF2_MF4,
25710 0 : 11868 => Opcode::PseudoVZEXT_VF2_MF4_MASK,
25711 0 : 11869 => Opcode::PseudoVZEXT_VF4_M1,
25712 0 : 11870 => Opcode::PseudoVZEXT_VF4_M1_MASK,
25713 0 : 11871 => Opcode::PseudoVZEXT_VF4_M2,
25714 0 : 11872 => Opcode::PseudoVZEXT_VF4_M2_MASK,
25715 0 : 11873 => Opcode::PseudoVZEXT_VF4_M4,
25716 0 : 11874 => Opcode::PseudoVZEXT_VF4_M4_MASK,
25717 0 : 11875 => Opcode::PseudoVZEXT_VF4_M8,
25718 0 : 11876 => Opcode::PseudoVZEXT_VF4_M8_MASK,
25719 0 : 11877 => Opcode::PseudoVZEXT_VF4_MF2,
25720 0 : 11878 => Opcode::PseudoVZEXT_VF4_MF2_MASK,
25721 0 : 11879 => Opcode::PseudoVZEXT_VF8_M1,
25722 0 : 11880 => Opcode::PseudoVZEXT_VF8_M1_MASK,
25723 0 : 11881 => Opcode::PseudoVZEXT_VF8_M2,
25724 0 : 11882 => Opcode::PseudoVZEXT_VF8_M2_MASK,
25725 0 : 11883 => Opcode::PseudoVZEXT_VF8_M4,
25726 0 : 11884 => Opcode::PseudoVZEXT_VF8_M4_MASK,
25727 0 : 11885 => Opcode::PseudoVZEXT_VF8_M8,
25728 0 : 11886 => Opcode::PseudoVZEXT_VF8_M8_MASK,
25729 0 : 11887 => Opcode::PseudoZEXT_H,
25730 0 : 11888 => Opcode::PseudoZEXT_W,
25731 0 : 11889 => Opcode::ReadCounterWide,
25732 0 : 11890 => Opcode::ReadFFLAGS,
25733 0 : 11891 => Opcode::ReadFRM,
25734 0 : 11892 => Opcode::Select_FPR16INX_Using_CC_GPR,
25735 0 : 11893 => Opcode::Select_FPR16_Using_CC_GPR,
25736 0 : 11894 => Opcode::Select_FPR32INX_Using_CC_GPR,
25737 0 : 11895 => Opcode::Select_FPR32_Using_CC_GPR,
25738 0 : 11896 => Opcode::Select_FPR64IN32X_Using_CC_GPR,
25739 0 : 11897 => Opcode::Select_FPR64INX_Using_CC_GPR,
25740 0 : 11898 => Opcode::Select_FPR64_Using_CC_GPR,
25741 0 : 11899 => Opcode::Select_GPR_Using_CC_GPR,
25742 0 : 11900 => Opcode::Select_GPR_Using_CC_Imm,
25743 0 : 11901 => Opcode::SplitF64Pseudo,
25744 0 : 11902 => Opcode::SwapFRMImm,
25745 0 : 11903 => Opcode::WriteFFLAGS,
25746 0 : 11904 => Opcode::WriteFRM,
25747 0 : 11905 => Opcode::WriteFRMImm,
25748 0 : 11906 => Opcode::WriteVXRMImm,
25749 0 : 11907 => Opcode::ADD,
25750 0 : 11908 => Opcode::ADDI,
25751 0 : 11909 => Opcode::ADDIW,
25752 0 : 11910 => Opcode::ADDW,
25753 0 : 11911 => Opcode::ADD_UW,
25754 0 : 11912 => Opcode::AES32DSI,
25755 0 : 11913 => Opcode::AES32DSMI,
25756 0 : 11914 => Opcode::AES32ESI,
25757 0 : 11915 => Opcode::AES32ESMI,
25758 0 : 11916 => Opcode::AES64DS,
25759 0 : 11917 => Opcode::AES64DSM,
25760 0 : 11918 => Opcode::AES64ES,
25761 0 : 11919 => Opcode::AES64ESM,
25762 0 : 11920 => Opcode::AES64IM,
25763 0 : 11921 => Opcode::AES64KS1I,
25764 0 : 11922 => Opcode::AES64KS2,
25765 0 : 11923 => Opcode::AMOADD_B,
25766 0 : 11924 => Opcode::AMOADD_B_AQ,
25767 0 : 11925 => Opcode::AMOADD_B_AQ_RL,
25768 0 : 11926 => Opcode::AMOADD_B_RL,
25769 0 : 11927 => Opcode::AMOADD_D,
25770 0 : 11928 => Opcode::AMOADD_D_AQ,
25771 0 : 11929 => Opcode::AMOADD_D_AQ_RL,
25772 0 : 11930 => Opcode::AMOADD_D_RL,
25773 0 : 11931 => Opcode::AMOADD_H,
25774 0 : 11932 => Opcode::AMOADD_H_AQ,
25775 0 : 11933 => Opcode::AMOADD_H_AQ_RL,
25776 0 : 11934 => Opcode::AMOADD_H_RL,
25777 0 : 11935 => Opcode::AMOADD_W,
25778 0 : 11936 => Opcode::AMOADD_W_AQ,
25779 0 : 11937 => Opcode::AMOADD_W_AQ_RL,
25780 0 : 11938 => Opcode::AMOADD_W_RL,
25781 0 : 11939 => Opcode::AMOAND_B,
25782 0 : 11940 => Opcode::AMOAND_B_AQ,
25783 0 : 11941 => Opcode::AMOAND_B_AQ_RL,
25784 0 : 11942 => Opcode::AMOAND_B_RL,
25785 0 : 11943 => Opcode::AMOAND_D,
25786 0 : 11944 => Opcode::AMOAND_D_AQ,
25787 0 : 11945 => Opcode::AMOAND_D_AQ_RL,
25788 0 : 11946 => Opcode::AMOAND_D_RL,
25789 0 : 11947 => Opcode::AMOAND_H,
25790 0 : 11948 => Opcode::AMOAND_H_AQ,
25791 0 : 11949 => Opcode::AMOAND_H_AQ_RL,
25792 0 : 11950 => Opcode::AMOAND_H_RL,
25793 0 : 11951 => Opcode::AMOAND_W,
25794 0 : 11952 => Opcode::AMOAND_W_AQ,
25795 0 : 11953 => Opcode::AMOAND_W_AQ_RL,
25796 0 : 11954 => Opcode::AMOAND_W_RL,
25797 0 : 11955 => Opcode::AMOCAS_B,
25798 0 : 11956 => Opcode::AMOCAS_B_AQ,
25799 0 : 11957 => Opcode::AMOCAS_B_AQ_RL,
25800 0 : 11958 => Opcode::AMOCAS_B_RL,
25801 0 : 11959 => Opcode::AMOCAS_D_RV32,
25802 0 : 11960 => Opcode::AMOCAS_D_RV32_AQ,
25803 0 : 11961 => Opcode::AMOCAS_D_RV32_AQ_RL,
25804 0 : 11962 => Opcode::AMOCAS_D_RV32_RL,
25805 0 : 11963 => Opcode::AMOCAS_D_RV64,
25806 0 : 11964 => Opcode::AMOCAS_D_RV64_AQ,
25807 0 : 11965 => Opcode::AMOCAS_D_RV64_AQ_RL,
25808 0 : 11966 => Opcode::AMOCAS_D_RV64_RL,
25809 0 : 11967 => Opcode::AMOCAS_H,
25810 0 : 11968 => Opcode::AMOCAS_H_AQ,
25811 0 : 11969 => Opcode::AMOCAS_H_AQ_RL,
25812 0 : 11970 => Opcode::AMOCAS_H_RL,
25813 0 : 11971 => Opcode::AMOCAS_Q,
25814 0 : 11972 => Opcode::AMOCAS_Q_AQ,
25815 0 : 11973 => Opcode::AMOCAS_Q_AQ_RL,
25816 0 : 11974 => Opcode::AMOCAS_Q_RL,
25817 0 : 11975 => Opcode::AMOCAS_W,
25818 0 : 11976 => Opcode::AMOCAS_W_AQ,
25819 0 : 11977 => Opcode::AMOCAS_W_AQ_RL,
25820 0 : 11978 => Opcode::AMOCAS_W_RL,
25821 0 : 11979 => Opcode::AMOMAXU_B,
25822 0 : 11980 => Opcode::AMOMAXU_B_AQ,
25823 0 : 11981 => Opcode::AMOMAXU_B_AQ_RL,
25824 0 : 11982 => Opcode::AMOMAXU_B_RL,
25825 0 : 11983 => Opcode::AMOMAXU_D,
25826 0 : 11984 => Opcode::AMOMAXU_D_AQ,
25827 0 : 11985 => Opcode::AMOMAXU_D_AQ_RL,
25828 0 : 11986 => Opcode::AMOMAXU_D_RL,
25829 0 : 11987 => Opcode::AMOMAXU_H,
25830 0 : 11988 => Opcode::AMOMAXU_H_AQ,
25831 0 : 11989 => Opcode::AMOMAXU_H_AQ_RL,
25832 0 : 11990 => Opcode::AMOMAXU_H_RL,
25833 0 : 11991 => Opcode::AMOMAXU_W,
25834 0 : 11992 => Opcode::AMOMAXU_W_AQ,
25835 0 : 11993 => Opcode::AMOMAXU_W_AQ_RL,
25836 0 : 11994 => Opcode::AMOMAXU_W_RL,
25837 0 : 11995 => Opcode::AMOMAX_B,
25838 0 : 11996 => Opcode::AMOMAX_B_AQ,
25839 0 : 11997 => Opcode::AMOMAX_B_AQ_RL,
25840 0 : 11998 => Opcode::AMOMAX_B_RL,
25841 0 : 11999 => Opcode::AMOMAX_D,
25842 0 : 12000 => Opcode::AMOMAX_D_AQ,
25843 0 : 12001 => Opcode::AMOMAX_D_AQ_RL,
25844 0 : 12002 => Opcode::AMOMAX_D_RL,
25845 0 : 12003 => Opcode::AMOMAX_H,
25846 0 : 12004 => Opcode::AMOMAX_H_AQ,
25847 0 : 12005 => Opcode::AMOMAX_H_AQ_RL,
25848 0 : 12006 => Opcode::AMOMAX_H_RL,
25849 0 : 12007 => Opcode::AMOMAX_W,
25850 0 : 12008 => Opcode::AMOMAX_W_AQ,
25851 0 : 12009 => Opcode::AMOMAX_W_AQ_RL,
25852 0 : 12010 => Opcode::AMOMAX_W_RL,
25853 0 : 12011 => Opcode::AMOMINU_B,
25854 0 : 12012 => Opcode::AMOMINU_B_AQ,
25855 0 : 12013 => Opcode::AMOMINU_B_AQ_RL,
25856 0 : 12014 => Opcode::AMOMINU_B_RL,
25857 0 : 12015 => Opcode::AMOMINU_D,
25858 0 : 12016 => Opcode::AMOMINU_D_AQ,
25859 0 : 12017 => Opcode::AMOMINU_D_AQ_RL,
25860 0 : 12018 => Opcode::AMOMINU_D_RL,
25861 0 : 12019 => Opcode::AMOMINU_H,
25862 0 : 12020 => Opcode::AMOMINU_H_AQ,
25863 0 : 12021 => Opcode::AMOMINU_H_AQ_RL,
25864 0 : 12022 => Opcode::AMOMINU_H_RL,
25865 0 : 12023 => Opcode::AMOMINU_W,
25866 0 : 12024 => Opcode::AMOMINU_W_AQ,
25867 0 : 12025 => Opcode::AMOMINU_W_AQ_RL,
25868 0 : 12026 => Opcode::AMOMINU_W_RL,
25869 0 : 12027 => Opcode::AMOMIN_B,
25870 0 : 12028 => Opcode::AMOMIN_B_AQ,
25871 0 : 12029 => Opcode::AMOMIN_B_AQ_RL,
25872 0 : 12030 => Opcode::AMOMIN_B_RL,
25873 0 : 12031 => Opcode::AMOMIN_D,
25874 0 : 12032 => Opcode::AMOMIN_D_AQ,
25875 0 : 12033 => Opcode::AMOMIN_D_AQ_RL,
25876 0 : 12034 => Opcode::AMOMIN_D_RL,
25877 0 : 12035 => Opcode::AMOMIN_H,
25878 0 : 12036 => Opcode::AMOMIN_H_AQ,
25879 0 : 12037 => Opcode::AMOMIN_H_AQ_RL,
25880 0 : 12038 => Opcode::AMOMIN_H_RL,
25881 0 : 12039 => Opcode::AMOMIN_W,
25882 0 : 12040 => Opcode::AMOMIN_W_AQ,
25883 0 : 12041 => Opcode::AMOMIN_W_AQ_RL,
25884 0 : 12042 => Opcode::AMOMIN_W_RL,
25885 0 : 12043 => Opcode::AMOOR_B,
25886 0 : 12044 => Opcode::AMOOR_B_AQ,
25887 0 : 12045 => Opcode::AMOOR_B_AQ_RL,
25888 0 : 12046 => Opcode::AMOOR_B_RL,
25889 0 : 12047 => Opcode::AMOOR_D,
25890 0 : 12048 => Opcode::AMOOR_D_AQ,
25891 0 : 12049 => Opcode::AMOOR_D_AQ_RL,
25892 0 : 12050 => Opcode::AMOOR_D_RL,
25893 0 : 12051 => Opcode::AMOOR_H,
25894 0 : 12052 => Opcode::AMOOR_H_AQ,
25895 0 : 12053 => Opcode::AMOOR_H_AQ_RL,
25896 0 : 12054 => Opcode::AMOOR_H_RL,
25897 0 : 12055 => Opcode::AMOOR_W,
25898 0 : 12056 => Opcode::AMOOR_W_AQ,
25899 0 : 12057 => Opcode::AMOOR_W_AQ_RL,
25900 0 : 12058 => Opcode::AMOOR_W_RL,
25901 0 : 12059 => Opcode::AMOSWAP_B,
25902 0 : 12060 => Opcode::AMOSWAP_B_AQ,
25903 0 : 12061 => Opcode::AMOSWAP_B_AQ_RL,
25904 0 : 12062 => Opcode::AMOSWAP_B_RL,
25905 0 : 12063 => Opcode::AMOSWAP_D,
25906 0 : 12064 => Opcode::AMOSWAP_D_AQ,
25907 0 : 12065 => Opcode::AMOSWAP_D_AQ_RL,
25908 0 : 12066 => Opcode::AMOSWAP_D_RL,
25909 0 : 12067 => Opcode::AMOSWAP_H,
25910 0 : 12068 => Opcode::AMOSWAP_H_AQ,
25911 0 : 12069 => Opcode::AMOSWAP_H_AQ_RL,
25912 0 : 12070 => Opcode::AMOSWAP_H_RL,
25913 0 : 12071 => Opcode::AMOSWAP_W,
25914 0 : 12072 => Opcode::AMOSWAP_W_AQ,
25915 0 : 12073 => Opcode::AMOSWAP_W_AQ_RL,
25916 0 : 12074 => Opcode::AMOSWAP_W_RL,
25917 0 : 12075 => Opcode::AMOXOR_B,
25918 0 : 12076 => Opcode::AMOXOR_B_AQ,
25919 0 : 12077 => Opcode::AMOXOR_B_AQ_RL,
25920 0 : 12078 => Opcode::AMOXOR_B_RL,
25921 0 : 12079 => Opcode::AMOXOR_D,
25922 0 : 12080 => Opcode::AMOXOR_D_AQ,
25923 0 : 12081 => Opcode::AMOXOR_D_AQ_RL,
25924 0 : 12082 => Opcode::AMOXOR_D_RL,
25925 0 : 12083 => Opcode::AMOXOR_H,
25926 0 : 12084 => Opcode::AMOXOR_H_AQ,
25927 0 : 12085 => Opcode::AMOXOR_H_AQ_RL,
25928 0 : 12086 => Opcode::AMOXOR_H_RL,
25929 0 : 12087 => Opcode::AMOXOR_W,
25930 0 : 12088 => Opcode::AMOXOR_W_AQ,
25931 0 : 12089 => Opcode::AMOXOR_W_AQ_RL,
25932 0 : 12090 => Opcode::AMOXOR_W_RL,
25933 0 : 12091 => Opcode::AND,
25934 0 : 12092 => Opcode::ANDI,
25935 0 : 12093 => Opcode::ANDN,
25936 0 : 12094 => Opcode::AUIPC,
25937 0 : 12095 => Opcode::BCLR,
25938 0 : 12096 => Opcode::BCLRI,
25939 0 : 12097 => Opcode::BEQ,
25940 0 : 12098 => Opcode::BEXT,
25941 0 : 12099 => Opcode::BEXTI,
25942 0 : 12100 => Opcode::BGE,
25943 0 : 12101 => Opcode::BGEU,
25944 0 : 12102 => Opcode::BINV,
25945 0 : 12103 => Opcode::BINVI,
25946 0 : 12104 => Opcode::BLT,
25947 0 : 12105 => Opcode::BLTU,
25948 0 : 12106 => Opcode::BNE,
25949 0 : 12107 => Opcode::BREV8,
25950 0 : 12108 => Opcode::BSET,
25951 0 : 12109 => Opcode::BSETI,
25952 0 : 12110 => Opcode::CBO_CLEAN,
25953 0 : 12111 => Opcode::CBO_FLUSH,
25954 0 : 12112 => Opcode::CBO_INVAL,
25955 0 : 12113 => Opcode::CBO_ZERO,
25956 0 : 12114 => Opcode::CLMUL,
25957 0 : 12115 => Opcode::CLMULH,
25958 0 : 12116 => Opcode::CLMULR,
25959 0 : 12117 => Opcode::CLZ,
25960 0 : 12118 => Opcode::CLZW,
25961 0 : 12119 => Opcode::CM_JALT,
25962 0 : 12120 => Opcode::CM_JT,
25963 0 : 12121 => Opcode::CM_MVA01S,
25964 0 : 12122 => Opcode::CM_MVSA01,
25965 0 : 12123 => Opcode::CM_POP,
25966 0 : 12124 => Opcode::CM_POPRET,
25967 0 : 12125 => Opcode::CM_POPRETZ,
25968 0 : 12126 => Opcode::CM_PUSH,
25969 0 : 12127 => Opcode::CPOP,
25970 0 : 12128 => Opcode::CPOPW,
25971 0 : 12129 => Opcode::CSRRC,
25972 0 : 12130 => Opcode::CSRRCI,
25973 0 : 12131 => Opcode::CSRRS,
25974 0 : 12132 => Opcode::CSRRSI,
25975 0 : 12133 => Opcode::CSRRW,
25976 0 : 12134 => Opcode::CSRRWI,
25977 0 : 12135 => Opcode::CTZ,
25978 0 : 12136 => Opcode::CTZW,
25979 0 : 12137 => Opcode::CV_ABS,
25980 0 : 12138 => Opcode::CV_ABS_B,
25981 0 : 12139 => Opcode::CV_ABS_H,
25982 0 : 12140 => Opcode::CV_ADDN,
25983 0 : 12141 => Opcode::CV_ADDNR,
25984 0 : 12142 => Opcode::CV_ADDRN,
25985 0 : 12143 => Opcode::CV_ADDRNR,
25986 0 : 12144 => Opcode::CV_ADDUN,
25987 0 : 12145 => Opcode::CV_ADDUNR,
25988 0 : 12146 => Opcode::CV_ADDURN,
25989 0 : 12147 => Opcode::CV_ADDURNR,
25990 0 : 12148 => Opcode::CV_ADD_B,
25991 0 : 12149 => Opcode::CV_ADD_DIV2,
25992 0 : 12150 => Opcode::CV_ADD_DIV4,
25993 0 : 12151 => Opcode::CV_ADD_DIV8,
25994 0 : 12152 => Opcode::CV_ADD_H,
25995 0 : 12153 => Opcode::CV_ADD_SCI_B,
25996 0 : 12154 => Opcode::CV_ADD_SCI_H,
25997 0 : 12155 => Opcode::CV_ADD_SC_B,
25998 0 : 12156 => Opcode::CV_ADD_SC_H,
25999 0 : 12157 => Opcode::CV_AND_B,
26000 0 : 12158 => Opcode::CV_AND_H,
26001 0 : 12159 => Opcode::CV_AND_SCI_B,
26002 0 : 12160 => Opcode::CV_AND_SCI_H,
26003 0 : 12161 => Opcode::CV_AND_SC_B,
26004 0 : 12162 => Opcode::CV_AND_SC_H,
26005 0 : 12163 => Opcode::CV_AVGU_B,
26006 0 : 12164 => Opcode::CV_AVGU_H,
26007 0 : 12165 => Opcode::CV_AVGU_SCI_B,
26008 0 : 12166 => Opcode::CV_AVGU_SCI_H,
26009 0 : 12167 => Opcode::CV_AVGU_SC_B,
26010 0 : 12168 => Opcode::CV_AVGU_SC_H,
26011 0 : 12169 => Opcode::CV_AVG_B,
26012 0 : 12170 => Opcode::CV_AVG_H,
26013 0 : 12171 => Opcode::CV_AVG_SCI_B,
26014 0 : 12172 => Opcode::CV_AVG_SCI_H,
26015 0 : 12173 => Opcode::CV_AVG_SC_B,
26016 0 : 12174 => Opcode::CV_AVG_SC_H,
26017 0 : 12175 => Opcode::CV_BCLR,
26018 0 : 12176 => Opcode::CV_BCLRR,
26019 0 : 12177 => Opcode::CV_BEQIMM,
26020 0 : 12178 => Opcode::CV_BITREV,
26021 0 : 12179 => Opcode::CV_BNEIMM,
26022 0 : 12180 => Opcode::CV_BSET,
26023 0 : 12181 => Opcode::CV_BSETR,
26024 0 : 12182 => Opcode::CV_CLB,
26025 0 : 12183 => Opcode::CV_CLIP,
26026 0 : 12184 => Opcode::CV_CLIPR,
26027 0 : 12185 => Opcode::CV_CLIPU,
26028 0 : 12186 => Opcode::CV_CLIPUR,
26029 0 : 12187 => Opcode::CV_CMPEQ_B,
26030 0 : 12188 => Opcode::CV_CMPEQ_H,
26031 0 : 12189 => Opcode::CV_CMPEQ_SCI_B,
26032 0 : 12190 => Opcode::CV_CMPEQ_SCI_H,
26033 0 : 12191 => Opcode::CV_CMPEQ_SC_B,
26034 0 : 12192 => Opcode::CV_CMPEQ_SC_H,
26035 0 : 12193 => Opcode::CV_CMPGEU_B,
26036 0 : 12194 => Opcode::CV_CMPGEU_H,
26037 0 : 12195 => Opcode::CV_CMPGEU_SCI_B,
26038 0 : 12196 => Opcode::CV_CMPGEU_SCI_H,
26039 0 : 12197 => Opcode::CV_CMPGEU_SC_B,
26040 0 : 12198 => Opcode::CV_CMPGEU_SC_H,
26041 0 : 12199 => Opcode::CV_CMPGE_B,
26042 0 : 12200 => Opcode::CV_CMPGE_H,
26043 0 : 12201 => Opcode::CV_CMPGE_SCI_B,
26044 0 : 12202 => Opcode::CV_CMPGE_SCI_H,
26045 0 : 12203 => Opcode::CV_CMPGE_SC_B,
26046 0 : 12204 => Opcode::CV_CMPGE_SC_H,
26047 0 : 12205 => Opcode::CV_CMPGTU_B,
26048 0 : 12206 => Opcode::CV_CMPGTU_H,
26049 0 : 12207 => Opcode::CV_CMPGTU_SCI_B,
26050 0 : 12208 => Opcode::CV_CMPGTU_SCI_H,
26051 0 : 12209 => Opcode::CV_CMPGTU_SC_B,
26052 0 : 12210 => Opcode::CV_CMPGTU_SC_H,
26053 0 : 12211 => Opcode::CV_CMPGT_B,
26054 0 : 12212 => Opcode::CV_CMPGT_H,
26055 0 : 12213 => Opcode::CV_CMPGT_SCI_B,
26056 0 : 12214 => Opcode::CV_CMPGT_SCI_H,
26057 0 : 12215 => Opcode::CV_CMPGT_SC_B,
26058 0 : 12216 => Opcode::CV_CMPGT_SC_H,
26059 0 : 12217 => Opcode::CV_CMPLEU_B,
26060 0 : 12218 => Opcode::CV_CMPLEU_H,
26061 0 : 12219 => Opcode::CV_CMPLEU_SCI_B,
26062 0 : 12220 => Opcode::CV_CMPLEU_SCI_H,
26063 0 : 12221 => Opcode::CV_CMPLEU_SC_B,
26064 0 : 12222 => Opcode::CV_CMPLEU_SC_H,
26065 0 : 12223 => Opcode::CV_CMPLE_B,
26066 0 : 12224 => Opcode::CV_CMPLE_H,
26067 0 : 12225 => Opcode::CV_CMPLE_SCI_B,
26068 0 : 12226 => Opcode::CV_CMPLE_SCI_H,
26069 0 : 12227 => Opcode::CV_CMPLE_SC_B,
26070 0 : 12228 => Opcode::CV_CMPLE_SC_H,
26071 0 : 12229 => Opcode::CV_CMPLTU_B,
26072 0 : 12230 => Opcode::CV_CMPLTU_H,
26073 0 : 12231 => Opcode::CV_CMPLTU_SCI_B,
26074 0 : 12232 => Opcode::CV_CMPLTU_SCI_H,
26075 0 : 12233 => Opcode::CV_CMPLTU_SC_B,
26076 0 : 12234 => Opcode::CV_CMPLTU_SC_H,
26077 0 : 12235 => Opcode::CV_CMPLT_B,
26078 0 : 12236 => Opcode::CV_CMPLT_H,
26079 0 : 12237 => Opcode::CV_CMPLT_SCI_B,
26080 0 : 12238 => Opcode::CV_CMPLT_SCI_H,
26081 0 : 12239 => Opcode::CV_CMPLT_SC_B,
26082 0 : 12240 => Opcode::CV_CMPLT_SC_H,
26083 0 : 12241 => Opcode::CV_CMPNE_B,
26084 0 : 12242 => Opcode::CV_CMPNE_H,
26085 0 : 12243 => Opcode::CV_CMPNE_SCI_B,
26086 0 : 12244 => Opcode::CV_CMPNE_SCI_H,
26087 0 : 12245 => Opcode::CV_CMPNE_SC_B,
26088 0 : 12246 => Opcode::CV_CMPNE_SC_H,
26089 0 : 12247 => Opcode::CV_CNT,
26090 0 : 12248 => Opcode::CV_CPLXCONJ,
26091 0 : 12249 => Opcode::CV_CPLXMUL_I,
26092 0 : 12250 => Opcode::CV_CPLXMUL_I_DIV2,
26093 0 : 12251 => Opcode::CV_CPLXMUL_I_DIV4,
26094 0 : 12252 => Opcode::CV_CPLXMUL_I_DIV8,
26095 0 : 12253 => Opcode::CV_CPLXMUL_R,
26096 0 : 12254 => Opcode::CV_CPLXMUL_R_DIV2,
26097 0 : 12255 => Opcode::CV_CPLXMUL_R_DIV4,
26098 0 : 12256 => Opcode::CV_CPLXMUL_R_DIV8,
26099 0 : 12257 => Opcode::CV_DOTSP_B,
26100 0 : 12258 => Opcode::CV_DOTSP_H,
26101 0 : 12259 => Opcode::CV_DOTSP_SCI_B,
26102 0 : 12260 => Opcode::CV_DOTSP_SCI_H,
26103 0 : 12261 => Opcode::CV_DOTSP_SC_B,
26104 0 : 12262 => Opcode::CV_DOTSP_SC_H,
26105 0 : 12263 => Opcode::CV_DOTUP_B,
26106 0 : 12264 => Opcode::CV_DOTUP_H,
26107 0 : 12265 => Opcode::CV_DOTUP_SCI_B,
26108 0 : 12266 => Opcode::CV_DOTUP_SCI_H,
26109 0 : 12267 => Opcode::CV_DOTUP_SC_B,
26110 0 : 12268 => Opcode::CV_DOTUP_SC_H,
26111 0 : 12269 => Opcode::CV_DOTUSP_B,
26112 0 : 12270 => Opcode::CV_DOTUSP_H,
26113 0 : 12271 => Opcode::CV_DOTUSP_SCI_B,
26114 0 : 12272 => Opcode::CV_DOTUSP_SCI_H,
26115 0 : 12273 => Opcode::CV_DOTUSP_SC_B,
26116 0 : 12274 => Opcode::CV_DOTUSP_SC_H,
26117 0 : 12275 => Opcode::CV_ELW,
26118 0 : 12276 => Opcode::CV_EXTBS,
26119 0 : 12277 => Opcode::CV_EXTBZ,
26120 0 : 12278 => Opcode::CV_EXTHS,
26121 0 : 12279 => Opcode::CV_EXTHZ,
26122 0 : 12280 => Opcode::CV_EXTRACT,
26123 0 : 12281 => Opcode::CV_EXTRACTR,
26124 0 : 12282 => Opcode::CV_EXTRACTU,
26125 0 : 12283 => Opcode::CV_EXTRACTUR,
26126 0 : 12284 => Opcode::CV_EXTRACTU_B,
26127 0 : 12285 => Opcode::CV_EXTRACTU_H,
26128 0 : 12286 => Opcode::CV_EXTRACT_B,
26129 0 : 12287 => Opcode::CV_EXTRACT_H,
26130 0 : 12288 => Opcode::CV_FF1,
26131 0 : 12289 => Opcode::CV_FL1,
26132 0 : 12290 => Opcode::CV_INSERT,
26133 0 : 12291 => Opcode::CV_INSERTR,
26134 0 : 12292 => Opcode::CV_INSERT_B,
26135 0 : 12293 => Opcode::CV_INSERT_H,
26136 0 : 12294 => Opcode::CV_LBU_ri_inc,
26137 0 : 12295 => Opcode::CV_LBU_rr,
26138 0 : 12296 => Opcode::CV_LBU_rr_inc,
26139 0 : 12297 => Opcode::CV_LB_ri_inc,
26140 0 : 12298 => Opcode::CV_LB_rr,
26141 0 : 12299 => Opcode::CV_LB_rr_inc,
26142 0 : 12300 => Opcode::CV_LHU_ri_inc,
26143 0 : 12301 => Opcode::CV_LHU_rr,
26144 0 : 12302 => Opcode::CV_LHU_rr_inc,
26145 0 : 12303 => Opcode::CV_LH_ri_inc,
26146 0 : 12304 => Opcode::CV_LH_rr,
26147 0 : 12305 => Opcode::CV_LH_rr_inc,
26148 0 : 12306 => Opcode::CV_LW_ri_inc,
26149 0 : 12307 => Opcode::CV_LW_rr,
26150 0 : 12308 => Opcode::CV_LW_rr_inc,
26151 0 : 12309 => Opcode::CV_MAC,
26152 0 : 12310 => Opcode::CV_MACHHSN,
26153 0 : 12311 => Opcode::CV_MACHHSRN,
26154 0 : 12312 => Opcode::CV_MACHHUN,
26155 0 : 12313 => Opcode::CV_MACHHURN,
26156 0 : 12314 => Opcode::CV_MACSN,
26157 0 : 12315 => Opcode::CV_MACSRN,
26158 0 : 12316 => Opcode::CV_MACUN,
26159 0 : 12317 => Opcode::CV_MACURN,
26160 0 : 12318 => Opcode::CV_MAX,
26161 0 : 12319 => Opcode::CV_MAXU,
26162 0 : 12320 => Opcode::CV_MAXU_B,
26163 0 : 12321 => Opcode::CV_MAXU_H,
26164 0 : 12322 => Opcode::CV_MAXU_SCI_B,
26165 0 : 12323 => Opcode::CV_MAXU_SCI_H,
26166 0 : 12324 => Opcode::CV_MAXU_SC_B,
26167 0 : 12325 => Opcode::CV_MAXU_SC_H,
26168 0 : 12326 => Opcode::CV_MAX_B,
26169 0 : 12327 => Opcode::CV_MAX_H,
26170 0 : 12328 => Opcode::CV_MAX_SCI_B,
26171 0 : 12329 => Opcode::CV_MAX_SCI_H,
26172 0 : 12330 => Opcode::CV_MAX_SC_B,
26173 0 : 12331 => Opcode::CV_MAX_SC_H,
26174 0 : 12332 => Opcode::CV_MIN,
26175 0 : 12333 => Opcode::CV_MINU,
26176 0 : 12334 => Opcode::CV_MINU_B,
26177 0 : 12335 => Opcode::CV_MINU_H,
26178 0 : 12336 => Opcode::CV_MINU_SCI_B,
26179 0 : 12337 => Opcode::CV_MINU_SCI_H,
26180 0 : 12338 => Opcode::CV_MINU_SC_B,
26181 0 : 12339 => Opcode::CV_MINU_SC_H,
26182 0 : 12340 => Opcode::CV_MIN_B,
26183 0 : 12341 => Opcode::CV_MIN_H,
26184 0 : 12342 => Opcode::CV_MIN_SCI_B,
26185 0 : 12343 => Opcode::CV_MIN_SCI_H,
26186 0 : 12344 => Opcode::CV_MIN_SC_B,
26187 0 : 12345 => Opcode::CV_MIN_SC_H,
26188 0 : 12346 => Opcode::CV_MSU,
26189 0 : 12347 => Opcode::CV_MULHHSN,
26190 0 : 12348 => Opcode::CV_MULHHSRN,
26191 0 : 12349 => Opcode::CV_MULHHUN,
26192 0 : 12350 => Opcode::CV_MULHHURN,
26193 0 : 12351 => Opcode::CV_MULSN,
26194 0 : 12352 => Opcode::CV_MULSRN,
26195 0 : 12353 => Opcode::CV_MULUN,
26196 0 : 12354 => Opcode::CV_MULURN,
26197 0 : 12355 => Opcode::CV_OR_B,
26198 0 : 12356 => Opcode::CV_OR_H,
26199 0 : 12357 => Opcode::CV_OR_SCI_B,
26200 0 : 12358 => Opcode::CV_OR_SCI_H,
26201 0 : 12359 => Opcode::CV_OR_SC_B,
26202 0 : 12360 => Opcode::CV_OR_SC_H,
26203 0 : 12361 => Opcode::CV_PACK,
26204 0 : 12362 => Opcode::CV_PACKHI_B,
26205 0 : 12363 => Opcode::CV_PACKLO_B,
26206 0 : 12364 => Opcode::CV_PACK_H,
26207 0 : 12365 => Opcode::CV_ROR,
26208 0 : 12366 => Opcode::CV_SB_ri_inc,
26209 0 : 12367 => Opcode::CV_SB_rr,
26210 0 : 12368 => Opcode::CV_SB_rr_inc,
26211 0 : 12369 => Opcode::CV_SDOTSP_B,
26212 0 : 12370 => Opcode::CV_SDOTSP_H,
26213 0 : 12371 => Opcode::CV_SDOTSP_SCI_B,
26214 0 : 12372 => Opcode::CV_SDOTSP_SCI_H,
26215 0 : 12373 => Opcode::CV_SDOTSP_SC_B,
26216 0 : 12374 => Opcode::CV_SDOTSP_SC_H,
26217 0 : 12375 => Opcode::CV_SDOTUP_B,
26218 0 : 12376 => Opcode::CV_SDOTUP_H,
26219 0 : 12377 => Opcode::CV_SDOTUP_SCI_B,
26220 0 : 12378 => Opcode::CV_SDOTUP_SCI_H,
26221 0 : 12379 => Opcode::CV_SDOTUP_SC_B,
26222 0 : 12380 => Opcode::CV_SDOTUP_SC_H,
26223 0 : 12381 => Opcode::CV_SDOTUSP_B,
26224 0 : 12382 => Opcode::CV_SDOTUSP_H,
26225 0 : 12383 => Opcode::CV_SDOTUSP_SCI_B,
26226 0 : 12384 => Opcode::CV_SDOTUSP_SCI_H,
26227 0 : 12385 => Opcode::CV_SDOTUSP_SC_B,
26228 0 : 12386 => Opcode::CV_SDOTUSP_SC_H,
26229 0 : 12387 => Opcode::CV_SHUFFLE2_B,
26230 0 : 12388 => Opcode::CV_SHUFFLE2_H,
26231 0 : 12389 => Opcode::CV_SHUFFLEI0_SCI_B,
26232 0 : 12390 => Opcode::CV_SHUFFLEI1_SCI_B,
26233 0 : 12391 => Opcode::CV_SHUFFLEI2_SCI_B,
26234 0 : 12392 => Opcode::CV_SHUFFLEI3_SCI_B,
26235 0 : 12393 => Opcode::CV_SHUFFLE_B,
26236 0 : 12394 => Opcode::CV_SHUFFLE_H,
26237 0 : 12395 => Opcode::CV_SHUFFLE_SCI_H,
26238 0 : 12396 => Opcode::CV_SH_ri_inc,
26239 0 : 12397 => Opcode::CV_SH_rr,
26240 0 : 12398 => Opcode::CV_SH_rr_inc,
26241 0 : 12399 => Opcode::CV_SLET,
26242 0 : 12400 => Opcode::CV_SLETU,
26243 0 : 12401 => Opcode::CV_SLL_B,
26244 0 : 12402 => Opcode::CV_SLL_H,
26245 0 : 12403 => Opcode::CV_SLL_SCI_B,
26246 0 : 12404 => Opcode::CV_SLL_SCI_H,
26247 0 : 12405 => Opcode::CV_SLL_SC_B,
26248 0 : 12406 => Opcode::CV_SLL_SC_H,
26249 0 : 12407 => Opcode::CV_SRA_B,
26250 0 : 12408 => Opcode::CV_SRA_H,
26251 0 : 12409 => Opcode::CV_SRA_SCI_B,
26252 0 : 12410 => Opcode::CV_SRA_SCI_H,
26253 0 : 12411 => Opcode::CV_SRA_SC_B,
26254 0 : 12412 => Opcode::CV_SRA_SC_H,
26255 0 : 12413 => Opcode::CV_SRL_B,
26256 0 : 12414 => Opcode::CV_SRL_H,
26257 0 : 12415 => Opcode::CV_SRL_SCI_B,
26258 0 : 12416 => Opcode::CV_SRL_SCI_H,
26259 0 : 12417 => Opcode::CV_SRL_SC_B,
26260 0 : 12418 => Opcode::CV_SRL_SC_H,
26261 0 : 12419 => Opcode::CV_SUBN,
26262 0 : 12420 => Opcode::CV_SUBNR,
26263 0 : 12421 => Opcode::CV_SUBRN,
26264 0 : 12422 => Opcode::CV_SUBRNR,
26265 0 : 12423 => Opcode::CV_SUBROTMJ,
26266 0 : 12424 => Opcode::CV_SUBROTMJ_DIV2,
26267 0 : 12425 => Opcode::CV_SUBROTMJ_DIV4,
26268 0 : 12426 => Opcode::CV_SUBROTMJ_DIV8,
26269 0 : 12427 => Opcode::CV_SUBUN,
26270 0 : 12428 => Opcode::CV_SUBUNR,
26271 0 : 12429 => Opcode::CV_SUBURN,
26272 0 : 12430 => Opcode::CV_SUBURNR,
26273 0 : 12431 => Opcode::CV_SUB_B,
26274 0 : 12432 => Opcode::CV_SUB_DIV2,
26275 0 : 12433 => Opcode::CV_SUB_DIV4,
26276 0 : 12434 => Opcode::CV_SUB_DIV8,
26277 0 : 12435 => Opcode::CV_SUB_H,
26278 0 : 12436 => Opcode::CV_SUB_SCI_B,
26279 0 : 12437 => Opcode::CV_SUB_SCI_H,
26280 0 : 12438 => Opcode::CV_SUB_SC_B,
26281 0 : 12439 => Opcode::CV_SUB_SC_H,
26282 0 : 12440 => Opcode::CV_SW_ri_inc,
26283 0 : 12441 => Opcode::CV_SW_rr,
26284 0 : 12442 => Opcode::CV_SW_rr_inc,
26285 0 : 12443 => Opcode::CV_XOR_B,
26286 0 : 12444 => Opcode::CV_XOR_H,
26287 0 : 12445 => Opcode::CV_XOR_SCI_B,
26288 0 : 12446 => Opcode::CV_XOR_SCI_H,
26289 0 : 12447 => Opcode::CV_XOR_SC_B,
26290 0 : 12448 => Opcode::CV_XOR_SC_H,
26291 0 : 12449 => Opcode::CZERO_EQZ,
26292 0 : 12450 => Opcode::CZERO_NEZ,
26293 0 : 12451 => Opcode::C_ADD,
26294 0 : 12452 => Opcode::C_ADDI,
26295 0 : 12453 => Opcode::C_ADDI16SP,
26296 0 : 12454 => Opcode::C_ADDI4SPN,
26297 0 : 12455 => Opcode::C_ADDIW,
26298 0 : 12456 => Opcode::C_ADDI_HINT_IMM_ZERO,
26299 0 : 12457 => Opcode::C_ADDI_NOP,
26300 0 : 12458 => Opcode::C_ADDW,
26301 0 : 12459 => Opcode::C_ADD_HINT,
26302 0 : 12460 => Opcode::C_AND,
26303 0 : 12461 => Opcode::C_ANDI,
26304 0 : 12462 => Opcode::C_BEQZ,
26305 0 : 12463 => Opcode::C_BNEZ,
26306 0 : 12464 => Opcode::C_EBREAK,
26307 0 : 12465 => Opcode::C_FLD,
26308 0 : 12466 => Opcode::C_FLDSP,
26309 0 : 12467 => Opcode::C_FLW,
26310 0 : 12468 => Opcode::C_FLWSP,
26311 0 : 12469 => Opcode::C_FSD,
26312 0 : 12470 => Opcode::C_FSDSP,
26313 0 : 12471 => Opcode::C_FSW,
26314 0 : 12472 => Opcode::C_FSWSP,
26315 0 : 12473 => Opcode::C_J,
26316 0 : 12474 => Opcode::C_JAL,
26317 0 : 12475 => Opcode::C_JALR,
26318 0 : 12476 => Opcode::C_JR,
26319 0 : 12477 => Opcode::C_LBU,
26320 0 : 12478 => Opcode::C_LD,
26321 0 : 12479 => Opcode::C_LDSP,
26322 0 : 12480 => Opcode::C_LH,
26323 0 : 12481 => Opcode::C_LHU,
26324 0 : 12482 => Opcode::C_LI,
26325 0 : 12483 => Opcode::C_LI_HINT,
26326 0 : 12484 => Opcode::C_LUI,
26327 0 : 12485 => Opcode::C_LUI_HINT,
26328 0 : 12486 => Opcode::C_LW,
26329 0 : 12487 => Opcode::C_LWSP,
26330 0 : 12488 => Opcode::C_MOP1,
26331 0 : 12489 => Opcode::C_MOP11,
26332 0 : 12490 => Opcode::C_MOP13,
26333 0 : 12491 => Opcode::C_MOP15,
26334 0 : 12492 => Opcode::C_MOP3,
26335 0 : 12493 => Opcode::C_MOP5,
26336 0 : 12494 => Opcode::C_MOP7,
26337 0 : 12495 => Opcode::C_MOP9,
26338 0 : 12496 => Opcode::C_MUL,
26339 0 : 12497 => Opcode::C_MV,
26340 0 : 12498 => Opcode::C_MV_HINT,
26341 0 : 12499 => Opcode::C_NOP,
26342 0 : 12500 => Opcode::C_NOP_HINT,
26343 0 : 12501 => Opcode::C_NOT,
26344 0 : 12502 => Opcode::C_OR,
26345 0 : 12503 => Opcode::C_SB,
26346 0 : 12504 => Opcode::C_SD,
26347 0 : 12505 => Opcode::C_SDSP,
26348 0 : 12506 => Opcode::C_SEXT_B,
26349 0 : 12507 => Opcode::C_SEXT_H,
26350 0 : 12508 => Opcode::C_SH,
26351 0 : 12509 => Opcode::C_SLLI,
26352 0 : 12510 => Opcode::C_SLLI64_HINT,
26353 0 : 12511 => Opcode::C_SLLI_HINT,
26354 0 : 12512 => Opcode::C_SRAI,
26355 0 : 12513 => Opcode::C_SRAI64_HINT,
26356 0 : 12514 => Opcode::C_SRLI,
26357 0 : 12515 => Opcode::C_SRLI64_HINT,
26358 0 : 12516 => Opcode::C_SSPOPCHK,
26359 0 : 12517 => Opcode::C_SSPUSH,
26360 0 : 12518 => Opcode::C_SUB,
26361 0 : 12519 => Opcode::C_SUBW,
26362 0 : 12520 => Opcode::C_SW,
26363 0 : 12521 => Opcode::C_SWSP,
26364 0 : 12522 => Opcode::C_UNIMP,
26365 0 : 12523 => Opcode::C_XOR,
26366 0 : 12524 => Opcode::C_ZEXT_B,
26367 0 : 12525 => Opcode::C_ZEXT_H,
26368 0 : 12526 => Opcode::C_ZEXT_W,
26369 0 : 12527 => Opcode::DIV,
26370 0 : 12528 => Opcode::DIVU,
26371 0 : 12529 => Opcode::DIVUW,
26372 0 : 12530 => Opcode::DIVW,
26373 0 : 12531 => Opcode::DRET,
26374 0 : 12532 => Opcode::EBREAK,
26375 0 : 12533 => Opcode::ECALL,
26376 0 : 12534 => Opcode::FADD_D,
26377 0 : 12535 => Opcode::FADD_D_IN32X,
26378 0 : 12536 => Opcode::FADD_D_INX,
26379 0 : 12537 => Opcode::FADD_H,
26380 0 : 12538 => Opcode::FADD_H_INX,
26381 0 : 12539 => Opcode::FADD_S,
26382 0 : 12540 => Opcode::FADD_S_INX,
26383 0 : 12541 => Opcode::FCLASS_D,
26384 0 : 12542 => Opcode::FCLASS_D_IN32X,
26385 0 : 12543 => Opcode::FCLASS_D_INX,
26386 0 : 12544 => Opcode::FCLASS_H,
26387 0 : 12545 => Opcode::FCLASS_H_INX,
26388 0 : 12546 => Opcode::FCLASS_S,
26389 0 : 12547 => Opcode::FCLASS_S_INX,
26390 0 : 12548 => Opcode::FCVTMOD_W_D,
26391 0 : 12549 => Opcode::FCVT_BF16_S,
26392 0 : 12550 => Opcode::FCVT_D_H,
26393 0 : 12551 => Opcode::FCVT_D_H_IN32X,
26394 0 : 12552 => Opcode::FCVT_D_H_INX,
26395 0 : 12553 => Opcode::FCVT_D_L,
26396 0 : 12554 => Opcode::FCVT_D_LU,
26397 0 : 12555 => Opcode::FCVT_D_LU_INX,
26398 0 : 12556 => Opcode::FCVT_D_L_INX,
26399 0 : 12557 => Opcode::FCVT_D_S,
26400 0 : 12558 => Opcode::FCVT_D_S_IN32X,
26401 0 : 12559 => Opcode::FCVT_D_S_INX,
26402 0 : 12560 => Opcode::FCVT_D_W,
26403 0 : 12561 => Opcode::FCVT_D_WU,
26404 0 : 12562 => Opcode::FCVT_D_WU_IN32X,
26405 0 : 12563 => Opcode::FCVT_D_WU_INX,
26406 0 : 12564 => Opcode::FCVT_D_W_IN32X,
26407 0 : 12565 => Opcode::FCVT_D_W_INX,
26408 0 : 12566 => Opcode::FCVT_H_D,
26409 0 : 12567 => Opcode::FCVT_H_D_IN32X,
26410 0 : 12568 => Opcode::FCVT_H_D_INX,
26411 0 : 12569 => Opcode::FCVT_H_L,
26412 0 : 12570 => Opcode::FCVT_H_LU,
26413 0 : 12571 => Opcode::FCVT_H_LU_INX,
26414 0 : 12572 => Opcode::FCVT_H_L_INX,
26415 0 : 12573 => Opcode::FCVT_H_S,
26416 0 : 12574 => Opcode::FCVT_H_S_INX,
26417 0 : 12575 => Opcode::FCVT_H_W,
26418 0 : 12576 => Opcode::FCVT_H_WU,
26419 0 : 12577 => Opcode::FCVT_H_WU_INX,
26420 0 : 12578 => Opcode::FCVT_H_W_INX,
26421 0 : 12579 => Opcode::FCVT_LU_D,
26422 0 : 12580 => Opcode::FCVT_LU_D_INX,
26423 0 : 12581 => Opcode::FCVT_LU_H,
26424 0 : 12582 => Opcode::FCVT_LU_H_INX,
26425 0 : 12583 => Opcode::FCVT_LU_S,
26426 0 : 12584 => Opcode::FCVT_LU_S_INX,
26427 0 : 12585 => Opcode::FCVT_L_D,
26428 0 : 12586 => Opcode::FCVT_L_D_INX,
26429 0 : 12587 => Opcode::FCVT_L_H,
26430 0 : 12588 => Opcode::FCVT_L_H_INX,
26431 0 : 12589 => Opcode::FCVT_L_S,
26432 0 : 12590 => Opcode::FCVT_L_S_INX,
26433 0 : 12591 => Opcode::FCVT_S_BF16,
26434 0 : 12592 => Opcode::FCVT_S_D,
26435 0 : 12593 => Opcode::FCVT_S_D_IN32X,
26436 0 : 12594 => Opcode::FCVT_S_D_INX,
26437 0 : 12595 => Opcode::FCVT_S_H,
26438 0 : 12596 => Opcode::FCVT_S_H_INX,
26439 0 : 12597 => Opcode::FCVT_S_L,
26440 0 : 12598 => Opcode::FCVT_S_LU,
26441 0 : 12599 => Opcode::FCVT_S_LU_INX,
26442 0 : 12600 => Opcode::FCVT_S_L_INX,
26443 0 : 12601 => Opcode::FCVT_S_W,
26444 0 : 12602 => Opcode::FCVT_S_WU,
26445 0 : 12603 => Opcode::FCVT_S_WU_INX,
26446 0 : 12604 => Opcode::FCVT_S_W_INX,
26447 0 : 12605 => Opcode::FCVT_WU_D,
26448 0 : 12606 => Opcode::FCVT_WU_D_IN32X,
26449 0 : 12607 => Opcode::FCVT_WU_D_INX,
26450 0 : 12608 => Opcode::FCVT_WU_H,
26451 0 : 12609 => Opcode::FCVT_WU_H_INX,
26452 0 : 12610 => Opcode::FCVT_WU_S,
26453 0 : 12611 => Opcode::FCVT_WU_S_INX,
26454 0 : 12612 => Opcode::FCVT_W_D,
26455 0 : 12613 => Opcode::FCVT_W_D_IN32X,
26456 0 : 12614 => Opcode::FCVT_W_D_INX,
26457 0 : 12615 => Opcode::FCVT_W_H,
26458 0 : 12616 => Opcode::FCVT_W_H_INX,
26459 0 : 12617 => Opcode::FCVT_W_S,
26460 0 : 12618 => Opcode::FCVT_W_S_INX,
26461 0 : 12619 => Opcode::FDIV_D,
26462 0 : 12620 => Opcode::FDIV_D_IN32X,
26463 0 : 12621 => Opcode::FDIV_D_INX,
26464 0 : 12622 => Opcode::FDIV_H,
26465 0 : 12623 => Opcode::FDIV_H_INX,
26466 0 : 12624 => Opcode::FDIV_S,
26467 0 : 12625 => Opcode::FDIV_S_INX,
26468 0 : 12626 => Opcode::FENCE,
26469 0 : 12627 => Opcode::FENCE_I,
26470 0 : 12628 => Opcode::FENCE_TSO,
26471 0 : 12629 => Opcode::FEQ_D,
26472 0 : 12630 => Opcode::FEQ_D_IN32X,
26473 0 : 12631 => Opcode::FEQ_D_INX,
26474 0 : 12632 => Opcode::FEQ_H,
26475 0 : 12633 => Opcode::FEQ_H_INX,
26476 0 : 12634 => Opcode::FEQ_S,
26477 0 : 12635 => Opcode::FEQ_S_INX,
26478 0 : 12636 => Opcode::FLD,
26479 0 : 12637 => Opcode::FLEQ_D,
26480 0 : 12638 => Opcode::FLEQ_H,
26481 0 : 12639 => Opcode::FLEQ_S,
26482 0 : 12640 => Opcode::FLE_D,
26483 0 : 12641 => Opcode::FLE_D_IN32X,
26484 0 : 12642 => Opcode::FLE_D_INX,
26485 0 : 12643 => Opcode::FLE_H,
26486 0 : 12644 => Opcode::FLE_H_INX,
26487 0 : 12645 => Opcode::FLE_S,
26488 0 : 12646 => Opcode::FLE_S_INX,
26489 0 : 12647 => Opcode::FLH,
26490 0 : 12648 => Opcode::FLI_D,
26491 0 : 12649 => Opcode::FLI_H,
26492 0 : 12650 => Opcode::FLI_S,
26493 0 : 12651 => Opcode::FLTQ_D,
26494 0 : 12652 => Opcode::FLTQ_H,
26495 0 : 12653 => Opcode::FLTQ_S,
26496 0 : 12654 => Opcode::FLT_D,
26497 0 : 12655 => Opcode::FLT_D_IN32X,
26498 0 : 12656 => Opcode::FLT_D_INX,
26499 0 : 12657 => Opcode::FLT_H,
26500 0 : 12658 => Opcode::FLT_H_INX,
26501 0 : 12659 => Opcode::FLT_S,
26502 0 : 12660 => Opcode::FLT_S_INX,
26503 0 : 12661 => Opcode::FLW,
26504 0 : 12662 => Opcode::FMADD_D,
26505 0 : 12663 => Opcode::FMADD_D_IN32X,
26506 0 : 12664 => Opcode::FMADD_D_INX,
26507 0 : 12665 => Opcode::FMADD_H,
26508 0 : 12666 => Opcode::FMADD_H_INX,
26509 0 : 12667 => Opcode::FMADD_S,
26510 0 : 12668 => Opcode::FMADD_S_INX,
26511 0 : 12669 => Opcode::FMAXM_D,
26512 0 : 12670 => Opcode::FMAXM_H,
26513 0 : 12671 => Opcode::FMAXM_S,
26514 0 : 12672 => Opcode::FMAX_D,
26515 0 : 12673 => Opcode::FMAX_D_IN32X,
26516 0 : 12674 => Opcode::FMAX_D_INX,
26517 0 : 12675 => Opcode::FMAX_H,
26518 0 : 12676 => Opcode::FMAX_H_INX,
26519 0 : 12677 => Opcode::FMAX_S,
26520 0 : 12678 => Opcode::FMAX_S_INX,
26521 0 : 12679 => Opcode::FMINM_D,
26522 0 : 12680 => Opcode::FMINM_H,
26523 0 : 12681 => Opcode::FMINM_S,
26524 0 : 12682 => Opcode::FMIN_D,
26525 0 : 12683 => Opcode::FMIN_D_IN32X,
26526 0 : 12684 => Opcode::FMIN_D_INX,
26527 0 : 12685 => Opcode::FMIN_H,
26528 0 : 12686 => Opcode::FMIN_H_INX,
26529 0 : 12687 => Opcode::FMIN_S,
26530 0 : 12688 => Opcode::FMIN_S_INX,
26531 0 : 12689 => Opcode::FMSUB_D,
26532 0 : 12690 => Opcode::FMSUB_D_IN32X,
26533 0 : 12691 => Opcode::FMSUB_D_INX,
26534 0 : 12692 => Opcode::FMSUB_H,
26535 0 : 12693 => Opcode::FMSUB_H_INX,
26536 0 : 12694 => Opcode::FMSUB_S,
26537 0 : 12695 => Opcode::FMSUB_S_INX,
26538 0 : 12696 => Opcode::FMUL_D,
26539 0 : 12697 => Opcode::FMUL_D_IN32X,
26540 0 : 12698 => Opcode::FMUL_D_INX,
26541 0 : 12699 => Opcode::FMUL_H,
26542 0 : 12700 => Opcode::FMUL_H_INX,
26543 0 : 12701 => Opcode::FMUL_S,
26544 0 : 12702 => Opcode::FMUL_S_INX,
26545 0 : 12703 => Opcode::FMVH_X_D,
26546 0 : 12704 => Opcode::FMVP_D_X,
26547 0 : 12705 => Opcode::FMV_D_X,
26548 0 : 12706 => Opcode::FMV_H_X,
26549 0 : 12707 => Opcode::FMV_W_X,
26550 0 : 12708 => Opcode::FMV_X_D,
26551 0 : 12709 => Opcode::FMV_X_H,
26552 0 : 12710 => Opcode::FMV_X_W,
26553 0 : 12711 => Opcode::FMV_X_W_FPR64,
26554 0 : 12712 => Opcode::FNMADD_D,
26555 0 : 12713 => Opcode::FNMADD_D_IN32X,
26556 0 : 12714 => Opcode::FNMADD_D_INX,
26557 0 : 12715 => Opcode::FNMADD_H,
26558 0 : 12716 => Opcode::FNMADD_H_INX,
26559 0 : 12717 => Opcode::FNMADD_S,
26560 0 : 12718 => Opcode::FNMADD_S_INX,
26561 0 : 12719 => Opcode::FNMSUB_D,
26562 0 : 12720 => Opcode::FNMSUB_D_IN32X,
26563 0 : 12721 => Opcode::FNMSUB_D_INX,
26564 0 : 12722 => Opcode::FNMSUB_H,
26565 0 : 12723 => Opcode::FNMSUB_H_INX,
26566 0 : 12724 => Opcode::FNMSUB_S,
26567 0 : 12725 => Opcode::FNMSUB_S_INX,
26568 0 : 12726 => Opcode::FROUNDNX_D,
26569 0 : 12727 => Opcode::FROUNDNX_H,
26570 0 : 12728 => Opcode::FROUNDNX_S,
26571 0 : 12729 => Opcode::FROUND_D,
26572 0 : 12730 => Opcode::FROUND_H,
26573 0 : 12731 => Opcode::FROUND_S,
26574 0 : 12732 => Opcode::FSD,
26575 0 : 12733 => Opcode::FSGNJN_D,
26576 0 : 12734 => Opcode::FSGNJN_D_IN32X,
26577 0 : 12735 => Opcode::FSGNJN_D_INX,
26578 0 : 12736 => Opcode::FSGNJN_H,
26579 0 : 12737 => Opcode::FSGNJN_H_INX,
26580 0 : 12738 => Opcode::FSGNJN_S,
26581 0 : 12739 => Opcode::FSGNJN_S_INX,
26582 0 : 12740 => Opcode::FSGNJX_D,
26583 0 : 12741 => Opcode::FSGNJX_D_IN32X,
26584 0 : 12742 => Opcode::FSGNJX_D_INX,
26585 0 : 12743 => Opcode::FSGNJX_H,
26586 0 : 12744 => Opcode::FSGNJX_H_INX,
26587 0 : 12745 => Opcode::FSGNJX_S,
26588 0 : 12746 => Opcode::FSGNJX_S_INX,
26589 0 : 12747 => Opcode::FSGNJ_D,
26590 0 : 12748 => Opcode::FSGNJ_D_IN32X,
26591 0 : 12749 => Opcode::FSGNJ_D_INX,
26592 0 : 12750 => Opcode::FSGNJ_H,
26593 0 : 12751 => Opcode::FSGNJ_H_INX,
26594 0 : 12752 => Opcode::FSGNJ_S,
26595 0 : 12753 => Opcode::FSGNJ_S_INX,
26596 0 : 12754 => Opcode::FSH,
26597 0 : 12755 => Opcode::FSQRT_D,
26598 0 : 12756 => Opcode::FSQRT_D_IN32X,
26599 0 : 12757 => Opcode::FSQRT_D_INX,
26600 0 : 12758 => Opcode::FSQRT_H,
26601 0 : 12759 => Opcode::FSQRT_H_INX,
26602 0 : 12760 => Opcode::FSQRT_S,
26603 0 : 12761 => Opcode::FSQRT_S_INX,
26604 0 : 12762 => Opcode::FSUB_D,
26605 0 : 12763 => Opcode::FSUB_D_IN32X,
26606 0 : 12764 => Opcode::FSUB_D_INX,
26607 0 : 12765 => Opcode::FSUB_H,
26608 0 : 12766 => Opcode::FSUB_H_INX,
26609 0 : 12767 => Opcode::FSUB_S,
26610 0 : 12768 => Opcode::FSUB_S_INX,
26611 0 : 12769 => Opcode::FSW,
26612 0 : 12770 => Opcode::HFENCE_GVMA,
26613 0 : 12771 => Opcode::HFENCE_VVMA,
26614 0 : 12772 => Opcode::HINVAL_GVMA,
26615 0 : 12773 => Opcode::HINVAL_VVMA,
26616 0 : 12774 => Opcode::HLVX_HU,
26617 0 : 12775 => Opcode::HLVX_WU,
26618 0 : 12776 => Opcode::HLV_B,
26619 0 : 12777 => Opcode::HLV_BU,
26620 0 : 12778 => Opcode::HLV_D,
26621 0 : 12779 => Opcode::HLV_H,
26622 0 : 12780 => Opcode::HLV_HU,
26623 0 : 12781 => Opcode::HLV_W,
26624 0 : 12782 => Opcode::HLV_WU,
26625 0 : 12783 => Opcode::HSV_B,
26626 0 : 12784 => Opcode::HSV_D,
26627 0 : 12785 => Opcode::HSV_H,
26628 0 : 12786 => Opcode::HSV_W,
26629 0 : 12787 => Opcode::Insn16,
26630 0 : 12788 => Opcode::Insn32,
26631 0 : 12789 => Opcode::InsnB,
26632 0 : 12790 => Opcode::InsnCA,
26633 0 : 12791 => Opcode::InsnCB,
26634 0 : 12792 => Opcode::InsnCI,
26635 0 : 12793 => Opcode::InsnCIW,
26636 0 : 12794 => Opcode::InsnCJ,
26637 0 : 12795 => Opcode::InsnCL,
26638 0 : 12796 => Opcode::InsnCR,
26639 0 : 12797 => Opcode::InsnCS,
26640 0 : 12798 => Opcode::InsnCSS,
26641 0 : 12799 => Opcode::InsnI,
26642 0 : 12800 => Opcode::InsnI_Mem,
26643 0 : 12801 => Opcode::InsnJ,
26644 0 : 12802 => Opcode::InsnR,
26645 0 : 12803 => Opcode::InsnR4,
26646 0 : 12804 => Opcode::InsnS,
26647 0 : 12805 => Opcode::InsnU,
26648 0 : 12806 => Opcode::JAL,
26649 0 : 12807 => Opcode::JALR,
26650 0 : 12808 => Opcode::LB,
26651 0 : 12809 => Opcode::LBU,
26652 0 : 12810 => Opcode::LB_AQ,
26653 0 : 12811 => Opcode::LB_AQ_RL,
26654 0 : 12812 => Opcode::LD,
26655 0 : 12813 => Opcode::LD_AQ,
26656 0 : 12814 => Opcode::LD_AQ_RL,
26657 0 : 12815 => Opcode::LH,
26658 0 : 12816 => Opcode::LHU,
26659 0 : 12817 => Opcode::LH_AQ,
26660 0 : 12818 => Opcode::LH_AQ_RL,
26661 0 : 12819 => Opcode::LR_D,
26662 0 : 12820 => Opcode::LR_D_AQ,
26663 0 : 12821 => Opcode::LR_D_AQ_RL,
26664 0 : 12822 => Opcode::LR_D_RL,
26665 0 : 12823 => Opcode::LR_W,
26666 0 : 12824 => Opcode::LR_W_AQ,
26667 0 : 12825 => Opcode::LR_W_AQ_RL,
26668 0 : 12826 => Opcode::LR_W_RL,
26669 0 : 12827 => Opcode::LUI,
26670 0 : 12828 => Opcode::LW,
26671 0 : 12829 => Opcode::LWU,
26672 0 : 12830 => Opcode::LW_AQ,
26673 0 : 12831 => Opcode::LW_AQ_RL,
26674 0 : 12832 => Opcode::MAX,
26675 0 : 12833 => Opcode::MAXU,
26676 0 : 12834 => Opcode::MIN,
26677 0 : 12835 => Opcode::MINU,
26678 0 : 12836 => Opcode::MOPR0,
26679 0 : 12837 => Opcode::MOPR1,
26680 0 : 12838 => Opcode::MOPR10,
26681 0 : 12839 => Opcode::MOPR11,
26682 0 : 12840 => Opcode::MOPR12,
26683 0 : 12841 => Opcode::MOPR13,
26684 0 : 12842 => Opcode::MOPR14,
26685 0 : 12843 => Opcode::MOPR15,
26686 0 : 12844 => Opcode::MOPR16,
26687 0 : 12845 => Opcode::MOPR17,
26688 0 : 12846 => Opcode::MOPR18,
26689 0 : 12847 => Opcode::MOPR19,
26690 0 : 12848 => Opcode::MOPR2,
26691 0 : 12849 => Opcode::MOPR20,
26692 0 : 12850 => Opcode::MOPR21,
26693 0 : 12851 => Opcode::MOPR22,
26694 0 : 12852 => Opcode::MOPR23,
26695 0 : 12853 => Opcode::MOPR24,
26696 0 : 12854 => Opcode::MOPR25,
26697 0 : 12855 => Opcode::MOPR26,
26698 0 : 12856 => Opcode::MOPR27,
26699 0 : 12857 => Opcode::MOPR28,
26700 0 : 12858 => Opcode::MOPR29,
26701 0 : 12859 => Opcode::MOPR3,
26702 0 : 12860 => Opcode::MOPR30,
26703 0 : 12861 => Opcode::MOPR31,
26704 0 : 12862 => Opcode::MOPR4,
26705 0 : 12863 => Opcode::MOPR5,
26706 0 : 12864 => Opcode::MOPR6,
26707 0 : 12865 => Opcode::MOPR7,
26708 0 : 12866 => Opcode::MOPR8,
26709 0 : 12867 => Opcode::MOPR9,
26710 0 : 12868 => Opcode::MOPRR0,
26711 0 : 12869 => Opcode::MOPRR1,
26712 0 : 12870 => Opcode::MOPRR2,
26713 0 : 12871 => Opcode::MOPRR3,
26714 0 : 12872 => Opcode::MOPRR4,
26715 0 : 12873 => Opcode::MOPRR5,
26716 0 : 12874 => Opcode::MOPRR6,
26717 0 : 12875 => Opcode::MOPRR7,
26718 0 : 12876 => Opcode::MRET,
26719 0 : 12877 => Opcode::MUL,
26720 0 : 12878 => Opcode::MULH,
26721 0 : 12879 => Opcode::MULHSU,
26722 0 : 12880 => Opcode::MULHU,
26723 0 : 12881 => Opcode::MULW,
26724 0 : 12882 => Opcode::OR,
26725 0 : 12883 => Opcode::ORC_B,
26726 0 : 12884 => Opcode::ORI,
26727 0 : 12885 => Opcode::ORN,
26728 0 : 12886 => Opcode::PACK,
26729 0 : 12887 => Opcode::PACKH,
26730 0 : 12888 => Opcode::PACKW,
26731 0 : 12889 => Opcode::PREFETCH_I,
26732 0 : 12890 => Opcode::PREFETCH_R,
26733 0 : 12891 => Opcode::PREFETCH_W,
26734 0 : 12892 => Opcode::QK_C_LBU,
26735 0 : 12893 => Opcode::QK_C_LBUSP,
26736 0 : 12894 => Opcode::QK_C_LHU,
26737 0 : 12895 => Opcode::QK_C_LHUSP,
26738 0 : 12896 => Opcode::QK_C_SB,
26739 0 : 12897 => Opcode::QK_C_SBSP,
26740 0 : 12898 => Opcode::QK_C_SH,
26741 0 : 12899 => Opcode::QK_C_SHSP,
26742 0 : 12900 => Opcode::REM,
26743 0 : 12901 => Opcode::REMU,
26744 0 : 12902 => Opcode::REMUW,
26745 0 : 12903 => Opcode::REMW,
26746 0 : 12904 => Opcode::REV8_RV32,
26747 0 : 12905 => Opcode::REV8_RV64,
26748 0 : 12906 => Opcode::ROL,
26749 0 : 12907 => Opcode::ROLW,
26750 0 : 12908 => Opcode::ROR,
26751 0 : 12909 => Opcode::RORI,
26752 0 : 12910 => Opcode::RORIW,
26753 0 : 12911 => Opcode::RORW,
26754 0 : 12912 => Opcode::SB,
26755 0 : 12913 => Opcode::SB_AQ_RL,
26756 0 : 12914 => Opcode::SB_RL,
26757 0 : 12915 => Opcode::SC_D,
26758 0 : 12916 => Opcode::SC_D_AQ,
26759 0 : 12917 => Opcode::SC_D_AQ_RL,
26760 0 : 12918 => Opcode::SC_D_RL,
26761 0 : 12919 => Opcode::SC_W,
26762 0 : 12920 => Opcode::SC_W_AQ,
26763 0 : 12921 => Opcode::SC_W_AQ_RL,
26764 0 : 12922 => Opcode::SC_W_RL,
26765 0 : 12923 => Opcode::SD,
26766 0 : 12924 => Opcode::SD_AQ_RL,
26767 0 : 12925 => Opcode::SD_RL,
26768 0 : 12926 => Opcode::SEXT_B,
26769 0 : 12927 => Opcode::SEXT_H,
26770 0 : 12928 => Opcode::SFENCE_INVAL_IR,
26771 0 : 12929 => Opcode::SFENCE_VMA,
26772 0 : 12930 => Opcode::SFENCE_W_INVAL,
26773 0 : 12931 => Opcode::SF_CDISCARD_D_L1,
26774 0 : 12932 => Opcode::SF_CEASE,
26775 0 : 12933 => Opcode::SF_CFLUSH_D_L1,
26776 0 : 12934 => Opcode::SH,
26777 0 : 12935 => Opcode::SH1ADD,
26778 0 : 12936 => Opcode::SH1ADD_UW,
26779 0 : 12937 => Opcode::SH2ADD,
26780 0 : 12938 => Opcode::SH2ADD_UW,
26781 0 : 12939 => Opcode::SH3ADD,
26782 0 : 12940 => Opcode::SH3ADD_UW,
26783 0 : 12941 => Opcode::SHA256SIG0,
26784 0 : 12942 => Opcode::SHA256SIG1,
26785 0 : 12943 => Opcode::SHA256SUM0,
26786 0 : 12944 => Opcode::SHA256SUM1,
26787 0 : 12945 => Opcode::SHA512SIG0,
26788 0 : 12946 => Opcode::SHA512SIG0H,
26789 0 : 12947 => Opcode::SHA512SIG0L,
26790 0 : 12948 => Opcode::SHA512SIG1,
26791 0 : 12949 => Opcode::SHA512SIG1H,
26792 0 : 12950 => Opcode::SHA512SIG1L,
26793 0 : 12951 => Opcode::SHA512SUM0,
26794 0 : 12952 => Opcode::SHA512SUM0R,
26795 0 : 12953 => Opcode::SHA512SUM1,
26796 0 : 12954 => Opcode::SHA512SUM1R,
26797 0 : 12955 => Opcode::SH_AQ_RL,
26798 0 : 12956 => Opcode::SH_RL,
26799 0 : 12957 => Opcode::SINVAL_VMA,
26800 0 : 12958 => Opcode::SLL,
26801 0 : 12959 => Opcode::SLLI,
26802 0 : 12960 => Opcode::SLLIW,
26803 0 : 12961 => Opcode::SLLI_UW,
26804 0 : 12962 => Opcode::SLLW,
26805 0 : 12963 => Opcode::SLT,
26806 0 : 12964 => Opcode::SLTI,
26807 0 : 12965 => Opcode::SLTIU,
26808 0 : 12966 => Opcode::SLTU,
26809 0 : 12967 => Opcode::SM3P0,
26810 0 : 12968 => Opcode::SM3P1,
26811 0 : 12969 => Opcode::SM4ED,
26812 0 : 12970 => Opcode::SM4KS,
26813 0 : 12971 => Opcode::SRA,
26814 0 : 12972 => Opcode::SRAI,
26815 0 : 12973 => Opcode::SRAIW,
26816 0 : 12974 => Opcode::SRAW,
26817 0 : 12975 => Opcode::SRET,
26818 0 : 12976 => Opcode::SRL,
26819 0 : 12977 => Opcode::SRLI,
26820 0 : 12978 => Opcode::SRLIW,
26821 0 : 12979 => Opcode::SRLW,
26822 0 : 12980 => Opcode::SSAMOSWAP_D,
26823 0 : 12981 => Opcode::SSAMOSWAP_D_AQ,
26824 0 : 12982 => Opcode::SSAMOSWAP_D_AQ_RL,
26825 0 : 12983 => Opcode::SSAMOSWAP_D_RL,
26826 0 : 12984 => Opcode::SSAMOSWAP_W,
26827 0 : 12985 => Opcode::SSAMOSWAP_W_AQ,
26828 0 : 12986 => Opcode::SSAMOSWAP_W_AQ_RL,
26829 0 : 12987 => Opcode::SSAMOSWAP_W_RL,
26830 0 : 12988 => Opcode::SSPOPCHK,
26831 0 : 12989 => Opcode::SSPUSH,
26832 0 : 12990 => Opcode::SSRDP,
26833 0 : 12991 => Opcode::SUB,
26834 0 : 12992 => Opcode::SUBW,
26835 0 : 12993 => Opcode::SW,
26836 0 : 12994 => Opcode::SW_AQ_RL,
26837 0 : 12995 => Opcode::SW_RL,
26838 0 : 12996 => Opcode::THVdotVMAQASU_VV,
26839 0 : 12997 => Opcode::THVdotVMAQASU_VX,
26840 0 : 12998 => Opcode::THVdotVMAQAUS_VX,
26841 0 : 12999 => Opcode::THVdotVMAQAU_VV,
26842 0 : 13000 => Opcode::THVdotVMAQAU_VX,
26843 0 : 13001 => Opcode::THVdotVMAQA_VV,
26844 0 : 13002 => Opcode::THVdotVMAQA_VX,
26845 0 : 13003 => Opcode::TH_ADDSL,
26846 0 : 13004 => Opcode::TH_DCACHE_CALL,
26847 0 : 13005 => Opcode::TH_DCACHE_CIALL,
26848 0 : 13006 => Opcode::TH_DCACHE_CIPA,
26849 0 : 13007 => Opcode::TH_DCACHE_CISW,
26850 0 : 13008 => Opcode::TH_DCACHE_CIVA,
26851 0 : 13009 => Opcode::TH_DCACHE_CPA,
26852 0 : 13010 => Opcode::TH_DCACHE_CPAL1,
26853 0 : 13011 => Opcode::TH_DCACHE_CSW,
26854 0 : 13012 => Opcode::TH_DCACHE_CVA,
26855 0 : 13013 => Opcode::TH_DCACHE_CVAL1,
26856 0 : 13014 => Opcode::TH_DCACHE_IALL,
26857 0 : 13015 => Opcode::TH_DCACHE_IPA,
26858 0 : 13016 => Opcode::TH_DCACHE_ISW,
26859 0 : 13017 => Opcode::TH_DCACHE_IVA,
26860 0 : 13018 => Opcode::TH_EXT,
26861 0 : 13019 => Opcode::TH_EXTU,
26862 0 : 13020 => Opcode::TH_FF0,
26863 0 : 13021 => Opcode::TH_FF1,
26864 0 : 13022 => Opcode::TH_FLRD,
26865 0 : 13023 => Opcode::TH_FLRW,
26866 0 : 13024 => Opcode::TH_FLURD,
26867 0 : 13025 => Opcode::TH_FLURW,
26868 0 : 13026 => Opcode::TH_FSRD,
26869 0 : 13027 => Opcode::TH_FSRW,
26870 0 : 13028 => Opcode::TH_FSURD,
26871 0 : 13029 => Opcode::TH_FSURW,
26872 0 : 13030 => Opcode::TH_ICACHE_IALL,
26873 0 : 13031 => Opcode::TH_ICACHE_IALLS,
26874 0 : 13032 => Opcode::TH_ICACHE_IPA,
26875 0 : 13033 => Opcode::TH_ICACHE_IVA,
26876 0 : 13034 => Opcode::TH_L2CACHE_CALL,
26877 0 : 13035 => Opcode::TH_L2CACHE_CIALL,
26878 0 : 13036 => Opcode::TH_L2CACHE_IALL,
26879 0 : 13037 => Opcode::TH_LBIA,
26880 0 : 13038 => Opcode::TH_LBIB,
26881 0 : 13039 => Opcode::TH_LBUIA,
26882 0 : 13040 => Opcode::TH_LBUIB,
26883 0 : 13041 => Opcode::TH_LDD,
26884 0 : 13042 => Opcode::TH_LDIA,
26885 0 : 13043 => Opcode::TH_LDIB,
26886 0 : 13044 => Opcode::TH_LHIA,
26887 0 : 13045 => Opcode::TH_LHIB,
26888 0 : 13046 => Opcode::TH_LHUIA,
26889 0 : 13047 => Opcode::TH_LHUIB,
26890 0 : 13048 => Opcode::TH_LRB,
26891 0 : 13049 => Opcode::TH_LRBU,
26892 0 : 13050 => Opcode::TH_LRD,
26893 0 : 13051 => Opcode::TH_LRH,
26894 0 : 13052 => Opcode::TH_LRHU,
26895 0 : 13053 => Opcode::TH_LRW,
26896 0 : 13054 => Opcode::TH_LRWU,
26897 0 : 13055 => Opcode::TH_LURB,
26898 0 : 13056 => Opcode::TH_LURBU,
26899 0 : 13057 => Opcode::TH_LURD,
26900 0 : 13058 => Opcode::TH_LURH,
26901 0 : 13059 => Opcode::TH_LURHU,
26902 0 : 13060 => Opcode::TH_LURW,
26903 0 : 13061 => Opcode::TH_LURWU,
26904 0 : 13062 => Opcode::TH_LWD,
26905 0 : 13063 => Opcode::TH_LWIA,
26906 0 : 13064 => Opcode::TH_LWIB,
26907 0 : 13065 => Opcode::TH_LWUD,
26908 0 : 13066 => Opcode::TH_LWUIA,
26909 0 : 13067 => Opcode::TH_LWUIB,
26910 0 : 13068 => Opcode::TH_MULA,
26911 0 : 13069 => Opcode::TH_MULAH,
26912 0 : 13070 => Opcode::TH_MULAW,
26913 0 : 13071 => Opcode::TH_MULS,
26914 0 : 13072 => Opcode::TH_MULSH,
26915 0 : 13073 => Opcode::TH_MULSW,
26916 0 : 13074 => Opcode::TH_MVEQZ,
26917 0 : 13075 => Opcode::TH_MVNEZ,
26918 0 : 13076 => Opcode::TH_REV,
26919 0 : 13077 => Opcode::TH_REVW,
26920 0 : 13078 => Opcode::TH_SBIA,
26921 0 : 13079 => Opcode::TH_SBIB,
26922 0 : 13080 => Opcode::TH_SDD,
26923 0 : 13081 => Opcode::TH_SDIA,
26924 0 : 13082 => Opcode::TH_SDIB,
26925 0 : 13083 => Opcode::TH_SFENCE_VMAS,
26926 0 : 13084 => Opcode::TH_SHIA,
26927 0 : 13085 => Opcode::TH_SHIB,
26928 0 : 13086 => Opcode::TH_SRB,
26929 0 : 13087 => Opcode::TH_SRD,
26930 0 : 13088 => Opcode::TH_SRH,
26931 0 : 13089 => Opcode::TH_SRRI,
26932 0 : 13090 => Opcode::TH_SRRIW,
26933 0 : 13091 => Opcode::TH_SRW,
26934 0 : 13092 => Opcode::TH_SURB,
26935 0 : 13093 => Opcode::TH_SURD,
26936 0 : 13094 => Opcode::TH_SURH,
26937 0 : 13095 => Opcode::TH_SURW,
26938 0 : 13096 => Opcode::TH_SWD,
26939 0 : 13097 => Opcode::TH_SWIA,
26940 0 : 13098 => Opcode::TH_SWIB,
26941 0 : 13099 => Opcode::TH_SYNC,
26942 0 : 13100 => Opcode::TH_SYNC_I,
26943 0 : 13101 => Opcode::TH_SYNC_IS,
26944 0 : 13102 => Opcode::TH_SYNC_S,
26945 0 : 13103 => Opcode::TH_TST,
26946 0 : 13104 => Opcode::TH_TSTNBZ,
26947 0 : 13105 => Opcode::UNIMP,
26948 0 : 13106 => Opcode::UNZIP_RV32,
26949 0 : 13107 => Opcode::VAADDU_VV,
26950 0 : 13108 => Opcode::VAADDU_VX,
26951 0 : 13109 => Opcode::VAADD_VV,
26952 0 : 13110 => Opcode::VAADD_VX,
26953 0 : 13111 => Opcode::VADC_VIM,
26954 0 : 13112 => Opcode::VADC_VVM,
26955 0 : 13113 => Opcode::VADC_VXM,
26956 0 : 13114 => Opcode::VADD_VI,
26957 0 : 13115 => Opcode::VADD_VV,
26958 0 : 13116 => Opcode::VADD_VX,
26959 0 : 13117 => Opcode::VAESDF_VS,
26960 0 : 13118 => Opcode::VAESDF_VV,
26961 0 : 13119 => Opcode::VAESDM_VS,
26962 0 : 13120 => Opcode::VAESDM_VV,
26963 0 : 13121 => Opcode::VAESEF_VS,
26964 0 : 13122 => Opcode::VAESEF_VV,
26965 0 : 13123 => Opcode::VAESEM_VS,
26966 0 : 13124 => Opcode::VAESEM_VV,
26967 0 : 13125 => Opcode::VAESKF1_VI,
26968 0 : 13126 => Opcode::VAESKF2_VI,
26969 0 : 13127 => Opcode::VAESZ_VS,
26970 0 : 13128 => Opcode::VANDN_VV,
26971 0 : 13129 => Opcode::VANDN_VX,
26972 0 : 13130 => Opcode::VAND_VI,
26973 0 : 13131 => Opcode::VAND_VV,
26974 0 : 13132 => Opcode::VAND_VX,
26975 0 : 13133 => Opcode::VASUBU_VV,
26976 0 : 13134 => Opcode::VASUBU_VX,
26977 0 : 13135 => Opcode::VASUB_VV,
26978 0 : 13136 => Opcode::VASUB_VX,
26979 0 : 13137 => Opcode::VBREV8_V,
26980 0 : 13138 => Opcode::VBREV_V,
26981 0 : 13139 => Opcode::VCLMULH_VV,
26982 0 : 13140 => Opcode::VCLMULH_VX,
26983 0 : 13141 => Opcode::VCLMUL_VV,
26984 0 : 13142 => Opcode::VCLMUL_VX,
26985 0 : 13143 => Opcode::VCLZ_V,
26986 0 : 13144 => Opcode::VCOMPRESS_VM,
26987 0 : 13145 => Opcode::VCPOP_M,
26988 0 : 13146 => Opcode::VCPOP_V,
26989 0 : 13147 => Opcode::VCTZ_V,
26990 0 : 13148 => Opcode::VC_FV,
26991 0 : 13149 => Opcode::VC_FVV,
26992 0 : 13150 => Opcode::VC_FVW,
26993 0 : 13151 => Opcode::VC_I,
26994 0 : 13152 => Opcode::VC_IV,
26995 0 : 13153 => Opcode::VC_IVV,
26996 0 : 13154 => Opcode::VC_IVW,
26997 0 : 13155 => Opcode::VC_VV,
26998 0 : 13156 => Opcode::VC_VVV,
26999 0 : 13157 => Opcode::VC_VVW,
27000 0 : 13158 => Opcode::VC_V_FV,
27001 0 : 13159 => Opcode::VC_V_FVV,
27002 0 : 13160 => Opcode::VC_V_FVW,
27003 0 : 13161 => Opcode::VC_V_I,
27004 0 : 13162 => Opcode::VC_V_IV,
27005 0 : 13163 => Opcode::VC_V_IVV,
27006 0 : 13164 => Opcode::VC_V_IVW,
27007 0 : 13165 => Opcode::VC_V_VV,
27008 0 : 13166 => Opcode::VC_V_VVV,
27009 0 : 13167 => Opcode::VC_V_VVW,
27010 0 : 13168 => Opcode::VC_V_X,
27011 0 : 13169 => Opcode::VC_V_XV,
27012 0 : 13170 => Opcode::VC_V_XVV,
27013 0 : 13171 => Opcode::VC_V_XVW,
27014 0 : 13172 => Opcode::VC_X,
27015 0 : 13173 => Opcode::VC_XV,
27016 0 : 13174 => Opcode::VC_XVV,
27017 0 : 13175 => Opcode::VC_XVW,
27018 0 : 13176 => Opcode::VDIVU_VV,
27019 0 : 13177 => Opcode::VDIVU_VX,
27020 0 : 13178 => Opcode::VDIV_VV,
27021 0 : 13179 => Opcode::VDIV_VX,
27022 0 : 13180 => Opcode::VFADD_VF,
27023 0 : 13181 => Opcode::VFADD_VV,
27024 0 : 13182 => Opcode::VFCLASS_V,
27025 0 : 13183 => Opcode::VFCVT_F_XU_V,
27026 0 : 13184 => Opcode::VFCVT_F_X_V,
27027 0 : 13185 => Opcode::VFCVT_RTZ_XU_F_V,
27028 0 : 13186 => Opcode::VFCVT_RTZ_X_F_V,
27029 0 : 13187 => Opcode::VFCVT_XU_F_V,
27030 0 : 13188 => Opcode::VFCVT_X_F_V,
27031 0 : 13189 => Opcode::VFDIV_VF,
27032 0 : 13190 => Opcode::VFDIV_VV,
27033 0 : 13191 => Opcode::VFIRST_M,
27034 0 : 13192 => Opcode::VFMACC_VF,
27035 0 : 13193 => Opcode::VFMACC_VV,
27036 0 : 13194 => Opcode::VFMADD_VF,
27037 0 : 13195 => Opcode::VFMADD_VV,
27038 0 : 13196 => Opcode::VFMAX_VF,
27039 0 : 13197 => Opcode::VFMAX_VV,
27040 0 : 13198 => Opcode::VFMERGE_VFM,
27041 0 : 13199 => Opcode::VFMIN_VF,
27042 0 : 13200 => Opcode::VFMIN_VV,
27043 0 : 13201 => Opcode::VFMSAC_VF,
27044 0 : 13202 => Opcode::VFMSAC_VV,
27045 0 : 13203 => Opcode::VFMSUB_VF,
27046 0 : 13204 => Opcode::VFMSUB_VV,
27047 0 : 13205 => Opcode::VFMUL_VF,
27048 0 : 13206 => Opcode::VFMUL_VV,
27049 0 : 13207 => Opcode::VFMV_F_S,
27050 0 : 13208 => Opcode::VFMV_S_F,
27051 0 : 13209 => Opcode::VFMV_V_F,
27052 0 : 13210 => Opcode::VFNCVTBF16_F_F_W,
27053 0 : 13211 => Opcode::VFNCVT_F_F_W,
27054 0 : 13212 => Opcode::VFNCVT_F_XU_W,
27055 0 : 13213 => Opcode::VFNCVT_F_X_W,
27056 0 : 13214 => Opcode::VFNCVT_ROD_F_F_W,
27057 0 : 13215 => Opcode::VFNCVT_RTZ_XU_F_W,
27058 0 : 13216 => Opcode::VFNCVT_RTZ_X_F_W,
27059 0 : 13217 => Opcode::VFNCVT_XU_F_W,
27060 0 : 13218 => Opcode::VFNCVT_X_F_W,
27061 0 : 13219 => Opcode::VFNMACC_VF,
27062 0 : 13220 => Opcode::VFNMACC_VV,
27063 0 : 13221 => Opcode::VFNMADD_VF,
27064 0 : 13222 => Opcode::VFNMADD_VV,
27065 0 : 13223 => Opcode::VFNMSAC_VF,
27066 0 : 13224 => Opcode::VFNMSAC_VV,
27067 0 : 13225 => Opcode::VFNMSUB_VF,
27068 0 : 13226 => Opcode::VFNMSUB_VV,
27069 0 : 13227 => Opcode::VFNRCLIP_XU_F_QF,
27070 0 : 13228 => Opcode::VFNRCLIP_X_F_QF,
27071 0 : 13229 => Opcode::VFRDIV_VF,
27072 0 : 13230 => Opcode::VFREC7_V,
27073 0 : 13231 => Opcode::VFREDMAX_VS,
27074 0 : 13232 => Opcode::VFREDMIN_VS,
27075 0 : 13233 => Opcode::VFREDOSUM_VS,
27076 0 : 13234 => Opcode::VFREDUSUM_VS,
27077 0 : 13235 => Opcode::VFRSQRT7_V,
27078 0 : 13236 => Opcode::VFRSUB_VF,
27079 0 : 13237 => Opcode::VFSGNJN_VF,
27080 0 : 13238 => Opcode::VFSGNJN_VV,
27081 0 : 13239 => Opcode::VFSGNJX_VF,
27082 0 : 13240 => Opcode::VFSGNJX_VV,
27083 0 : 13241 => Opcode::VFSGNJ_VF,
27084 0 : 13242 => Opcode::VFSGNJ_VV,
27085 0 : 13243 => Opcode::VFSLIDE1DOWN_VF,
27086 0 : 13244 => Opcode::VFSLIDE1UP_VF,
27087 0 : 13245 => Opcode::VFSQRT_V,
27088 0 : 13246 => Opcode::VFSUB_VF,
27089 0 : 13247 => Opcode::VFSUB_VV,
27090 0 : 13248 => Opcode::VFWADD_VF,
27091 0 : 13249 => Opcode::VFWADD_VV,
27092 0 : 13250 => Opcode::VFWADD_WF,
27093 0 : 13251 => Opcode::VFWADD_WV,
27094 0 : 13252 => Opcode::VFWCVTBF16_F_F_V,
27095 0 : 13253 => Opcode::VFWCVT_F_F_V,
27096 0 : 13254 => Opcode::VFWCVT_F_XU_V,
27097 0 : 13255 => Opcode::VFWCVT_F_X_V,
27098 0 : 13256 => Opcode::VFWCVT_RTZ_XU_F_V,
27099 0 : 13257 => Opcode::VFWCVT_RTZ_X_F_V,
27100 0 : 13258 => Opcode::VFWCVT_XU_F_V,
27101 0 : 13259 => Opcode::VFWCVT_X_F_V,
27102 0 : 13260 => Opcode::VFWMACCBF16_VF,
27103 0 : 13261 => Opcode::VFWMACCBF16_VV,
27104 0 : 13262 => Opcode::VFWMACC_4x4x4,
27105 0 : 13263 => Opcode::VFWMACC_VF,
27106 0 : 13264 => Opcode::VFWMACC_VV,
27107 0 : 13265 => Opcode::VFWMSAC_VF,
27108 0 : 13266 => Opcode::VFWMSAC_VV,
27109 0 : 13267 => Opcode::VFWMUL_VF,
27110 0 : 13268 => Opcode::VFWMUL_VV,
27111 0 : 13269 => Opcode::VFWNMACC_VF,
27112 0 : 13270 => Opcode::VFWNMACC_VV,
27113 0 : 13271 => Opcode::VFWNMSAC_VF,
27114 0 : 13272 => Opcode::VFWNMSAC_VV,
27115 0 : 13273 => Opcode::VFWREDOSUM_VS,
27116 0 : 13274 => Opcode::VFWREDUSUM_VS,
27117 0 : 13275 => Opcode::VFWSUB_VF,
27118 0 : 13276 => Opcode::VFWSUB_VV,
27119 0 : 13277 => Opcode::VFWSUB_WF,
27120 0 : 13278 => Opcode::VFWSUB_WV,
27121 0 : 13279 => Opcode::VGHSH_VV,
27122 0 : 13280 => Opcode::VGMUL_VV,
27123 0 : 13281 => Opcode::VID_V,
27124 0 : 13282 => Opcode::VIOTA_M,
27125 0 : 13283 => Opcode::VL1RE16_V,
27126 0 : 13284 => Opcode::VL1RE32_V,
27127 0 : 13285 => Opcode::VL1RE64_V,
27128 0 : 13286 => Opcode::VL1RE8_V,
27129 0 : 13287 => Opcode::VL2RE16_V,
27130 0 : 13288 => Opcode::VL2RE32_V,
27131 0 : 13289 => Opcode::VL2RE64_V,
27132 0 : 13290 => Opcode::VL2RE8_V,
27133 0 : 13291 => Opcode::VL4RE16_V,
27134 0 : 13292 => Opcode::VL4RE32_V,
27135 0 : 13293 => Opcode::VL4RE64_V,
27136 0 : 13294 => Opcode::VL4RE8_V,
27137 0 : 13295 => Opcode::VL8RE16_V,
27138 0 : 13296 => Opcode::VL8RE32_V,
27139 0 : 13297 => Opcode::VL8RE64_V,
27140 0 : 13298 => Opcode::VL8RE8_V,
27141 0 : 13299 => Opcode::VLE16FF_V,
27142 0 : 13300 => Opcode::VLE16_V,
27143 0 : 13301 => Opcode::VLE32FF_V,
27144 0 : 13302 => Opcode::VLE32_V,
27145 0 : 13303 => Opcode::VLE64FF_V,
27146 0 : 13304 => Opcode::VLE64_V,
27147 0 : 13305 => Opcode::VLE8FF_V,
27148 0 : 13306 => Opcode::VLE8_V,
27149 0 : 13307 => Opcode::VLM_V,
27150 0 : 13308 => Opcode::VLOXEI16_V,
27151 0 : 13309 => Opcode::VLOXEI32_V,
27152 0 : 13310 => Opcode::VLOXEI64_V,
27153 0 : 13311 => Opcode::VLOXEI8_V,
27154 0 : 13312 => Opcode::VLOXSEG2EI16_V,
27155 0 : 13313 => Opcode::VLOXSEG2EI32_V,
27156 0 : 13314 => Opcode::VLOXSEG2EI64_V,
27157 0 : 13315 => Opcode::VLOXSEG2EI8_V,
27158 0 : 13316 => Opcode::VLOXSEG3EI16_V,
27159 0 : 13317 => Opcode::VLOXSEG3EI32_V,
27160 0 : 13318 => Opcode::VLOXSEG3EI64_V,
27161 0 : 13319 => Opcode::VLOXSEG3EI8_V,
27162 0 : 13320 => Opcode::VLOXSEG4EI16_V,
27163 0 : 13321 => Opcode::VLOXSEG4EI32_V,
27164 0 : 13322 => Opcode::VLOXSEG4EI64_V,
27165 0 : 13323 => Opcode::VLOXSEG4EI8_V,
27166 0 : 13324 => Opcode::VLOXSEG5EI16_V,
27167 0 : 13325 => Opcode::VLOXSEG5EI32_V,
27168 0 : 13326 => Opcode::VLOXSEG5EI64_V,
27169 0 : 13327 => Opcode::VLOXSEG5EI8_V,
27170 0 : 13328 => Opcode::VLOXSEG6EI16_V,
27171 0 : 13329 => Opcode::VLOXSEG6EI32_V,
27172 0 : 13330 => Opcode::VLOXSEG6EI64_V,
27173 0 : 13331 => Opcode::VLOXSEG6EI8_V,
27174 0 : 13332 => Opcode::VLOXSEG7EI16_V,
27175 0 : 13333 => Opcode::VLOXSEG7EI32_V,
27176 0 : 13334 => Opcode::VLOXSEG7EI64_V,
27177 0 : 13335 => Opcode::VLOXSEG7EI8_V,
27178 0 : 13336 => Opcode::VLOXSEG8EI16_V,
27179 0 : 13337 => Opcode::VLOXSEG8EI32_V,
27180 0 : 13338 => Opcode::VLOXSEG8EI64_V,
27181 0 : 13339 => Opcode::VLOXSEG8EI8_V,
27182 0 : 13340 => Opcode::VLSE16_V,
27183 0 : 13341 => Opcode::VLSE32_V,
27184 0 : 13342 => Opcode::VLSE64_V,
27185 0 : 13343 => Opcode::VLSE8_V,
27186 0 : 13344 => Opcode::VLSEG2E16FF_V,
27187 0 : 13345 => Opcode::VLSEG2E16_V,
27188 0 : 13346 => Opcode::VLSEG2E32FF_V,
27189 0 : 13347 => Opcode::VLSEG2E32_V,
27190 0 : 13348 => Opcode::VLSEG2E64FF_V,
27191 0 : 13349 => Opcode::VLSEG2E64_V,
27192 0 : 13350 => Opcode::VLSEG2E8FF_V,
27193 0 : 13351 => Opcode::VLSEG2E8_V,
27194 0 : 13352 => Opcode::VLSEG3E16FF_V,
27195 0 : 13353 => Opcode::VLSEG3E16_V,
27196 0 : 13354 => Opcode::VLSEG3E32FF_V,
27197 0 : 13355 => Opcode::VLSEG3E32_V,
27198 0 : 13356 => Opcode::VLSEG3E64FF_V,
27199 0 : 13357 => Opcode::VLSEG3E64_V,
27200 0 : 13358 => Opcode::VLSEG3E8FF_V,
27201 0 : 13359 => Opcode::VLSEG3E8_V,
27202 0 : 13360 => Opcode::VLSEG4E16FF_V,
27203 0 : 13361 => Opcode::VLSEG4E16_V,
27204 0 : 13362 => Opcode::VLSEG4E32FF_V,
27205 0 : 13363 => Opcode::VLSEG4E32_V,
27206 0 : 13364 => Opcode::VLSEG4E64FF_V,
27207 0 : 13365 => Opcode::VLSEG4E64_V,
27208 0 : 13366 => Opcode::VLSEG4E8FF_V,
27209 0 : 13367 => Opcode::VLSEG4E8_V,
27210 0 : 13368 => Opcode::VLSEG5E16FF_V,
27211 0 : 13369 => Opcode::VLSEG5E16_V,
27212 0 : 13370 => Opcode::VLSEG5E32FF_V,
27213 0 : 13371 => Opcode::VLSEG5E32_V,
27214 0 : 13372 => Opcode::VLSEG5E64FF_V,
27215 0 : 13373 => Opcode::VLSEG5E64_V,
27216 0 : 13374 => Opcode::VLSEG5E8FF_V,
27217 0 : 13375 => Opcode::VLSEG5E8_V,
27218 0 : 13376 => Opcode::VLSEG6E16FF_V,
27219 0 : 13377 => Opcode::VLSEG6E16_V,
27220 0 : 13378 => Opcode::VLSEG6E32FF_V,
27221 0 : 13379 => Opcode::VLSEG6E32_V,
27222 0 : 13380 => Opcode::VLSEG6E64FF_V,
27223 0 : 13381 => Opcode::VLSEG6E64_V,
27224 0 : 13382 => Opcode::VLSEG6E8FF_V,
27225 0 : 13383 => Opcode::VLSEG6E8_V,
27226 0 : 13384 => Opcode::VLSEG7E16FF_V,
27227 0 : 13385 => Opcode::VLSEG7E16_V,
27228 0 : 13386 => Opcode::VLSEG7E32FF_V,
27229 0 : 13387 => Opcode::VLSEG7E32_V,
27230 0 : 13388 => Opcode::VLSEG7E64FF_V,
27231 0 : 13389 => Opcode::VLSEG7E64_V,
27232 0 : 13390 => Opcode::VLSEG7E8FF_V,
27233 0 : 13391 => Opcode::VLSEG7E8_V,
27234 0 : 13392 => Opcode::VLSEG8E16FF_V,
27235 0 : 13393 => Opcode::VLSEG8E16_V,
27236 0 : 13394 => Opcode::VLSEG8E32FF_V,
27237 0 : 13395 => Opcode::VLSEG8E32_V,
27238 0 : 13396 => Opcode::VLSEG8E64FF_V,
27239 0 : 13397 => Opcode::VLSEG8E64_V,
27240 0 : 13398 => Opcode::VLSEG8E8FF_V,
27241 0 : 13399 => Opcode::VLSEG8E8_V,
27242 0 : 13400 => Opcode::VLSSEG2E16_V,
27243 0 : 13401 => Opcode::VLSSEG2E32_V,
27244 0 : 13402 => Opcode::VLSSEG2E64_V,
27245 0 : 13403 => Opcode::VLSSEG2E8_V,
27246 0 : 13404 => Opcode::VLSSEG3E16_V,
27247 0 : 13405 => Opcode::VLSSEG3E32_V,
27248 0 : 13406 => Opcode::VLSSEG3E64_V,
27249 0 : 13407 => Opcode::VLSSEG3E8_V,
27250 0 : 13408 => Opcode::VLSSEG4E16_V,
27251 0 : 13409 => Opcode::VLSSEG4E32_V,
27252 0 : 13410 => Opcode::VLSSEG4E64_V,
27253 0 : 13411 => Opcode::VLSSEG4E8_V,
27254 0 : 13412 => Opcode::VLSSEG5E16_V,
27255 0 : 13413 => Opcode::VLSSEG5E32_V,
27256 0 : 13414 => Opcode::VLSSEG5E64_V,
27257 0 : 13415 => Opcode::VLSSEG5E8_V,
27258 0 : 13416 => Opcode::VLSSEG6E16_V,
27259 0 : 13417 => Opcode::VLSSEG6E32_V,
27260 0 : 13418 => Opcode::VLSSEG6E64_V,
27261 0 : 13419 => Opcode::VLSSEG6E8_V,
27262 0 : 13420 => Opcode::VLSSEG7E16_V,
27263 0 : 13421 => Opcode::VLSSEG7E32_V,
27264 0 : 13422 => Opcode::VLSSEG7E64_V,
27265 0 : 13423 => Opcode::VLSSEG7E8_V,
27266 0 : 13424 => Opcode::VLSSEG8E16_V,
27267 0 : 13425 => Opcode::VLSSEG8E32_V,
27268 0 : 13426 => Opcode::VLSSEG8E64_V,
27269 0 : 13427 => Opcode::VLSSEG8E8_V,
27270 0 : 13428 => Opcode::VLUXEI16_V,
27271 0 : 13429 => Opcode::VLUXEI32_V,
27272 0 : 13430 => Opcode::VLUXEI64_V,
27273 0 : 13431 => Opcode::VLUXEI8_V,
27274 0 : 13432 => Opcode::VLUXSEG2EI16_V,
27275 0 : 13433 => Opcode::VLUXSEG2EI32_V,
27276 0 : 13434 => Opcode::VLUXSEG2EI64_V,
27277 0 : 13435 => Opcode::VLUXSEG2EI8_V,
27278 0 : 13436 => Opcode::VLUXSEG3EI16_V,
27279 0 : 13437 => Opcode::VLUXSEG3EI32_V,
27280 0 : 13438 => Opcode::VLUXSEG3EI64_V,
27281 0 : 13439 => Opcode::VLUXSEG3EI8_V,
27282 0 : 13440 => Opcode::VLUXSEG4EI16_V,
27283 0 : 13441 => Opcode::VLUXSEG4EI32_V,
27284 0 : 13442 => Opcode::VLUXSEG4EI64_V,
27285 0 : 13443 => Opcode::VLUXSEG4EI8_V,
27286 0 : 13444 => Opcode::VLUXSEG5EI16_V,
27287 0 : 13445 => Opcode::VLUXSEG5EI32_V,
27288 0 : 13446 => Opcode::VLUXSEG5EI64_V,
27289 0 : 13447 => Opcode::VLUXSEG5EI8_V,
27290 0 : 13448 => Opcode::VLUXSEG6EI16_V,
27291 0 : 13449 => Opcode::VLUXSEG6EI32_V,
27292 0 : 13450 => Opcode::VLUXSEG6EI64_V,
27293 0 : 13451 => Opcode::VLUXSEG6EI8_V,
27294 0 : 13452 => Opcode::VLUXSEG7EI16_V,
27295 0 : 13453 => Opcode::VLUXSEG7EI32_V,
27296 0 : 13454 => Opcode::VLUXSEG7EI64_V,
27297 0 : 13455 => Opcode::VLUXSEG7EI8_V,
27298 0 : 13456 => Opcode::VLUXSEG8EI16_V,
27299 0 : 13457 => Opcode::VLUXSEG8EI32_V,
27300 0 : 13458 => Opcode::VLUXSEG8EI64_V,
27301 0 : 13459 => Opcode::VLUXSEG8EI8_V,
27302 0 : 13460 => Opcode::VMACC_VV,
27303 0 : 13461 => Opcode::VMACC_VX,
27304 0 : 13462 => Opcode::VMADC_VI,
27305 0 : 13463 => Opcode::VMADC_VIM,
27306 0 : 13464 => Opcode::VMADC_VV,
27307 0 : 13465 => Opcode::VMADC_VVM,
27308 0 : 13466 => Opcode::VMADC_VX,
27309 0 : 13467 => Opcode::VMADC_VXM,
27310 0 : 13468 => Opcode::VMADD_VV,
27311 0 : 13469 => Opcode::VMADD_VX,
27312 0 : 13470 => Opcode::VMANDN_MM,
27313 0 : 13471 => Opcode::VMAND_MM,
27314 0 : 13472 => Opcode::VMAXU_VV,
27315 0 : 13473 => Opcode::VMAXU_VX,
27316 0 : 13474 => Opcode::VMAX_VV,
27317 0 : 13475 => Opcode::VMAX_VX,
27318 0 : 13476 => Opcode::VMERGE_VIM,
27319 0 : 13477 => Opcode::VMERGE_VVM,
27320 0 : 13478 => Opcode::VMERGE_VXM,
27321 0 : 13479 => Opcode::VMFEQ_VF,
27322 0 : 13480 => Opcode::VMFEQ_VV,
27323 0 : 13481 => Opcode::VMFGE_VF,
27324 0 : 13482 => Opcode::VMFGT_VF,
27325 0 : 13483 => Opcode::VMFLE_VF,
27326 0 : 13484 => Opcode::VMFLE_VV,
27327 0 : 13485 => Opcode::VMFLT_VF,
27328 0 : 13486 => Opcode::VMFLT_VV,
27329 0 : 13487 => Opcode::VMFNE_VF,
27330 0 : 13488 => Opcode::VMFNE_VV,
27331 0 : 13489 => Opcode::VMINU_VV,
27332 0 : 13490 => Opcode::VMINU_VX,
27333 0 : 13491 => Opcode::VMIN_VV,
27334 0 : 13492 => Opcode::VMIN_VX,
27335 0 : 13493 => Opcode::VMNAND_MM,
27336 0 : 13494 => Opcode::VMNOR_MM,
27337 0 : 13495 => Opcode::VMORN_MM,
27338 0 : 13496 => Opcode::VMOR_MM,
27339 0 : 13497 => Opcode::VMSBC_VV,
27340 0 : 13498 => Opcode::VMSBC_VVM,
27341 0 : 13499 => Opcode::VMSBC_VX,
27342 0 : 13500 => Opcode::VMSBC_VXM,
27343 0 : 13501 => Opcode::VMSBF_M,
27344 0 : 13502 => Opcode::VMSEQ_VI,
27345 0 : 13503 => Opcode::VMSEQ_VV,
27346 0 : 13504 => Opcode::VMSEQ_VX,
27347 0 : 13505 => Opcode::VMSGTU_VI,
27348 0 : 13506 => Opcode::VMSGTU_VX,
27349 0 : 13507 => Opcode::VMSGT_VI,
27350 0 : 13508 => Opcode::VMSGT_VX,
27351 0 : 13509 => Opcode::VMSIF_M,
27352 0 : 13510 => Opcode::VMSLEU_VI,
27353 0 : 13511 => Opcode::VMSLEU_VV,
27354 0 : 13512 => Opcode::VMSLEU_VX,
27355 0 : 13513 => Opcode::VMSLE_VI,
27356 0 : 13514 => Opcode::VMSLE_VV,
27357 0 : 13515 => Opcode::VMSLE_VX,
27358 0 : 13516 => Opcode::VMSLTU_VV,
27359 0 : 13517 => Opcode::VMSLTU_VX,
27360 0 : 13518 => Opcode::VMSLT_VV,
27361 0 : 13519 => Opcode::VMSLT_VX,
27362 0 : 13520 => Opcode::VMSNE_VI,
27363 0 : 13521 => Opcode::VMSNE_VV,
27364 0 : 13522 => Opcode::VMSNE_VX,
27365 0 : 13523 => Opcode::VMSOF_M,
27366 0 : 13524 => Opcode::VMULHSU_VV,
27367 0 : 13525 => Opcode::VMULHSU_VX,
27368 0 : 13526 => Opcode::VMULHU_VV,
27369 0 : 13527 => Opcode::VMULHU_VX,
27370 0 : 13528 => Opcode::VMULH_VV,
27371 0 : 13529 => Opcode::VMULH_VX,
27372 0 : 13530 => Opcode::VMUL_VV,
27373 0 : 13531 => Opcode::VMUL_VX,
27374 0 : 13532 => Opcode::VMV1R_V,
27375 0 : 13533 => Opcode::VMV2R_V,
27376 0 : 13534 => Opcode::VMV4R_V,
27377 0 : 13535 => Opcode::VMV8R_V,
27378 0 : 13536 => Opcode::VMV_S_X,
27379 0 : 13537 => Opcode::VMV_V_I,
27380 0 : 13538 => Opcode::VMV_V_V,
27381 0 : 13539 => Opcode::VMV_V_X,
27382 0 : 13540 => Opcode::VMV_X_S,
27383 0 : 13541 => Opcode::VMXNOR_MM,
27384 0 : 13542 => Opcode::VMXOR_MM,
27385 0 : 13543 => Opcode::VNCLIPU_WI,
27386 0 : 13544 => Opcode::VNCLIPU_WV,
27387 0 : 13545 => Opcode::VNCLIPU_WX,
27388 0 : 13546 => Opcode::VNCLIP_WI,
27389 0 : 13547 => Opcode::VNCLIP_WV,
27390 0 : 13548 => Opcode::VNCLIP_WX,
27391 0 : 13549 => Opcode::VNMSAC_VV,
27392 0 : 13550 => Opcode::VNMSAC_VX,
27393 0 : 13551 => Opcode::VNMSUB_VV,
27394 0 : 13552 => Opcode::VNMSUB_VX,
27395 0 : 13553 => Opcode::VNSRA_WI,
27396 0 : 13554 => Opcode::VNSRA_WV,
27397 0 : 13555 => Opcode::VNSRA_WX,
27398 0 : 13556 => Opcode::VNSRL_WI,
27399 0 : 13557 => Opcode::VNSRL_WV,
27400 0 : 13558 => Opcode::VNSRL_WX,
27401 0 : 13559 => Opcode::VOR_VI,
27402 0 : 13560 => Opcode::VOR_VV,
27403 0 : 13561 => Opcode::VOR_VX,
27404 0 : 13562 => Opcode::VQMACCSU_2x8x2,
27405 0 : 13563 => Opcode::VQMACCSU_4x8x4,
27406 0 : 13564 => Opcode::VQMACCUS_2x8x2,
27407 0 : 13565 => Opcode::VQMACCUS_4x8x4,
27408 0 : 13566 => Opcode::VQMACCU_2x8x2,
27409 0 : 13567 => Opcode::VQMACCU_4x8x4,
27410 0 : 13568 => Opcode::VQMACC_2x8x2,
27411 0 : 13569 => Opcode::VQMACC_4x8x4,
27412 0 : 13570 => Opcode::VREDAND_VS,
27413 0 : 13571 => Opcode::VREDMAXU_VS,
27414 0 : 13572 => Opcode::VREDMAX_VS,
27415 0 : 13573 => Opcode::VREDMINU_VS,
27416 0 : 13574 => Opcode::VREDMIN_VS,
27417 0 : 13575 => Opcode::VREDOR_VS,
27418 0 : 13576 => Opcode::VREDSUM_VS,
27419 0 : 13577 => Opcode::VREDXOR_VS,
27420 0 : 13578 => Opcode::VREMU_VV,
27421 0 : 13579 => Opcode::VREMU_VX,
27422 0 : 13580 => Opcode::VREM_VV,
27423 0 : 13581 => Opcode::VREM_VX,
27424 0 : 13582 => Opcode::VREV8_V,
27425 0 : 13583 => Opcode::VRGATHEREI16_VV,
27426 0 : 13584 => Opcode::VRGATHER_VI,
27427 0 : 13585 => Opcode::VRGATHER_VV,
27428 0 : 13586 => Opcode::VRGATHER_VX,
27429 0 : 13587 => Opcode::VROL_VV,
27430 0 : 13588 => Opcode::VROL_VX,
27431 0 : 13589 => Opcode::VROR_VI,
27432 0 : 13590 => Opcode::VROR_VV,
27433 0 : 13591 => Opcode::VROR_VX,
27434 0 : 13592 => Opcode::VRSUB_VI,
27435 0 : 13593 => Opcode::VRSUB_VX,
27436 0 : 13594 => Opcode::VS1R_V,
27437 0 : 13595 => Opcode::VS2R_V,
27438 0 : 13596 => Opcode::VS4R_V,
27439 0 : 13597 => Opcode::VS8R_V,
27440 0 : 13598 => Opcode::VSADDU_VI,
27441 0 : 13599 => Opcode::VSADDU_VV,
27442 0 : 13600 => Opcode::VSADDU_VX,
27443 0 : 13601 => Opcode::VSADD_VI,
27444 0 : 13602 => Opcode::VSADD_VV,
27445 0 : 13603 => Opcode::VSADD_VX,
27446 0 : 13604 => Opcode::VSBC_VVM,
27447 0 : 13605 => Opcode::VSBC_VXM,
27448 0 : 13606 => Opcode::VSE16_V,
27449 0 : 13607 => Opcode::VSE32_V,
27450 0 : 13608 => Opcode::VSE64_V,
27451 0 : 13609 => Opcode::VSE8_V,
27452 0 : 13610 => Opcode::VSETIVLI,
27453 0 : 13611 => Opcode::VSETVL,
27454 0 : 13612 => Opcode::VSETVLI,
27455 0 : 13613 => Opcode::VSEXT_VF2,
27456 0 : 13614 => Opcode::VSEXT_VF4,
27457 0 : 13615 => Opcode::VSEXT_VF8,
27458 0 : 13616 => Opcode::VSHA2CH_VV,
27459 0 : 13617 => Opcode::VSHA2CL_VV,
27460 0 : 13618 => Opcode::VSHA2MS_VV,
27461 0 : 13619 => Opcode::VSLIDE1DOWN_VX,
27462 0 : 13620 => Opcode::VSLIDE1UP_VX,
27463 0 : 13621 => Opcode::VSLIDEDOWN_VI,
27464 0 : 13622 => Opcode::VSLIDEDOWN_VX,
27465 0 : 13623 => Opcode::VSLIDEUP_VI,
27466 0 : 13624 => Opcode::VSLIDEUP_VX,
27467 0 : 13625 => Opcode::VSLL_VI,
27468 0 : 13626 => Opcode::VSLL_VV,
27469 0 : 13627 => Opcode::VSLL_VX,
27470 0 : 13628 => Opcode::VSM3C_VI,
27471 0 : 13629 => Opcode::VSM3ME_VV,
27472 0 : 13630 => Opcode::VSM4K_VI,
27473 0 : 13631 => Opcode::VSM4R_VS,
27474 0 : 13632 => Opcode::VSM4R_VV,
27475 0 : 13633 => Opcode::VSMUL_VV,
27476 0 : 13634 => Opcode::VSMUL_VX,
27477 0 : 13635 => Opcode::VSM_V,
27478 0 : 13636 => Opcode::VSOXEI16_V,
27479 0 : 13637 => Opcode::VSOXEI32_V,
27480 0 : 13638 => Opcode::VSOXEI64_V,
27481 0 : 13639 => Opcode::VSOXEI8_V,
27482 0 : 13640 => Opcode::VSOXSEG2EI16_V,
27483 0 : 13641 => Opcode::VSOXSEG2EI32_V,
27484 0 : 13642 => Opcode::VSOXSEG2EI64_V,
27485 0 : 13643 => Opcode::VSOXSEG2EI8_V,
27486 0 : 13644 => Opcode::VSOXSEG3EI16_V,
27487 0 : 13645 => Opcode::VSOXSEG3EI32_V,
27488 0 : 13646 => Opcode::VSOXSEG3EI64_V,
27489 0 : 13647 => Opcode::VSOXSEG3EI8_V,
27490 0 : 13648 => Opcode::VSOXSEG4EI16_V,
27491 0 : 13649 => Opcode::VSOXSEG4EI32_V,
27492 0 : 13650 => Opcode::VSOXSEG4EI64_V,
27493 0 : 13651 => Opcode::VSOXSEG4EI8_V,
27494 0 : 13652 => Opcode::VSOXSEG5EI16_V,
27495 0 : 13653 => Opcode::VSOXSEG5EI32_V,
27496 0 : 13654 => Opcode::VSOXSEG5EI64_V,
27497 0 : 13655 => Opcode::VSOXSEG5EI8_V,
27498 0 : 13656 => Opcode::VSOXSEG6EI16_V,
27499 0 : 13657 => Opcode::VSOXSEG6EI32_V,
27500 0 : 13658 => Opcode::VSOXSEG6EI64_V,
27501 0 : 13659 => Opcode::VSOXSEG6EI8_V,
27502 0 : 13660 => Opcode::VSOXSEG7EI16_V,
27503 0 : 13661 => Opcode::VSOXSEG7EI32_V,
27504 0 : 13662 => Opcode::VSOXSEG7EI64_V,
27505 0 : 13663 => Opcode::VSOXSEG7EI8_V,
27506 0 : 13664 => Opcode::VSOXSEG8EI16_V,
27507 0 : 13665 => Opcode::VSOXSEG8EI32_V,
27508 0 : 13666 => Opcode::VSOXSEG8EI64_V,
27509 0 : 13667 => Opcode::VSOXSEG8EI8_V,
27510 0 : 13668 => Opcode::VSRA_VI,
27511 0 : 13669 => Opcode::VSRA_VV,
27512 0 : 13670 => Opcode::VSRA_VX,
27513 0 : 13671 => Opcode::VSRL_VI,
27514 0 : 13672 => Opcode::VSRL_VV,
27515 0 : 13673 => Opcode::VSRL_VX,
27516 0 : 13674 => Opcode::VSSE16_V,
27517 0 : 13675 => Opcode::VSSE32_V,
27518 0 : 13676 => Opcode::VSSE64_V,
27519 0 : 13677 => Opcode::VSSE8_V,
27520 0 : 13678 => Opcode::VSSEG2E16_V,
27521 0 : 13679 => Opcode::VSSEG2E32_V,
27522 0 : 13680 => Opcode::VSSEG2E64_V,
27523 0 : 13681 => Opcode::VSSEG2E8_V,
27524 0 : 13682 => Opcode::VSSEG3E16_V,
27525 0 : 13683 => Opcode::VSSEG3E32_V,
27526 0 : 13684 => Opcode::VSSEG3E64_V,
27527 0 : 13685 => Opcode::VSSEG3E8_V,
27528 0 : 13686 => Opcode::VSSEG4E16_V,
27529 0 : 13687 => Opcode::VSSEG4E32_V,
27530 0 : 13688 => Opcode::VSSEG4E64_V,
27531 0 : 13689 => Opcode::VSSEG4E8_V,
27532 0 : 13690 => Opcode::VSSEG5E16_V,
27533 0 : 13691 => Opcode::VSSEG5E32_V,
27534 0 : 13692 => Opcode::VSSEG5E64_V,
27535 0 : 13693 => Opcode::VSSEG5E8_V,
27536 0 : 13694 => Opcode::VSSEG6E16_V,
27537 0 : 13695 => Opcode::VSSEG6E32_V,
27538 0 : 13696 => Opcode::VSSEG6E64_V,
27539 0 : 13697 => Opcode::VSSEG6E8_V,
27540 0 : 13698 => Opcode::VSSEG7E16_V,
27541 0 : 13699 => Opcode::VSSEG7E32_V,
27542 0 : 13700 => Opcode::VSSEG7E64_V,
27543 0 : 13701 => Opcode::VSSEG7E8_V,
27544 0 : 13702 => Opcode::VSSEG8E16_V,
27545 0 : 13703 => Opcode::VSSEG8E32_V,
27546 0 : 13704 => Opcode::VSSEG8E64_V,
27547 0 : 13705 => Opcode::VSSEG8E8_V,
27548 0 : 13706 => Opcode::VSSRA_VI,
27549 0 : 13707 => Opcode::VSSRA_VV,
27550 0 : 13708 => Opcode::VSSRA_VX,
27551 0 : 13709 => Opcode::VSSRL_VI,
27552 0 : 13710 => Opcode::VSSRL_VV,
27553 0 : 13711 => Opcode::VSSRL_VX,
27554 0 : 13712 => Opcode::VSSSEG2E16_V,
27555 0 : 13713 => Opcode::VSSSEG2E32_V,
27556 0 : 13714 => Opcode::VSSSEG2E64_V,
27557 0 : 13715 => Opcode::VSSSEG2E8_V,
27558 0 : 13716 => Opcode::VSSSEG3E16_V,
27559 0 : 13717 => Opcode::VSSSEG3E32_V,
27560 0 : 13718 => Opcode::VSSSEG3E64_V,
27561 0 : 13719 => Opcode::VSSSEG3E8_V,
27562 0 : 13720 => Opcode::VSSSEG4E16_V,
27563 0 : 13721 => Opcode::VSSSEG4E32_V,
27564 0 : 13722 => Opcode::VSSSEG4E64_V,
27565 0 : 13723 => Opcode::VSSSEG4E8_V,
27566 0 : 13724 => Opcode::VSSSEG5E16_V,
27567 0 : 13725 => Opcode::VSSSEG5E32_V,
27568 0 : 13726 => Opcode::VSSSEG5E64_V,
27569 0 : 13727 => Opcode::VSSSEG5E8_V,
27570 0 : 13728 => Opcode::VSSSEG6E16_V,
27571 0 : 13729 => Opcode::VSSSEG6E32_V,
27572 0 : 13730 => Opcode::VSSSEG6E64_V,
27573 0 : 13731 => Opcode::VSSSEG6E8_V,
27574 0 : 13732 => Opcode::VSSSEG7E16_V,
27575 0 : 13733 => Opcode::VSSSEG7E32_V,
27576 0 : 13734 => Opcode::VSSSEG7E64_V,
27577 0 : 13735 => Opcode::VSSSEG7E8_V,
27578 0 : 13736 => Opcode::VSSSEG8E16_V,
27579 0 : 13737 => Opcode::VSSSEG8E32_V,
27580 0 : 13738 => Opcode::VSSSEG8E64_V,
27581 0 : 13739 => Opcode::VSSSEG8E8_V,
27582 0 : 13740 => Opcode::VSSUBU_VV,
27583 0 : 13741 => Opcode::VSSUBU_VX,
27584 0 : 13742 => Opcode::VSSUB_VV,
27585 0 : 13743 => Opcode::VSSUB_VX,
27586 0 : 13744 => Opcode::VSUB_VV,
27587 0 : 13745 => Opcode::VSUB_VX,
27588 0 : 13746 => Opcode::VSUXEI16_V,
27589 0 : 13747 => Opcode::VSUXEI32_V,
27590 0 : 13748 => Opcode::VSUXEI64_V,
27591 0 : 13749 => Opcode::VSUXEI8_V,
27592 0 : 13750 => Opcode::VSUXSEG2EI16_V,
27593 0 : 13751 => Opcode::VSUXSEG2EI32_V,
27594 0 : 13752 => Opcode::VSUXSEG2EI64_V,
27595 0 : 13753 => Opcode::VSUXSEG2EI8_V,
27596 0 : 13754 => Opcode::VSUXSEG3EI16_V,
27597 0 : 13755 => Opcode::VSUXSEG3EI32_V,
27598 0 : 13756 => Opcode::VSUXSEG3EI64_V,
27599 0 : 13757 => Opcode::VSUXSEG3EI8_V,
27600 0 : 13758 => Opcode::VSUXSEG4EI16_V,
27601 0 : 13759 => Opcode::VSUXSEG4EI32_V,
27602 0 : 13760 => Opcode::VSUXSEG4EI64_V,
27603 0 : 13761 => Opcode::VSUXSEG4EI8_V,
27604 0 : 13762 => Opcode::VSUXSEG5EI16_V,
27605 0 : 13763 => Opcode::VSUXSEG5EI32_V,
27606 0 : 13764 => Opcode::VSUXSEG5EI64_V,
27607 0 : 13765 => Opcode::VSUXSEG5EI8_V,
27608 0 : 13766 => Opcode::VSUXSEG6EI16_V,
27609 0 : 13767 => Opcode::VSUXSEG6EI32_V,
27610 0 : 13768 => Opcode::VSUXSEG6EI64_V,
27611 0 : 13769 => Opcode::VSUXSEG6EI8_V,
27612 0 : 13770 => Opcode::VSUXSEG7EI16_V,
27613 0 : 13771 => Opcode::VSUXSEG7EI32_V,
27614 0 : 13772 => Opcode::VSUXSEG7EI64_V,
27615 0 : 13773 => Opcode::VSUXSEG7EI8_V,
27616 0 : 13774 => Opcode::VSUXSEG8EI16_V,
27617 0 : 13775 => Opcode::VSUXSEG8EI32_V,
27618 0 : 13776 => Opcode::VSUXSEG8EI64_V,
27619 0 : 13777 => Opcode::VSUXSEG8EI8_V,
27620 0 : 13778 => Opcode::VT_MASKC,
27621 0 : 13779 => Opcode::VT_MASKCN,
27622 0 : 13780 => Opcode::VWADDU_VV,
27623 0 : 13781 => Opcode::VWADDU_VX,
27624 0 : 13782 => Opcode::VWADDU_WV,
27625 0 : 13783 => Opcode::VWADDU_WX,
27626 0 : 13784 => Opcode::VWADD_VV,
27627 0 : 13785 => Opcode::VWADD_VX,
27628 0 : 13786 => Opcode::VWADD_WV,
27629 0 : 13787 => Opcode::VWADD_WX,
27630 0 : 13788 => Opcode::VWMACCSU_VV,
27631 0 : 13789 => Opcode::VWMACCSU_VX,
27632 0 : 13790 => Opcode::VWMACCUS_VX,
27633 0 : 13791 => Opcode::VWMACCU_VV,
27634 0 : 13792 => Opcode::VWMACCU_VX,
27635 0 : 13793 => Opcode::VWMACC_VV,
27636 0 : 13794 => Opcode::VWMACC_VX,
27637 0 : 13795 => Opcode::VWMULSU_VV,
27638 0 : 13796 => Opcode::VWMULSU_VX,
27639 0 : 13797 => Opcode::VWMULU_VV,
27640 0 : 13798 => Opcode::VWMULU_VX,
27641 0 : 13799 => Opcode::VWMUL_VV,
27642 0 : 13800 => Opcode::VWMUL_VX,
27643 0 : 13801 => Opcode::VWREDSUMU_VS,
27644 0 : 13802 => Opcode::VWREDSUM_VS,
27645 0 : 13803 => Opcode::VWSLL_VI,
27646 0 : 13804 => Opcode::VWSLL_VV,
27647 0 : 13805 => Opcode::VWSLL_VX,
27648 0 : 13806 => Opcode::VWSUBU_VV,
27649 0 : 13807 => Opcode::VWSUBU_VX,
27650 0 : 13808 => Opcode::VWSUBU_WV,
27651 0 : 13809 => Opcode::VWSUBU_WX,
27652 0 : 13810 => Opcode::VWSUB_VV,
27653 0 : 13811 => Opcode::VWSUB_VX,
27654 0 : 13812 => Opcode::VWSUB_WV,
27655 0 : 13813 => Opcode::VWSUB_WX,
27656 0 : 13814 => Opcode::VXOR_VI,
27657 0 : 13815 => Opcode::VXOR_VV,
27658 0 : 13816 => Opcode::VXOR_VX,
27659 0 : 13817 => Opcode::VZEXT_VF2,
27660 0 : 13818 => Opcode::VZEXT_VF4,
27661 0 : 13819 => Opcode::VZEXT_VF8,
27662 0 : 13820 => Opcode::WFI,
27663 0 : 13821 => Opcode::WRS_NTO,
27664 0 : 13822 => Opcode::WRS_STO,
27665 0 : 13823 => Opcode::XNOR,
27666 0 : 13824 => Opcode::XOR,
27667 0 : 13825 => Opcode::XORI,
27668 0 : 13826 => Opcode::XPERM4,
27669 0 : 13827 => Opcode::XPERM8,
27670 0 : 13828 => Opcode::ZEXT_H_RV32,
27671 0 : 13829 => Opcode::ZEXT_H_RV64,
27672 0 : 13830 => Opcode::ZIP_RV32,
27673 0 : 13831 => Opcode::INSTRUCTION_LIST_END,
27674 0 : _ => Opcode::UNKNOWN(value),
27675 : }
27676 0 : }
27677 : }
|
