Line data Source code
1 : #[allow(non_camel_case_types)]
2 0 : #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
3 : pub enum Opcode {
4 : PHI,
5 : INLINEASM,
6 : INLINEASM_BR,
7 : CFI_INSTRUCTION,
8 : EH_LABEL,
9 : GC_LABEL,
10 : ANNOTATION_LABEL,
11 : KILL,
12 : EXTRACT_SUBREG,
13 : INSERT_SUBREG,
14 : IMPLICIT_DEF,
15 : INIT_UNDEF,
16 : SUBREG_TO_REG,
17 : COPY_TO_REGCLASS,
18 : DBG_VALUE,
19 : DBG_VALUE_LIST,
20 : DBG_INSTR_REF,
21 : DBG_PHI,
22 : DBG_LABEL,
23 : REG_SEQUENCE,
24 : COPY,
25 : COPY_LANEMASK,
26 : BUNDLE,
27 : LIFETIME_START,
28 : LIFETIME_END,
29 : PSEUDO_PROBE,
30 : ARITH_FENCE,
31 : STACKMAP,
32 : FENTRY_CALL,
33 : PATCHPOINT,
34 : LOAD_STACK_GUARD,
35 : PREALLOCATED_SETUP,
36 : PREALLOCATED_ARG,
37 : STATEPOINT,
38 : LOCAL_ESCAPE,
39 : FAULTING_OP,
40 : PATCHABLE_OP,
41 : PATCHABLE_FUNCTION_ENTER,
42 : PATCHABLE_RET,
43 : PATCHABLE_FUNCTION_EXIT,
44 : PATCHABLE_TAIL_CALL,
45 : PATCHABLE_EVENT_CALL,
46 : PATCHABLE_TYPED_EVENT_CALL,
47 : ICALL_BRANCH_FUNNEL,
48 : FAKE_USE,
49 : MEMBARRIER,
50 : JUMP_TABLE_DEBUG_INFO,
51 : RELOC_NONE,
52 : CONVERGENCECTRL_ENTRY,
53 : CONVERGENCECTRL_ANCHOR,
54 : CONVERGENCECTRL_LOOP,
55 : CONVERGENCECTRL_GLUE,
56 : G_ASSERT_SEXT,
57 : G_ASSERT_ZEXT,
58 : G_ASSERT_ALIGN,
59 : G_ADD,
60 : G_SUB,
61 : G_MUL,
62 : G_SDIV,
63 : G_UDIV,
64 : G_SREM,
65 : G_UREM,
66 : G_SDIVREM,
67 : G_UDIVREM,
68 : G_AND,
69 : G_OR,
70 : G_XOR,
71 : G_ABDS,
72 : G_ABDU,
73 : G_UAVGFLOOR,
74 : G_UAVGCEIL,
75 : G_SAVGFLOOR,
76 : G_SAVGCEIL,
77 : G_IMPLICIT_DEF,
78 : G_PHI,
79 : G_FRAME_INDEX,
80 : G_GLOBAL_VALUE,
81 : G_PTRAUTH_GLOBAL_VALUE,
82 : G_CONSTANT_POOL,
83 : G_EXTRACT,
84 : G_UNMERGE_VALUES,
85 : G_INSERT,
86 : G_MERGE_VALUES,
87 : G_BUILD_VECTOR,
88 : G_BUILD_VECTOR_TRUNC,
89 : G_CONCAT_VECTORS,
90 : G_PTRTOINT,
91 : G_INTTOPTR,
92 : G_BITCAST,
93 : G_FREEZE,
94 : G_CONSTANT_FOLD_BARRIER,
95 : G_INTRINSIC_FPTRUNC_ROUND,
96 : G_INTRINSIC_TRUNC,
97 : G_INTRINSIC_ROUND,
98 : G_INTRINSIC_LRINT,
99 : G_INTRINSIC_LLRINT,
100 : G_INTRINSIC_ROUNDEVEN,
101 : G_READCYCLECOUNTER,
102 : G_READSTEADYCOUNTER,
103 : G_LOAD,
104 : G_SEXTLOAD,
105 : G_ZEXTLOAD,
106 : G_INDEXED_LOAD,
107 : G_INDEXED_SEXTLOAD,
108 : G_INDEXED_ZEXTLOAD,
109 : G_STORE,
110 : G_INDEXED_STORE,
111 : G_ATOMIC_CMPXCHG_WITH_SUCCESS,
112 : G_ATOMIC_CMPXCHG,
113 : G_ATOMICRMW_XCHG,
114 : G_ATOMICRMW_ADD,
115 : G_ATOMICRMW_SUB,
116 : G_ATOMICRMW_AND,
117 : G_ATOMICRMW_NAND,
118 : G_ATOMICRMW_OR,
119 : G_ATOMICRMW_XOR,
120 : G_ATOMICRMW_MAX,
121 : G_ATOMICRMW_MIN,
122 : G_ATOMICRMW_UMAX,
123 : G_ATOMICRMW_UMIN,
124 : G_ATOMICRMW_FADD,
125 : G_ATOMICRMW_FSUB,
126 : G_ATOMICRMW_FMAX,
127 : G_ATOMICRMW_FMIN,
128 : G_ATOMICRMW_FMAXIMUM,
129 : G_ATOMICRMW_FMINIMUM,
130 : G_ATOMICRMW_UINC_WRAP,
131 : G_ATOMICRMW_UDEC_WRAP,
132 : G_ATOMICRMW_USUB_COND,
133 : G_ATOMICRMW_USUB_SAT,
134 : G_FENCE,
135 : G_PREFETCH,
136 : G_BRCOND,
137 : G_BRINDIRECT,
138 : G_INVOKE_REGION_START,
139 : G_INTRINSIC,
140 : G_INTRINSIC_W_SIDE_EFFECTS,
141 : G_INTRINSIC_CONVERGENT,
142 : G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS,
143 : G_ANYEXT,
144 : G_TRUNC,
145 : G_TRUNC_SSAT_S,
146 : G_TRUNC_SSAT_U,
147 : G_TRUNC_USAT_U,
148 : G_CONSTANT,
149 : G_FCONSTANT,
150 : G_VASTART,
151 : G_VAARG,
152 : G_SEXT,
153 : G_SEXT_INREG,
154 : G_ZEXT,
155 : G_SHL,
156 : G_LSHR,
157 : G_ASHR,
158 : G_FSHL,
159 : G_FSHR,
160 : G_ROTR,
161 : G_ROTL,
162 : G_ICMP,
163 : G_FCMP,
164 : G_SCMP,
165 : G_UCMP,
166 : G_SELECT,
167 : G_UADDO,
168 : G_UADDE,
169 : G_USUBO,
170 : G_USUBE,
171 : G_SADDO,
172 : G_SADDE,
173 : G_SSUBO,
174 : G_SSUBE,
175 : G_UMULO,
176 : G_SMULO,
177 : G_UMULH,
178 : G_SMULH,
179 : G_UADDSAT,
180 : G_SADDSAT,
181 : G_USUBSAT,
182 : G_SSUBSAT,
183 : G_USHLSAT,
184 : G_SSHLSAT,
185 : G_SMULFIX,
186 : G_UMULFIX,
187 : G_SMULFIXSAT,
188 : G_UMULFIXSAT,
189 : G_SDIVFIX,
190 : G_UDIVFIX,
191 : G_SDIVFIXSAT,
192 : G_UDIVFIXSAT,
193 : G_FADD,
194 : G_FSUB,
195 : G_FMUL,
196 : G_FMA,
197 : G_FMAD,
198 : G_FDIV,
199 : G_FREM,
200 : G_FMODF,
201 : G_FPOW,
202 : G_FPOWI,
203 : G_FEXP,
204 : G_FEXP2,
205 : G_FEXP10,
206 : G_FLOG,
207 : G_FLOG2,
208 : G_FLOG10,
209 : G_FLDEXP,
210 : G_FFREXP,
211 : G_FNEG,
212 : G_FPEXT,
213 : G_FPTRUNC,
214 : G_FPTOSI,
215 : G_FPTOUI,
216 : G_SITOFP,
217 : G_UITOFP,
218 : G_FPTOSI_SAT,
219 : G_FPTOUI_SAT,
220 : G_FABS,
221 : G_FCOPYSIGN,
222 : G_IS_FPCLASS,
223 : G_FCANONICALIZE,
224 : G_FMINNUM,
225 : G_FMAXNUM,
226 : G_FMINNUM_IEEE,
227 : G_FMAXNUM_IEEE,
228 : G_FMINIMUM,
229 : G_FMAXIMUM,
230 : G_FMINIMUMNUM,
231 : G_FMAXIMUMNUM,
232 : G_GET_FPENV,
233 : G_SET_FPENV,
234 : G_RESET_FPENV,
235 : G_GET_FPMODE,
236 : G_SET_FPMODE,
237 : G_RESET_FPMODE,
238 : G_GET_ROUNDING,
239 : G_SET_ROUNDING,
240 : G_PTR_ADD,
241 : G_PTRMASK,
242 : G_SMIN,
243 : G_SMAX,
244 : G_UMIN,
245 : G_UMAX,
246 : G_ABS,
247 : G_LROUND,
248 : G_LLROUND,
249 : G_BR,
250 : G_BRJT,
251 : G_VSCALE,
252 : G_INSERT_SUBVECTOR,
253 : G_EXTRACT_SUBVECTOR,
254 : G_INSERT_VECTOR_ELT,
255 : G_EXTRACT_VECTOR_ELT,
256 : G_SHUFFLE_VECTOR,
257 : G_SPLAT_VECTOR,
258 : G_STEP_VECTOR,
259 : G_VECTOR_COMPRESS,
260 : G_CTTZ,
261 : G_CTTZ_ZERO_UNDEF,
262 : G_CTLZ,
263 : G_CTLZ_ZERO_UNDEF,
264 : G_CTPOP,
265 : G_BSWAP,
266 : G_BITREVERSE,
267 : G_FCEIL,
268 : G_FCOS,
269 : G_FSIN,
270 : G_FSINCOS,
271 : G_FTAN,
272 : G_FACOS,
273 : G_FASIN,
274 : G_FATAN,
275 : G_FATAN2,
276 : G_FCOSH,
277 : G_FSINH,
278 : G_FTANH,
279 : G_FSQRT,
280 : G_FFLOOR,
281 : G_FRINT,
282 : G_FNEARBYINT,
283 : G_ADDRSPACE_CAST,
284 : G_BLOCK_ADDR,
285 : G_JUMP_TABLE,
286 : G_DYN_STACKALLOC,
287 : G_STACKSAVE,
288 : G_STACKRESTORE,
289 : G_STRICT_FADD,
290 : G_STRICT_FSUB,
291 : G_STRICT_FMUL,
292 : G_STRICT_FDIV,
293 : G_STRICT_FREM,
294 : G_STRICT_FMA,
295 : G_STRICT_FSQRT,
296 : G_STRICT_FLDEXP,
297 : G_READ_REGISTER,
298 : G_WRITE_REGISTER,
299 : G_MEMCPY,
300 : G_MEMCPY_INLINE,
301 : G_MEMMOVE,
302 : G_MEMSET,
303 : G_BZERO,
304 : G_TRAP,
305 : G_DEBUGTRAP,
306 : G_UBSANTRAP,
307 : G_VECREDUCE_SEQ_FADD,
308 : G_VECREDUCE_SEQ_FMUL,
309 : G_VECREDUCE_FADD,
310 : G_VECREDUCE_FMUL,
311 : G_VECREDUCE_FMAX,
312 : G_VECREDUCE_FMIN,
313 : G_VECREDUCE_FMAXIMUM,
314 : G_VECREDUCE_FMINIMUM,
315 : G_VECREDUCE_ADD,
316 : G_VECREDUCE_MUL,
317 : G_VECREDUCE_AND,
318 : G_VECREDUCE_OR,
319 : G_VECREDUCE_XOR,
320 : G_VECREDUCE_SMAX,
321 : G_VECREDUCE_SMIN,
322 : G_VECREDUCE_UMAX,
323 : G_VECREDUCE_UMIN,
324 : G_SBFX,
325 : G_UBFX,
326 : ADDSri,
327 : ADDSrr,
328 : ADDSrsi,
329 : ADDSrsr,
330 : ADJCALLSTACKDOWN,
331 : ADJCALLSTACKUP,
332 : ASRi,
333 : ASRr,
334 : ASRs1,
335 : B,
336 : BCCZi64,
337 : BCCi64,
338 : BLX_noip,
339 : BLX_pred_noip,
340 : BL_PUSHLR,
341 : BMOVPCB_CALL,
342 : BMOVPCRX_CALL,
343 : BR_JTadd,
344 : BR_JTm_i12,
345 : BR_JTm_rs,
346 : BR_JTr,
347 : BX_CALL,
348 : CMP_SWAP_16,
349 : CMP_SWAP_32,
350 : CMP_SWAP_64,
351 : CMP_SWAP_8,
352 : CONSTPOOL_ENTRY,
353 : COPY_STRUCT_BYVAL_I32,
354 : ITasm,
355 : Int_eh_sjlj_dispatchsetup,
356 : Int_eh_sjlj_longjmp,
357 : Int_eh_sjlj_setjmp,
358 : Int_eh_sjlj_setjmp_nofp,
359 : Int_eh_sjlj_setup_dispatch,
360 : JUMPTABLE_ADDRS,
361 : JUMPTABLE_INSTS,
362 : JUMPTABLE_TBB,
363 : JUMPTABLE_TBH,
364 : KCFI_CHECK_ARM,
365 : KCFI_CHECK_Thumb1,
366 : KCFI_CHECK_Thumb2,
367 : LDMIA_RET,
368 : LDRBT_POST,
369 : LDRConstPool,
370 : LDRHTii,
371 : LDRLIT_ga_abs,
372 : LDRLIT_ga_pcrel,
373 : LDRLIT_ga_pcrel_ldr,
374 : LDRSBTii,
375 : LDRSHTii,
376 : LDRT_POST,
377 : LEApcrel,
378 : LEApcrelJT,
379 : LOADDUAL,
380 : LSLi,
381 : LSLr,
382 : LSRi,
383 : LSRr,
384 : LSRs1,
385 : MEMCPY,
386 : MLAv5,
387 : MOVCCi,
388 : MOVCCi16,
389 : MOVCCi32imm,
390 : MOVCCr,
391 : MOVCCsi,
392 : MOVCCsr,
393 : MOVPCRX,
394 : MOVTi16_ga_pcrel,
395 : MOV_ga_pcrel,
396 : MOV_ga_pcrel_ldr,
397 : MOVi16_ga_pcrel,
398 : MOVi32imm,
399 : MQPRCopy,
400 : MQQPRLoad,
401 : MQQPRStore,
402 : MQQQQPRLoad,
403 : MQQQQPRStore,
404 : MULv5,
405 : MVE_MEMCPYLOOPINST,
406 : MVE_MEMSETLOOPINST,
407 : MVNCCi,
408 : PICADD,
409 : PICLDR,
410 : PICLDRB,
411 : PICLDRH,
412 : PICLDRSB,
413 : PICLDRSH,
414 : PICSTR,
415 : PICSTRB,
416 : PICSTRH,
417 : RORi,
418 : RORr,
419 : RRX,
420 : RRXi,
421 : RSBSri,
422 : RSBSrsi,
423 : RSBSrsr,
424 : SEH_EpilogEnd,
425 : SEH_EpilogStart,
426 : SEH_Nop,
427 : SEH_Nop_Ret,
428 : SEH_PrologEnd,
429 : SEH_SaveFRegs,
430 : SEH_SaveLR,
431 : SEH_SaveRegs,
432 : SEH_SaveRegs_Ret,
433 : SEH_SaveSP,
434 : SEH_StackAlloc,
435 : SMLALv5,
436 : SMULLv5,
437 : SPACE,
438 : STOREDUAL,
439 : STRBT_POST,
440 : STRBi_preidx,
441 : STRBr_preidx,
442 : STRH_preidx,
443 : STRT_POST,
444 : STRi_preidx,
445 : STRr_preidx,
446 : SUBS_PC_LR,
447 : SUBSri,
448 : SUBSrr,
449 : SUBSrsi,
450 : SUBSrsr,
451 : SpeculationBarrierISBDSBEndBB,
452 : SpeculationBarrierSBEndBB,
453 : TAILJMPd,
454 : TAILJMPr,
455 : TAILJMPr4,
456 : TCRETURNdi,
457 : TCRETURNri,
458 : TCRETURNrinotr12,
459 : TPsoft,
460 : UMLALv5,
461 : UMULLv5,
462 : VLD1LNdAsm_16,
463 : VLD1LNdAsm_32,
464 : VLD1LNdAsm_8,
465 : VLD1LNdWB_fixed_Asm_16,
466 : VLD1LNdWB_fixed_Asm_32,
467 : VLD1LNdWB_fixed_Asm_8,
468 : VLD1LNdWB_register_Asm_16,
469 : VLD1LNdWB_register_Asm_32,
470 : VLD1LNdWB_register_Asm_8,
471 : VLD2LNdAsm_16,
472 : VLD2LNdAsm_32,
473 : VLD2LNdAsm_8,
474 : VLD2LNdWB_fixed_Asm_16,
475 : VLD2LNdWB_fixed_Asm_32,
476 : VLD2LNdWB_fixed_Asm_8,
477 : VLD2LNdWB_register_Asm_16,
478 : VLD2LNdWB_register_Asm_32,
479 : VLD2LNdWB_register_Asm_8,
480 : VLD2LNqAsm_16,
481 : VLD2LNqAsm_32,
482 : VLD2LNqWB_fixed_Asm_16,
483 : VLD2LNqWB_fixed_Asm_32,
484 : VLD2LNqWB_register_Asm_16,
485 : VLD2LNqWB_register_Asm_32,
486 : VLD3DUPdAsm_16,
487 : VLD3DUPdAsm_32,
488 : VLD3DUPdAsm_8,
489 : VLD3DUPdWB_fixed_Asm_16,
490 : VLD3DUPdWB_fixed_Asm_32,
491 : VLD3DUPdWB_fixed_Asm_8,
492 : VLD3DUPdWB_register_Asm_16,
493 : VLD3DUPdWB_register_Asm_32,
494 : VLD3DUPdWB_register_Asm_8,
495 : VLD3DUPqAsm_16,
496 : VLD3DUPqAsm_32,
497 : VLD3DUPqAsm_8,
498 : VLD3DUPqWB_fixed_Asm_16,
499 : VLD3DUPqWB_fixed_Asm_32,
500 : VLD3DUPqWB_fixed_Asm_8,
501 : VLD3DUPqWB_register_Asm_16,
502 : VLD3DUPqWB_register_Asm_32,
503 : VLD3DUPqWB_register_Asm_8,
504 : VLD3LNdAsm_16,
505 : VLD3LNdAsm_32,
506 : VLD3LNdAsm_8,
507 : VLD3LNdWB_fixed_Asm_16,
508 : VLD3LNdWB_fixed_Asm_32,
509 : VLD3LNdWB_fixed_Asm_8,
510 : VLD3LNdWB_register_Asm_16,
511 : VLD3LNdWB_register_Asm_32,
512 : VLD3LNdWB_register_Asm_8,
513 : VLD3LNqAsm_16,
514 : VLD3LNqAsm_32,
515 : VLD3LNqWB_fixed_Asm_16,
516 : VLD3LNqWB_fixed_Asm_32,
517 : VLD3LNqWB_register_Asm_16,
518 : VLD3LNqWB_register_Asm_32,
519 : VLD3dAsm_16,
520 : VLD3dAsm_32,
521 : VLD3dAsm_8,
522 : VLD3dWB_fixed_Asm_16,
523 : VLD3dWB_fixed_Asm_32,
524 : VLD3dWB_fixed_Asm_8,
525 : VLD3dWB_register_Asm_16,
526 : VLD3dWB_register_Asm_32,
527 : VLD3dWB_register_Asm_8,
528 : VLD3qAsm_16,
529 : VLD3qAsm_32,
530 : VLD3qAsm_8,
531 : VLD3qWB_fixed_Asm_16,
532 : VLD3qWB_fixed_Asm_32,
533 : VLD3qWB_fixed_Asm_8,
534 : VLD3qWB_register_Asm_16,
535 : VLD3qWB_register_Asm_32,
536 : VLD3qWB_register_Asm_8,
537 : VLD4DUPdAsm_16,
538 : VLD4DUPdAsm_32,
539 : VLD4DUPdAsm_8,
540 : VLD4DUPdWB_fixed_Asm_16,
541 : VLD4DUPdWB_fixed_Asm_32,
542 : VLD4DUPdWB_fixed_Asm_8,
543 : VLD4DUPdWB_register_Asm_16,
544 : VLD4DUPdWB_register_Asm_32,
545 : VLD4DUPdWB_register_Asm_8,
546 : VLD4DUPqAsm_16,
547 : VLD4DUPqAsm_32,
548 : VLD4DUPqAsm_8,
549 : VLD4DUPqWB_fixed_Asm_16,
550 : VLD4DUPqWB_fixed_Asm_32,
551 : VLD4DUPqWB_fixed_Asm_8,
552 : VLD4DUPqWB_register_Asm_16,
553 : VLD4DUPqWB_register_Asm_32,
554 : VLD4DUPqWB_register_Asm_8,
555 : VLD4LNdAsm_16,
556 : VLD4LNdAsm_32,
557 : VLD4LNdAsm_8,
558 : VLD4LNdWB_fixed_Asm_16,
559 : VLD4LNdWB_fixed_Asm_32,
560 : VLD4LNdWB_fixed_Asm_8,
561 : VLD4LNdWB_register_Asm_16,
562 : VLD4LNdWB_register_Asm_32,
563 : VLD4LNdWB_register_Asm_8,
564 : VLD4LNqAsm_16,
565 : VLD4LNqAsm_32,
566 : VLD4LNqWB_fixed_Asm_16,
567 : VLD4LNqWB_fixed_Asm_32,
568 : VLD4LNqWB_register_Asm_16,
569 : VLD4LNqWB_register_Asm_32,
570 : VLD4dAsm_16,
571 : VLD4dAsm_32,
572 : VLD4dAsm_8,
573 : VLD4dWB_fixed_Asm_16,
574 : VLD4dWB_fixed_Asm_32,
575 : VLD4dWB_fixed_Asm_8,
576 : VLD4dWB_register_Asm_16,
577 : VLD4dWB_register_Asm_32,
578 : VLD4dWB_register_Asm_8,
579 : VLD4qAsm_16,
580 : VLD4qAsm_32,
581 : VLD4qAsm_8,
582 : VLD4qWB_fixed_Asm_16,
583 : VLD4qWB_fixed_Asm_32,
584 : VLD4qWB_fixed_Asm_8,
585 : VLD4qWB_register_Asm_16,
586 : VLD4qWB_register_Asm_32,
587 : VLD4qWB_register_Asm_8,
588 : VMOVD0,
589 : VMOVDcc,
590 : VMOVHcc,
591 : VMOVQ0,
592 : VMOVScc,
593 : VST1LNdAsm_16,
594 : VST1LNdAsm_32,
595 : VST1LNdAsm_8,
596 : VST1LNdWB_fixed_Asm_16,
597 : VST1LNdWB_fixed_Asm_32,
598 : VST1LNdWB_fixed_Asm_8,
599 : VST1LNdWB_register_Asm_16,
600 : VST1LNdWB_register_Asm_32,
601 : VST1LNdWB_register_Asm_8,
602 : VST2LNdAsm_16,
603 : VST2LNdAsm_32,
604 : VST2LNdAsm_8,
605 : VST2LNdWB_fixed_Asm_16,
606 : VST2LNdWB_fixed_Asm_32,
607 : VST2LNdWB_fixed_Asm_8,
608 : VST2LNdWB_register_Asm_16,
609 : VST2LNdWB_register_Asm_32,
610 : VST2LNdWB_register_Asm_8,
611 : VST2LNqAsm_16,
612 : VST2LNqAsm_32,
613 : VST2LNqWB_fixed_Asm_16,
614 : VST2LNqWB_fixed_Asm_32,
615 : VST2LNqWB_register_Asm_16,
616 : VST2LNqWB_register_Asm_32,
617 : VST3LNdAsm_16,
618 : VST3LNdAsm_32,
619 : VST3LNdAsm_8,
620 : VST3LNdWB_fixed_Asm_16,
621 : VST3LNdWB_fixed_Asm_32,
622 : VST3LNdWB_fixed_Asm_8,
623 : VST3LNdWB_register_Asm_16,
624 : VST3LNdWB_register_Asm_32,
625 : VST3LNdWB_register_Asm_8,
626 : VST3LNqAsm_16,
627 : VST3LNqAsm_32,
628 : VST3LNqWB_fixed_Asm_16,
629 : VST3LNqWB_fixed_Asm_32,
630 : VST3LNqWB_register_Asm_16,
631 : VST3LNqWB_register_Asm_32,
632 : VST3dAsm_16,
633 : VST3dAsm_32,
634 : VST3dAsm_8,
635 : VST3dWB_fixed_Asm_16,
636 : VST3dWB_fixed_Asm_32,
637 : VST3dWB_fixed_Asm_8,
638 : VST3dWB_register_Asm_16,
639 : VST3dWB_register_Asm_32,
640 : VST3dWB_register_Asm_8,
641 : VST3qAsm_16,
642 : VST3qAsm_32,
643 : VST3qAsm_8,
644 : VST3qWB_fixed_Asm_16,
645 : VST3qWB_fixed_Asm_32,
646 : VST3qWB_fixed_Asm_8,
647 : VST3qWB_register_Asm_16,
648 : VST3qWB_register_Asm_32,
649 : VST3qWB_register_Asm_8,
650 : VST4LNdAsm_16,
651 : VST4LNdAsm_32,
652 : VST4LNdAsm_8,
653 : VST4LNdWB_fixed_Asm_16,
654 : VST4LNdWB_fixed_Asm_32,
655 : VST4LNdWB_fixed_Asm_8,
656 : VST4LNdWB_register_Asm_16,
657 : VST4LNdWB_register_Asm_32,
658 : VST4LNdWB_register_Asm_8,
659 : VST4LNqAsm_16,
660 : VST4LNqAsm_32,
661 : VST4LNqWB_fixed_Asm_16,
662 : VST4LNqWB_fixed_Asm_32,
663 : VST4LNqWB_register_Asm_16,
664 : VST4LNqWB_register_Asm_32,
665 : VST4dAsm_16,
666 : VST4dAsm_32,
667 : VST4dAsm_8,
668 : VST4dWB_fixed_Asm_16,
669 : VST4dWB_fixed_Asm_32,
670 : VST4dWB_fixed_Asm_8,
671 : VST4dWB_register_Asm_16,
672 : VST4dWB_register_Asm_32,
673 : VST4dWB_register_Asm_8,
674 : VST4qAsm_16,
675 : VST4qAsm_32,
676 : VST4qAsm_8,
677 : VST4qWB_fixed_Asm_16,
678 : VST4qWB_fixed_Asm_32,
679 : VST4qWB_fixed_Asm_8,
680 : VST4qWB_register_Asm_16,
681 : VST4qWB_register_Asm_32,
682 : VST4qWB_register_Asm_8,
683 : WIN__CHKSTK,
684 : WIN__DBZCHK,
685 : t2ADDSri,
686 : t2ADDSrr,
687 : t2ADDSrs,
688 : t2BF_LabelPseudo,
689 : t2BR_JT,
690 : t2CALL_BTI,
691 : t2DoLoopStart,
692 : t2DoLoopStartTP,
693 : t2LDMIA_RET,
694 : t2LDRB_OFFSET_imm,
695 : t2LDRB_POST_imm,
696 : t2LDRB_PRE_imm,
697 : t2LDRBpcrel,
698 : t2LDRConstPool,
699 : t2LDRH_OFFSET_imm,
700 : t2LDRH_POST_imm,
701 : t2LDRH_PRE_imm,
702 : t2LDRHpcrel,
703 : t2LDRLIT_ga_pcrel,
704 : t2LDRSB_OFFSET_imm,
705 : t2LDRSB_POST_imm,
706 : t2LDRSB_PRE_imm,
707 : t2LDRSBpcrel,
708 : t2LDRSH_OFFSET_imm,
709 : t2LDRSH_POST_imm,
710 : t2LDRSH_PRE_imm,
711 : t2LDRSHpcrel,
712 : t2LDR_POST_imm,
713 : t2LDR_PRE_imm,
714 : t2LDRpci_pic,
715 : t2LDRpcrel,
716 : t2LEApcrel,
717 : t2LEApcrelJT,
718 : t2LoopDec,
719 : t2LoopEnd,
720 : t2LoopEndDec,
721 : t2MOVCCasr,
722 : t2MOVCCi,
723 : t2MOVCCi16,
724 : t2MOVCCi32imm,
725 : t2MOVCClsl,
726 : t2MOVCClsr,
727 : t2MOVCCr,
728 : t2MOVCCror,
729 : t2MOVSsi,
730 : t2MOVSsr,
731 : t2MOVTi16_ga_pcrel,
732 : t2MOV_ga_pcrel,
733 : t2MOVi16_ga_pcrel,
734 : t2MOVi32imm,
735 : t2MOVsi,
736 : t2MOVsr,
737 : t2MVNCCi,
738 : t2RSBSri,
739 : t2RSBSrs,
740 : t2STRB_OFFSET_imm,
741 : t2STRB_POST_imm,
742 : t2STRB_PRE_imm,
743 : t2STRB_preidx,
744 : t2STRH_OFFSET_imm,
745 : t2STRH_POST_imm,
746 : t2STRH_PRE_imm,
747 : t2STRH_preidx,
748 : t2STR_POST_imm,
749 : t2STR_PRE_imm,
750 : t2STR_preidx,
751 : t2SUBSri,
752 : t2SUBSrr,
753 : t2SUBSrs,
754 : t2SpeculationBarrierISBDSBEndBB,
755 : t2SpeculationBarrierSBEndBB,
756 : t2TBB_JT,
757 : t2TBH_JT,
758 : t2WhileLoopSetup,
759 : t2WhileLoopStart,
760 : t2WhileLoopStartLR,
761 : t2WhileLoopStartTP,
762 : tADCS,
763 : tADDSi3,
764 : tADDSi8,
765 : tADDSrr,
766 : tADDframe,
767 : tADJCALLSTACKDOWN,
768 : tADJCALLSTACKUP,
769 : tBLXNS_CALL,
770 : tBLXr_noip,
771 : tBL_PUSHLR,
772 : tBRIND,
773 : tBR_JTr,
774 : tBXNS_RET,
775 : tBX_CALL,
776 : tBX_RET,
777 : tBX_RET_vararg,
778 : tBfar,
779 : tCMP_SWAP_16,
780 : tCMP_SWAP_32,
781 : tCMP_SWAP_8,
782 : tLDMIA_UPD,
783 : tLDRConstPool,
784 : tLDRLIT_ga_abs,
785 : tLDRLIT_ga_pcrel,
786 : tLDR_postidx,
787 : tLDRpci_pic,
788 : tLEApcrel,
789 : tLEApcrelJT,
790 : tLSLSri,
791 : tMOVCCr_pseudo,
792 : tMOVi32imm,
793 : tPOP_RET,
794 : tRSBS,
795 : tSBCS,
796 : tSUBSi3,
797 : tSUBSi8,
798 : tSUBSrr,
799 : tTAILJMPd,
800 : tTAILJMPdND,
801 : tTAILJMPr,
802 : tTBB_JT,
803 : tTBH_JT,
804 : tTPsoft,
805 : ADCri,
806 : ADCrr,
807 : ADCrsi,
808 : ADCrsr,
809 : ADDri,
810 : ADDrr,
811 : ADDrsi,
812 : ADDrsr,
813 : ADR,
814 : AESD,
815 : AESE,
816 : AESIMC,
817 : AESMC,
818 : ANDri,
819 : ANDrr,
820 : ANDrsi,
821 : ANDrsr,
822 : BF16VDOTI_VDOTD,
823 : BF16VDOTI_VDOTQ,
824 : BF16VDOTS_VDOTD,
825 : BF16VDOTS_VDOTQ,
826 : BF16_VCVT,
827 : BF16_VCVTB,
828 : BF16_VCVTT,
829 : BFC,
830 : BFI,
831 : BICri,
832 : BICrr,
833 : BICrsi,
834 : BICrsr,
835 : BKPT,
836 : BL,
837 : BLX,
838 : BLX_pred,
839 : BLXi,
840 : BL_pred,
841 : BX,
842 : BXJ,
843 : BX_RET,
844 : BX_pred,
845 : Bcc,
846 : CDE_CX1,
847 : CDE_CX1A,
848 : CDE_CX1D,
849 : CDE_CX1DA,
850 : CDE_CX2,
851 : CDE_CX2A,
852 : CDE_CX2D,
853 : CDE_CX2DA,
854 : CDE_CX3,
855 : CDE_CX3A,
856 : CDE_CX3D,
857 : CDE_CX3DA,
858 : CDE_VCX1A_fpdp,
859 : CDE_VCX1A_fpsp,
860 : CDE_VCX1A_vec,
861 : CDE_VCX1_fpdp,
862 : CDE_VCX1_fpsp,
863 : CDE_VCX1_vec,
864 : CDE_VCX2A_fpdp,
865 : CDE_VCX2A_fpsp,
866 : CDE_VCX2A_vec,
867 : CDE_VCX2_fpdp,
868 : CDE_VCX2_fpsp,
869 : CDE_VCX2_vec,
870 : CDE_VCX3A_fpdp,
871 : CDE_VCX3A_fpsp,
872 : CDE_VCX3A_vec,
873 : CDE_VCX3_fpdp,
874 : CDE_VCX3_fpsp,
875 : CDE_VCX3_vec,
876 : CDP,
877 : CDP2,
878 : CLREX,
879 : CLZ,
880 : CMNri,
881 : CMNzrr,
882 : CMNzrsi,
883 : CMNzrsr,
884 : CMPri,
885 : CMPrr,
886 : CMPrsi,
887 : CMPrsr,
888 : CPS1p,
889 : CPS2p,
890 : CPS3p,
891 : CRC32B,
892 : CRC32CB,
893 : CRC32CH,
894 : CRC32CW,
895 : CRC32H,
896 : CRC32W,
897 : DBG,
898 : DMB,
899 : DSB,
900 : EORri,
901 : EORrr,
902 : EORrsi,
903 : EORrsr,
904 : ERET,
905 : FCONSTD,
906 : FCONSTH,
907 : FCONSTS,
908 : FLDMXDB_UPD,
909 : FLDMXIA,
910 : FLDMXIA_UPD,
911 : FMSTAT,
912 : FSTMXDB_UPD,
913 : FSTMXIA,
914 : FSTMXIA_UPD,
915 : HINT,
916 : HLT,
917 : HVC,
918 : ISB,
919 : LDA,
920 : LDAB,
921 : LDAEX,
922 : LDAEXB,
923 : LDAEXD,
924 : LDAEXH,
925 : LDAH,
926 : LDC2L_OFFSET,
927 : LDC2L_OPTION,
928 : LDC2L_POST,
929 : LDC2L_PRE,
930 : LDC2_OFFSET,
931 : LDC2_OPTION,
932 : LDC2_POST,
933 : LDC2_PRE,
934 : LDCL_OFFSET,
935 : LDCL_OPTION,
936 : LDCL_POST,
937 : LDCL_PRE,
938 : LDC_OFFSET,
939 : LDC_OPTION,
940 : LDC_POST,
941 : LDC_PRE,
942 : LDMDA,
943 : LDMDA_UPD,
944 : LDMDB,
945 : LDMDB_UPD,
946 : LDMIA,
947 : LDMIA_UPD,
948 : LDMIB,
949 : LDMIB_UPD,
950 : LDRBT_POST_IMM,
951 : LDRBT_POST_REG,
952 : LDRB_POST_IMM,
953 : LDRB_POST_REG,
954 : LDRB_PRE_IMM,
955 : LDRB_PRE_REG,
956 : LDRBi12,
957 : LDRBrs,
958 : LDRD,
959 : LDRD_POST,
960 : LDRD_PRE,
961 : LDREX,
962 : LDREXB,
963 : LDREXD,
964 : LDREXH,
965 : LDRH,
966 : LDRHTi,
967 : LDRHTr,
968 : LDRH_POST,
969 : LDRH_PRE,
970 : LDRSB,
971 : LDRSBTi,
972 : LDRSBTr,
973 : LDRSB_POST,
974 : LDRSB_PRE,
975 : LDRSH,
976 : LDRSHTi,
977 : LDRSHTr,
978 : LDRSH_POST,
979 : LDRSH_PRE,
980 : LDRT_POST_IMM,
981 : LDRT_POST_REG,
982 : LDR_POST_IMM,
983 : LDR_POST_REG,
984 : LDR_PRE_IMM,
985 : LDR_PRE_REG,
986 : LDRcp,
987 : LDRi12,
988 : LDRrs,
989 : MCR,
990 : MCR2,
991 : MCRR,
992 : MCRR2,
993 : MLA,
994 : MLS,
995 : MOVPCLR,
996 : MOVTi16,
997 : MOVi,
998 : MOVi16,
999 : MOVr,
1000 : MOVr_TC,
1001 : MOVsi,
1002 : MOVsr,
1003 : MRC,
1004 : MRC2,
1005 : MRRC,
1006 : MRRC2,
1007 : MRS,
1008 : MRSbanked,
1009 : MRSsys,
1010 : MSR,
1011 : MSRbanked,
1012 : MSRi,
1013 : MUL,
1014 : MVE_ASRLi,
1015 : MVE_ASRLr,
1016 : MVE_DLSTP_16,
1017 : MVE_DLSTP_32,
1018 : MVE_DLSTP_64,
1019 : MVE_DLSTP_8,
1020 : MVE_LCTP,
1021 : MVE_LETP,
1022 : MVE_LSLLi,
1023 : MVE_LSLLr,
1024 : MVE_LSRL,
1025 : MVE_SQRSHR,
1026 : MVE_SQRSHRL,
1027 : MVE_SQSHL,
1028 : MVE_SQSHLL,
1029 : MVE_SRSHR,
1030 : MVE_SRSHRL,
1031 : MVE_UQRSHL,
1032 : MVE_UQRSHLL,
1033 : MVE_UQSHL,
1034 : MVE_UQSHLL,
1035 : MVE_URSHR,
1036 : MVE_URSHRL,
1037 : MVE_VABAVs16,
1038 : MVE_VABAVs32,
1039 : MVE_VABAVs8,
1040 : MVE_VABAVu16,
1041 : MVE_VABAVu32,
1042 : MVE_VABAVu8,
1043 : MVE_VABDf16,
1044 : MVE_VABDf32,
1045 : MVE_VABDs16,
1046 : MVE_VABDs32,
1047 : MVE_VABDs8,
1048 : MVE_VABDu16,
1049 : MVE_VABDu32,
1050 : MVE_VABDu8,
1051 : MVE_VABSf16,
1052 : MVE_VABSf32,
1053 : MVE_VABSs16,
1054 : MVE_VABSs32,
1055 : MVE_VABSs8,
1056 : MVE_VADC,
1057 : MVE_VADCI,
1058 : MVE_VADDLVs32acc,
1059 : MVE_VADDLVs32no_acc,
1060 : MVE_VADDLVu32acc,
1061 : MVE_VADDLVu32no_acc,
1062 : MVE_VADDVs16acc,
1063 : MVE_VADDVs16no_acc,
1064 : MVE_VADDVs32acc,
1065 : MVE_VADDVs32no_acc,
1066 : MVE_VADDVs8acc,
1067 : MVE_VADDVs8no_acc,
1068 : MVE_VADDVu16acc,
1069 : MVE_VADDVu16no_acc,
1070 : MVE_VADDVu32acc,
1071 : MVE_VADDVu32no_acc,
1072 : MVE_VADDVu8acc,
1073 : MVE_VADDVu8no_acc,
1074 : MVE_VADD_qr_f16,
1075 : MVE_VADD_qr_f32,
1076 : MVE_VADD_qr_i16,
1077 : MVE_VADD_qr_i32,
1078 : MVE_VADD_qr_i8,
1079 : MVE_VADDf16,
1080 : MVE_VADDf32,
1081 : MVE_VADDi16,
1082 : MVE_VADDi32,
1083 : MVE_VADDi8,
1084 : MVE_VAND,
1085 : MVE_VBIC,
1086 : MVE_VBICimmi16,
1087 : MVE_VBICimmi32,
1088 : MVE_VBRSR16,
1089 : MVE_VBRSR32,
1090 : MVE_VBRSR8,
1091 : MVE_VCADDf16,
1092 : MVE_VCADDf32,
1093 : MVE_VCADDi16,
1094 : MVE_VCADDi32,
1095 : MVE_VCADDi8,
1096 : MVE_VCLSs16,
1097 : MVE_VCLSs32,
1098 : MVE_VCLSs8,
1099 : MVE_VCLZs16,
1100 : MVE_VCLZs32,
1101 : MVE_VCLZs8,
1102 : MVE_VCMLAf16,
1103 : MVE_VCMLAf32,
1104 : MVE_VCMPf16,
1105 : MVE_VCMPf16r,
1106 : MVE_VCMPf32,
1107 : MVE_VCMPf32r,
1108 : MVE_VCMPi16,
1109 : MVE_VCMPi16r,
1110 : MVE_VCMPi32,
1111 : MVE_VCMPi32r,
1112 : MVE_VCMPi8,
1113 : MVE_VCMPi8r,
1114 : MVE_VCMPs16,
1115 : MVE_VCMPs16r,
1116 : MVE_VCMPs32,
1117 : MVE_VCMPs32r,
1118 : MVE_VCMPs8,
1119 : MVE_VCMPs8r,
1120 : MVE_VCMPu16,
1121 : MVE_VCMPu16r,
1122 : MVE_VCMPu32,
1123 : MVE_VCMPu32r,
1124 : MVE_VCMPu8,
1125 : MVE_VCMPu8r,
1126 : MVE_VCMULf16,
1127 : MVE_VCMULf32,
1128 : MVE_VCTP16,
1129 : MVE_VCTP32,
1130 : MVE_VCTP64,
1131 : MVE_VCTP8,
1132 : MVE_VCVTf16f32bh,
1133 : MVE_VCVTf16f32th,
1134 : MVE_VCVTf16s16_fix,
1135 : MVE_VCVTf16s16n,
1136 : MVE_VCVTf16u16_fix,
1137 : MVE_VCVTf16u16n,
1138 : MVE_VCVTf32f16bh,
1139 : MVE_VCVTf32f16th,
1140 : MVE_VCVTf32s32_fix,
1141 : MVE_VCVTf32s32n,
1142 : MVE_VCVTf32u32_fix,
1143 : MVE_VCVTf32u32n,
1144 : MVE_VCVTs16f16_fix,
1145 : MVE_VCVTs16f16a,
1146 : MVE_VCVTs16f16m,
1147 : MVE_VCVTs16f16n,
1148 : MVE_VCVTs16f16p,
1149 : MVE_VCVTs16f16z,
1150 : MVE_VCVTs32f32_fix,
1151 : MVE_VCVTs32f32a,
1152 : MVE_VCVTs32f32m,
1153 : MVE_VCVTs32f32n,
1154 : MVE_VCVTs32f32p,
1155 : MVE_VCVTs32f32z,
1156 : MVE_VCVTu16f16_fix,
1157 : MVE_VCVTu16f16a,
1158 : MVE_VCVTu16f16m,
1159 : MVE_VCVTu16f16n,
1160 : MVE_VCVTu16f16p,
1161 : MVE_VCVTu16f16z,
1162 : MVE_VCVTu32f32_fix,
1163 : MVE_VCVTu32f32a,
1164 : MVE_VCVTu32f32m,
1165 : MVE_VCVTu32f32n,
1166 : MVE_VCVTu32f32p,
1167 : MVE_VCVTu32f32z,
1168 : MVE_VDDUPu16,
1169 : MVE_VDDUPu32,
1170 : MVE_VDDUPu8,
1171 : MVE_VDUP16,
1172 : MVE_VDUP32,
1173 : MVE_VDUP8,
1174 : MVE_VDWDUPu16,
1175 : MVE_VDWDUPu32,
1176 : MVE_VDWDUPu8,
1177 : MVE_VEOR,
1178 : MVE_VFMA_qr_Sf16,
1179 : MVE_VFMA_qr_Sf32,
1180 : MVE_VFMA_qr_f16,
1181 : MVE_VFMA_qr_f32,
1182 : MVE_VFMAf16,
1183 : MVE_VFMAf32,
1184 : MVE_VFMSf16,
1185 : MVE_VFMSf32,
1186 : MVE_VHADD_qr_s16,
1187 : MVE_VHADD_qr_s32,
1188 : MVE_VHADD_qr_s8,
1189 : MVE_VHADD_qr_u16,
1190 : MVE_VHADD_qr_u32,
1191 : MVE_VHADD_qr_u8,
1192 : MVE_VHADDs16,
1193 : MVE_VHADDs32,
1194 : MVE_VHADDs8,
1195 : MVE_VHADDu16,
1196 : MVE_VHADDu32,
1197 : MVE_VHADDu8,
1198 : MVE_VHCADDs16,
1199 : MVE_VHCADDs32,
1200 : MVE_VHCADDs8,
1201 : MVE_VHSUB_qr_s16,
1202 : MVE_VHSUB_qr_s32,
1203 : MVE_VHSUB_qr_s8,
1204 : MVE_VHSUB_qr_u16,
1205 : MVE_VHSUB_qr_u32,
1206 : MVE_VHSUB_qr_u8,
1207 : MVE_VHSUBs16,
1208 : MVE_VHSUBs32,
1209 : MVE_VHSUBs8,
1210 : MVE_VHSUBu16,
1211 : MVE_VHSUBu32,
1212 : MVE_VHSUBu8,
1213 : MVE_VIDUPu16,
1214 : MVE_VIDUPu32,
1215 : MVE_VIDUPu8,
1216 : MVE_VIWDUPu16,
1217 : MVE_VIWDUPu32,
1218 : MVE_VIWDUPu8,
1219 : MVE_VLD20_16,
1220 : MVE_VLD20_16_wb,
1221 : MVE_VLD20_32,
1222 : MVE_VLD20_32_wb,
1223 : MVE_VLD20_8,
1224 : MVE_VLD20_8_wb,
1225 : MVE_VLD21_16,
1226 : MVE_VLD21_16_wb,
1227 : MVE_VLD21_32,
1228 : MVE_VLD21_32_wb,
1229 : MVE_VLD21_8,
1230 : MVE_VLD21_8_wb,
1231 : MVE_VLD40_16,
1232 : MVE_VLD40_16_wb,
1233 : MVE_VLD40_32,
1234 : MVE_VLD40_32_wb,
1235 : MVE_VLD40_8,
1236 : MVE_VLD40_8_wb,
1237 : MVE_VLD41_16,
1238 : MVE_VLD41_16_wb,
1239 : MVE_VLD41_32,
1240 : MVE_VLD41_32_wb,
1241 : MVE_VLD41_8,
1242 : MVE_VLD41_8_wb,
1243 : MVE_VLD42_16,
1244 : MVE_VLD42_16_wb,
1245 : MVE_VLD42_32,
1246 : MVE_VLD42_32_wb,
1247 : MVE_VLD42_8,
1248 : MVE_VLD42_8_wb,
1249 : MVE_VLD43_16,
1250 : MVE_VLD43_16_wb,
1251 : MVE_VLD43_32,
1252 : MVE_VLD43_32_wb,
1253 : MVE_VLD43_8,
1254 : MVE_VLD43_8_wb,
1255 : MVE_VLDRBS16,
1256 : MVE_VLDRBS16_post,
1257 : MVE_VLDRBS16_pre,
1258 : MVE_VLDRBS16_rq,
1259 : MVE_VLDRBS32,
1260 : MVE_VLDRBS32_post,
1261 : MVE_VLDRBS32_pre,
1262 : MVE_VLDRBS32_rq,
1263 : MVE_VLDRBU16,
1264 : MVE_VLDRBU16_post,
1265 : MVE_VLDRBU16_pre,
1266 : MVE_VLDRBU16_rq,
1267 : MVE_VLDRBU32,
1268 : MVE_VLDRBU32_post,
1269 : MVE_VLDRBU32_pre,
1270 : MVE_VLDRBU32_rq,
1271 : MVE_VLDRBU8,
1272 : MVE_VLDRBU8_post,
1273 : MVE_VLDRBU8_pre,
1274 : MVE_VLDRBU8_rq,
1275 : MVE_VLDRDU64_qi,
1276 : MVE_VLDRDU64_qi_pre,
1277 : MVE_VLDRDU64_rq,
1278 : MVE_VLDRDU64_rq_u,
1279 : MVE_VLDRHS32,
1280 : MVE_VLDRHS32_post,
1281 : MVE_VLDRHS32_pre,
1282 : MVE_VLDRHS32_rq,
1283 : MVE_VLDRHS32_rq_u,
1284 : MVE_VLDRHU16,
1285 : MVE_VLDRHU16_post,
1286 : MVE_VLDRHU16_pre,
1287 : MVE_VLDRHU16_rq,
1288 : MVE_VLDRHU16_rq_u,
1289 : MVE_VLDRHU32,
1290 : MVE_VLDRHU32_post,
1291 : MVE_VLDRHU32_pre,
1292 : MVE_VLDRHU32_rq,
1293 : MVE_VLDRHU32_rq_u,
1294 : MVE_VLDRWU32,
1295 : MVE_VLDRWU32_post,
1296 : MVE_VLDRWU32_pre,
1297 : MVE_VLDRWU32_qi,
1298 : MVE_VLDRWU32_qi_pre,
1299 : MVE_VLDRWU32_rq,
1300 : MVE_VLDRWU32_rq_u,
1301 : MVE_VMAXAVs16,
1302 : MVE_VMAXAVs32,
1303 : MVE_VMAXAVs8,
1304 : MVE_VMAXAs16,
1305 : MVE_VMAXAs32,
1306 : MVE_VMAXAs8,
1307 : MVE_VMAXNMAVf16,
1308 : MVE_VMAXNMAVf32,
1309 : MVE_VMAXNMAf16,
1310 : MVE_VMAXNMAf32,
1311 : MVE_VMAXNMVf16,
1312 : MVE_VMAXNMVf32,
1313 : MVE_VMAXNMf16,
1314 : MVE_VMAXNMf32,
1315 : MVE_VMAXVs16,
1316 : MVE_VMAXVs32,
1317 : MVE_VMAXVs8,
1318 : MVE_VMAXVu16,
1319 : MVE_VMAXVu32,
1320 : MVE_VMAXVu8,
1321 : MVE_VMAXs16,
1322 : MVE_VMAXs32,
1323 : MVE_VMAXs8,
1324 : MVE_VMAXu16,
1325 : MVE_VMAXu32,
1326 : MVE_VMAXu8,
1327 : MVE_VMINAVs16,
1328 : MVE_VMINAVs32,
1329 : MVE_VMINAVs8,
1330 : MVE_VMINAs16,
1331 : MVE_VMINAs32,
1332 : MVE_VMINAs8,
1333 : MVE_VMINNMAVf16,
1334 : MVE_VMINNMAVf32,
1335 : MVE_VMINNMAf16,
1336 : MVE_VMINNMAf32,
1337 : MVE_VMINNMVf16,
1338 : MVE_VMINNMVf32,
1339 : MVE_VMINNMf16,
1340 : MVE_VMINNMf32,
1341 : MVE_VMINVs16,
1342 : MVE_VMINVs32,
1343 : MVE_VMINVs8,
1344 : MVE_VMINVu16,
1345 : MVE_VMINVu32,
1346 : MVE_VMINVu8,
1347 : MVE_VMINs16,
1348 : MVE_VMINs32,
1349 : MVE_VMINs8,
1350 : MVE_VMINu16,
1351 : MVE_VMINu32,
1352 : MVE_VMINu8,
1353 : MVE_VMLADAVas16,
1354 : MVE_VMLADAVas32,
1355 : MVE_VMLADAVas8,
1356 : MVE_VMLADAVau16,
1357 : MVE_VMLADAVau32,
1358 : MVE_VMLADAVau8,
1359 : MVE_VMLADAVaxs16,
1360 : MVE_VMLADAVaxs32,
1361 : MVE_VMLADAVaxs8,
1362 : MVE_VMLADAVs16,
1363 : MVE_VMLADAVs32,
1364 : MVE_VMLADAVs8,
1365 : MVE_VMLADAVu16,
1366 : MVE_VMLADAVu32,
1367 : MVE_VMLADAVu8,
1368 : MVE_VMLADAVxs16,
1369 : MVE_VMLADAVxs32,
1370 : MVE_VMLADAVxs8,
1371 : MVE_VMLALDAVas16,
1372 : MVE_VMLALDAVas32,
1373 : MVE_VMLALDAVau16,
1374 : MVE_VMLALDAVau32,
1375 : MVE_VMLALDAVaxs16,
1376 : MVE_VMLALDAVaxs32,
1377 : MVE_VMLALDAVs16,
1378 : MVE_VMLALDAVs32,
1379 : MVE_VMLALDAVu16,
1380 : MVE_VMLALDAVu32,
1381 : MVE_VMLALDAVxs16,
1382 : MVE_VMLALDAVxs32,
1383 : MVE_VMLAS_qr_i16,
1384 : MVE_VMLAS_qr_i32,
1385 : MVE_VMLAS_qr_i8,
1386 : MVE_VMLA_qr_i16,
1387 : MVE_VMLA_qr_i32,
1388 : MVE_VMLA_qr_i8,
1389 : MVE_VMLSDAVas16,
1390 : MVE_VMLSDAVas32,
1391 : MVE_VMLSDAVas8,
1392 : MVE_VMLSDAVaxs16,
1393 : MVE_VMLSDAVaxs32,
1394 : MVE_VMLSDAVaxs8,
1395 : MVE_VMLSDAVs16,
1396 : MVE_VMLSDAVs32,
1397 : MVE_VMLSDAVs8,
1398 : MVE_VMLSDAVxs16,
1399 : MVE_VMLSDAVxs32,
1400 : MVE_VMLSDAVxs8,
1401 : MVE_VMLSLDAVas16,
1402 : MVE_VMLSLDAVas32,
1403 : MVE_VMLSLDAVaxs16,
1404 : MVE_VMLSLDAVaxs32,
1405 : MVE_VMLSLDAVs16,
1406 : MVE_VMLSLDAVs32,
1407 : MVE_VMLSLDAVxs16,
1408 : MVE_VMLSLDAVxs32,
1409 : MVE_VMOVLs16bh,
1410 : MVE_VMOVLs16th,
1411 : MVE_VMOVLs8bh,
1412 : MVE_VMOVLs8th,
1413 : MVE_VMOVLu16bh,
1414 : MVE_VMOVLu16th,
1415 : MVE_VMOVLu8bh,
1416 : MVE_VMOVLu8th,
1417 : MVE_VMOVNi16bh,
1418 : MVE_VMOVNi16th,
1419 : MVE_VMOVNi32bh,
1420 : MVE_VMOVNi32th,
1421 : MVE_VMOV_from_lane_32,
1422 : MVE_VMOV_from_lane_s16,
1423 : MVE_VMOV_from_lane_s8,
1424 : MVE_VMOV_from_lane_u16,
1425 : MVE_VMOV_from_lane_u8,
1426 : MVE_VMOV_q_rr,
1427 : MVE_VMOV_rr_q,
1428 : MVE_VMOV_to_lane_16,
1429 : MVE_VMOV_to_lane_32,
1430 : MVE_VMOV_to_lane_8,
1431 : MVE_VMOVimmf32,
1432 : MVE_VMOVimmi16,
1433 : MVE_VMOVimmi32,
1434 : MVE_VMOVimmi64,
1435 : MVE_VMOVimmi8,
1436 : MVE_VMULHs16,
1437 : MVE_VMULHs32,
1438 : MVE_VMULHs8,
1439 : MVE_VMULHu16,
1440 : MVE_VMULHu32,
1441 : MVE_VMULHu8,
1442 : MVE_VMULLBp16,
1443 : MVE_VMULLBp8,
1444 : MVE_VMULLBs16,
1445 : MVE_VMULLBs32,
1446 : MVE_VMULLBs8,
1447 : MVE_VMULLBu16,
1448 : MVE_VMULLBu32,
1449 : MVE_VMULLBu8,
1450 : MVE_VMULLTp16,
1451 : MVE_VMULLTp8,
1452 : MVE_VMULLTs16,
1453 : MVE_VMULLTs32,
1454 : MVE_VMULLTs8,
1455 : MVE_VMULLTu16,
1456 : MVE_VMULLTu32,
1457 : MVE_VMULLTu8,
1458 : MVE_VMUL_qr_f16,
1459 : MVE_VMUL_qr_f32,
1460 : MVE_VMUL_qr_i16,
1461 : MVE_VMUL_qr_i32,
1462 : MVE_VMUL_qr_i8,
1463 : MVE_VMULf16,
1464 : MVE_VMULf32,
1465 : MVE_VMULi16,
1466 : MVE_VMULi32,
1467 : MVE_VMULi8,
1468 : MVE_VMVN,
1469 : MVE_VMVNimmi16,
1470 : MVE_VMVNimmi32,
1471 : MVE_VNEGf16,
1472 : MVE_VNEGf32,
1473 : MVE_VNEGs16,
1474 : MVE_VNEGs32,
1475 : MVE_VNEGs8,
1476 : MVE_VORN,
1477 : MVE_VORR,
1478 : MVE_VORRimmi16,
1479 : MVE_VORRimmi32,
1480 : MVE_VPNOT,
1481 : MVE_VPSEL,
1482 : MVE_VPST,
1483 : MVE_VPTv16i8,
1484 : MVE_VPTv16i8r,
1485 : MVE_VPTv16s8,
1486 : MVE_VPTv16s8r,
1487 : MVE_VPTv16u8,
1488 : MVE_VPTv16u8r,
1489 : MVE_VPTv4f32,
1490 : MVE_VPTv4f32r,
1491 : MVE_VPTv4i32,
1492 : MVE_VPTv4i32r,
1493 : MVE_VPTv4s32,
1494 : MVE_VPTv4s32r,
1495 : MVE_VPTv4u32,
1496 : MVE_VPTv4u32r,
1497 : MVE_VPTv8f16,
1498 : MVE_VPTv8f16r,
1499 : MVE_VPTv8i16,
1500 : MVE_VPTv8i16r,
1501 : MVE_VPTv8s16,
1502 : MVE_VPTv8s16r,
1503 : MVE_VPTv8u16,
1504 : MVE_VPTv8u16r,
1505 : MVE_VQABSs16,
1506 : MVE_VQABSs32,
1507 : MVE_VQABSs8,
1508 : MVE_VQADD_qr_s16,
1509 : MVE_VQADD_qr_s32,
1510 : MVE_VQADD_qr_s8,
1511 : MVE_VQADD_qr_u16,
1512 : MVE_VQADD_qr_u32,
1513 : MVE_VQADD_qr_u8,
1514 : MVE_VQADDs16,
1515 : MVE_VQADDs32,
1516 : MVE_VQADDs8,
1517 : MVE_VQADDu16,
1518 : MVE_VQADDu32,
1519 : MVE_VQADDu8,
1520 : MVE_VQDMLADHXs16,
1521 : MVE_VQDMLADHXs32,
1522 : MVE_VQDMLADHXs8,
1523 : MVE_VQDMLADHs16,
1524 : MVE_VQDMLADHs32,
1525 : MVE_VQDMLADHs8,
1526 : MVE_VQDMLAH_qrs16,
1527 : MVE_VQDMLAH_qrs32,
1528 : MVE_VQDMLAH_qrs8,
1529 : MVE_VQDMLASH_qrs16,
1530 : MVE_VQDMLASH_qrs32,
1531 : MVE_VQDMLASH_qrs8,
1532 : MVE_VQDMLSDHXs16,
1533 : MVE_VQDMLSDHXs32,
1534 : MVE_VQDMLSDHXs8,
1535 : MVE_VQDMLSDHs16,
1536 : MVE_VQDMLSDHs32,
1537 : MVE_VQDMLSDHs8,
1538 : MVE_VQDMULH_qr_s16,
1539 : MVE_VQDMULH_qr_s32,
1540 : MVE_VQDMULH_qr_s8,
1541 : MVE_VQDMULHi16,
1542 : MVE_VQDMULHi32,
1543 : MVE_VQDMULHi8,
1544 : MVE_VQDMULL_qr_s16bh,
1545 : MVE_VQDMULL_qr_s16th,
1546 : MVE_VQDMULL_qr_s32bh,
1547 : MVE_VQDMULL_qr_s32th,
1548 : MVE_VQDMULLs16bh,
1549 : MVE_VQDMULLs16th,
1550 : MVE_VQDMULLs32bh,
1551 : MVE_VQDMULLs32th,
1552 : MVE_VQMOVNs16bh,
1553 : MVE_VQMOVNs16th,
1554 : MVE_VQMOVNs32bh,
1555 : MVE_VQMOVNs32th,
1556 : MVE_VQMOVNu16bh,
1557 : MVE_VQMOVNu16th,
1558 : MVE_VQMOVNu32bh,
1559 : MVE_VQMOVNu32th,
1560 : MVE_VQMOVUNs16bh,
1561 : MVE_VQMOVUNs16th,
1562 : MVE_VQMOVUNs32bh,
1563 : MVE_VQMOVUNs32th,
1564 : MVE_VQNEGs16,
1565 : MVE_VQNEGs32,
1566 : MVE_VQNEGs8,
1567 : MVE_VQRDMLADHXs16,
1568 : MVE_VQRDMLADHXs32,
1569 : MVE_VQRDMLADHXs8,
1570 : MVE_VQRDMLADHs16,
1571 : MVE_VQRDMLADHs32,
1572 : MVE_VQRDMLADHs8,
1573 : MVE_VQRDMLAH_qrs16,
1574 : MVE_VQRDMLAH_qrs32,
1575 : MVE_VQRDMLAH_qrs8,
1576 : MVE_VQRDMLASH_qrs16,
1577 : MVE_VQRDMLASH_qrs32,
1578 : MVE_VQRDMLASH_qrs8,
1579 : MVE_VQRDMLSDHXs16,
1580 : MVE_VQRDMLSDHXs32,
1581 : MVE_VQRDMLSDHXs8,
1582 : MVE_VQRDMLSDHs16,
1583 : MVE_VQRDMLSDHs32,
1584 : MVE_VQRDMLSDHs8,
1585 : MVE_VQRDMULH_qr_s16,
1586 : MVE_VQRDMULH_qr_s32,
1587 : MVE_VQRDMULH_qr_s8,
1588 : MVE_VQRDMULHi16,
1589 : MVE_VQRDMULHi32,
1590 : MVE_VQRDMULHi8,
1591 : MVE_VQRSHL_by_vecs16,
1592 : MVE_VQRSHL_by_vecs32,
1593 : MVE_VQRSHL_by_vecs8,
1594 : MVE_VQRSHL_by_vecu16,
1595 : MVE_VQRSHL_by_vecu32,
1596 : MVE_VQRSHL_by_vecu8,
1597 : MVE_VQRSHL_qrs16,
1598 : MVE_VQRSHL_qrs32,
1599 : MVE_VQRSHL_qrs8,
1600 : MVE_VQRSHL_qru16,
1601 : MVE_VQRSHL_qru32,
1602 : MVE_VQRSHL_qru8,
1603 : MVE_VQRSHRNbhs16,
1604 : MVE_VQRSHRNbhs32,
1605 : MVE_VQRSHRNbhu16,
1606 : MVE_VQRSHRNbhu32,
1607 : MVE_VQRSHRNths16,
1608 : MVE_VQRSHRNths32,
1609 : MVE_VQRSHRNthu16,
1610 : MVE_VQRSHRNthu32,
1611 : MVE_VQRSHRUNs16bh,
1612 : MVE_VQRSHRUNs16th,
1613 : MVE_VQRSHRUNs32bh,
1614 : MVE_VQRSHRUNs32th,
1615 : MVE_VQSHLU_imms16,
1616 : MVE_VQSHLU_imms32,
1617 : MVE_VQSHLU_imms8,
1618 : MVE_VQSHL_by_vecs16,
1619 : MVE_VQSHL_by_vecs32,
1620 : MVE_VQSHL_by_vecs8,
1621 : MVE_VQSHL_by_vecu16,
1622 : MVE_VQSHL_by_vecu32,
1623 : MVE_VQSHL_by_vecu8,
1624 : MVE_VQSHL_qrs16,
1625 : MVE_VQSHL_qrs32,
1626 : MVE_VQSHL_qrs8,
1627 : MVE_VQSHL_qru16,
1628 : MVE_VQSHL_qru32,
1629 : MVE_VQSHL_qru8,
1630 : MVE_VQSHLimms16,
1631 : MVE_VQSHLimms32,
1632 : MVE_VQSHLimms8,
1633 : MVE_VQSHLimmu16,
1634 : MVE_VQSHLimmu32,
1635 : MVE_VQSHLimmu8,
1636 : MVE_VQSHRNbhs16,
1637 : MVE_VQSHRNbhs32,
1638 : MVE_VQSHRNbhu16,
1639 : MVE_VQSHRNbhu32,
1640 : MVE_VQSHRNths16,
1641 : MVE_VQSHRNths32,
1642 : MVE_VQSHRNthu16,
1643 : MVE_VQSHRNthu32,
1644 : MVE_VQSHRUNs16bh,
1645 : MVE_VQSHRUNs16th,
1646 : MVE_VQSHRUNs32bh,
1647 : MVE_VQSHRUNs32th,
1648 : MVE_VQSUB_qr_s16,
1649 : MVE_VQSUB_qr_s32,
1650 : MVE_VQSUB_qr_s8,
1651 : MVE_VQSUB_qr_u16,
1652 : MVE_VQSUB_qr_u32,
1653 : MVE_VQSUB_qr_u8,
1654 : MVE_VQSUBs16,
1655 : MVE_VQSUBs32,
1656 : MVE_VQSUBs8,
1657 : MVE_VQSUBu16,
1658 : MVE_VQSUBu32,
1659 : MVE_VQSUBu8,
1660 : MVE_VREV16_8,
1661 : MVE_VREV32_16,
1662 : MVE_VREV32_8,
1663 : MVE_VREV64_16,
1664 : MVE_VREV64_32,
1665 : MVE_VREV64_8,
1666 : MVE_VRHADDs16,
1667 : MVE_VRHADDs32,
1668 : MVE_VRHADDs8,
1669 : MVE_VRHADDu16,
1670 : MVE_VRHADDu32,
1671 : MVE_VRHADDu8,
1672 : MVE_VRINTf16A,
1673 : MVE_VRINTf16M,
1674 : MVE_VRINTf16N,
1675 : MVE_VRINTf16P,
1676 : MVE_VRINTf16X,
1677 : MVE_VRINTf16Z,
1678 : MVE_VRINTf32A,
1679 : MVE_VRINTf32M,
1680 : MVE_VRINTf32N,
1681 : MVE_VRINTf32P,
1682 : MVE_VRINTf32X,
1683 : MVE_VRINTf32Z,
1684 : MVE_VRMLALDAVHas32,
1685 : MVE_VRMLALDAVHau32,
1686 : MVE_VRMLALDAVHaxs32,
1687 : MVE_VRMLALDAVHs32,
1688 : MVE_VRMLALDAVHu32,
1689 : MVE_VRMLALDAVHxs32,
1690 : MVE_VRMLSLDAVHas32,
1691 : MVE_VRMLSLDAVHaxs32,
1692 : MVE_VRMLSLDAVHs32,
1693 : MVE_VRMLSLDAVHxs32,
1694 : MVE_VRMULHs16,
1695 : MVE_VRMULHs32,
1696 : MVE_VRMULHs8,
1697 : MVE_VRMULHu16,
1698 : MVE_VRMULHu32,
1699 : MVE_VRMULHu8,
1700 : MVE_VRSHL_by_vecs16,
1701 : MVE_VRSHL_by_vecs32,
1702 : MVE_VRSHL_by_vecs8,
1703 : MVE_VRSHL_by_vecu16,
1704 : MVE_VRSHL_by_vecu32,
1705 : MVE_VRSHL_by_vecu8,
1706 : MVE_VRSHL_qrs16,
1707 : MVE_VRSHL_qrs32,
1708 : MVE_VRSHL_qrs8,
1709 : MVE_VRSHL_qru16,
1710 : MVE_VRSHL_qru32,
1711 : MVE_VRSHL_qru8,
1712 : MVE_VRSHRNi16bh,
1713 : MVE_VRSHRNi16th,
1714 : MVE_VRSHRNi32bh,
1715 : MVE_VRSHRNi32th,
1716 : MVE_VRSHR_imms16,
1717 : MVE_VRSHR_imms32,
1718 : MVE_VRSHR_imms8,
1719 : MVE_VRSHR_immu16,
1720 : MVE_VRSHR_immu32,
1721 : MVE_VRSHR_immu8,
1722 : MVE_VSBC,
1723 : MVE_VSBCI,
1724 : MVE_VSHLC,
1725 : MVE_VSHLL_imms16bh,
1726 : MVE_VSHLL_imms16th,
1727 : MVE_VSHLL_imms8bh,
1728 : MVE_VSHLL_imms8th,
1729 : MVE_VSHLL_immu16bh,
1730 : MVE_VSHLL_immu16th,
1731 : MVE_VSHLL_immu8bh,
1732 : MVE_VSHLL_immu8th,
1733 : MVE_VSHLL_lws16bh,
1734 : MVE_VSHLL_lws16th,
1735 : MVE_VSHLL_lws8bh,
1736 : MVE_VSHLL_lws8th,
1737 : MVE_VSHLL_lwu16bh,
1738 : MVE_VSHLL_lwu16th,
1739 : MVE_VSHLL_lwu8bh,
1740 : MVE_VSHLL_lwu8th,
1741 : MVE_VSHL_by_vecs16,
1742 : MVE_VSHL_by_vecs32,
1743 : MVE_VSHL_by_vecs8,
1744 : MVE_VSHL_by_vecu16,
1745 : MVE_VSHL_by_vecu32,
1746 : MVE_VSHL_by_vecu8,
1747 : MVE_VSHL_immi16,
1748 : MVE_VSHL_immi32,
1749 : MVE_VSHL_immi8,
1750 : MVE_VSHL_qrs16,
1751 : MVE_VSHL_qrs32,
1752 : MVE_VSHL_qrs8,
1753 : MVE_VSHL_qru16,
1754 : MVE_VSHL_qru32,
1755 : MVE_VSHL_qru8,
1756 : MVE_VSHRNi16bh,
1757 : MVE_VSHRNi16th,
1758 : MVE_VSHRNi32bh,
1759 : MVE_VSHRNi32th,
1760 : MVE_VSHR_imms16,
1761 : MVE_VSHR_imms32,
1762 : MVE_VSHR_imms8,
1763 : MVE_VSHR_immu16,
1764 : MVE_VSHR_immu32,
1765 : MVE_VSHR_immu8,
1766 : MVE_VSLIimm16,
1767 : MVE_VSLIimm32,
1768 : MVE_VSLIimm8,
1769 : MVE_VSRIimm16,
1770 : MVE_VSRIimm32,
1771 : MVE_VSRIimm8,
1772 : MVE_VST20_16,
1773 : MVE_VST20_16_wb,
1774 : MVE_VST20_32,
1775 : MVE_VST20_32_wb,
1776 : MVE_VST20_8,
1777 : MVE_VST20_8_wb,
1778 : MVE_VST21_16,
1779 : MVE_VST21_16_wb,
1780 : MVE_VST21_32,
1781 : MVE_VST21_32_wb,
1782 : MVE_VST21_8,
1783 : MVE_VST21_8_wb,
1784 : MVE_VST40_16,
1785 : MVE_VST40_16_wb,
1786 : MVE_VST40_32,
1787 : MVE_VST40_32_wb,
1788 : MVE_VST40_8,
1789 : MVE_VST40_8_wb,
1790 : MVE_VST41_16,
1791 : MVE_VST41_16_wb,
1792 : MVE_VST41_32,
1793 : MVE_VST41_32_wb,
1794 : MVE_VST41_8,
1795 : MVE_VST41_8_wb,
1796 : MVE_VST42_16,
1797 : MVE_VST42_16_wb,
1798 : MVE_VST42_32,
1799 : MVE_VST42_32_wb,
1800 : MVE_VST42_8,
1801 : MVE_VST42_8_wb,
1802 : MVE_VST43_16,
1803 : MVE_VST43_16_wb,
1804 : MVE_VST43_32,
1805 : MVE_VST43_32_wb,
1806 : MVE_VST43_8,
1807 : MVE_VST43_8_wb,
1808 : MVE_VSTRB16,
1809 : MVE_VSTRB16_post,
1810 : MVE_VSTRB16_pre,
1811 : MVE_VSTRB16_rq,
1812 : MVE_VSTRB32,
1813 : MVE_VSTRB32_post,
1814 : MVE_VSTRB32_pre,
1815 : MVE_VSTRB32_rq,
1816 : MVE_VSTRB8_rq,
1817 : MVE_VSTRBU8,
1818 : MVE_VSTRBU8_post,
1819 : MVE_VSTRBU8_pre,
1820 : MVE_VSTRD64_qi,
1821 : MVE_VSTRD64_qi_pre,
1822 : MVE_VSTRD64_rq,
1823 : MVE_VSTRD64_rq_u,
1824 : MVE_VSTRH16_rq,
1825 : MVE_VSTRH16_rq_u,
1826 : MVE_VSTRH32,
1827 : MVE_VSTRH32_post,
1828 : MVE_VSTRH32_pre,
1829 : MVE_VSTRH32_rq,
1830 : MVE_VSTRH32_rq_u,
1831 : MVE_VSTRHU16,
1832 : MVE_VSTRHU16_post,
1833 : MVE_VSTRHU16_pre,
1834 : MVE_VSTRW32_qi,
1835 : MVE_VSTRW32_qi_pre,
1836 : MVE_VSTRW32_rq,
1837 : MVE_VSTRW32_rq_u,
1838 : MVE_VSTRWU32,
1839 : MVE_VSTRWU32_post,
1840 : MVE_VSTRWU32_pre,
1841 : MVE_VSUB_qr_f16,
1842 : MVE_VSUB_qr_f32,
1843 : MVE_VSUB_qr_i16,
1844 : MVE_VSUB_qr_i32,
1845 : MVE_VSUB_qr_i8,
1846 : MVE_VSUBf16,
1847 : MVE_VSUBf32,
1848 : MVE_VSUBi16,
1849 : MVE_VSUBi32,
1850 : MVE_VSUBi8,
1851 : MVE_WLSTP_16,
1852 : MVE_WLSTP_32,
1853 : MVE_WLSTP_64,
1854 : MVE_WLSTP_8,
1855 : MVNi,
1856 : MVNr,
1857 : MVNsi,
1858 : MVNsr,
1859 : NEON_VMAXNMNDf,
1860 : NEON_VMAXNMNDh,
1861 : NEON_VMAXNMNQf,
1862 : NEON_VMAXNMNQh,
1863 : NEON_VMINNMNDf,
1864 : NEON_VMINNMNDh,
1865 : NEON_VMINNMNQf,
1866 : NEON_VMINNMNQh,
1867 : ORRri,
1868 : ORRrr,
1869 : ORRrsi,
1870 : ORRrsr,
1871 : PKHBT,
1872 : PKHTB,
1873 : PLDWi12,
1874 : PLDWrs,
1875 : PLDi12,
1876 : PLDrs,
1877 : PLIi12,
1878 : PLIrs,
1879 : QADD,
1880 : QADD16,
1881 : QADD8,
1882 : QASX,
1883 : QDADD,
1884 : QDSUB,
1885 : QSAX,
1886 : QSUB,
1887 : QSUB16,
1888 : QSUB8,
1889 : RBIT,
1890 : REV,
1891 : REV16,
1892 : REVSH,
1893 : RFEDA,
1894 : RFEDA_UPD,
1895 : RFEDB,
1896 : RFEDB_UPD,
1897 : RFEIA,
1898 : RFEIA_UPD,
1899 : RFEIB,
1900 : RFEIB_UPD,
1901 : RSBri,
1902 : RSBrr,
1903 : RSBrsi,
1904 : RSBrsr,
1905 : RSCri,
1906 : RSCrr,
1907 : RSCrsi,
1908 : RSCrsr,
1909 : SADD16,
1910 : SADD8,
1911 : SASX,
1912 : SB,
1913 : SBCri,
1914 : SBCrr,
1915 : SBCrsi,
1916 : SBCrsr,
1917 : SBFX,
1918 : SDIV,
1919 : SEL,
1920 : SETEND,
1921 : SETPAN,
1922 : SHA1C,
1923 : SHA1H,
1924 : SHA1M,
1925 : SHA1P,
1926 : SHA1SU0,
1927 : SHA1SU1,
1928 : SHA256H,
1929 : SHA256H2,
1930 : SHA256SU0,
1931 : SHA256SU1,
1932 : SHADD16,
1933 : SHADD8,
1934 : SHASX,
1935 : SHSAX,
1936 : SHSUB16,
1937 : SHSUB8,
1938 : SMC,
1939 : SMLABB,
1940 : SMLABT,
1941 : SMLAD,
1942 : SMLADX,
1943 : SMLAL,
1944 : SMLALBB,
1945 : SMLALBT,
1946 : SMLALD,
1947 : SMLALDX,
1948 : SMLALTB,
1949 : SMLALTT,
1950 : SMLATB,
1951 : SMLATT,
1952 : SMLAWB,
1953 : SMLAWT,
1954 : SMLSD,
1955 : SMLSDX,
1956 : SMLSLD,
1957 : SMLSLDX,
1958 : SMMLA,
1959 : SMMLAR,
1960 : SMMLS,
1961 : SMMLSR,
1962 : SMMUL,
1963 : SMMULR,
1964 : SMUAD,
1965 : SMUADX,
1966 : SMULBB,
1967 : SMULBT,
1968 : SMULL,
1969 : SMULTB,
1970 : SMULTT,
1971 : SMULWB,
1972 : SMULWT,
1973 : SMUSD,
1974 : SMUSDX,
1975 : SRSDA,
1976 : SRSDA_UPD,
1977 : SRSDB,
1978 : SRSDB_UPD,
1979 : SRSIA,
1980 : SRSIA_UPD,
1981 : SRSIB,
1982 : SRSIB_UPD,
1983 : SSAT,
1984 : SSAT16,
1985 : SSAX,
1986 : SSUB16,
1987 : SSUB8,
1988 : STC2L_OFFSET,
1989 : STC2L_OPTION,
1990 : STC2L_POST,
1991 : STC2L_PRE,
1992 : STC2_OFFSET,
1993 : STC2_OPTION,
1994 : STC2_POST,
1995 : STC2_PRE,
1996 : STCL_OFFSET,
1997 : STCL_OPTION,
1998 : STCL_POST,
1999 : STCL_PRE,
2000 : STC_OFFSET,
2001 : STC_OPTION,
2002 : STC_POST,
2003 : STC_PRE,
2004 : STL,
2005 : STLB,
2006 : STLEX,
2007 : STLEXB,
2008 : STLEXD,
2009 : STLEXH,
2010 : STLH,
2011 : STMDA,
2012 : STMDA_UPD,
2013 : STMDB,
2014 : STMDB_UPD,
2015 : STMIA,
2016 : STMIA_UPD,
2017 : STMIB,
2018 : STMIB_UPD,
2019 : STRBT_POST_IMM,
2020 : STRBT_POST_REG,
2021 : STRB_POST_IMM,
2022 : STRB_POST_REG,
2023 : STRB_PRE_IMM,
2024 : STRB_PRE_REG,
2025 : STRBi12,
2026 : STRBrs,
2027 : STRD,
2028 : STRD_POST,
2029 : STRD_PRE,
2030 : STREX,
2031 : STREXB,
2032 : STREXD,
2033 : STREXH,
2034 : STRH,
2035 : STRHTi,
2036 : STRHTr,
2037 : STRH_POST,
2038 : STRH_PRE,
2039 : STRT_POST_IMM,
2040 : STRT_POST_REG,
2041 : STR_POST_IMM,
2042 : STR_POST_REG,
2043 : STR_PRE_IMM,
2044 : STR_PRE_REG,
2045 : STRi12,
2046 : STRrs,
2047 : SUBri,
2048 : SUBrr,
2049 : SUBrsi,
2050 : SUBrsr,
2051 : SVC,
2052 : SWP,
2053 : SWPB,
2054 : SXTAB,
2055 : SXTAB16,
2056 : SXTAH,
2057 : SXTB,
2058 : SXTB16,
2059 : SXTH,
2060 : TEQri,
2061 : TEQrr,
2062 : TEQrsi,
2063 : TEQrsr,
2064 : TRAP,
2065 : TSB,
2066 : TSTri,
2067 : TSTrr,
2068 : TSTrsi,
2069 : TSTrsr,
2070 : UADD16,
2071 : UADD8,
2072 : UASX,
2073 : UBFX,
2074 : UDF,
2075 : UDIV,
2076 : UHADD16,
2077 : UHADD8,
2078 : UHASX,
2079 : UHSAX,
2080 : UHSUB16,
2081 : UHSUB8,
2082 : UMAAL,
2083 : UMLAL,
2084 : UMULL,
2085 : UQADD16,
2086 : UQADD8,
2087 : UQASX,
2088 : UQSAX,
2089 : UQSUB16,
2090 : UQSUB8,
2091 : USAD8,
2092 : USADA8,
2093 : USAT,
2094 : USAT16,
2095 : USAX,
2096 : USUB16,
2097 : USUB8,
2098 : UXTAB,
2099 : UXTAB16,
2100 : UXTAH,
2101 : UXTB,
2102 : UXTB16,
2103 : UXTH,
2104 : VABALsv2i64,
2105 : VABALsv4i32,
2106 : VABALsv8i16,
2107 : VABALuv2i64,
2108 : VABALuv4i32,
2109 : VABALuv8i16,
2110 : VABAsv16i8,
2111 : VABAsv2i32,
2112 : VABAsv4i16,
2113 : VABAsv4i32,
2114 : VABAsv8i16,
2115 : VABAsv8i8,
2116 : VABAuv16i8,
2117 : VABAuv2i32,
2118 : VABAuv4i16,
2119 : VABAuv4i32,
2120 : VABAuv8i16,
2121 : VABAuv8i8,
2122 : VABDLsv2i64,
2123 : VABDLsv4i32,
2124 : VABDLsv8i16,
2125 : VABDLuv2i64,
2126 : VABDLuv4i32,
2127 : VABDLuv8i16,
2128 : VABDfd,
2129 : VABDfq,
2130 : VABDhd,
2131 : VABDhq,
2132 : VABDsv16i8,
2133 : VABDsv2i32,
2134 : VABDsv4i16,
2135 : VABDsv4i32,
2136 : VABDsv8i16,
2137 : VABDsv8i8,
2138 : VABDuv16i8,
2139 : VABDuv2i32,
2140 : VABDuv4i16,
2141 : VABDuv4i32,
2142 : VABDuv8i16,
2143 : VABDuv8i8,
2144 : VABSD,
2145 : VABSH,
2146 : VABSS,
2147 : VABSfd,
2148 : VABSfq,
2149 : VABShd,
2150 : VABShq,
2151 : VABSv16i8,
2152 : VABSv2i32,
2153 : VABSv4i16,
2154 : VABSv4i32,
2155 : VABSv8i16,
2156 : VABSv8i8,
2157 : VACGEfd,
2158 : VACGEfq,
2159 : VACGEhd,
2160 : VACGEhq,
2161 : VACGTfd,
2162 : VACGTfq,
2163 : VACGThd,
2164 : VACGThq,
2165 : VADDD,
2166 : VADDH,
2167 : VADDHNv2i32,
2168 : VADDHNv4i16,
2169 : VADDHNv8i8,
2170 : VADDLsv2i64,
2171 : VADDLsv4i32,
2172 : VADDLsv8i16,
2173 : VADDLuv2i64,
2174 : VADDLuv4i32,
2175 : VADDLuv8i16,
2176 : VADDS,
2177 : VADDWsv2i64,
2178 : VADDWsv4i32,
2179 : VADDWsv8i16,
2180 : VADDWuv2i64,
2181 : VADDWuv4i32,
2182 : VADDWuv8i16,
2183 : VADDfd,
2184 : VADDfq,
2185 : VADDhd,
2186 : VADDhq,
2187 : VADDv16i8,
2188 : VADDv1i64,
2189 : VADDv2i32,
2190 : VADDv2i64,
2191 : VADDv4i16,
2192 : VADDv4i32,
2193 : VADDv8i16,
2194 : VADDv8i8,
2195 : VANDd,
2196 : VANDq,
2197 : VBF16MALBQ,
2198 : VBF16MALBQI,
2199 : VBF16MALTQ,
2200 : VBF16MALTQI,
2201 : VBICd,
2202 : VBICiv2i32,
2203 : VBICiv4i16,
2204 : VBICiv4i32,
2205 : VBICiv8i16,
2206 : VBICq,
2207 : VBIFd,
2208 : VBIFq,
2209 : VBITd,
2210 : VBITq,
2211 : VBSLd,
2212 : VBSLq,
2213 : VBSPd,
2214 : VBSPq,
2215 : VCADDv2f32,
2216 : VCADDv4f16,
2217 : VCADDv4f32,
2218 : VCADDv8f16,
2219 : VCEQfd,
2220 : VCEQfq,
2221 : VCEQhd,
2222 : VCEQhq,
2223 : VCEQv16i8,
2224 : VCEQv2i32,
2225 : VCEQv4i16,
2226 : VCEQv4i32,
2227 : VCEQv8i16,
2228 : VCEQv8i8,
2229 : VCEQzv16i8,
2230 : VCEQzv2f32,
2231 : VCEQzv2i32,
2232 : VCEQzv4f16,
2233 : VCEQzv4f32,
2234 : VCEQzv4i16,
2235 : VCEQzv4i32,
2236 : VCEQzv8f16,
2237 : VCEQzv8i16,
2238 : VCEQzv8i8,
2239 : VCGEfd,
2240 : VCGEfq,
2241 : VCGEhd,
2242 : VCGEhq,
2243 : VCGEsv16i8,
2244 : VCGEsv2i32,
2245 : VCGEsv4i16,
2246 : VCGEsv4i32,
2247 : VCGEsv8i16,
2248 : VCGEsv8i8,
2249 : VCGEuv16i8,
2250 : VCGEuv2i32,
2251 : VCGEuv4i16,
2252 : VCGEuv4i32,
2253 : VCGEuv8i16,
2254 : VCGEuv8i8,
2255 : VCGEzv16i8,
2256 : VCGEzv2f32,
2257 : VCGEzv2i32,
2258 : VCGEzv4f16,
2259 : VCGEzv4f32,
2260 : VCGEzv4i16,
2261 : VCGEzv4i32,
2262 : VCGEzv8f16,
2263 : VCGEzv8i16,
2264 : VCGEzv8i8,
2265 : VCGTfd,
2266 : VCGTfq,
2267 : VCGThd,
2268 : VCGThq,
2269 : VCGTsv16i8,
2270 : VCGTsv2i32,
2271 : VCGTsv4i16,
2272 : VCGTsv4i32,
2273 : VCGTsv8i16,
2274 : VCGTsv8i8,
2275 : VCGTuv16i8,
2276 : VCGTuv2i32,
2277 : VCGTuv4i16,
2278 : VCGTuv4i32,
2279 : VCGTuv8i16,
2280 : VCGTuv8i8,
2281 : VCGTzv16i8,
2282 : VCGTzv2f32,
2283 : VCGTzv2i32,
2284 : VCGTzv4f16,
2285 : VCGTzv4f32,
2286 : VCGTzv4i16,
2287 : VCGTzv4i32,
2288 : VCGTzv8f16,
2289 : VCGTzv8i16,
2290 : VCGTzv8i8,
2291 : VCLEzv16i8,
2292 : VCLEzv2f32,
2293 : VCLEzv2i32,
2294 : VCLEzv4f16,
2295 : VCLEzv4f32,
2296 : VCLEzv4i16,
2297 : VCLEzv4i32,
2298 : VCLEzv8f16,
2299 : VCLEzv8i16,
2300 : VCLEzv8i8,
2301 : VCLSv16i8,
2302 : VCLSv2i32,
2303 : VCLSv4i16,
2304 : VCLSv4i32,
2305 : VCLSv8i16,
2306 : VCLSv8i8,
2307 : VCLTzv16i8,
2308 : VCLTzv2f32,
2309 : VCLTzv2i32,
2310 : VCLTzv4f16,
2311 : VCLTzv4f32,
2312 : VCLTzv4i16,
2313 : VCLTzv4i32,
2314 : VCLTzv8f16,
2315 : VCLTzv8i16,
2316 : VCLTzv8i8,
2317 : VCLZv16i8,
2318 : VCLZv2i32,
2319 : VCLZv4i16,
2320 : VCLZv4i32,
2321 : VCLZv8i16,
2322 : VCLZv8i8,
2323 : VCMLAv2f32,
2324 : VCMLAv2f32_indexed,
2325 : VCMLAv4f16,
2326 : VCMLAv4f16_indexed,
2327 : VCMLAv4f32,
2328 : VCMLAv4f32_indexed,
2329 : VCMLAv8f16,
2330 : VCMLAv8f16_indexed,
2331 : VCMPD,
2332 : VCMPED,
2333 : VCMPEH,
2334 : VCMPES,
2335 : VCMPEZD,
2336 : VCMPEZH,
2337 : VCMPEZS,
2338 : VCMPH,
2339 : VCMPS,
2340 : VCMPZD,
2341 : VCMPZH,
2342 : VCMPZS,
2343 : VCNTd,
2344 : VCNTq,
2345 : VCVTANSDf,
2346 : VCVTANSDh,
2347 : VCVTANSQf,
2348 : VCVTANSQh,
2349 : VCVTANUDf,
2350 : VCVTANUDh,
2351 : VCVTANUQf,
2352 : VCVTANUQh,
2353 : VCVTASD,
2354 : VCVTASH,
2355 : VCVTASS,
2356 : VCVTAUD,
2357 : VCVTAUH,
2358 : VCVTAUS,
2359 : VCVTBDH,
2360 : VCVTBHD,
2361 : VCVTBHS,
2362 : VCVTBSH,
2363 : VCVTDS,
2364 : VCVTMNSDf,
2365 : VCVTMNSDh,
2366 : VCVTMNSQf,
2367 : VCVTMNSQh,
2368 : VCVTMNUDf,
2369 : VCVTMNUDh,
2370 : VCVTMNUQf,
2371 : VCVTMNUQh,
2372 : VCVTMSD,
2373 : VCVTMSH,
2374 : VCVTMSS,
2375 : VCVTMUD,
2376 : VCVTMUH,
2377 : VCVTMUS,
2378 : VCVTNNSDf,
2379 : VCVTNNSDh,
2380 : VCVTNNSQf,
2381 : VCVTNNSQh,
2382 : VCVTNNUDf,
2383 : VCVTNNUDh,
2384 : VCVTNNUQf,
2385 : VCVTNNUQh,
2386 : VCVTNSD,
2387 : VCVTNSH,
2388 : VCVTNSS,
2389 : VCVTNUD,
2390 : VCVTNUH,
2391 : VCVTNUS,
2392 : VCVTPNSDf,
2393 : VCVTPNSDh,
2394 : VCVTPNSQf,
2395 : VCVTPNSQh,
2396 : VCVTPNUDf,
2397 : VCVTPNUDh,
2398 : VCVTPNUQf,
2399 : VCVTPNUQh,
2400 : VCVTPSD,
2401 : VCVTPSH,
2402 : VCVTPSS,
2403 : VCVTPUD,
2404 : VCVTPUH,
2405 : VCVTPUS,
2406 : VCVTSD,
2407 : VCVTTDH,
2408 : VCVTTHD,
2409 : VCVTTHS,
2410 : VCVTTSH,
2411 : VCVTf2h,
2412 : VCVTf2sd,
2413 : VCVTf2sq,
2414 : VCVTf2ud,
2415 : VCVTf2uq,
2416 : VCVTf2xsd,
2417 : VCVTf2xsq,
2418 : VCVTf2xud,
2419 : VCVTf2xuq,
2420 : VCVTh2f,
2421 : VCVTh2sd,
2422 : VCVTh2sq,
2423 : VCVTh2ud,
2424 : VCVTh2uq,
2425 : VCVTh2xsd,
2426 : VCVTh2xsq,
2427 : VCVTh2xud,
2428 : VCVTh2xuq,
2429 : VCVTs2fd,
2430 : VCVTs2fq,
2431 : VCVTs2hd,
2432 : VCVTs2hq,
2433 : VCVTu2fd,
2434 : VCVTu2fq,
2435 : VCVTu2hd,
2436 : VCVTu2hq,
2437 : VCVTxs2fd,
2438 : VCVTxs2fq,
2439 : VCVTxs2hd,
2440 : VCVTxs2hq,
2441 : VCVTxu2fd,
2442 : VCVTxu2fq,
2443 : VCVTxu2hd,
2444 : VCVTxu2hq,
2445 : VDIVD,
2446 : VDIVH,
2447 : VDIVS,
2448 : VDUP16d,
2449 : VDUP16q,
2450 : VDUP32d,
2451 : VDUP32q,
2452 : VDUP8d,
2453 : VDUP8q,
2454 : VDUPLN16d,
2455 : VDUPLN16q,
2456 : VDUPLN32d,
2457 : VDUPLN32q,
2458 : VDUPLN8d,
2459 : VDUPLN8q,
2460 : VEORd,
2461 : VEORq,
2462 : VEXTd16,
2463 : VEXTd32,
2464 : VEXTd8,
2465 : VEXTq16,
2466 : VEXTq32,
2467 : VEXTq64,
2468 : VEXTq8,
2469 : VFMAD,
2470 : VFMAH,
2471 : VFMALD,
2472 : VFMALDI,
2473 : VFMALQ,
2474 : VFMALQI,
2475 : VFMAS,
2476 : VFMAfd,
2477 : VFMAfq,
2478 : VFMAhd,
2479 : VFMAhq,
2480 : VFMSD,
2481 : VFMSH,
2482 : VFMSLD,
2483 : VFMSLDI,
2484 : VFMSLQ,
2485 : VFMSLQI,
2486 : VFMSS,
2487 : VFMSfd,
2488 : VFMSfq,
2489 : VFMShd,
2490 : VFMShq,
2491 : VFNMAD,
2492 : VFNMAH,
2493 : VFNMAS,
2494 : VFNMSD,
2495 : VFNMSH,
2496 : VFNMSS,
2497 : VFP_VMAXNMD,
2498 : VFP_VMAXNMH,
2499 : VFP_VMAXNMS,
2500 : VFP_VMINNMD,
2501 : VFP_VMINNMH,
2502 : VFP_VMINNMS,
2503 : VGETLNi32,
2504 : VGETLNs16,
2505 : VGETLNs8,
2506 : VGETLNu16,
2507 : VGETLNu8,
2508 : VHADDsv16i8,
2509 : VHADDsv2i32,
2510 : VHADDsv4i16,
2511 : VHADDsv4i32,
2512 : VHADDsv8i16,
2513 : VHADDsv8i8,
2514 : VHADDuv16i8,
2515 : VHADDuv2i32,
2516 : VHADDuv4i16,
2517 : VHADDuv4i32,
2518 : VHADDuv8i16,
2519 : VHADDuv8i8,
2520 : VHSUBsv16i8,
2521 : VHSUBsv2i32,
2522 : VHSUBsv4i16,
2523 : VHSUBsv4i32,
2524 : VHSUBsv8i16,
2525 : VHSUBsv8i8,
2526 : VHSUBuv16i8,
2527 : VHSUBuv2i32,
2528 : VHSUBuv4i16,
2529 : VHSUBuv4i32,
2530 : VHSUBuv8i16,
2531 : VHSUBuv8i8,
2532 : VINSH,
2533 : VJCVT,
2534 : VLD1DUPd16,
2535 : VLD1DUPd16wb_fixed,
2536 : VLD1DUPd16wb_register,
2537 : VLD1DUPd32,
2538 : VLD1DUPd32wb_fixed,
2539 : VLD1DUPd32wb_register,
2540 : VLD1DUPd8,
2541 : VLD1DUPd8wb_fixed,
2542 : VLD1DUPd8wb_register,
2543 : VLD1DUPq16,
2544 : VLD1DUPq16wb_fixed,
2545 : VLD1DUPq16wb_register,
2546 : VLD1DUPq32,
2547 : VLD1DUPq32wb_fixed,
2548 : VLD1DUPq32wb_register,
2549 : VLD1DUPq8,
2550 : VLD1DUPq8wb_fixed,
2551 : VLD1DUPq8wb_register,
2552 : VLD1LNd16,
2553 : VLD1LNd16_UPD,
2554 : VLD1LNd32,
2555 : VLD1LNd32_UPD,
2556 : VLD1LNd8,
2557 : VLD1LNd8_UPD,
2558 : VLD1LNq16Pseudo,
2559 : VLD1LNq16Pseudo_UPD,
2560 : VLD1LNq32Pseudo,
2561 : VLD1LNq32Pseudo_UPD,
2562 : VLD1LNq8Pseudo,
2563 : VLD1LNq8Pseudo_UPD,
2564 : VLD1d16,
2565 : VLD1d16Q,
2566 : VLD1d16QPseudo,
2567 : VLD1d16QPseudoWB_fixed,
2568 : VLD1d16QPseudoWB_register,
2569 : VLD1d16Qwb_fixed,
2570 : VLD1d16Qwb_register,
2571 : VLD1d16T,
2572 : VLD1d16TPseudo,
2573 : VLD1d16TPseudoWB_fixed,
2574 : VLD1d16TPseudoWB_register,
2575 : VLD1d16Twb_fixed,
2576 : VLD1d16Twb_register,
2577 : VLD1d16wb_fixed,
2578 : VLD1d16wb_register,
2579 : VLD1d32,
2580 : VLD1d32Q,
2581 : VLD1d32QPseudo,
2582 : VLD1d32QPseudoWB_fixed,
2583 : VLD1d32QPseudoWB_register,
2584 : VLD1d32Qwb_fixed,
2585 : VLD1d32Qwb_register,
2586 : VLD1d32T,
2587 : VLD1d32TPseudo,
2588 : VLD1d32TPseudoWB_fixed,
2589 : VLD1d32TPseudoWB_register,
2590 : VLD1d32Twb_fixed,
2591 : VLD1d32Twb_register,
2592 : VLD1d32wb_fixed,
2593 : VLD1d32wb_register,
2594 : VLD1d64,
2595 : VLD1d64Q,
2596 : VLD1d64QPseudo,
2597 : VLD1d64QPseudoWB_fixed,
2598 : VLD1d64QPseudoWB_register,
2599 : VLD1d64Qwb_fixed,
2600 : VLD1d64Qwb_register,
2601 : VLD1d64T,
2602 : VLD1d64TPseudo,
2603 : VLD1d64TPseudoWB_fixed,
2604 : VLD1d64TPseudoWB_register,
2605 : VLD1d64Twb_fixed,
2606 : VLD1d64Twb_register,
2607 : VLD1d64wb_fixed,
2608 : VLD1d64wb_register,
2609 : VLD1d8,
2610 : VLD1d8Q,
2611 : VLD1d8QPseudo,
2612 : VLD1d8QPseudoWB_fixed,
2613 : VLD1d8QPseudoWB_register,
2614 : VLD1d8Qwb_fixed,
2615 : VLD1d8Qwb_register,
2616 : VLD1d8T,
2617 : VLD1d8TPseudo,
2618 : VLD1d8TPseudoWB_fixed,
2619 : VLD1d8TPseudoWB_register,
2620 : VLD1d8Twb_fixed,
2621 : VLD1d8Twb_register,
2622 : VLD1d8wb_fixed,
2623 : VLD1d8wb_register,
2624 : VLD1q16,
2625 : VLD1q16HighQPseudo,
2626 : VLD1q16HighQPseudo_UPD,
2627 : VLD1q16HighTPseudo,
2628 : VLD1q16HighTPseudo_UPD,
2629 : VLD1q16LowQPseudo_UPD,
2630 : VLD1q16LowTPseudo_UPD,
2631 : VLD1q16wb_fixed,
2632 : VLD1q16wb_register,
2633 : VLD1q32,
2634 : VLD1q32HighQPseudo,
2635 : VLD1q32HighQPseudo_UPD,
2636 : VLD1q32HighTPseudo,
2637 : VLD1q32HighTPseudo_UPD,
2638 : VLD1q32LowQPseudo_UPD,
2639 : VLD1q32LowTPseudo_UPD,
2640 : VLD1q32wb_fixed,
2641 : VLD1q32wb_register,
2642 : VLD1q64,
2643 : VLD1q64HighQPseudo,
2644 : VLD1q64HighQPseudo_UPD,
2645 : VLD1q64HighTPseudo,
2646 : VLD1q64HighTPseudo_UPD,
2647 : VLD1q64LowQPseudo_UPD,
2648 : VLD1q64LowTPseudo_UPD,
2649 : VLD1q64wb_fixed,
2650 : VLD1q64wb_register,
2651 : VLD1q8,
2652 : VLD1q8HighQPseudo,
2653 : VLD1q8HighQPseudo_UPD,
2654 : VLD1q8HighTPseudo,
2655 : VLD1q8HighTPseudo_UPD,
2656 : VLD1q8LowQPseudo_UPD,
2657 : VLD1q8LowTPseudo_UPD,
2658 : VLD1q8wb_fixed,
2659 : VLD1q8wb_register,
2660 : VLD2DUPd16,
2661 : VLD2DUPd16wb_fixed,
2662 : VLD2DUPd16wb_register,
2663 : VLD2DUPd16x2,
2664 : VLD2DUPd16x2wb_fixed,
2665 : VLD2DUPd16x2wb_register,
2666 : VLD2DUPd32,
2667 : VLD2DUPd32wb_fixed,
2668 : VLD2DUPd32wb_register,
2669 : VLD2DUPd32x2,
2670 : VLD2DUPd32x2wb_fixed,
2671 : VLD2DUPd32x2wb_register,
2672 : VLD2DUPd8,
2673 : VLD2DUPd8wb_fixed,
2674 : VLD2DUPd8wb_register,
2675 : VLD2DUPd8x2,
2676 : VLD2DUPd8x2wb_fixed,
2677 : VLD2DUPd8x2wb_register,
2678 : VLD2DUPq16EvenPseudo,
2679 : VLD2DUPq16OddPseudo,
2680 : VLD2DUPq16OddPseudoWB_fixed,
2681 : VLD2DUPq16OddPseudoWB_register,
2682 : VLD2DUPq32EvenPseudo,
2683 : VLD2DUPq32OddPseudo,
2684 : VLD2DUPq32OddPseudoWB_fixed,
2685 : VLD2DUPq32OddPseudoWB_register,
2686 : VLD2DUPq8EvenPseudo,
2687 : VLD2DUPq8OddPseudo,
2688 : VLD2DUPq8OddPseudoWB_fixed,
2689 : VLD2DUPq8OddPseudoWB_register,
2690 : VLD2LNd16,
2691 : VLD2LNd16Pseudo,
2692 : VLD2LNd16Pseudo_UPD,
2693 : VLD2LNd16_UPD,
2694 : VLD2LNd32,
2695 : VLD2LNd32Pseudo,
2696 : VLD2LNd32Pseudo_UPD,
2697 : VLD2LNd32_UPD,
2698 : VLD2LNd8,
2699 : VLD2LNd8Pseudo,
2700 : VLD2LNd8Pseudo_UPD,
2701 : VLD2LNd8_UPD,
2702 : VLD2LNq16,
2703 : VLD2LNq16Pseudo,
2704 : VLD2LNq16Pseudo_UPD,
2705 : VLD2LNq16_UPD,
2706 : VLD2LNq32,
2707 : VLD2LNq32Pseudo,
2708 : VLD2LNq32Pseudo_UPD,
2709 : VLD2LNq32_UPD,
2710 : VLD2b16,
2711 : VLD2b16wb_fixed,
2712 : VLD2b16wb_register,
2713 : VLD2b32,
2714 : VLD2b32wb_fixed,
2715 : VLD2b32wb_register,
2716 : VLD2b8,
2717 : VLD2b8wb_fixed,
2718 : VLD2b8wb_register,
2719 : VLD2d16,
2720 : VLD2d16wb_fixed,
2721 : VLD2d16wb_register,
2722 : VLD2d32,
2723 : VLD2d32wb_fixed,
2724 : VLD2d32wb_register,
2725 : VLD2d8,
2726 : VLD2d8wb_fixed,
2727 : VLD2d8wb_register,
2728 : VLD2q16,
2729 : VLD2q16Pseudo,
2730 : VLD2q16PseudoWB_fixed,
2731 : VLD2q16PseudoWB_register,
2732 : VLD2q16wb_fixed,
2733 : VLD2q16wb_register,
2734 : VLD2q32,
2735 : VLD2q32Pseudo,
2736 : VLD2q32PseudoWB_fixed,
2737 : VLD2q32PseudoWB_register,
2738 : VLD2q32wb_fixed,
2739 : VLD2q32wb_register,
2740 : VLD2q8,
2741 : VLD2q8Pseudo,
2742 : VLD2q8PseudoWB_fixed,
2743 : VLD2q8PseudoWB_register,
2744 : VLD2q8wb_fixed,
2745 : VLD2q8wb_register,
2746 : VLD3DUPd16,
2747 : VLD3DUPd16Pseudo,
2748 : VLD3DUPd16Pseudo_UPD,
2749 : VLD3DUPd16_UPD,
2750 : VLD3DUPd32,
2751 : VLD3DUPd32Pseudo,
2752 : VLD3DUPd32Pseudo_UPD,
2753 : VLD3DUPd32_UPD,
2754 : VLD3DUPd8,
2755 : VLD3DUPd8Pseudo,
2756 : VLD3DUPd8Pseudo_UPD,
2757 : VLD3DUPd8_UPD,
2758 : VLD3DUPq16,
2759 : VLD3DUPq16EvenPseudo,
2760 : VLD3DUPq16OddPseudo,
2761 : VLD3DUPq16OddPseudo_UPD,
2762 : VLD3DUPq16_UPD,
2763 : VLD3DUPq32,
2764 : VLD3DUPq32EvenPseudo,
2765 : VLD3DUPq32OddPseudo,
2766 : VLD3DUPq32OddPseudo_UPD,
2767 : VLD3DUPq32_UPD,
2768 : VLD3DUPq8,
2769 : VLD3DUPq8EvenPseudo,
2770 : VLD3DUPq8OddPseudo,
2771 : VLD3DUPq8OddPseudo_UPD,
2772 : VLD3DUPq8_UPD,
2773 : VLD3LNd16,
2774 : VLD3LNd16Pseudo,
2775 : VLD3LNd16Pseudo_UPD,
2776 : VLD3LNd16_UPD,
2777 : VLD3LNd32,
2778 : VLD3LNd32Pseudo,
2779 : VLD3LNd32Pseudo_UPD,
2780 : VLD3LNd32_UPD,
2781 : VLD3LNd8,
2782 : VLD3LNd8Pseudo,
2783 : VLD3LNd8Pseudo_UPD,
2784 : VLD3LNd8_UPD,
2785 : VLD3LNq16,
2786 : VLD3LNq16Pseudo,
2787 : VLD3LNq16Pseudo_UPD,
2788 : VLD3LNq16_UPD,
2789 : VLD3LNq32,
2790 : VLD3LNq32Pseudo,
2791 : VLD3LNq32Pseudo_UPD,
2792 : VLD3LNq32_UPD,
2793 : VLD3d16,
2794 : VLD3d16Pseudo,
2795 : VLD3d16Pseudo_UPD,
2796 : VLD3d16_UPD,
2797 : VLD3d32,
2798 : VLD3d32Pseudo,
2799 : VLD3d32Pseudo_UPD,
2800 : VLD3d32_UPD,
2801 : VLD3d8,
2802 : VLD3d8Pseudo,
2803 : VLD3d8Pseudo_UPD,
2804 : VLD3d8_UPD,
2805 : VLD3q16,
2806 : VLD3q16Pseudo_UPD,
2807 : VLD3q16_UPD,
2808 : VLD3q16oddPseudo,
2809 : VLD3q16oddPseudo_UPD,
2810 : VLD3q32,
2811 : VLD3q32Pseudo_UPD,
2812 : VLD3q32_UPD,
2813 : VLD3q32oddPseudo,
2814 : VLD3q32oddPseudo_UPD,
2815 : VLD3q8,
2816 : VLD3q8Pseudo_UPD,
2817 : VLD3q8_UPD,
2818 : VLD3q8oddPseudo,
2819 : VLD3q8oddPseudo_UPD,
2820 : VLD4DUPd16,
2821 : VLD4DUPd16Pseudo,
2822 : VLD4DUPd16Pseudo_UPD,
2823 : VLD4DUPd16_UPD,
2824 : VLD4DUPd32,
2825 : VLD4DUPd32Pseudo,
2826 : VLD4DUPd32Pseudo_UPD,
2827 : VLD4DUPd32_UPD,
2828 : VLD4DUPd8,
2829 : VLD4DUPd8Pseudo,
2830 : VLD4DUPd8Pseudo_UPD,
2831 : VLD4DUPd8_UPD,
2832 : VLD4DUPq16,
2833 : VLD4DUPq16EvenPseudo,
2834 : VLD4DUPq16OddPseudo,
2835 : VLD4DUPq16OddPseudo_UPD,
2836 : VLD4DUPq16_UPD,
2837 : VLD4DUPq32,
2838 : VLD4DUPq32EvenPseudo,
2839 : VLD4DUPq32OddPseudo,
2840 : VLD4DUPq32OddPseudo_UPD,
2841 : VLD4DUPq32_UPD,
2842 : VLD4DUPq8,
2843 : VLD4DUPq8EvenPseudo,
2844 : VLD4DUPq8OddPseudo,
2845 : VLD4DUPq8OddPseudo_UPD,
2846 : VLD4DUPq8_UPD,
2847 : VLD4LNd16,
2848 : VLD4LNd16Pseudo,
2849 : VLD4LNd16Pseudo_UPD,
2850 : VLD4LNd16_UPD,
2851 : VLD4LNd32,
2852 : VLD4LNd32Pseudo,
2853 : VLD4LNd32Pseudo_UPD,
2854 : VLD4LNd32_UPD,
2855 : VLD4LNd8,
2856 : VLD4LNd8Pseudo,
2857 : VLD4LNd8Pseudo_UPD,
2858 : VLD4LNd8_UPD,
2859 : VLD4LNq16,
2860 : VLD4LNq16Pseudo,
2861 : VLD4LNq16Pseudo_UPD,
2862 : VLD4LNq16_UPD,
2863 : VLD4LNq32,
2864 : VLD4LNq32Pseudo,
2865 : VLD4LNq32Pseudo_UPD,
2866 : VLD4LNq32_UPD,
2867 : VLD4d16,
2868 : VLD4d16Pseudo,
2869 : VLD4d16Pseudo_UPD,
2870 : VLD4d16_UPD,
2871 : VLD4d32,
2872 : VLD4d32Pseudo,
2873 : VLD4d32Pseudo_UPD,
2874 : VLD4d32_UPD,
2875 : VLD4d8,
2876 : VLD4d8Pseudo,
2877 : VLD4d8Pseudo_UPD,
2878 : VLD4d8_UPD,
2879 : VLD4q16,
2880 : VLD4q16Pseudo_UPD,
2881 : VLD4q16_UPD,
2882 : VLD4q16oddPseudo,
2883 : VLD4q16oddPseudo_UPD,
2884 : VLD4q32,
2885 : VLD4q32Pseudo_UPD,
2886 : VLD4q32_UPD,
2887 : VLD4q32oddPseudo,
2888 : VLD4q32oddPseudo_UPD,
2889 : VLD4q8,
2890 : VLD4q8Pseudo_UPD,
2891 : VLD4q8_UPD,
2892 : VLD4q8oddPseudo,
2893 : VLD4q8oddPseudo_UPD,
2894 : VLDMDDB_UPD,
2895 : VLDMDIA,
2896 : VLDMDIA_UPD,
2897 : VLDMQIA,
2898 : VLDMSDB_UPD,
2899 : VLDMSIA,
2900 : VLDMSIA_UPD,
2901 : VLDRD,
2902 : VLDRH,
2903 : VLDRS,
2904 : VLDR_FPCXTNS_off,
2905 : VLDR_FPCXTNS_post,
2906 : VLDR_FPCXTNS_pre,
2907 : VLDR_FPCXTS_off,
2908 : VLDR_FPCXTS_post,
2909 : VLDR_FPCXTS_pre,
2910 : VLDR_FPSCR_NZCVQC_off,
2911 : VLDR_FPSCR_NZCVQC_post,
2912 : VLDR_FPSCR_NZCVQC_pre,
2913 : VLDR_FPSCR_off,
2914 : VLDR_FPSCR_post,
2915 : VLDR_FPSCR_pre,
2916 : VLDR_P0_off,
2917 : VLDR_P0_post,
2918 : VLDR_P0_pre,
2919 : VLDR_VPR_off,
2920 : VLDR_VPR_post,
2921 : VLDR_VPR_pre,
2922 : VLLDM,
2923 : VLLDM_T2,
2924 : VLSTM,
2925 : VLSTM_T2,
2926 : VMAXfd,
2927 : VMAXfq,
2928 : VMAXhd,
2929 : VMAXhq,
2930 : VMAXsv16i8,
2931 : VMAXsv2i32,
2932 : VMAXsv4i16,
2933 : VMAXsv4i32,
2934 : VMAXsv8i16,
2935 : VMAXsv8i8,
2936 : VMAXuv16i8,
2937 : VMAXuv2i32,
2938 : VMAXuv4i16,
2939 : VMAXuv4i32,
2940 : VMAXuv8i16,
2941 : VMAXuv8i8,
2942 : VMINfd,
2943 : VMINfq,
2944 : VMINhd,
2945 : VMINhq,
2946 : VMINsv16i8,
2947 : VMINsv2i32,
2948 : VMINsv4i16,
2949 : VMINsv4i32,
2950 : VMINsv8i16,
2951 : VMINsv8i8,
2952 : VMINuv16i8,
2953 : VMINuv2i32,
2954 : VMINuv4i16,
2955 : VMINuv4i32,
2956 : VMINuv8i16,
2957 : VMINuv8i8,
2958 : VMLAD,
2959 : VMLAH,
2960 : VMLALslsv2i32,
2961 : VMLALslsv4i16,
2962 : VMLALsluv2i32,
2963 : VMLALsluv4i16,
2964 : VMLALsv2i64,
2965 : VMLALsv4i32,
2966 : VMLALsv8i16,
2967 : VMLALuv2i64,
2968 : VMLALuv4i32,
2969 : VMLALuv8i16,
2970 : VMLAS,
2971 : VMLAfd,
2972 : VMLAfq,
2973 : VMLAhd,
2974 : VMLAhq,
2975 : VMLAslfd,
2976 : VMLAslfq,
2977 : VMLAslhd,
2978 : VMLAslhq,
2979 : VMLAslv2i32,
2980 : VMLAslv4i16,
2981 : VMLAslv4i32,
2982 : VMLAslv8i16,
2983 : VMLAv16i8,
2984 : VMLAv2i32,
2985 : VMLAv4i16,
2986 : VMLAv4i32,
2987 : VMLAv8i16,
2988 : VMLAv8i8,
2989 : VMLSD,
2990 : VMLSH,
2991 : VMLSLslsv2i32,
2992 : VMLSLslsv4i16,
2993 : VMLSLsluv2i32,
2994 : VMLSLsluv4i16,
2995 : VMLSLsv2i64,
2996 : VMLSLsv4i32,
2997 : VMLSLsv8i16,
2998 : VMLSLuv2i64,
2999 : VMLSLuv4i32,
3000 : VMLSLuv8i16,
3001 : VMLSS,
3002 : VMLSfd,
3003 : VMLSfq,
3004 : VMLShd,
3005 : VMLShq,
3006 : VMLSslfd,
3007 : VMLSslfq,
3008 : VMLSslhd,
3009 : VMLSslhq,
3010 : VMLSslv2i32,
3011 : VMLSslv4i16,
3012 : VMLSslv4i32,
3013 : VMLSslv8i16,
3014 : VMLSv16i8,
3015 : VMLSv2i32,
3016 : VMLSv4i16,
3017 : VMLSv4i32,
3018 : VMLSv8i16,
3019 : VMLSv8i8,
3020 : VMMLA,
3021 : VMOVD,
3022 : VMOVDRR,
3023 : VMOVH,
3024 : VMOVHR,
3025 : VMOVLsv2i64,
3026 : VMOVLsv4i32,
3027 : VMOVLsv8i16,
3028 : VMOVLuv2i64,
3029 : VMOVLuv4i32,
3030 : VMOVLuv8i16,
3031 : VMOVNv2i32,
3032 : VMOVNv4i16,
3033 : VMOVNv8i8,
3034 : VMOVRH,
3035 : VMOVRRD,
3036 : VMOVRRS,
3037 : VMOVRS,
3038 : VMOVS,
3039 : VMOVSR,
3040 : VMOVSRR,
3041 : VMOVv16i8,
3042 : VMOVv1i64,
3043 : VMOVv2f32,
3044 : VMOVv2i32,
3045 : VMOVv2i64,
3046 : VMOVv4f32,
3047 : VMOVv4i16,
3048 : VMOVv4i32,
3049 : VMOVv8i16,
3050 : VMOVv8i8,
3051 : VMRS,
3052 : VMRS_FPCXTNS,
3053 : VMRS_FPCXTS,
3054 : VMRS_FPEXC,
3055 : VMRS_FPINST,
3056 : VMRS_FPINST2,
3057 : VMRS_FPSCR_NZCVQC,
3058 : VMRS_FPSID,
3059 : VMRS_MVFR0,
3060 : VMRS_MVFR1,
3061 : VMRS_MVFR2,
3062 : VMRS_P0,
3063 : VMRS_VPR,
3064 : VMSR,
3065 : VMSR_FPCXTNS,
3066 : VMSR_FPCXTS,
3067 : VMSR_FPEXC,
3068 : VMSR_FPINST,
3069 : VMSR_FPINST2,
3070 : VMSR_FPSCR_NZCVQC,
3071 : VMSR_FPSID,
3072 : VMSR_P0,
3073 : VMSR_VPR,
3074 : VMULD,
3075 : VMULH,
3076 : VMULLp64,
3077 : VMULLp8,
3078 : VMULLslsv2i32,
3079 : VMULLslsv4i16,
3080 : VMULLsluv2i32,
3081 : VMULLsluv4i16,
3082 : VMULLsv2i64,
3083 : VMULLsv4i32,
3084 : VMULLsv8i16,
3085 : VMULLuv2i64,
3086 : VMULLuv4i32,
3087 : VMULLuv8i16,
3088 : VMULS,
3089 : VMULfd,
3090 : VMULfq,
3091 : VMULhd,
3092 : VMULhq,
3093 : VMULpd,
3094 : VMULpq,
3095 : VMULslfd,
3096 : VMULslfq,
3097 : VMULslhd,
3098 : VMULslhq,
3099 : VMULslv2i32,
3100 : VMULslv4i16,
3101 : VMULslv4i32,
3102 : VMULslv8i16,
3103 : VMULv16i8,
3104 : VMULv2i32,
3105 : VMULv4i16,
3106 : VMULv4i32,
3107 : VMULv8i16,
3108 : VMULv8i8,
3109 : VMVNd,
3110 : VMVNq,
3111 : VMVNv2i32,
3112 : VMVNv4i16,
3113 : VMVNv4i32,
3114 : VMVNv8i16,
3115 : VNEGD,
3116 : VNEGH,
3117 : VNEGS,
3118 : VNEGf32q,
3119 : VNEGfd,
3120 : VNEGhd,
3121 : VNEGhq,
3122 : VNEGs16d,
3123 : VNEGs16q,
3124 : VNEGs32d,
3125 : VNEGs32q,
3126 : VNEGs8d,
3127 : VNEGs8q,
3128 : VNMLAD,
3129 : VNMLAH,
3130 : VNMLAS,
3131 : VNMLSD,
3132 : VNMLSH,
3133 : VNMLSS,
3134 : VNMULD,
3135 : VNMULH,
3136 : VNMULS,
3137 : VORNd,
3138 : VORNq,
3139 : VORRd,
3140 : VORRiv2i32,
3141 : VORRiv4i16,
3142 : VORRiv4i32,
3143 : VORRiv8i16,
3144 : VORRq,
3145 : VPADALsv16i8,
3146 : VPADALsv2i32,
3147 : VPADALsv4i16,
3148 : VPADALsv4i32,
3149 : VPADALsv8i16,
3150 : VPADALsv8i8,
3151 : VPADALuv16i8,
3152 : VPADALuv2i32,
3153 : VPADALuv4i16,
3154 : VPADALuv4i32,
3155 : VPADALuv8i16,
3156 : VPADALuv8i8,
3157 : VPADDLsv16i8,
3158 : VPADDLsv2i32,
3159 : VPADDLsv4i16,
3160 : VPADDLsv4i32,
3161 : VPADDLsv8i16,
3162 : VPADDLsv8i8,
3163 : VPADDLuv16i8,
3164 : VPADDLuv2i32,
3165 : VPADDLuv4i16,
3166 : VPADDLuv4i32,
3167 : VPADDLuv8i16,
3168 : VPADDLuv8i8,
3169 : VPADDf,
3170 : VPADDh,
3171 : VPADDi16,
3172 : VPADDi32,
3173 : VPADDi8,
3174 : VPMAXf,
3175 : VPMAXh,
3176 : VPMAXs16,
3177 : VPMAXs32,
3178 : VPMAXs8,
3179 : VPMAXu16,
3180 : VPMAXu32,
3181 : VPMAXu8,
3182 : VPMINf,
3183 : VPMINh,
3184 : VPMINs16,
3185 : VPMINs32,
3186 : VPMINs8,
3187 : VPMINu16,
3188 : VPMINu32,
3189 : VPMINu8,
3190 : VQABSv16i8,
3191 : VQABSv2i32,
3192 : VQABSv4i16,
3193 : VQABSv4i32,
3194 : VQABSv8i16,
3195 : VQABSv8i8,
3196 : VQADDsv16i8,
3197 : VQADDsv1i64,
3198 : VQADDsv2i32,
3199 : VQADDsv2i64,
3200 : VQADDsv4i16,
3201 : VQADDsv4i32,
3202 : VQADDsv8i16,
3203 : VQADDsv8i8,
3204 : VQADDuv16i8,
3205 : VQADDuv1i64,
3206 : VQADDuv2i32,
3207 : VQADDuv2i64,
3208 : VQADDuv4i16,
3209 : VQADDuv4i32,
3210 : VQADDuv8i16,
3211 : VQADDuv8i8,
3212 : VQDMLALslv2i32,
3213 : VQDMLALslv4i16,
3214 : VQDMLALv2i64,
3215 : VQDMLALv4i32,
3216 : VQDMLSLslv2i32,
3217 : VQDMLSLslv4i16,
3218 : VQDMLSLv2i64,
3219 : VQDMLSLv4i32,
3220 : VQDMULHslv2i32,
3221 : VQDMULHslv4i16,
3222 : VQDMULHslv4i32,
3223 : VQDMULHslv8i16,
3224 : VQDMULHv2i32,
3225 : VQDMULHv4i16,
3226 : VQDMULHv4i32,
3227 : VQDMULHv8i16,
3228 : VQDMULLslv2i32,
3229 : VQDMULLslv4i16,
3230 : VQDMULLv2i64,
3231 : VQDMULLv4i32,
3232 : VQMOVNsuv2i32,
3233 : VQMOVNsuv4i16,
3234 : VQMOVNsuv8i8,
3235 : VQMOVNsv2i32,
3236 : VQMOVNsv4i16,
3237 : VQMOVNsv8i8,
3238 : VQMOVNuv2i32,
3239 : VQMOVNuv4i16,
3240 : VQMOVNuv8i8,
3241 : VQNEGv16i8,
3242 : VQNEGv2i32,
3243 : VQNEGv4i16,
3244 : VQNEGv4i32,
3245 : VQNEGv8i16,
3246 : VQNEGv8i8,
3247 : VQRDMLAHslv2i32,
3248 : VQRDMLAHslv4i16,
3249 : VQRDMLAHslv4i32,
3250 : VQRDMLAHslv8i16,
3251 : VQRDMLAHv2i32,
3252 : VQRDMLAHv4i16,
3253 : VQRDMLAHv4i32,
3254 : VQRDMLAHv8i16,
3255 : VQRDMLSHslv2i32,
3256 : VQRDMLSHslv4i16,
3257 : VQRDMLSHslv4i32,
3258 : VQRDMLSHslv8i16,
3259 : VQRDMLSHv2i32,
3260 : VQRDMLSHv4i16,
3261 : VQRDMLSHv4i32,
3262 : VQRDMLSHv8i16,
3263 : VQRDMULHslv2i32,
3264 : VQRDMULHslv4i16,
3265 : VQRDMULHslv4i32,
3266 : VQRDMULHslv8i16,
3267 : VQRDMULHv2i32,
3268 : VQRDMULHv4i16,
3269 : VQRDMULHv4i32,
3270 : VQRDMULHv8i16,
3271 : VQRSHLsv16i8,
3272 : VQRSHLsv1i64,
3273 : VQRSHLsv2i32,
3274 : VQRSHLsv2i64,
3275 : VQRSHLsv4i16,
3276 : VQRSHLsv4i32,
3277 : VQRSHLsv8i16,
3278 : VQRSHLsv8i8,
3279 : VQRSHLuv16i8,
3280 : VQRSHLuv1i64,
3281 : VQRSHLuv2i32,
3282 : VQRSHLuv2i64,
3283 : VQRSHLuv4i16,
3284 : VQRSHLuv4i32,
3285 : VQRSHLuv8i16,
3286 : VQRSHLuv8i8,
3287 : VQRSHRNsv2i32,
3288 : VQRSHRNsv4i16,
3289 : VQRSHRNsv8i8,
3290 : VQRSHRNuv2i32,
3291 : VQRSHRNuv4i16,
3292 : VQRSHRNuv8i8,
3293 : VQRSHRUNv2i32,
3294 : VQRSHRUNv4i16,
3295 : VQRSHRUNv8i8,
3296 : VQSHLsiv16i8,
3297 : VQSHLsiv1i64,
3298 : VQSHLsiv2i32,
3299 : VQSHLsiv2i64,
3300 : VQSHLsiv4i16,
3301 : VQSHLsiv4i32,
3302 : VQSHLsiv8i16,
3303 : VQSHLsiv8i8,
3304 : VQSHLsuv16i8,
3305 : VQSHLsuv1i64,
3306 : VQSHLsuv2i32,
3307 : VQSHLsuv2i64,
3308 : VQSHLsuv4i16,
3309 : VQSHLsuv4i32,
3310 : VQSHLsuv8i16,
3311 : VQSHLsuv8i8,
3312 : VQSHLsv16i8,
3313 : VQSHLsv1i64,
3314 : VQSHLsv2i32,
3315 : VQSHLsv2i64,
3316 : VQSHLsv4i16,
3317 : VQSHLsv4i32,
3318 : VQSHLsv8i16,
3319 : VQSHLsv8i8,
3320 : VQSHLuiv16i8,
3321 : VQSHLuiv1i64,
3322 : VQSHLuiv2i32,
3323 : VQSHLuiv2i64,
3324 : VQSHLuiv4i16,
3325 : VQSHLuiv4i32,
3326 : VQSHLuiv8i16,
3327 : VQSHLuiv8i8,
3328 : VQSHLuv16i8,
3329 : VQSHLuv1i64,
3330 : VQSHLuv2i32,
3331 : VQSHLuv2i64,
3332 : VQSHLuv4i16,
3333 : VQSHLuv4i32,
3334 : VQSHLuv8i16,
3335 : VQSHLuv8i8,
3336 : VQSHRNsv2i32,
3337 : VQSHRNsv4i16,
3338 : VQSHRNsv8i8,
3339 : VQSHRNuv2i32,
3340 : VQSHRNuv4i16,
3341 : VQSHRNuv8i8,
3342 : VQSHRUNv2i32,
3343 : VQSHRUNv4i16,
3344 : VQSHRUNv8i8,
3345 : VQSUBsv16i8,
3346 : VQSUBsv1i64,
3347 : VQSUBsv2i32,
3348 : VQSUBsv2i64,
3349 : VQSUBsv4i16,
3350 : VQSUBsv4i32,
3351 : VQSUBsv8i16,
3352 : VQSUBsv8i8,
3353 : VQSUBuv16i8,
3354 : VQSUBuv1i64,
3355 : VQSUBuv2i32,
3356 : VQSUBuv2i64,
3357 : VQSUBuv4i16,
3358 : VQSUBuv4i32,
3359 : VQSUBuv8i16,
3360 : VQSUBuv8i8,
3361 : VRADDHNv2i32,
3362 : VRADDHNv4i16,
3363 : VRADDHNv8i8,
3364 : VRECPEd,
3365 : VRECPEfd,
3366 : VRECPEfq,
3367 : VRECPEhd,
3368 : VRECPEhq,
3369 : VRECPEq,
3370 : VRECPSfd,
3371 : VRECPSfq,
3372 : VRECPShd,
3373 : VRECPShq,
3374 : VREV16d8,
3375 : VREV16q8,
3376 : VREV32d16,
3377 : VREV32d8,
3378 : VREV32q16,
3379 : VREV32q8,
3380 : VREV64d16,
3381 : VREV64d32,
3382 : VREV64d8,
3383 : VREV64q16,
3384 : VREV64q32,
3385 : VREV64q8,
3386 : VRHADDsv16i8,
3387 : VRHADDsv2i32,
3388 : VRHADDsv4i16,
3389 : VRHADDsv4i32,
3390 : VRHADDsv8i16,
3391 : VRHADDsv8i8,
3392 : VRHADDuv16i8,
3393 : VRHADDuv2i32,
3394 : VRHADDuv4i16,
3395 : VRHADDuv4i32,
3396 : VRHADDuv8i16,
3397 : VRHADDuv8i8,
3398 : VRINTAD,
3399 : VRINTAH,
3400 : VRINTANDf,
3401 : VRINTANDh,
3402 : VRINTANQf,
3403 : VRINTANQh,
3404 : VRINTAS,
3405 : VRINTMD,
3406 : VRINTMH,
3407 : VRINTMNDf,
3408 : VRINTMNDh,
3409 : VRINTMNQf,
3410 : VRINTMNQh,
3411 : VRINTMS,
3412 : VRINTND,
3413 : VRINTNH,
3414 : VRINTNNDf,
3415 : VRINTNNDh,
3416 : VRINTNNQf,
3417 : VRINTNNQh,
3418 : VRINTNS,
3419 : VRINTPD,
3420 : VRINTPH,
3421 : VRINTPNDf,
3422 : VRINTPNDh,
3423 : VRINTPNQf,
3424 : VRINTPNQh,
3425 : VRINTPS,
3426 : VRINTRD,
3427 : VRINTRH,
3428 : VRINTRS,
3429 : VRINTXD,
3430 : VRINTXH,
3431 : VRINTXNDf,
3432 : VRINTXNDh,
3433 : VRINTXNQf,
3434 : VRINTXNQh,
3435 : VRINTXS,
3436 : VRINTZD,
3437 : VRINTZH,
3438 : VRINTZNDf,
3439 : VRINTZNDh,
3440 : VRINTZNQf,
3441 : VRINTZNQh,
3442 : VRINTZS,
3443 : VRSHLsv16i8,
3444 : VRSHLsv1i64,
3445 : VRSHLsv2i32,
3446 : VRSHLsv2i64,
3447 : VRSHLsv4i16,
3448 : VRSHLsv4i32,
3449 : VRSHLsv8i16,
3450 : VRSHLsv8i8,
3451 : VRSHLuv16i8,
3452 : VRSHLuv1i64,
3453 : VRSHLuv2i32,
3454 : VRSHLuv2i64,
3455 : VRSHLuv4i16,
3456 : VRSHLuv4i32,
3457 : VRSHLuv8i16,
3458 : VRSHLuv8i8,
3459 : VRSHRNv2i32,
3460 : VRSHRNv4i16,
3461 : VRSHRNv8i8,
3462 : VRSHRsv16i8,
3463 : VRSHRsv1i64,
3464 : VRSHRsv2i32,
3465 : VRSHRsv2i64,
3466 : VRSHRsv4i16,
3467 : VRSHRsv4i32,
3468 : VRSHRsv8i16,
3469 : VRSHRsv8i8,
3470 : VRSHRuv16i8,
3471 : VRSHRuv1i64,
3472 : VRSHRuv2i32,
3473 : VRSHRuv2i64,
3474 : VRSHRuv4i16,
3475 : VRSHRuv4i32,
3476 : VRSHRuv8i16,
3477 : VRSHRuv8i8,
3478 : VRSQRTEd,
3479 : VRSQRTEfd,
3480 : VRSQRTEfq,
3481 : VRSQRTEhd,
3482 : VRSQRTEhq,
3483 : VRSQRTEq,
3484 : VRSQRTSfd,
3485 : VRSQRTSfq,
3486 : VRSQRTShd,
3487 : VRSQRTShq,
3488 : VRSRAsv16i8,
3489 : VRSRAsv1i64,
3490 : VRSRAsv2i32,
3491 : VRSRAsv2i64,
3492 : VRSRAsv4i16,
3493 : VRSRAsv4i32,
3494 : VRSRAsv8i16,
3495 : VRSRAsv8i8,
3496 : VRSRAuv16i8,
3497 : VRSRAuv1i64,
3498 : VRSRAuv2i32,
3499 : VRSRAuv2i64,
3500 : VRSRAuv4i16,
3501 : VRSRAuv4i32,
3502 : VRSRAuv8i16,
3503 : VRSRAuv8i8,
3504 : VRSUBHNv2i32,
3505 : VRSUBHNv4i16,
3506 : VRSUBHNv8i8,
3507 : VSCCLRMD,
3508 : VSCCLRMS,
3509 : VSDOTD,
3510 : VSDOTDI,
3511 : VSDOTQ,
3512 : VSDOTQI,
3513 : VSELEQD,
3514 : VSELEQH,
3515 : VSELEQS,
3516 : VSELGED,
3517 : VSELGEH,
3518 : VSELGES,
3519 : VSELGTD,
3520 : VSELGTH,
3521 : VSELGTS,
3522 : VSELVSD,
3523 : VSELVSH,
3524 : VSELVSS,
3525 : VSETLNi16,
3526 : VSETLNi32,
3527 : VSETLNi8,
3528 : VSHLLi16,
3529 : VSHLLi32,
3530 : VSHLLi8,
3531 : VSHLLsv2i64,
3532 : VSHLLsv4i32,
3533 : VSHLLsv8i16,
3534 : VSHLLuv2i64,
3535 : VSHLLuv4i32,
3536 : VSHLLuv8i16,
3537 : VSHLiv16i8,
3538 : VSHLiv1i64,
3539 : VSHLiv2i32,
3540 : VSHLiv2i64,
3541 : VSHLiv4i16,
3542 : VSHLiv4i32,
3543 : VSHLiv8i16,
3544 : VSHLiv8i8,
3545 : VSHLsv16i8,
3546 : VSHLsv1i64,
3547 : VSHLsv2i32,
3548 : VSHLsv2i64,
3549 : VSHLsv4i16,
3550 : VSHLsv4i32,
3551 : VSHLsv8i16,
3552 : VSHLsv8i8,
3553 : VSHLuv16i8,
3554 : VSHLuv1i64,
3555 : VSHLuv2i32,
3556 : VSHLuv2i64,
3557 : VSHLuv4i16,
3558 : VSHLuv4i32,
3559 : VSHLuv8i16,
3560 : VSHLuv8i8,
3561 : VSHRNv2i32,
3562 : VSHRNv4i16,
3563 : VSHRNv8i8,
3564 : VSHRsv16i8,
3565 : VSHRsv1i64,
3566 : VSHRsv2i32,
3567 : VSHRsv2i64,
3568 : VSHRsv4i16,
3569 : VSHRsv4i32,
3570 : VSHRsv8i16,
3571 : VSHRsv8i8,
3572 : VSHRuv16i8,
3573 : VSHRuv1i64,
3574 : VSHRuv2i32,
3575 : VSHRuv2i64,
3576 : VSHRuv4i16,
3577 : VSHRuv4i32,
3578 : VSHRuv8i16,
3579 : VSHRuv8i8,
3580 : VSHTOD,
3581 : VSHTOH,
3582 : VSHTOS,
3583 : VSITOD,
3584 : VSITOH,
3585 : VSITOS,
3586 : VSLIv16i8,
3587 : VSLIv1i64,
3588 : VSLIv2i32,
3589 : VSLIv2i64,
3590 : VSLIv4i16,
3591 : VSLIv4i32,
3592 : VSLIv8i16,
3593 : VSLIv8i8,
3594 : VSLTOD,
3595 : VSLTOH,
3596 : VSLTOS,
3597 : VSMMLA,
3598 : VSQRTD,
3599 : VSQRTH,
3600 : VSQRTS,
3601 : VSRAsv16i8,
3602 : VSRAsv1i64,
3603 : VSRAsv2i32,
3604 : VSRAsv2i64,
3605 : VSRAsv4i16,
3606 : VSRAsv4i32,
3607 : VSRAsv8i16,
3608 : VSRAsv8i8,
3609 : VSRAuv16i8,
3610 : VSRAuv1i64,
3611 : VSRAuv2i32,
3612 : VSRAuv2i64,
3613 : VSRAuv4i16,
3614 : VSRAuv4i32,
3615 : VSRAuv8i16,
3616 : VSRAuv8i8,
3617 : VSRIv16i8,
3618 : VSRIv1i64,
3619 : VSRIv2i32,
3620 : VSRIv2i64,
3621 : VSRIv4i16,
3622 : VSRIv4i32,
3623 : VSRIv8i16,
3624 : VSRIv8i8,
3625 : VST1LNd16,
3626 : VST1LNd16_UPD,
3627 : VST1LNd32,
3628 : VST1LNd32_UPD,
3629 : VST1LNd8,
3630 : VST1LNd8_UPD,
3631 : VST1LNq16Pseudo,
3632 : VST1LNq16Pseudo_UPD,
3633 : VST1LNq32Pseudo,
3634 : VST1LNq32Pseudo_UPD,
3635 : VST1LNq8Pseudo,
3636 : VST1LNq8Pseudo_UPD,
3637 : VST1d16,
3638 : VST1d16Q,
3639 : VST1d16QPseudo,
3640 : VST1d16QPseudoWB_fixed,
3641 : VST1d16QPseudoWB_register,
3642 : VST1d16Qwb_fixed,
3643 : VST1d16Qwb_register,
3644 : VST1d16T,
3645 : VST1d16TPseudo,
3646 : VST1d16TPseudoWB_fixed,
3647 : VST1d16TPseudoWB_register,
3648 : VST1d16Twb_fixed,
3649 : VST1d16Twb_register,
3650 : VST1d16wb_fixed,
3651 : VST1d16wb_register,
3652 : VST1d32,
3653 : VST1d32Q,
3654 : VST1d32QPseudo,
3655 : VST1d32QPseudoWB_fixed,
3656 : VST1d32QPseudoWB_register,
3657 : VST1d32Qwb_fixed,
3658 : VST1d32Qwb_register,
3659 : VST1d32T,
3660 : VST1d32TPseudo,
3661 : VST1d32TPseudoWB_fixed,
3662 : VST1d32TPseudoWB_register,
3663 : VST1d32Twb_fixed,
3664 : VST1d32Twb_register,
3665 : VST1d32wb_fixed,
3666 : VST1d32wb_register,
3667 : VST1d64,
3668 : VST1d64Q,
3669 : VST1d64QPseudo,
3670 : VST1d64QPseudoWB_fixed,
3671 : VST1d64QPseudoWB_register,
3672 : VST1d64Qwb_fixed,
3673 : VST1d64Qwb_register,
3674 : VST1d64T,
3675 : VST1d64TPseudo,
3676 : VST1d64TPseudoWB_fixed,
3677 : VST1d64TPseudoWB_register,
3678 : VST1d64Twb_fixed,
3679 : VST1d64Twb_register,
3680 : VST1d64wb_fixed,
3681 : VST1d64wb_register,
3682 : VST1d8,
3683 : VST1d8Q,
3684 : VST1d8QPseudo,
3685 : VST1d8QPseudoWB_fixed,
3686 : VST1d8QPseudoWB_register,
3687 : VST1d8Qwb_fixed,
3688 : VST1d8Qwb_register,
3689 : VST1d8T,
3690 : VST1d8TPseudo,
3691 : VST1d8TPseudoWB_fixed,
3692 : VST1d8TPseudoWB_register,
3693 : VST1d8Twb_fixed,
3694 : VST1d8Twb_register,
3695 : VST1d8wb_fixed,
3696 : VST1d8wb_register,
3697 : VST1q16,
3698 : VST1q16HighQPseudo,
3699 : VST1q16HighQPseudo_UPD,
3700 : VST1q16HighTPseudo,
3701 : VST1q16HighTPseudo_UPD,
3702 : VST1q16LowQPseudo_UPD,
3703 : VST1q16LowTPseudo_UPD,
3704 : VST1q16wb_fixed,
3705 : VST1q16wb_register,
3706 : VST1q32,
3707 : VST1q32HighQPseudo,
3708 : VST1q32HighQPseudo_UPD,
3709 : VST1q32HighTPseudo,
3710 : VST1q32HighTPseudo_UPD,
3711 : VST1q32LowQPseudo_UPD,
3712 : VST1q32LowTPseudo_UPD,
3713 : VST1q32wb_fixed,
3714 : VST1q32wb_register,
3715 : VST1q64,
3716 : VST1q64HighQPseudo,
3717 : VST1q64HighQPseudo_UPD,
3718 : VST1q64HighTPseudo,
3719 : VST1q64HighTPseudo_UPD,
3720 : VST1q64LowQPseudo_UPD,
3721 : VST1q64LowTPseudo_UPD,
3722 : VST1q64wb_fixed,
3723 : VST1q64wb_register,
3724 : VST1q8,
3725 : VST1q8HighQPseudo,
3726 : VST1q8HighQPseudo_UPD,
3727 : VST1q8HighTPseudo,
3728 : VST1q8HighTPseudo_UPD,
3729 : VST1q8LowQPseudo_UPD,
3730 : VST1q8LowTPseudo_UPD,
3731 : VST1q8wb_fixed,
3732 : VST1q8wb_register,
3733 : VST2LNd16,
3734 : VST2LNd16Pseudo,
3735 : VST2LNd16Pseudo_UPD,
3736 : VST2LNd16_UPD,
3737 : VST2LNd32,
3738 : VST2LNd32Pseudo,
3739 : VST2LNd32Pseudo_UPD,
3740 : VST2LNd32_UPD,
3741 : VST2LNd8,
3742 : VST2LNd8Pseudo,
3743 : VST2LNd8Pseudo_UPD,
3744 : VST2LNd8_UPD,
3745 : VST2LNq16,
3746 : VST2LNq16Pseudo,
3747 : VST2LNq16Pseudo_UPD,
3748 : VST2LNq16_UPD,
3749 : VST2LNq32,
3750 : VST2LNq32Pseudo,
3751 : VST2LNq32Pseudo_UPD,
3752 : VST2LNq32_UPD,
3753 : VST2b16,
3754 : VST2b16wb_fixed,
3755 : VST2b16wb_register,
3756 : VST2b32,
3757 : VST2b32wb_fixed,
3758 : VST2b32wb_register,
3759 : VST2b8,
3760 : VST2b8wb_fixed,
3761 : VST2b8wb_register,
3762 : VST2d16,
3763 : VST2d16wb_fixed,
3764 : VST2d16wb_register,
3765 : VST2d32,
3766 : VST2d32wb_fixed,
3767 : VST2d32wb_register,
3768 : VST2d8,
3769 : VST2d8wb_fixed,
3770 : VST2d8wb_register,
3771 : VST2q16,
3772 : VST2q16Pseudo,
3773 : VST2q16PseudoWB_fixed,
3774 : VST2q16PseudoWB_register,
3775 : VST2q16wb_fixed,
3776 : VST2q16wb_register,
3777 : VST2q32,
3778 : VST2q32Pseudo,
3779 : VST2q32PseudoWB_fixed,
3780 : VST2q32PseudoWB_register,
3781 : VST2q32wb_fixed,
3782 : VST2q32wb_register,
3783 : VST2q8,
3784 : VST2q8Pseudo,
3785 : VST2q8PseudoWB_fixed,
3786 : VST2q8PseudoWB_register,
3787 : VST2q8wb_fixed,
3788 : VST2q8wb_register,
3789 : VST3LNd16,
3790 : VST3LNd16Pseudo,
3791 : VST3LNd16Pseudo_UPD,
3792 : VST3LNd16_UPD,
3793 : VST3LNd32,
3794 : VST3LNd32Pseudo,
3795 : VST3LNd32Pseudo_UPD,
3796 : VST3LNd32_UPD,
3797 : VST3LNd8,
3798 : VST3LNd8Pseudo,
3799 : VST3LNd8Pseudo_UPD,
3800 : VST3LNd8_UPD,
3801 : VST3LNq16,
3802 : VST3LNq16Pseudo,
3803 : VST3LNq16Pseudo_UPD,
3804 : VST3LNq16_UPD,
3805 : VST3LNq32,
3806 : VST3LNq32Pseudo,
3807 : VST3LNq32Pseudo_UPD,
3808 : VST3LNq32_UPD,
3809 : VST3d16,
3810 : VST3d16Pseudo,
3811 : VST3d16Pseudo_UPD,
3812 : VST3d16_UPD,
3813 : VST3d32,
3814 : VST3d32Pseudo,
3815 : VST3d32Pseudo_UPD,
3816 : VST3d32_UPD,
3817 : VST3d8,
3818 : VST3d8Pseudo,
3819 : VST3d8Pseudo_UPD,
3820 : VST3d8_UPD,
3821 : VST3q16,
3822 : VST3q16Pseudo_UPD,
3823 : VST3q16_UPD,
3824 : VST3q16oddPseudo,
3825 : VST3q16oddPseudo_UPD,
3826 : VST3q32,
3827 : VST3q32Pseudo_UPD,
3828 : VST3q32_UPD,
3829 : VST3q32oddPseudo,
3830 : VST3q32oddPseudo_UPD,
3831 : VST3q8,
3832 : VST3q8Pseudo_UPD,
3833 : VST3q8_UPD,
3834 : VST3q8oddPseudo,
3835 : VST3q8oddPseudo_UPD,
3836 : VST4LNd16,
3837 : VST4LNd16Pseudo,
3838 : VST4LNd16Pseudo_UPD,
3839 : VST4LNd16_UPD,
3840 : VST4LNd32,
3841 : VST4LNd32Pseudo,
3842 : VST4LNd32Pseudo_UPD,
3843 : VST4LNd32_UPD,
3844 : VST4LNd8,
3845 : VST4LNd8Pseudo,
3846 : VST4LNd8Pseudo_UPD,
3847 : VST4LNd8_UPD,
3848 : VST4LNq16,
3849 : VST4LNq16Pseudo,
3850 : VST4LNq16Pseudo_UPD,
3851 : VST4LNq16_UPD,
3852 : VST4LNq32,
3853 : VST4LNq32Pseudo,
3854 : VST4LNq32Pseudo_UPD,
3855 : VST4LNq32_UPD,
3856 : VST4d16,
3857 : VST4d16Pseudo,
3858 : VST4d16Pseudo_UPD,
3859 : VST4d16_UPD,
3860 : VST4d32,
3861 : VST4d32Pseudo,
3862 : VST4d32Pseudo_UPD,
3863 : VST4d32_UPD,
3864 : VST4d8,
3865 : VST4d8Pseudo,
3866 : VST4d8Pseudo_UPD,
3867 : VST4d8_UPD,
3868 : VST4q16,
3869 : VST4q16Pseudo_UPD,
3870 : VST4q16_UPD,
3871 : VST4q16oddPseudo,
3872 : VST4q16oddPseudo_UPD,
3873 : VST4q32,
3874 : VST4q32Pseudo_UPD,
3875 : VST4q32_UPD,
3876 : VST4q32oddPseudo,
3877 : VST4q32oddPseudo_UPD,
3878 : VST4q8,
3879 : VST4q8Pseudo_UPD,
3880 : VST4q8_UPD,
3881 : VST4q8oddPseudo,
3882 : VST4q8oddPseudo_UPD,
3883 : VSTMDDB_UPD,
3884 : VSTMDIA,
3885 : VSTMDIA_UPD,
3886 : VSTMQIA,
3887 : VSTMSDB_UPD,
3888 : VSTMSIA,
3889 : VSTMSIA_UPD,
3890 : VSTRD,
3891 : VSTRH,
3892 : VSTRS,
3893 : VSTR_FPCXTNS_off,
3894 : VSTR_FPCXTNS_post,
3895 : VSTR_FPCXTNS_pre,
3896 : VSTR_FPCXTS_off,
3897 : VSTR_FPCXTS_post,
3898 : VSTR_FPCXTS_pre,
3899 : VSTR_FPSCR_NZCVQC_off,
3900 : VSTR_FPSCR_NZCVQC_post,
3901 : VSTR_FPSCR_NZCVQC_pre,
3902 : VSTR_FPSCR_off,
3903 : VSTR_FPSCR_post,
3904 : VSTR_FPSCR_pre,
3905 : VSTR_P0_off,
3906 : VSTR_P0_post,
3907 : VSTR_P0_pre,
3908 : VSTR_VPR_off,
3909 : VSTR_VPR_post,
3910 : VSTR_VPR_pre,
3911 : VSUBD,
3912 : VSUBH,
3913 : VSUBHNv2i32,
3914 : VSUBHNv4i16,
3915 : VSUBHNv8i8,
3916 : VSUBLsv2i64,
3917 : VSUBLsv4i32,
3918 : VSUBLsv8i16,
3919 : VSUBLuv2i64,
3920 : VSUBLuv4i32,
3921 : VSUBLuv8i16,
3922 : VSUBS,
3923 : VSUBWsv2i64,
3924 : VSUBWsv4i32,
3925 : VSUBWsv8i16,
3926 : VSUBWuv2i64,
3927 : VSUBWuv4i32,
3928 : VSUBWuv8i16,
3929 : VSUBfd,
3930 : VSUBfq,
3931 : VSUBhd,
3932 : VSUBhq,
3933 : VSUBv16i8,
3934 : VSUBv1i64,
3935 : VSUBv2i32,
3936 : VSUBv2i64,
3937 : VSUBv4i16,
3938 : VSUBv4i32,
3939 : VSUBv8i16,
3940 : VSUBv8i8,
3941 : VSUDOTDI,
3942 : VSUDOTQI,
3943 : VSWPd,
3944 : VSWPq,
3945 : VTBL1,
3946 : VTBL2,
3947 : VTBL3,
3948 : VTBL3Pseudo,
3949 : VTBL4,
3950 : VTBL4Pseudo,
3951 : VTBX1,
3952 : VTBX2,
3953 : VTBX3,
3954 : VTBX3Pseudo,
3955 : VTBX4,
3956 : VTBX4Pseudo,
3957 : VTOSHD,
3958 : VTOSHH,
3959 : VTOSHS,
3960 : VTOSIRD,
3961 : VTOSIRH,
3962 : VTOSIRS,
3963 : VTOSIZD,
3964 : VTOSIZH,
3965 : VTOSIZS,
3966 : VTOSLD,
3967 : VTOSLH,
3968 : VTOSLS,
3969 : VTOUHD,
3970 : VTOUHH,
3971 : VTOUHS,
3972 : VTOUIRD,
3973 : VTOUIRH,
3974 : VTOUIRS,
3975 : VTOUIZD,
3976 : VTOUIZH,
3977 : VTOUIZS,
3978 : VTOULD,
3979 : VTOULH,
3980 : VTOULS,
3981 : VTRNd16,
3982 : VTRNd32,
3983 : VTRNd8,
3984 : VTRNq16,
3985 : VTRNq32,
3986 : VTRNq8,
3987 : VTSTv16i8,
3988 : VTSTv2i32,
3989 : VTSTv4i16,
3990 : VTSTv4i32,
3991 : VTSTv8i16,
3992 : VTSTv8i8,
3993 : VUDOTD,
3994 : VUDOTDI,
3995 : VUDOTQ,
3996 : VUDOTQI,
3997 : VUHTOD,
3998 : VUHTOH,
3999 : VUHTOS,
4000 : VUITOD,
4001 : VUITOH,
4002 : VUITOS,
4003 : VULTOD,
4004 : VULTOH,
4005 : VULTOS,
4006 : VUMMLA,
4007 : VUSDOTD,
4008 : VUSDOTDI,
4009 : VUSDOTQ,
4010 : VUSDOTQI,
4011 : VUSMMLA,
4012 : VUZPd16,
4013 : VUZPd8,
4014 : VUZPq16,
4015 : VUZPq32,
4016 : VUZPq8,
4017 : VZIPd16,
4018 : VZIPd8,
4019 : VZIPq16,
4020 : VZIPq32,
4021 : VZIPq8,
4022 : sysLDMDA,
4023 : sysLDMDA_UPD,
4024 : sysLDMDB,
4025 : sysLDMDB_UPD,
4026 : sysLDMIA,
4027 : sysLDMIA_UPD,
4028 : sysLDMIB,
4029 : sysLDMIB_UPD,
4030 : sysSTMDA,
4031 : sysSTMDA_UPD,
4032 : sysSTMDB,
4033 : sysSTMDB_UPD,
4034 : sysSTMIA,
4035 : sysSTMIA_UPD,
4036 : sysSTMIB,
4037 : sysSTMIB_UPD,
4038 : t2ADCri,
4039 : t2ADCrr,
4040 : t2ADCrs,
4041 : t2ADDri,
4042 : t2ADDri12,
4043 : t2ADDrr,
4044 : t2ADDrs,
4045 : t2ADDspImm,
4046 : t2ADDspImm12,
4047 : t2ADR,
4048 : t2ANDri,
4049 : t2ANDrr,
4050 : t2ANDrs,
4051 : t2ASRri,
4052 : t2ASRrr,
4053 : t2ASRs1,
4054 : t2AUT,
4055 : t2AUTG,
4056 : t2B,
4057 : t2BFC,
4058 : t2BFI,
4059 : t2BFLi,
4060 : t2BFLr,
4061 : t2BFi,
4062 : t2BFic,
4063 : t2BFr,
4064 : t2BICri,
4065 : t2BICrr,
4066 : t2BICrs,
4067 : t2BTI,
4068 : t2BXAUT,
4069 : t2BXJ,
4070 : t2Bcc,
4071 : t2CDP,
4072 : t2CDP2,
4073 : t2CLREX,
4074 : t2CLRM,
4075 : t2CLZ,
4076 : t2CMNri,
4077 : t2CMNzrr,
4078 : t2CMNzrs,
4079 : t2CMPri,
4080 : t2CMPrr,
4081 : t2CMPrs,
4082 : t2CPS1p,
4083 : t2CPS2p,
4084 : t2CPS3p,
4085 : t2CRC32B,
4086 : t2CRC32CB,
4087 : t2CRC32CH,
4088 : t2CRC32CW,
4089 : t2CRC32H,
4090 : t2CRC32W,
4091 : t2CSEL,
4092 : t2CSINC,
4093 : t2CSINV,
4094 : t2CSNEG,
4095 : t2DBG,
4096 : t2DCPS1,
4097 : t2DCPS2,
4098 : t2DCPS3,
4099 : t2DLS,
4100 : t2DMB,
4101 : t2DSB,
4102 : t2EORri,
4103 : t2EORrr,
4104 : t2EORrs,
4105 : t2HINT,
4106 : t2HVC,
4107 : t2ISB,
4108 : t2IT,
4109 : t2Int_eh_sjlj_setjmp,
4110 : t2Int_eh_sjlj_setjmp_nofp,
4111 : t2LDA,
4112 : t2LDAB,
4113 : t2LDAEX,
4114 : t2LDAEXB,
4115 : t2LDAEXD,
4116 : t2LDAEXH,
4117 : t2LDAH,
4118 : t2LDC2L_OFFSET,
4119 : t2LDC2L_OPTION,
4120 : t2LDC2L_POST,
4121 : t2LDC2L_PRE,
4122 : t2LDC2_OFFSET,
4123 : t2LDC2_OPTION,
4124 : t2LDC2_POST,
4125 : t2LDC2_PRE,
4126 : t2LDCL_OFFSET,
4127 : t2LDCL_OPTION,
4128 : t2LDCL_POST,
4129 : t2LDCL_PRE,
4130 : t2LDC_OFFSET,
4131 : t2LDC_OPTION,
4132 : t2LDC_POST,
4133 : t2LDC_PRE,
4134 : t2LDMDB,
4135 : t2LDMDB_UPD,
4136 : t2LDMIA,
4137 : t2LDMIA_UPD,
4138 : t2LDRBT,
4139 : t2LDRB_POST,
4140 : t2LDRB_PRE,
4141 : t2LDRBi12,
4142 : t2LDRBi8,
4143 : t2LDRBpci,
4144 : t2LDRBs,
4145 : t2LDRD_POST,
4146 : t2LDRD_PRE,
4147 : t2LDRDi8,
4148 : t2LDREX,
4149 : t2LDREXB,
4150 : t2LDREXD,
4151 : t2LDREXH,
4152 : t2LDRHT,
4153 : t2LDRH_POST,
4154 : t2LDRH_PRE,
4155 : t2LDRHi12,
4156 : t2LDRHi8,
4157 : t2LDRHpci,
4158 : t2LDRHs,
4159 : t2LDRSBT,
4160 : t2LDRSB_POST,
4161 : t2LDRSB_PRE,
4162 : t2LDRSBi12,
4163 : t2LDRSBi8,
4164 : t2LDRSBpci,
4165 : t2LDRSBs,
4166 : t2LDRSHT,
4167 : t2LDRSH_POST,
4168 : t2LDRSH_PRE,
4169 : t2LDRSHi12,
4170 : t2LDRSHi8,
4171 : t2LDRSHpci,
4172 : t2LDRSHs,
4173 : t2LDRT,
4174 : t2LDR_POST,
4175 : t2LDR_PRE,
4176 : t2LDRi12,
4177 : t2LDRi8,
4178 : t2LDRpci,
4179 : t2LDRs,
4180 : t2LE,
4181 : t2LEUpdate,
4182 : t2LSLri,
4183 : t2LSLrr,
4184 : t2LSRri,
4185 : t2LSRrr,
4186 : t2LSRs1,
4187 : t2MCR,
4188 : t2MCR2,
4189 : t2MCRR,
4190 : t2MCRR2,
4191 : t2MLA,
4192 : t2MLS,
4193 : t2MOVTi16,
4194 : t2MOVi,
4195 : t2MOVi16,
4196 : t2MOVr,
4197 : t2MRC,
4198 : t2MRC2,
4199 : t2MRRC,
4200 : t2MRRC2,
4201 : t2MRS_AR,
4202 : t2MRS_M,
4203 : t2MRSbanked,
4204 : t2MRSsys_AR,
4205 : t2MSR_AR,
4206 : t2MSR_M,
4207 : t2MSRbanked,
4208 : t2MUL,
4209 : t2MVNi,
4210 : t2MVNr,
4211 : t2MVNs,
4212 : t2ORNri,
4213 : t2ORNrr,
4214 : t2ORNrs,
4215 : t2ORRri,
4216 : t2ORRrr,
4217 : t2ORRrs,
4218 : t2PAC,
4219 : t2PACBTI,
4220 : t2PACG,
4221 : t2PKHBT,
4222 : t2PKHTB,
4223 : t2PLDWi12,
4224 : t2PLDWi8,
4225 : t2PLDWs,
4226 : t2PLDi12,
4227 : t2PLDi8,
4228 : t2PLDpci,
4229 : t2PLDs,
4230 : t2PLIi12,
4231 : t2PLIi8,
4232 : t2PLIpci,
4233 : t2PLIs,
4234 : t2QADD,
4235 : t2QADD16,
4236 : t2QADD8,
4237 : t2QASX,
4238 : t2QDADD,
4239 : t2QDSUB,
4240 : t2QSAX,
4241 : t2QSUB,
4242 : t2QSUB16,
4243 : t2QSUB8,
4244 : t2RBIT,
4245 : t2REV,
4246 : t2REV16,
4247 : t2REVSH,
4248 : t2RFEDB,
4249 : t2RFEDBW,
4250 : t2RFEIA,
4251 : t2RFEIAW,
4252 : t2RORri,
4253 : t2RORrr,
4254 : t2RRX,
4255 : t2RSBri,
4256 : t2RSBrr,
4257 : t2RSBrs,
4258 : t2SADD16,
4259 : t2SADD8,
4260 : t2SASX,
4261 : t2SB,
4262 : t2SBCri,
4263 : t2SBCrr,
4264 : t2SBCrs,
4265 : t2SBFX,
4266 : t2SDIV,
4267 : t2SEL,
4268 : t2SETPAN,
4269 : t2SG,
4270 : t2SHADD16,
4271 : t2SHADD8,
4272 : t2SHASX,
4273 : t2SHSAX,
4274 : t2SHSUB16,
4275 : t2SHSUB8,
4276 : t2SMC,
4277 : t2SMLABB,
4278 : t2SMLABT,
4279 : t2SMLAD,
4280 : t2SMLADX,
4281 : t2SMLAL,
4282 : t2SMLALBB,
4283 : t2SMLALBT,
4284 : t2SMLALD,
4285 : t2SMLALDX,
4286 : t2SMLALTB,
4287 : t2SMLALTT,
4288 : t2SMLATB,
4289 : t2SMLATT,
4290 : t2SMLAWB,
4291 : t2SMLAWT,
4292 : t2SMLSD,
4293 : t2SMLSDX,
4294 : t2SMLSLD,
4295 : t2SMLSLDX,
4296 : t2SMMLA,
4297 : t2SMMLAR,
4298 : t2SMMLS,
4299 : t2SMMLSR,
4300 : t2SMMUL,
4301 : t2SMMULR,
4302 : t2SMUAD,
4303 : t2SMUADX,
4304 : t2SMULBB,
4305 : t2SMULBT,
4306 : t2SMULL,
4307 : t2SMULTB,
4308 : t2SMULTT,
4309 : t2SMULWB,
4310 : t2SMULWT,
4311 : t2SMUSD,
4312 : t2SMUSDX,
4313 : t2SRSDB,
4314 : t2SRSDB_UPD,
4315 : t2SRSIA,
4316 : t2SRSIA_UPD,
4317 : t2SSAT,
4318 : t2SSAT16,
4319 : t2SSAX,
4320 : t2SSUB16,
4321 : t2SSUB8,
4322 : t2STC2L_OFFSET,
4323 : t2STC2L_OPTION,
4324 : t2STC2L_POST,
4325 : t2STC2L_PRE,
4326 : t2STC2_OFFSET,
4327 : t2STC2_OPTION,
4328 : t2STC2_POST,
4329 : t2STC2_PRE,
4330 : t2STCL_OFFSET,
4331 : t2STCL_OPTION,
4332 : t2STCL_POST,
4333 : t2STCL_PRE,
4334 : t2STC_OFFSET,
4335 : t2STC_OPTION,
4336 : t2STC_POST,
4337 : t2STC_PRE,
4338 : t2STL,
4339 : t2STLB,
4340 : t2STLEX,
4341 : t2STLEXB,
4342 : t2STLEXD,
4343 : t2STLEXH,
4344 : t2STLH,
4345 : t2STMDB,
4346 : t2STMDB_UPD,
4347 : t2STMIA,
4348 : t2STMIA_UPD,
4349 : t2STRBT,
4350 : t2STRB_POST,
4351 : t2STRB_PRE,
4352 : t2STRBi12,
4353 : t2STRBi8,
4354 : t2STRBs,
4355 : t2STRD_POST,
4356 : t2STRD_PRE,
4357 : t2STRDi8,
4358 : t2STREX,
4359 : t2STREXB,
4360 : t2STREXD,
4361 : t2STREXH,
4362 : t2STRHT,
4363 : t2STRH_POST,
4364 : t2STRH_PRE,
4365 : t2STRHi12,
4366 : t2STRHi8,
4367 : t2STRHs,
4368 : t2STRT,
4369 : t2STR_POST,
4370 : t2STR_PRE,
4371 : t2STRi12,
4372 : t2STRi8,
4373 : t2STRs,
4374 : t2SUBS_PC_LR,
4375 : t2SUBri,
4376 : t2SUBri12,
4377 : t2SUBrr,
4378 : t2SUBrs,
4379 : t2SUBspImm,
4380 : t2SUBspImm12,
4381 : t2SXTAB,
4382 : t2SXTAB16,
4383 : t2SXTAH,
4384 : t2SXTB,
4385 : t2SXTB16,
4386 : t2SXTH,
4387 : t2TBB,
4388 : t2TBH,
4389 : t2TEQri,
4390 : t2TEQrr,
4391 : t2TEQrs,
4392 : t2TSB,
4393 : t2TSTri,
4394 : t2TSTrr,
4395 : t2TSTrs,
4396 : t2TT,
4397 : t2TTA,
4398 : t2TTAT,
4399 : t2TTT,
4400 : t2UADD16,
4401 : t2UADD8,
4402 : t2UASX,
4403 : t2UBFX,
4404 : t2UDF,
4405 : t2UDIV,
4406 : t2UHADD16,
4407 : t2UHADD8,
4408 : t2UHASX,
4409 : t2UHSAX,
4410 : t2UHSUB16,
4411 : t2UHSUB8,
4412 : t2UMAAL,
4413 : t2UMLAL,
4414 : t2UMULL,
4415 : t2UQADD16,
4416 : t2UQADD8,
4417 : t2UQASX,
4418 : t2UQSAX,
4419 : t2UQSUB16,
4420 : t2UQSUB8,
4421 : t2USAD8,
4422 : t2USADA8,
4423 : t2USAT,
4424 : t2USAT16,
4425 : t2USAX,
4426 : t2USUB16,
4427 : t2USUB8,
4428 : t2UXTAB,
4429 : t2UXTAB16,
4430 : t2UXTAH,
4431 : t2UXTB,
4432 : t2UXTB16,
4433 : t2UXTH,
4434 : t2WLS,
4435 : tADC,
4436 : tADDhirr,
4437 : tADDi3,
4438 : tADDi8,
4439 : tADDrSP,
4440 : tADDrSPi,
4441 : tADDrr,
4442 : tADDspi,
4443 : tADDspr,
4444 : tADR,
4445 : tAND,
4446 : tASRri,
4447 : tASRrr,
4448 : tB,
4449 : tBIC,
4450 : tBKPT,
4451 : tBL,
4452 : tBLXNSr,
4453 : tBLXi,
4454 : tBLXr,
4455 : tBX,
4456 : tBXNS,
4457 : tBcc,
4458 : tCBNZ,
4459 : tCBZ,
4460 : tCMNz,
4461 : tCMPhir,
4462 : tCMPi8,
4463 : tCMPr,
4464 : tCPS,
4465 : tEOR,
4466 : tHINT,
4467 : tHLT,
4468 : tInt_WIN_eh_sjlj_longjmp,
4469 : tInt_eh_sjlj_longjmp,
4470 : tInt_eh_sjlj_setjmp,
4471 : tLDMIA,
4472 : tLDRBi,
4473 : tLDRBr,
4474 : tLDRHi,
4475 : tLDRHr,
4476 : tLDRSB,
4477 : tLDRSH,
4478 : tLDRi,
4479 : tLDRpci,
4480 : tLDRr,
4481 : tLDRspi,
4482 : tLSLri,
4483 : tLSLrr,
4484 : tLSRri,
4485 : tLSRrr,
4486 : tMOVSr,
4487 : tMOVi8,
4488 : tMOVr,
4489 : tMUL,
4490 : tMVN,
4491 : tORR,
4492 : tPICADD,
4493 : tPOP,
4494 : tPUSH,
4495 : tREV,
4496 : tREV16,
4497 : tREVSH,
4498 : tROR,
4499 : tRSB,
4500 : tSBC,
4501 : tSETEND,
4502 : tSTMIA_UPD,
4503 : tSTRBi,
4504 : tSTRBr,
4505 : tSTRHi,
4506 : tSTRHr,
4507 : tSTRi,
4508 : tSTRr,
4509 : tSTRspi,
4510 : tSUBi3,
4511 : tSUBi8,
4512 : tSUBrr,
4513 : tSUBspi,
4514 : tSVC,
4515 : tSXTB,
4516 : tSXTH,
4517 : tTRAP,
4518 : tTST,
4519 : tUDF,
4520 : tUXTB,
4521 : tUXTH,
4522 : t__brkdiv0,
4523 : INSTRUCTION_LIST_END,
4524 : UNKNOWN(u64),
4525 : }
4526 :
4527 : impl From<u64> for Opcode {
4528 0 : fn from(value: u64) -> Self {
4529 0 : match value {
4530 0 : 0 => Opcode::PHI,
4531 0 : 1 => Opcode::INLINEASM,
4532 0 : 2 => Opcode::INLINEASM_BR,
4533 0 : 3 => Opcode::CFI_INSTRUCTION,
4534 0 : 4 => Opcode::EH_LABEL,
4535 0 : 5 => Opcode::GC_LABEL,
4536 0 : 6 => Opcode::ANNOTATION_LABEL,
4537 0 : 7 => Opcode::KILL,
4538 0 : 8 => Opcode::EXTRACT_SUBREG,
4539 0 : 9 => Opcode::INSERT_SUBREG,
4540 0 : 10 => Opcode::IMPLICIT_DEF,
4541 0 : 11 => Opcode::INIT_UNDEF,
4542 0 : 12 => Opcode::SUBREG_TO_REG,
4543 0 : 13 => Opcode::COPY_TO_REGCLASS,
4544 0 : 14 => Opcode::DBG_VALUE,
4545 0 : 15 => Opcode::DBG_VALUE_LIST,
4546 0 : 16 => Opcode::DBG_INSTR_REF,
4547 0 : 17 => Opcode::DBG_PHI,
4548 0 : 18 => Opcode::DBG_LABEL,
4549 0 : 19 => Opcode::REG_SEQUENCE,
4550 0 : 20 => Opcode::COPY,
4551 0 : 21 => Opcode::COPY_LANEMASK,
4552 0 : 22 => Opcode::BUNDLE,
4553 0 : 23 => Opcode::LIFETIME_START,
4554 0 : 24 => Opcode::LIFETIME_END,
4555 0 : 25 => Opcode::PSEUDO_PROBE,
4556 0 : 26 => Opcode::ARITH_FENCE,
4557 0 : 27 => Opcode::STACKMAP,
4558 0 : 28 => Opcode::FENTRY_CALL,
4559 0 : 29 => Opcode::PATCHPOINT,
4560 0 : 30 => Opcode::LOAD_STACK_GUARD,
4561 0 : 31 => Opcode::PREALLOCATED_SETUP,
4562 0 : 32 => Opcode::PREALLOCATED_ARG,
4563 0 : 33 => Opcode::STATEPOINT,
4564 0 : 34 => Opcode::LOCAL_ESCAPE,
4565 0 : 35 => Opcode::FAULTING_OP,
4566 0 : 36 => Opcode::PATCHABLE_OP,
4567 0 : 37 => Opcode::PATCHABLE_FUNCTION_ENTER,
4568 0 : 38 => Opcode::PATCHABLE_RET,
4569 0 : 39 => Opcode::PATCHABLE_FUNCTION_EXIT,
4570 0 : 40 => Opcode::PATCHABLE_TAIL_CALL,
4571 0 : 41 => Opcode::PATCHABLE_EVENT_CALL,
4572 0 : 42 => Opcode::PATCHABLE_TYPED_EVENT_CALL,
4573 0 : 43 => Opcode::ICALL_BRANCH_FUNNEL,
4574 0 : 44 => Opcode::FAKE_USE,
4575 0 : 45 => Opcode::MEMBARRIER,
4576 0 : 46 => Opcode::JUMP_TABLE_DEBUG_INFO,
4577 0 : 47 => Opcode::RELOC_NONE,
4578 0 : 48 => Opcode::CONVERGENCECTRL_ENTRY,
4579 0 : 49 => Opcode::CONVERGENCECTRL_ANCHOR,
4580 0 : 50 => Opcode::CONVERGENCECTRL_LOOP,
4581 0 : 51 => Opcode::CONVERGENCECTRL_GLUE,
4582 0 : 52 => Opcode::G_ASSERT_SEXT,
4583 0 : 53 => Opcode::G_ASSERT_ZEXT,
4584 0 : 54 => Opcode::G_ASSERT_ALIGN,
4585 0 : 55 => Opcode::G_ADD,
4586 0 : 56 => Opcode::G_SUB,
4587 0 : 57 => Opcode::G_MUL,
4588 0 : 58 => Opcode::G_SDIV,
4589 0 : 59 => Opcode::G_UDIV,
4590 0 : 60 => Opcode::G_SREM,
4591 0 : 61 => Opcode::G_UREM,
4592 0 : 62 => Opcode::G_SDIVREM,
4593 0 : 63 => Opcode::G_UDIVREM,
4594 0 : 64 => Opcode::G_AND,
4595 0 : 65 => Opcode::G_OR,
4596 0 : 66 => Opcode::G_XOR,
4597 0 : 67 => Opcode::G_ABDS,
4598 0 : 68 => Opcode::G_ABDU,
4599 0 : 69 => Opcode::G_UAVGFLOOR,
4600 0 : 70 => Opcode::G_UAVGCEIL,
4601 0 : 71 => Opcode::G_SAVGFLOOR,
4602 0 : 72 => Opcode::G_SAVGCEIL,
4603 0 : 73 => Opcode::G_IMPLICIT_DEF,
4604 0 : 74 => Opcode::G_PHI,
4605 0 : 75 => Opcode::G_FRAME_INDEX,
4606 0 : 76 => Opcode::G_GLOBAL_VALUE,
4607 0 : 77 => Opcode::G_PTRAUTH_GLOBAL_VALUE,
4608 0 : 78 => Opcode::G_CONSTANT_POOL,
4609 0 : 79 => Opcode::G_EXTRACT,
4610 0 : 80 => Opcode::G_UNMERGE_VALUES,
4611 0 : 81 => Opcode::G_INSERT,
4612 0 : 82 => Opcode::G_MERGE_VALUES,
4613 0 : 83 => Opcode::G_BUILD_VECTOR,
4614 0 : 84 => Opcode::G_BUILD_VECTOR_TRUNC,
4615 0 : 85 => Opcode::G_CONCAT_VECTORS,
4616 0 : 86 => Opcode::G_PTRTOINT,
4617 0 : 87 => Opcode::G_INTTOPTR,
4618 0 : 88 => Opcode::G_BITCAST,
4619 0 : 89 => Opcode::G_FREEZE,
4620 0 : 90 => Opcode::G_CONSTANT_FOLD_BARRIER,
4621 0 : 91 => Opcode::G_INTRINSIC_FPTRUNC_ROUND,
4622 0 : 92 => Opcode::G_INTRINSIC_TRUNC,
4623 0 : 93 => Opcode::G_INTRINSIC_ROUND,
4624 0 : 94 => Opcode::G_INTRINSIC_LRINT,
4625 0 : 95 => Opcode::G_INTRINSIC_LLRINT,
4626 0 : 96 => Opcode::G_INTRINSIC_ROUNDEVEN,
4627 0 : 97 => Opcode::G_READCYCLECOUNTER,
4628 0 : 98 => Opcode::G_READSTEADYCOUNTER,
4629 0 : 99 => Opcode::G_LOAD,
4630 0 : 100 => Opcode::G_SEXTLOAD,
4631 0 : 101 => Opcode::G_ZEXTLOAD,
4632 0 : 102 => Opcode::G_INDEXED_LOAD,
4633 0 : 103 => Opcode::G_INDEXED_SEXTLOAD,
4634 0 : 104 => Opcode::G_INDEXED_ZEXTLOAD,
4635 0 : 105 => Opcode::G_STORE,
4636 0 : 106 => Opcode::G_INDEXED_STORE,
4637 0 : 107 => Opcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS,
4638 0 : 108 => Opcode::G_ATOMIC_CMPXCHG,
4639 0 : 109 => Opcode::G_ATOMICRMW_XCHG,
4640 0 : 110 => Opcode::G_ATOMICRMW_ADD,
4641 0 : 111 => Opcode::G_ATOMICRMW_SUB,
4642 0 : 112 => Opcode::G_ATOMICRMW_AND,
4643 0 : 113 => Opcode::G_ATOMICRMW_NAND,
4644 0 : 114 => Opcode::G_ATOMICRMW_OR,
4645 0 : 115 => Opcode::G_ATOMICRMW_XOR,
4646 0 : 116 => Opcode::G_ATOMICRMW_MAX,
4647 0 : 117 => Opcode::G_ATOMICRMW_MIN,
4648 0 : 118 => Opcode::G_ATOMICRMW_UMAX,
4649 0 : 119 => Opcode::G_ATOMICRMW_UMIN,
4650 0 : 120 => Opcode::G_ATOMICRMW_FADD,
4651 0 : 121 => Opcode::G_ATOMICRMW_FSUB,
4652 0 : 122 => Opcode::G_ATOMICRMW_FMAX,
4653 0 : 123 => Opcode::G_ATOMICRMW_FMIN,
4654 0 : 124 => Opcode::G_ATOMICRMW_FMAXIMUM,
4655 0 : 125 => Opcode::G_ATOMICRMW_FMINIMUM,
4656 0 : 126 => Opcode::G_ATOMICRMW_UINC_WRAP,
4657 0 : 127 => Opcode::G_ATOMICRMW_UDEC_WRAP,
4658 0 : 128 => Opcode::G_ATOMICRMW_USUB_COND,
4659 0 : 129 => Opcode::G_ATOMICRMW_USUB_SAT,
4660 0 : 130 => Opcode::G_FENCE,
4661 0 : 131 => Opcode::G_PREFETCH,
4662 0 : 132 => Opcode::G_BRCOND,
4663 0 : 133 => Opcode::G_BRINDIRECT,
4664 0 : 134 => Opcode::G_INVOKE_REGION_START,
4665 0 : 135 => Opcode::G_INTRINSIC,
4666 0 : 136 => Opcode::G_INTRINSIC_W_SIDE_EFFECTS,
4667 0 : 137 => Opcode::G_INTRINSIC_CONVERGENT,
4668 0 : 138 => Opcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS,
4669 0 : 139 => Opcode::G_ANYEXT,
4670 0 : 140 => Opcode::G_TRUNC,
4671 0 : 141 => Opcode::G_TRUNC_SSAT_S,
4672 0 : 142 => Opcode::G_TRUNC_SSAT_U,
4673 0 : 143 => Opcode::G_TRUNC_USAT_U,
4674 0 : 144 => Opcode::G_CONSTANT,
4675 0 : 145 => Opcode::G_FCONSTANT,
4676 0 : 146 => Opcode::G_VASTART,
4677 0 : 147 => Opcode::G_VAARG,
4678 0 : 148 => Opcode::G_SEXT,
4679 0 : 149 => Opcode::G_SEXT_INREG,
4680 0 : 150 => Opcode::G_ZEXT,
4681 0 : 151 => Opcode::G_SHL,
4682 0 : 152 => Opcode::G_LSHR,
4683 0 : 153 => Opcode::G_ASHR,
4684 0 : 154 => Opcode::G_FSHL,
4685 0 : 155 => Opcode::G_FSHR,
4686 0 : 156 => Opcode::G_ROTR,
4687 0 : 157 => Opcode::G_ROTL,
4688 0 : 158 => Opcode::G_ICMP,
4689 0 : 159 => Opcode::G_FCMP,
4690 0 : 160 => Opcode::G_SCMP,
4691 0 : 161 => Opcode::G_UCMP,
4692 0 : 162 => Opcode::G_SELECT,
4693 0 : 163 => Opcode::G_UADDO,
4694 0 : 164 => Opcode::G_UADDE,
4695 0 : 165 => Opcode::G_USUBO,
4696 0 : 166 => Opcode::G_USUBE,
4697 0 : 167 => Opcode::G_SADDO,
4698 0 : 168 => Opcode::G_SADDE,
4699 0 : 169 => Opcode::G_SSUBO,
4700 0 : 170 => Opcode::G_SSUBE,
4701 0 : 171 => Opcode::G_UMULO,
4702 0 : 172 => Opcode::G_SMULO,
4703 0 : 173 => Opcode::G_UMULH,
4704 0 : 174 => Opcode::G_SMULH,
4705 0 : 175 => Opcode::G_UADDSAT,
4706 0 : 176 => Opcode::G_SADDSAT,
4707 0 : 177 => Opcode::G_USUBSAT,
4708 0 : 178 => Opcode::G_SSUBSAT,
4709 0 : 179 => Opcode::G_USHLSAT,
4710 0 : 180 => Opcode::G_SSHLSAT,
4711 0 : 181 => Opcode::G_SMULFIX,
4712 0 : 182 => Opcode::G_UMULFIX,
4713 0 : 183 => Opcode::G_SMULFIXSAT,
4714 0 : 184 => Opcode::G_UMULFIXSAT,
4715 0 : 185 => Opcode::G_SDIVFIX,
4716 0 : 186 => Opcode::G_UDIVFIX,
4717 0 : 187 => Opcode::G_SDIVFIXSAT,
4718 0 : 188 => Opcode::G_UDIVFIXSAT,
4719 0 : 189 => Opcode::G_FADD,
4720 0 : 190 => Opcode::G_FSUB,
4721 0 : 191 => Opcode::G_FMUL,
4722 0 : 192 => Opcode::G_FMA,
4723 0 : 193 => Opcode::G_FMAD,
4724 0 : 194 => Opcode::G_FDIV,
4725 0 : 195 => Opcode::G_FREM,
4726 0 : 196 => Opcode::G_FMODF,
4727 0 : 197 => Opcode::G_FPOW,
4728 0 : 198 => Opcode::G_FPOWI,
4729 0 : 199 => Opcode::G_FEXP,
4730 0 : 200 => Opcode::G_FEXP2,
4731 0 : 201 => Opcode::G_FEXP10,
4732 0 : 202 => Opcode::G_FLOG,
4733 0 : 203 => Opcode::G_FLOG2,
4734 0 : 204 => Opcode::G_FLOG10,
4735 0 : 205 => Opcode::G_FLDEXP,
4736 0 : 206 => Opcode::G_FFREXP,
4737 0 : 207 => Opcode::G_FNEG,
4738 0 : 208 => Opcode::G_FPEXT,
4739 0 : 209 => Opcode::G_FPTRUNC,
4740 0 : 210 => Opcode::G_FPTOSI,
4741 0 : 211 => Opcode::G_FPTOUI,
4742 0 : 212 => Opcode::G_SITOFP,
4743 0 : 213 => Opcode::G_UITOFP,
4744 0 : 214 => Opcode::G_FPTOSI_SAT,
4745 0 : 215 => Opcode::G_FPTOUI_SAT,
4746 0 : 216 => Opcode::G_FABS,
4747 0 : 217 => Opcode::G_FCOPYSIGN,
4748 0 : 218 => Opcode::G_IS_FPCLASS,
4749 0 : 219 => Opcode::G_FCANONICALIZE,
4750 0 : 220 => Opcode::G_FMINNUM,
4751 0 : 221 => Opcode::G_FMAXNUM,
4752 0 : 222 => Opcode::G_FMINNUM_IEEE,
4753 0 : 223 => Opcode::G_FMAXNUM_IEEE,
4754 0 : 224 => Opcode::G_FMINIMUM,
4755 0 : 225 => Opcode::G_FMAXIMUM,
4756 0 : 226 => Opcode::G_FMINIMUMNUM,
4757 0 : 227 => Opcode::G_FMAXIMUMNUM,
4758 0 : 228 => Opcode::G_GET_FPENV,
4759 0 : 229 => Opcode::G_SET_FPENV,
4760 0 : 230 => Opcode::G_RESET_FPENV,
4761 0 : 231 => Opcode::G_GET_FPMODE,
4762 0 : 232 => Opcode::G_SET_FPMODE,
4763 0 : 233 => Opcode::G_RESET_FPMODE,
4764 0 : 234 => Opcode::G_GET_ROUNDING,
4765 0 : 235 => Opcode::G_SET_ROUNDING,
4766 0 : 236 => Opcode::G_PTR_ADD,
4767 0 : 237 => Opcode::G_PTRMASK,
4768 0 : 238 => Opcode::G_SMIN,
4769 0 : 239 => Opcode::G_SMAX,
4770 0 : 240 => Opcode::G_UMIN,
4771 0 : 241 => Opcode::G_UMAX,
4772 0 : 242 => Opcode::G_ABS,
4773 0 : 243 => Opcode::G_LROUND,
4774 0 : 244 => Opcode::G_LLROUND,
4775 0 : 245 => Opcode::G_BR,
4776 0 : 246 => Opcode::G_BRJT,
4777 0 : 247 => Opcode::G_VSCALE,
4778 0 : 248 => Opcode::G_INSERT_SUBVECTOR,
4779 0 : 249 => Opcode::G_EXTRACT_SUBVECTOR,
4780 0 : 250 => Opcode::G_INSERT_VECTOR_ELT,
4781 0 : 251 => Opcode::G_EXTRACT_VECTOR_ELT,
4782 0 : 252 => Opcode::G_SHUFFLE_VECTOR,
4783 0 : 253 => Opcode::G_SPLAT_VECTOR,
4784 0 : 254 => Opcode::G_STEP_VECTOR,
4785 0 : 255 => Opcode::G_VECTOR_COMPRESS,
4786 0 : 256 => Opcode::G_CTTZ,
4787 0 : 257 => Opcode::G_CTTZ_ZERO_UNDEF,
4788 0 : 258 => Opcode::G_CTLZ,
4789 0 : 259 => Opcode::G_CTLZ_ZERO_UNDEF,
4790 0 : 260 => Opcode::G_CTPOP,
4791 0 : 261 => Opcode::G_BSWAP,
4792 0 : 262 => Opcode::G_BITREVERSE,
4793 0 : 263 => Opcode::G_FCEIL,
4794 0 : 264 => Opcode::G_FCOS,
4795 0 : 265 => Opcode::G_FSIN,
4796 0 : 266 => Opcode::G_FSINCOS,
4797 0 : 267 => Opcode::G_FTAN,
4798 0 : 268 => Opcode::G_FACOS,
4799 0 : 269 => Opcode::G_FASIN,
4800 0 : 270 => Opcode::G_FATAN,
4801 0 : 271 => Opcode::G_FATAN2,
4802 0 : 272 => Opcode::G_FCOSH,
4803 0 : 273 => Opcode::G_FSINH,
4804 0 : 274 => Opcode::G_FTANH,
4805 0 : 275 => Opcode::G_FSQRT,
4806 0 : 276 => Opcode::G_FFLOOR,
4807 0 : 277 => Opcode::G_FRINT,
4808 0 : 278 => Opcode::G_FNEARBYINT,
4809 0 : 279 => Opcode::G_ADDRSPACE_CAST,
4810 0 : 280 => Opcode::G_BLOCK_ADDR,
4811 0 : 281 => Opcode::G_JUMP_TABLE,
4812 0 : 282 => Opcode::G_DYN_STACKALLOC,
4813 0 : 283 => Opcode::G_STACKSAVE,
4814 0 : 284 => Opcode::G_STACKRESTORE,
4815 0 : 285 => Opcode::G_STRICT_FADD,
4816 0 : 286 => Opcode::G_STRICT_FSUB,
4817 0 : 287 => Opcode::G_STRICT_FMUL,
4818 0 : 288 => Opcode::G_STRICT_FDIV,
4819 0 : 289 => Opcode::G_STRICT_FREM,
4820 0 : 290 => Opcode::G_STRICT_FMA,
4821 0 : 291 => Opcode::G_STRICT_FSQRT,
4822 0 : 292 => Opcode::G_STRICT_FLDEXP,
4823 0 : 293 => Opcode::G_READ_REGISTER,
4824 0 : 294 => Opcode::G_WRITE_REGISTER,
4825 0 : 295 => Opcode::G_MEMCPY,
4826 0 : 296 => Opcode::G_MEMCPY_INLINE,
4827 0 : 297 => Opcode::G_MEMMOVE,
4828 0 : 298 => Opcode::G_MEMSET,
4829 0 : 299 => Opcode::G_BZERO,
4830 0 : 300 => Opcode::G_TRAP,
4831 0 : 301 => Opcode::G_DEBUGTRAP,
4832 0 : 302 => Opcode::G_UBSANTRAP,
4833 0 : 303 => Opcode::G_VECREDUCE_SEQ_FADD,
4834 0 : 304 => Opcode::G_VECREDUCE_SEQ_FMUL,
4835 0 : 305 => Opcode::G_VECREDUCE_FADD,
4836 0 : 306 => Opcode::G_VECREDUCE_FMUL,
4837 0 : 307 => Opcode::G_VECREDUCE_FMAX,
4838 0 : 308 => Opcode::G_VECREDUCE_FMIN,
4839 0 : 309 => Opcode::G_VECREDUCE_FMAXIMUM,
4840 0 : 310 => Opcode::G_VECREDUCE_FMINIMUM,
4841 0 : 311 => Opcode::G_VECREDUCE_ADD,
4842 0 : 312 => Opcode::G_VECREDUCE_MUL,
4843 0 : 313 => Opcode::G_VECREDUCE_AND,
4844 0 : 314 => Opcode::G_VECREDUCE_OR,
4845 0 : 315 => Opcode::G_VECREDUCE_XOR,
4846 0 : 316 => Opcode::G_VECREDUCE_SMAX,
4847 0 : 317 => Opcode::G_VECREDUCE_SMIN,
4848 0 : 318 => Opcode::G_VECREDUCE_UMAX,
4849 0 : 319 => Opcode::G_VECREDUCE_UMIN,
4850 0 : 320 => Opcode::G_SBFX,
4851 0 : 321 => Opcode::G_UBFX,
4852 0 : 322 => Opcode::ADDSri,
4853 0 : 323 => Opcode::ADDSrr,
4854 0 : 324 => Opcode::ADDSrsi,
4855 0 : 325 => Opcode::ADDSrsr,
4856 0 : 326 => Opcode::ADJCALLSTACKDOWN,
4857 0 : 327 => Opcode::ADJCALLSTACKUP,
4858 0 : 328 => Opcode::ASRi,
4859 0 : 329 => Opcode::ASRr,
4860 0 : 330 => Opcode::ASRs1,
4861 0 : 331 => Opcode::B,
4862 0 : 332 => Opcode::BCCZi64,
4863 0 : 333 => Opcode::BCCi64,
4864 0 : 334 => Opcode::BLX_noip,
4865 0 : 335 => Opcode::BLX_pred_noip,
4866 0 : 336 => Opcode::BL_PUSHLR,
4867 0 : 337 => Opcode::BMOVPCB_CALL,
4868 0 : 338 => Opcode::BMOVPCRX_CALL,
4869 0 : 339 => Opcode::BR_JTadd,
4870 0 : 340 => Opcode::BR_JTm_i12,
4871 0 : 341 => Opcode::BR_JTm_rs,
4872 0 : 342 => Opcode::BR_JTr,
4873 0 : 343 => Opcode::BX_CALL,
4874 0 : 344 => Opcode::CMP_SWAP_16,
4875 0 : 345 => Opcode::CMP_SWAP_32,
4876 0 : 346 => Opcode::CMP_SWAP_64,
4877 0 : 347 => Opcode::CMP_SWAP_8,
4878 0 : 348 => Opcode::CONSTPOOL_ENTRY,
4879 0 : 349 => Opcode::COPY_STRUCT_BYVAL_I32,
4880 0 : 350 => Opcode::ITasm,
4881 0 : 351 => Opcode::Int_eh_sjlj_dispatchsetup,
4882 0 : 352 => Opcode::Int_eh_sjlj_longjmp,
4883 0 : 353 => Opcode::Int_eh_sjlj_setjmp,
4884 0 : 354 => Opcode::Int_eh_sjlj_setjmp_nofp,
4885 0 : 355 => Opcode::Int_eh_sjlj_setup_dispatch,
4886 0 : 356 => Opcode::JUMPTABLE_ADDRS,
4887 0 : 357 => Opcode::JUMPTABLE_INSTS,
4888 0 : 358 => Opcode::JUMPTABLE_TBB,
4889 0 : 359 => Opcode::JUMPTABLE_TBH,
4890 0 : 360 => Opcode::KCFI_CHECK_ARM,
4891 0 : 361 => Opcode::KCFI_CHECK_Thumb1,
4892 0 : 362 => Opcode::KCFI_CHECK_Thumb2,
4893 0 : 363 => Opcode::LDMIA_RET,
4894 0 : 364 => Opcode::LDRBT_POST,
4895 0 : 365 => Opcode::LDRConstPool,
4896 0 : 366 => Opcode::LDRHTii,
4897 0 : 367 => Opcode::LDRLIT_ga_abs,
4898 0 : 368 => Opcode::LDRLIT_ga_pcrel,
4899 0 : 369 => Opcode::LDRLIT_ga_pcrel_ldr,
4900 0 : 370 => Opcode::LDRSBTii,
4901 0 : 371 => Opcode::LDRSHTii,
4902 0 : 372 => Opcode::LDRT_POST,
4903 0 : 373 => Opcode::LEApcrel,
4904 0 : 374 => Opcode::LEApcrelJT,
4905 0 : 375 => Opcode::LOADDUAL,
4906 0 : 376 => Opcode::LSLi,
4907 0 : 377 => Opcode::LSLr,
4908 0 : 378 => Opcode::LSRi,
4909 0 : 379 => Opcode::LSRr,
4910 0 : 380 => Opcode::LSRs1,
4911 0 : 381 => Opcode::MEMCPY,
4912 0 : 382 => Opcode::MLAv5,
4913 0 : 383 => Opcode::MOVCCi,
4914 0 : 384 => Opcode::MOVCCi16,
4915 0 : 385 => Opcode::MOVCCi32imm,
4916 0 : 386 => Opcode::MOVCCr,
4917 0 : 387 => Opcode::MOVCCsi,
4918 0 : 388 => Opcode::MOVCCsr,
4919 0 : 389 => Opcode::MOVPCRX,
4920 0 : 390 => Opcode::MOVTi16_ga_pcrel,
4921 0 : 391 => Opcode::MOV_ga_pcrel,
4922 0 : 392 => Opcode::MOV_ga_pcrel_ldr,
4923 0 : 393 => Opcode::MOVi16_ga_pcrel,
4924 0 : 394 => Opcode::MOVi32imm,
4925 0 : 395 => Opcode::MQPRCopy,
4926 0 : 396 => Opcode::MQQPRLoad,
4927 0 : 397 => Opcode::MQQPRStore,
4928 0 : 398 => Opcode::MQQQQPRLoad,
4929 0 : 399 => Opcode::MQQQQPRStore,
4930 0 : 400 => Opcode::MULv5,
4931 0 : 401 => Opcode::MVE_MEMCPYLOOPINST,
4932 0 : 402 => Opcode::MVE_MEMSETLOOPINST,
4933 0 : 403 => Opcode::MVNCCi,
4934 0 : 404 => Opcode::PICADD,
4935 0 : 405 => Opcode::PICLDR,
4936 0 : 406 => Opcode::PICLDRB,
4937 0 : 407 => Opcode::PICLDRH,
4938 0 : 408 => Opcode::PICLDRSB,
4939 0 : 409 => Opcode::PICLDRSH,
4940 0 : 410 => Opcode::PICSTR,
4941 0 : 411 => Opcode::PICSTRB,
4942 0 : 412 => Opcode::PICSTRH,
4943 0 : 413 => Opcode::RORi,
4944 0 : 414 => Opcode::RORr,
4945 0 : 415 => Opcode::RRX,
4946 0 : 416 => Opcode::RRXi,
4947 0 : 417 => Opcode::RSBSri,
4948 0 : 418 => Opcode::RSBSrsi,
4949 0 : 419 => Opcode::RSBSrsr,
4950 0 : 420 => Opcode::SEH_EpilogEnd,
4951 0 : 421 => Opcode::SEH_EpilogStart,
4952 0 : 422 => Opcode::SEH_Nop,
4953 0 : 423 => Opcode::SEH_Nop_Ret,
4954 0 : 424 => Opcode::SEH_PrologEnd,
4955 0 : 425 => Opcode::SEH_SaveFRegs,
4956 0 : 426 => Opcode::SEH_SaveLR,
4957 0 : 427 => Opcode::SEH_SaveRegs,
4958 0 : 428 => Opcode::SEH_SaveRegs_Ret,
4959 0 : 429 => Opcode::SEH_SaveSP,
4960 0 : 430 => Opcode::SEH_StackAlloc,
4961 0 : 431 => Opcode::SMLALv5,
4962 0 : 432 => Opcode::SMULLv5,
4963 0 : 433 => Opcode::SPACE,
4964 0 : 434 => Opcode::STOREDUAL,
4965 0 : 435 => Opcode::STRBT_POST,
4966 0 : 436 => Opcode::STRBi_preidx,
4967 0 : 437 => Opcode::STRBr_preidx,
4968 0 : 438 => Opcode::STRH_preidx,
4969 0 : 439 => Opcode::STRT_POST,
4970 0 : 440 => Opcode::STRi_preidx,
4971 0 : 441 => Opcode::STRr_preidx,
4972 0 : 442 => Opcode::SUBS_PC_LR,
4973 0 : 443 => Opcode::SUBSri,
4974 0 : 444 => Opcode::SUBSrr,
4975 0 : 445 => Opcode::SUBSrsi,
4976 0 : 446 => Opcode::SUBSrsr,
4977 0 : 447 => Opcode::SpeculationBarrierISBDSBEndBB,
4978 0 : 448 => Opcode::SpeculationBarrierSBEndBB,
4979 0 : 449 => Opcode::TAILJMPd,
4980 0 : 450 => Opcode::TAILJMPr,
4981 0 : 451 => Opcode::TAILJMPr4,
4982 0 : 452 => Opcode::TCRETURNdi,
4983 0 : 453 => Opcode::TCRETURNri,
4984 0 : 454 => Opcode::TCRETURNrinotr12,
4985 0 : 455 => Opcode::TPsoft,
4986 0 : 456 => Opcode::UMLALv5,
4987 0 : 457 => Opcode::UMULLv5,
4988 0 : 458 => Opcode::VLD1LNdAsm_16,
4989 0 : 459 => Opcode::VLD1LNdAsm_32,
4990 0 : 460 => Opcode::VLD1LNdAsm_8,
4991 0 : 461 => Opcode::VLD1LNdWB_fixed_Asm_16,
4992 0 : 462 => Opcode::VLD1LNdWB_fixed_Asm_32,
4993 0 : 463 => Opcode::VLD1LNdWB_fixed_Asm_8,
4994 0 : 464 => Opcode::VLD1LNdWB_register_Asm_16,
4995 0 : 465 => Opcode::VLD1LNdWB_register_Asm_32,
4996 0 : 466 => Opcode::VLD1LNdWB_register_Asm_8,
4997 0 : 467 => Opcode::VLD2LNdAsm_16,
4998 0 : 468 => Opcode::VLD2LNdAsm_32,
4999 0 : 469 => Opcode::VLD2LNdAsm_8,
5000 0 : 470 => Opcode::VLD2LNdWB_fixed_Asm_16,
5001 0 : 471 => Opcode::VLD2LNdWB_fixed_Asm_32,
5002 0 : 472 => Opcode::VLD2LNdWB_fixed_Asm_8,
5003 0 : 473 => Opcode::VLD2LNdWB_register_Asm_16,
5004 0 : 474 => Opcode::VLD2LNdWB_register_Asm_32,
5005 0 : 475 => Opcode::VLD2LNdWB_register_Asm_8,
5006 0 : 476 => Opcode::VLD2LNqAsm_16,
5007 0 : 477 => Opcode::VLD2LNqAsm_32,
5008 0 : 478 => Opcode::VLD2LNqWB_fixed_Asm_16,
5009 0 : 479 => Opcode::VLD2LNqWB_fixed_Asm_32,
5010 0 : 480 => Opcode::VLD2LNqWB_register_Asm_16,
5011 0 : 481 => Opcode::VLD2LNqWB_register_Asm_32,
5012 0 : 482 => Opcode::VLD3DUPdAsm_16,
5013 0 : 483 => Opcode::VLD3DUPdAsm_32,
5014 0 : 484 => Opcode::VLD3DUPdAsm_8,
5015 0 : 485 => Opcode::VLD3DUPdWB_fixed_Asm_16,
5016 0 : 486 => Opcode::VLD3DUPdWB_fixed_Asm_32,
5017 0 : 487 => Opcode::VLD3DUPdWB_fixed_Asm_8,
5018 0 : 488 => Opcode::VLD3DUPdWB_register_Asm_16,
5019 0 : 489 => Opcode::VLD3DUPdWB_register_Asm_32,
5020 0 : 490 => Opcode::VLD3DUPdWB_register_Asm_8,
5021 0 : 491 => Opcode::VLD3DUPqAsm_16,
5022 0 : 492 => Opcode::VLD3DUPqAsm_32,
5023 0 : 493 => Opcode::VLD3DUPqAsm_8,
5024 0 : 494 => Opcode::VLD3DUPqWB_fixed_Asm_16,
5025 0 : 495 => Opcode::VLD3DUPqWB_fixed_Asm_32,
5026 0 : 496 => Opcode::VLD3DUPqWB_fixed_Asm_8,
5027 0 : 497 => Opcode::VLD3DUPqWB_register_Asm_16,
5028 0 : 498 => Opcode::VLD3DUPqWB_register_Asm_32,
5029 0 : 499 => Opcode::VLD3DUPqWB_register_Asm_8,
5030 0 : 500 => Opcode::VLD3LNdAsm_16,
5031 0 : 501 => Opcode::VLD3LNdAsm_32,
5032 0 : 502 => Opcode::VLD3LNdAsm_8,
5033 0 : 503 => Opcode::VLD3LNdWB_fixed_Asm_16,
5034 0 : 504 => Opcode::VLD3LNdWB_fixed_Asm_32,
5035 0 : 505 => Opcode::VLD3LNdWB_fixed_Asm_8,
5036 0 : 506 => Opcode::VLD3LNdWB_register_Asm_16,
5037 0 : 507 => Opcode::VLD3LNdWB_register_Asm_32,
5038 0 : 508 => Opcode::VLD3LNdWB_register_Asm_8,
5039 0 : 509 => Opcode::VLD3LNqAsm_16,
5040 0 : 510 => Opcode::VLD3LNqAsm_32,
5041 0 : 511 => Opcode::VLD3LNqWB_fixed_Asm_16,
5042 0 : 512 => Opcode::VLD3LNqWB_fixed_Asm_32,
5043 0 : 513 => Opcode::VLD3LNqWB_register_Asm_16,
5044 0 : 514 => Opcode::VLD3LNqWB_register_Asm_32,
5045 0 : 515 => Opcode::VLD3dAsm_16,
5046 0 : 516 => Opcode::VLD3dAsm_32,
5047 0 : 517 => Opcode::VLD3dAsm_8,
5048 0 : 518 => Opcode::VLD3dWB_fixed_Asm_16,
5049 0 : 519 => Opcode::VLD3dWB_fixed_Asm_32,
5050 0 : 520 => Opcode::VLD3dWB_fixed_Asm_8,
5051 0 : 521 => Opcode::VLD3dWB_register_Asm_16,
5052 0 : 522 => Opcode::VLD3dWB_register_Asm_32,
5053 0 : 523 => Opcode::VLD3dWB_register_Asm_8,
5054 0 : 524 => Opcode::VLD3qAsm_16,
5055 0 : 525 => Opcode::VLD3qAsm_32,
5056 0 : 526 => Opcode::VLD3qAsm_8,
5057 0 : 527 => Opcode::VLD3qWB_fixed_Asm_16,
5058 0 : 528 => Opcode::VLD3qWB_fixed_Asm_32,
5059 0 : 529 => Opcode::VLD3qWB_fixed_Asm_8,
5060 0 : 530 => Opcode::VLD3qWB_register_Asm_16,
5061 0 : 531 => Opcode::VLD3qWB_register_Asm_32,
5062 0 : 532 => Opcode::VLD3qWB_register_Asm_8,
5063 0 : 533 => Opcode::VLD4DUPdAsm_16,
5064 0 : 534 => Opcode::VLD4DUPdAsm_32,
5065 0 : 535 => Opcode::VLD4DUPdAsm_8,
5066 0 : 536 => Opcode::VLD4DUPdWB_fixed_Asm_16,
5067 0 : 537 => Opcode::VLD4DUPdWB_fixed_Asm_32,
5068 0 : 538 => Opcode::VLD4DUPdWB_fixed_Asm_8,
5069 0 : 539 => Opcode::VLD4DUPdWB_register_Asm_16,
5070 0 : 540 => Opcode::VLD4DUPdWB_register_Asm_32,
5071 0 : 541 => Opcode::VLD4DUPdWB_register_Asm_8,
5072 0 : 542 => Opcode::VLD4DUPqAsm_16,
5073 0 : 543 => Opcode::VLD4DUPqAsm_32,
5074 0 : 544 => Opcode::VLD4DUPqAsm_8,
5075 0 : 545 => Opcode::VLD4DUPqWB_fixed_Asm_16,
5076 0 : 546 => Opcode::VLD4DUPqWB_fixed_Asm_32,
5077 0 : 547 => Opcode::VLD4DUPqWB_fixed_Asm_8,
5078 0 : 548 => Opcode::VLD4DUPqWB_register_Asm_16,
5079 0 : 549 => Opcode::VLD4DUPqWB_register_Asm_32,
5080 0 : 550 => Opcode::VLD4DUPqWB_register_Asm_8,
5081 0 : 551 => Opcode::VLD4LNdAsm_16,
5082 0 : 552 => Opcode::VLD4LNdAsm_32,
5083 0 : 553 => Opcode::VLD4LNdAsm_8,
5084 0 : 554 => Opcode::VLD4LNdWB_fixed_Asm_16,
5085 0 : 555 => Opcode::VLD4LNdWB_fixed_Asm_32,
5086 0 : 556 => Opcode::VLD4LNdWB_fixed_Asm_8,
5087 0 : 557 => Opcode::VLD4LNdWB_register_Asm_16,
5088 0 : 558 => Opcode::VLD4LNdWB_register_Asm_32,
5089 0 : 559 => Opcode::VLD4LNdWB_register_Asm_8,
5090 0 : 560 => Opcode::VLD4LNqAsm_16,
5091 0 : 561 => Opcode::VLD4LNqAsm_32,
5092 0 : 562 => Opcode::VLD4LNqWB_fixed_Asm_16,
5093 0 : 563 => Opcode::VLD4LNqWB_fixed_Asm_32,
5094 0 : 564 => Opcode::VLD4LNqWB_register_Asm_16,
5095 0 : 565 => Opcode::VLD4LNqWB_register_Asm_32,
5096 0 : 566 => Opcode::VLD4dAsm_16,
5097 0 : 567 => Opcode::VLD4dAsm_32,
5098 0 : 568 => Opcode::VLD4dAsm_8,
5099 0 : 569 => Opcode::VLD4dWB_fixed_Asm_16,
5100 0 : 570 => Opcode::VLD4dWB_fixed_Asm_32,
5101 0 : 571 => Opcode::VLD4dWB_fixed_Asm_8,
5102 0 : 572 => Opcode::VLD4dWB_register_Asm_16,
5103 0 : 573 => Opcode::VLD4dWB_register_Asm_32,
5104 0 : 574 => Opcode::VLD4dWB_register_Asm_8,
5105 0 : 575 => Opcode::VLD4qAsm_16,
5106 0 : 576 => Opcode::VLD4qAsm_32,
5107 0 : 577 => Opcode::VLD4qAsm_8,
5108 0 : 578 => Opcode::VLD4qWB_fixed_Asm_16,
5109 0 : 579 => Opcode::VLD4qWB_fixed_Asm_32,
5110 0 : 580 => Opcode::VLD4qWB_fixed_Asm_8,
5111 0 : 581 => Opcode::VLD4qWB_register_Asm_16,
5112 0 : 582 => Opcode::VLD4qWB_register_Asm_32,
5113 0 : 583 => Opcode::VLD4qWB_register_Asm_8,
5114 0 : 584 => Opcode::VMOVD0,
5115 0 : 585 => Opcode::VMOVDcc,
5116 0 : 586 => Opcode::VMOVHcc,
5117 0 : 587 => Opcode::VMOVQ0,
5118 0 : 588 => Opcode::VMOVScc,
5119 0 : 589 => Opcode::VST1LNdAsm_16,
5120 0 : 590 => Opcode::VST1LNdAsm_32,
5121 0 : 591 => Opcode::VST1LNdAsm_8,
5122 0 : 592 => Opcode::VST1LNdWB_fixed_Asm_16,
5123 0 : 593 => Opcode::VST1LNdWB_fixed_Asm_32,
5124 0 : 594 => Opcode::VST1LNdWB_fixed_Asm_8,
5125 0 : 595 => Opcode::VST1LNdWB_register_Asm_16,
5126 0 : 596 => Opcode::VST1LNdWB_register_Asm_32,
5127 0 : 597 => Opcode::VST1LNdWB_register_Asm_8,
5128 0 : 598 => Opcode::VST2LNdAsm_16,
5129 0 : 599 => Opcode::VST2LNdAsm_32,
5130 0 : 600 => Opcode::VST2LNdAsm_8,
5131 0 : 601 => Opcode::VST2LNdWB_fixed_Asm_16,
5132 0 : 602 => Opcode::VST2LNdWB_fixed_Asm_32,
5133 0 : 603 => Opcode::VST2LNdWB_fixed_Asm_8,
5134 0 : 604 => Opcode::VST2LNdWB_register_Asm_16,
5135 0 : 605 => Opcode::VST2LNdWB_register_Asm_32,
5136 0 : 606 => Opcode::VST2LNdWB_register_Asm_8,
5137 0 : 607 => Opcode::VST2LNqAsm_16,
5138 0 : 608 => Opcode::VST2LNqAsm_32,
5139 0 : 609 => Opcode::VST2LNqWB_fixed_Asm_16,
5140 0 : 610 => Opcode::VST2LNqWB_fixed_Asm_32,
5141 0 : 611 => Opcode::VST2LNqWB_register_Asm_16,
5142 0 : 612 => Opcode::VST2LNqWB_register_Asm_32,
5143 0 : 613 => Opcode::VST3LNdAsm_16,
5144 0 : 614 => Opcode::VST3LNdAsm_32,
5145 0 : 615 => Opcode::VST3LNdAsm_8,
5146 0 : 616 => Opcode::VST3LNdWB_fixed_Asm_16,
5147 0 : 617 => Opcode::VST3LNdWB_fixed_Asm_32,
5148 0 : 618 => Opcode::VST3LNdWB_fixed_Asm_8,
5149 0 : 619 => Opcode::VST3LNdWB_register_Asm_16,
5150 0 : 620 => Opcode::VST3LNdWB_register_Asm_32,
5151 0 : 621 => Opcode::VST3LNdWB_register_Asm_8,
5152 0 : 622 => Opcode::VST3LNqAsm_16,
5153 0 : 623 => Opcode::VST3LNqAsm_32,
5154 0 : 624 => Opcode::VST3LNqWB_fixed_Asm_16,
5155 0 : 625 => Opcode::VST3LNqWB_fixed_Asm_32,
5156 0 : 626 => Opcode::VST3LNqWB_register_Asm_16,
5157 0 : 627 => Opcode::VST3LNqWB_register_Asm_32,
5158 0 : 628 => Opcode::VST3dAsm_16,
5159 0 : 629 => Opcode::VST3dAsm_32,
5160 0 : 630 => Opcode::VST3dAsm_8,
5161 0 : 631 => Opcode::VST3dWB_fixed_Asm_16,
5162 0 : 632 => Opcode::VST3dWB_fixed_Asm_32,
5163 0 : 633 => Opcode::VST3dWB_fixed_Asm_8,
5164 0 : 634 => Opcode::VST3dWB_register_Asm_16,
5165 0 : 635 => Opcode::VST3dWB_register_Asm_32,
5166 0 : 636 => Opcode::VST3dWB_register_Asm_8,
5167 0 : 637 => Opcode::VST3qAsm_16,
5168 0 : 638 => Opcode::VST3qAsm_32,
5169 0 : 639 => Opcode::VST3qAsm_8,
5170 0 : 640 => Opcode::VST3qWB_fixed_Asm_16,
5171 0 : 641 => Opcode::VST3qWB_fixed_Asm_32,
5172 0 : 642 => Opcode::VST3qWB_fixed_Asm_8,
5173 0 : 643 => Opcode::VST3qWB_register_Asm_16,
5174 0 : 644 => Opcode::VST3qWB_register_Asm_32,
5175 0 : 645 => Opcode::VST3qWB_register_Asm_8,
5176 0 : 646 => Opcode::VST4LNdAsm_16,
5177 0 : 647 => Opcode::VST4LNdAsm_32,
5178 0 : 648 => Opcode::VST4LNdAsm_8,
5179 0 : 649 => Opcode::VST4LNdWB_fixed_Asm_16,
5180 0 : 650 => Opcode::VST4LNdWB_fixed_Asm_32,
5181 0 : 651 => Opcode::VST4LNdWB_fixed_Asm_8,
5182 0 : 652 => Opcode::VST4LNdWB_register_Asm_16,
5183 0 : 653 => Opcode::VST4LNdWB_register_Asm_32,
5184 0 : 654 => Opcode::VST4LNdWB_register_Asm_8,
5185 0 : 655 => Opcode::VST4LNqAsm_16,
5186 0 : 656 => Opcode::VST4LNqAsm_32,
5187 0 : 657 => Opcode::VST4LNqWB_fixed_Asm_16,
5188 0 : 658 => Opcode::VST4LNqWB_fixed_Asm_32,
5189 0 : 659 => Opcode::VST4LNqWB_register_Asm_16,
5190 0 : 660 => Opcode::VST4LNqWB_register_Asm_32,
5191 0 : 661 => Opcode::VST4dAsm_16,
5192 0 : 662 => Opcode::VST4dAsm_32,
5193 0 : 663 => Opcode::VST4dAsm_8,
5194 0 : 664 => Opcode::VST4dWB_fixed_Asm_16,
5195 0 : 665 => Opcode::VST4dWB_fixed_Asm_32,
5196 0 : 666 => Opcode::VST4dWB_fixed_Asm_8,
5197 0 : 667 => Opcode::VST4dWB_register_Asm_16,
5198 0 : 668 => Opcode::VST4dWB_register_Asm_32,
5199 0 : 669 => Opcode::VST4dWB_register_Asm_8,
5200 0 : 670 => Opcode::VST4qAsm_16,
5201 0 : 671 => Opcode::VST4qAsm_32,
5202 0 : 672 => Opcode::VST4qAsm_8,
5203 0 : 673 => Opcode::VST4qWB_fixed_Asm_16,
5204 0 : 674 => Opcode::VST4qWB_fixed_Asm_32,
5205 0 : 675 => Opcode::VST4qWB_fixed_Asm_8,
5206 0 : 676 => Opcode::VST4qWB_register_Asm_16,
5207 0 : 677 => Opcode::VST4qWB_register_Asm_32,
5208 0 : 678 => Opcode::VST4qWB_register_Asm_8,
5209 0 : 679 => Opcode::WIN__CHKSTK,
5210 0 : 680 => Opcode::WIN__DBZCHK,
5211 0 : 681 => Opcode::t2ADDSri,
5212 0 : 682 => Opcode::t2ADDSrr,
5213 0 : 683 => Opcode::t2ADDSrs,
5214 0 : 684 => Opcode::t2BF_LabelPseudo,
5215 0 : 685 => Opcode::t2BR_JT,
5216 0 : 686 => Opcode::t2CALL_BTI,
5217 0 : 687 => Opcode::t2DoLoopStart,
5218 0 : 688 => Opcode::t2DoLoopStartTP,
5219 0 : 689 => Opcode::t2LDMIA_RET,
5220 0 : 690 => Opcode::t2LDRB_OFFSET_imm,
5221 0 : 691 => Opcode::t2LDRB_POST_imm,
5222 0 : 692 => Opcode::t2LDRB_PRE_imm,
5223 0 : 693 => Opcode::t2LDRBpcrel,
5224 0 : 694 => Opcode::t2LDRConstPool,
5225 0 : 695 => Opcode::t2LDRH_OFFSET_imm,
5226 0 : 696 => Opcode::t2LDRH_POST_imm,
5227 0 : 697 => Opcode::t2LDRH_PRE_imm,
5228 0 : 698 => Opcode::t2LDRHpcrel,
5229 0 : 699 => Opcode::t2LDRLIT_ga_pcrel,
5230 0 : 700 => Opcode::t2LDRSB_OFFSET_imm,
5231 0 : 701 => Opcode::t2LDRSB_POST_imm,
5232 0 : 702 => Opcode::t2LDRSB_PRE_imm,
5233 0 : 703 => Opcode::t2LDRSBpcrel,
5234 0 : 704 => Opcode::t2LDRSH_OFFSET_imm,
5235 0 : 705 => Opcode::t2LDRSH_POST_imm,
5236 0 : 706 => Opcode::t2LDRSH_PRE_imm,
5237 0 : 707 => Opcode::t2LDRSHpcrel,
5238 0 : 708 => Opcode::t2LDR_POST_imm,
5239 0 : 709 => Opcode::t2LDR_PRE_imm,
5240 0 : 710 => Opcode::t2LDRpci_pic,
5241 0 : 711 => Opcode::t2LDRpcrel,
5242 0 : 712 => Opcode::t2LEApcrel,
5243 0 : 713 => Opcode::t2LEApcrelJT,
5244 0 : 714 => Opcode::t2LoopDec,
5245 0 : 715 => Opcode::t2LoopEnd,
5246 0 : 716 => Opcode::t2LoopEndDec,
5247 0 : 717 => Opcode::t2MOVCCasr,
5248 0 : 718 => Opcode::t2MOVCCi,
5249 0 : 719 => Opcode::t2MOVCCi16,
5250 0 : 720 => Opcode::t2MOVCCi32imm,
5251 0 : 721 => Opcode::t2MOVCClsl,
5252 0 : 722 => Opcode::t2MOVCClsr,
5253 0 : 723 => Opcode::t2MOVCCr,
5254 0 : 724 => Opcode::t2MOVCCror,
5255 0 : 725 => Opcode::t2MOVSsi,
5256 0 : 726 => Opcode::t2MOVSsr,
5257 0 : 727 => Opcode::t2MOVTi16_ga_pcrel,
5258 0 : 728 => Opcode::t2MOV_ga_pcrel,
5259 0 : 729 => Opcode::t2MOVi16_ga_pcrel,
5260 0 : 730 => Opcode::t2MOVi32imm,
5261 0 : 731 => Opcode::t2MOVsi,
5262 0 : 732 => Opcode::t2MOVsr,
5263 0 : 733 => Opcode::t2MVNCCi,
5264 0 : 734 => Opcode::t2RSBSri,
5265 0 : 735 => Opcode::t2RSBSrs,
5266 0 : 736 => Opcode::t2STRB_OFFSET_imm,
5267 0 : 737 => Opcode::t2STRB_POST_imm,
5268 0 : 738 => Opcode::t2STRB_PRE_imm,
5269 0 : 739 => Opcode::t2STRB_preidx,
5270 0 : 740 => Opcode::t2STRH_OFFSET_imm,
5271 0 : 741 => Opcode::t2STRH_POST_imm,
5272 0 : 742 => Opcode::t2STRH_PRE_imm,
5273 0 : 743 => Opcode::t2STRH_preidx,
5274 0 : 744 => Opcode::t2STR_POST_imm,
5275 0 : 745 => Opcode::t2STR_PRE_imm,
5276 0 : 746 => Opcode::t2STR_preidx,
5277 0 : 747 => Opcode::t2SUBSri,
5278 0 : 748 => Opcode::t2SUBSrr,
5279 0 : 749 => Opcode::t2SUBSrs,
5280 0 : 750 => Opcode::t2SpeculationBarrierISBDSBEndBB,
5281 0 : 751 => Opcode::t2SpeculationBarrierSBEndBB,
5282 0 : 752 => Opcode::t2TBB_JT,
5283 0 : 753 => Opcode::t2TBH_JT,
5284 0 : 754 => Opcode::t2WhileLoopSetup,
5285 0 : 755 => Opcode::t2WhileLoopStart,
5286 0 : 756 => Opcode::t2WhileLoopStartLR,
5287 0 : 757 => Opcode::t2WhileLoopStartTP,
5288 0 : 758 => Opcode::tADCS,
5289 0 : 759 => Opcode::tADDSi3,
5290 0 : 760 => Opcode::tADDSi8,
5291 0 : 761 => Opcode::tADDSrr,
5292 0 : 762 => Opcode::tADDframe,
5293 0 : 763 => Opcode::tADJCALLSTACKDOWN,
5294 0 : 764 => Opcode::tADJCALLSTACKUP,
5295 0 : 765 => Opcode::tBLXNS_CALL,
5296 0 : 766 => Opcode::tBLXr_noip,
5297 0 : 767 => Opcode::tBL_PUSHLR,
5298 0 : 768 => Opcode::tBRIND,
5299 0 : 769 => Opcode::tBR_JTr,
5300 0 : 770 => Opcode::tBXNS_RET,
5301 0 : 771 => Opcode::tBX_CALL,
5302 0 : 772 => Opcode::tBX_RET,
5303 0 : 773 => Opcode::tBX_RET_vararg,
5304 0 : 774 => Opcode::tBfar,
5305 0 : 775 => Opcode::tCMP_SWAP_16,
5306 0 : 776 => Opcode::tCMP_SWAP_32,
5307 0 : 777 => Opcode::tCMP_SWAP_8,
5308 0 : 778 => Opcode::tLDMIA_UPD,
5309 0 : 779 => Opcode::tLDRConstPool,
5310 0 : 780 => Opcode::tLDRLIT_ga_abs,
5311 0 : 781 => Opcode::tLDRLIT_ga_pcrel,
5312 0 : 782 => Opcode::tLDR_postidx,
5313 0 : 783 => Opcode::tLDRpci_pic,
5314 0 : 784 => Opcode::tLEApcrel,
5315 0 : 785 => Opcode::tLEApcrelJT,
5316 0 : 786 => Opcode::tLSLSri,
5317 0 : 787 => Opcode::tMOVCCr_pseudo,
5318 0 : 788 => Opcode::tMOVi32imm,
5319 0 : 789 => Opcode::tPOP_RET,
5320 0 : 790 => Opcode::tRSBS,
5321 0 : 791 => Opcode::tSBCS,
5322 0 : 792 => Opcode::tSUBSi3,
5323 0 : 793 => Opcode::tSUBSi8,
5324 0 : 794 => Opcode::tSUBSrr,
5325 0 : 795 => Opcode::tTAILJMPd,
5326 0 : 796 => Opcode::tTAILJMPdND,
5327 0 : 797 => Opcode::tTAILJMPr,
5328 0 : 798 => Opcode::tTBB_JT,
5329 0 : 799 => Opcode::tTBH_JT,
5330 0 : 800 => Opcode::tTPsoft,
5331 0 : 801 => Opcode::ADCri,
5332 0 : 802 => Opcode::ADCrr,
5333 0 : 803 => Opcode::ADCrsi,
5334 0 : 804 => Opcode::ADCrsr,
5335 0 : 805 => Opcode::ADDri,
5336 0 : 806 => Opcode::ADDrr,
5337 0 : 807 => Opcode::ADDrsi,
5338 0 : 808 => Opcode::ADDrsr,
5339 0 : 809 => Opcode::ADR,
5340 0 : 810 => Opcode::AESD,
5341 0 : 811 => Opcode::AESE,
5342 0 : 812 => Opcode::AESIMC,
5343 0 : 813 => Opcode::AESMC,
5344 0 : 814 => Opcode::ANDri,
5345 0 : 815 => Opcode::ANDrr,
5346 0 : 816 => Opcode::ANDrsi,
5347 0 : 817 => Opcode::ANDrsr,
5348 0 : 818 => Opcode::BF16VDOTI_VDOTD,
5349 0 : 819 => Opcode::BF16VDOTI_VDOTQ,
5350 0 : 820 => Opcode::BF16VDOTS_VDOTD,
5351 0 : 821 => Opcode::BF16VDOTS_VDOTQ,
5352 0 : 822 => Opcode::BF16_VCVT,
5353 0 : 823 => Opcode::BF16_VCVTB,
5354 0 : 824 => Opcode::BF16_VCVTT,
5355 0 : 825 => Opcode::BFC,
5356 0 : 826 => Opcode::BFI,
5357 0 : 827 => Opcode::BICri,
5358 0 : 828 => Opcode::BICrr,
5359 0 : 829 => Opcode::BICrsi,
5360 0 : 830 => Opcode::BICrsr,
5361 0 : 831 => Opcode::BKPT,
5362 0 : 832 => Opcode::BL,
5363 0 : 833 => Opcode::BLX,
5364 0 : 834 => Opcode::BLX_pred,
5365 0 : 835 => Opcode::BLXi,
5366 0 : 836 => Opcode::BL_pred,
5367 0 : 837 => Opcode::BX,
5368 0 : 838 => Opcode::BXJ,
5369 0 : 839 => Opcode::BX_RET,
5370 0 : 840 => Opcode::BX_pred,
5371 0 : 841 => Opcode::Bcc,
5372 0 : 842 => Opcode::CDE_CX1,
5373 0 : 843 => Opcode::CDE_CX1A,
5374 0 : 844 => Opcode::CDE_CX1D,
5375 0 : 845 => Opcode::CDE_CX1DA,
5376 0 : 846 => Opcode::CDE_CX2,
5377 0 : 847 => Opcode::CDE_CX2A,
5378 0 : 848 => Opcode::CDE_CX2D,
5379 0 : 849 => Opcode::CDE_CX2DA,
5380 0 : 850 => Opcode::CDE_CX3,
5381 0 : 851 => Opcode::CDE_CX3A,
5382 0 : 852 => Opcode::CDE_CX3D,
5383 0 : 853 => Opcode::CDE_CX3DA,
5384 0 : 854 => Opcode::CDE_VCX1A_fpdp,
5385 0 : 855 => Opcode::CDE_VCX1A_fpsp,
5386 0 : 856 => Opcode::CDE_VCX1A_vec,
5387 0 : 857 => Opcode::CDE_VCX1_fpdp,
5388 0 : 858 => Opcode::CDE_VCX1_fpsp,
5389 0 : 859 => Opcode::CDE_VCX1_vec,
5390 0 : 860 => Opcode::CDE_VCX2A_fpdp,
5391 0 : 861 => Opcode::CDE_VCX2A_fpsp,
5392 0 : 862 => Opcode::CDE_VCX2A_vec,
5393 0 : 863 => Opcode::CDE_VCX2_fpdp,
5394 0 : 864 => Opcode::CDE_VCX2_fpsp,
5395 0 : 865 => Opcode::CDE_VCX2_vec,
5396 0 : 866 => Opcode::CDE_VCX3A_fpdp,
5397 0 : 867 => Opcode::CDE_VCX3A_fpsp,
5398 0 : 868 => Opcode::CDE_VCX3A_vec,
5399 0 : 869 => Opcode::CDE_VCX3_fpdp,
5400 0 : 870 => Opcode::CDE_VCX3_fpsp,
5401 0 : 871 => Opcode::CDE_VCX3_vec,
5402 0 : 872 => Opcode::CDP,
5403 0 : 873 => Opcode::CDP2,
5404 0 : 874 => Opcode::CLREX,
5405 0 : 875 => Opcode::CLZ,
5406 0 : 876 => Opcode::CMNri,
5407 0 : 877 => Opcode::CMNzrr,
5408 0 : 878 => Opcode::CMNzrsi,
5409 0 : 879 => Opcode::CMNzrsr,
5410 0 : 880 => Opcode::CMPri,
5411 0 : 881 => Opcode::CMPrr,
5412 0 : 882 => Opcode::CMPrsi,
5413 0 : 883 => Opcode::CMPrsr,
5414 0 : 884 => Opcode::CPS1p,
5415 0 : 885 => Opcode::CPS2p,
5416 0 : 886 => Opcode::CPS3p,
5417 0 : 887 => Opcode::CRC32B,
5418 0 : 888 => Opcode::CRC32CB,
5419 0 : 889 => Opcode::CRC32CH,
5420 0 : 890 => Opcode::CRC32CW,
5421 0 : 891 => Opcode::CRC32H,
5422 0 : 892 => Opcode::CRC32W,
5423 0 : 893 => Opcode::DBG,
5424 0 : 894 => Opcode::DMB,
5425 0 : 895 => Opcode::DSB,
5426 0 : 896 => Opcode::EORri,
5427 0 : 897 => Opcode::EORrr,
5428 0 : 898 => Opcode::EORrsi,
5429 0 : 899 => Opcode::EORrsr,
5430 0 : 900 => Opcode::ERET,
5431 0 : 901 => Opcode::FCONSTD,
5432 0 : 902 => Opcode::FCONSTH,
5433 0 : 903 => Opcode::FCONSTS,
5434 0 : 904 => Opcode::FLDMXDB_UPD,
5435 0 : 905 => Opcode::FLDMXIA,
5436 0 : 906 => Opcode::FLDMXIA_UPD,
5437 0 : 907 => Opcode::FMSTAT,
5438 0 : 908 => Opcode::FSTMXDB_UPD,
5439 0 : 909 => Opcode::FSTMXIA,
5440 0 : 910 => Opcode::FSTMXIA_UPD,
5441 0 : 911 => Opcode::HINT,
5442 0 : 912 => Opcode::HLT,
5443 0 : 913 => Opcode::HVC,
5444 0 : 914 => Opcode::ISB,
5445 0 : 915 => Opcode::LDA,
5446 0 : 916 => Opcode::LDAB,
5447 0 : 917 => Opcode::LDAEX,
5448 0 : 918 => Opcode::LDAEXB,
5449 0 : 919 => Opcode::LDAEXD,
5450 0 : 920 => Opcode::LDAEXH,
5451 0 : 921 => Opcode::LDAH,
5452 0 : 922 => Opcode::LDC2L_OFFSET,
5453 0 : 923 => Opcode::LDC2L_OPTION,
5454 0 : 924 => Opcode::LDC2L_POST,
5455 0 : 925 => Opcode::LDC2L_PRE,
5456 0 : 926 => Opcode::LDC2_OFFSET,
5457 0 : 927 => Opcode::LDC2_OPTION,
5458 0 : 928 => Opcode::LDC2_POST,
5459 0 : 929 => Opcode::LDC2_PRE,
5460 0 : 930 => Opcode::LDCL_OFFSET,
5461 0 : 931 => Opcode::LDCL_OPTION,
5462 0 : 932 => Opcode::LDCL_POST,
5463 0 : 933 => Opcode::LDCL_PRE,
5464 0 : 934 => Opcode::LDC_OFFSET,
5465 0 : 935 => Opcode::LDC_OPTION,
5466 0 : 936 => Opcode::LDC_POST,
5467 0 : 937 => Opcode::LDC_PRE,
5468 0 : 938 => Opcode::LDMDA,
5469 0 : 939 => Opcode::LDMDA_UPD,
5470 0 : 940 => Opcode::LDMDB,
5471 0 : 941 => Opcode::LDMDB_UPD,
5472 0 : 942 => Opcode::LDMIA,
5473 0 : 943 => Opcode::LDMIA_UPD,
5474 0 : 944 => Opcode::LDMIB,
5475 0 : 945 => Opcode::LDMIB_UPD,
5476 0 : 946 => Opcode::LDRBT_POST_IMM,
5477 0 : 947 => Opcode::LDRBT_POST_REG,
5478 0 : 948 => Opcode::LDRB_POST_IMM,
5479 0 : 949 => Opcode::LDRB_POST_REG,
5480 0 : 950 => Opcode::LDRB_PRE_IMM,
5481 0 : 951 => Opcode::LDRB_PRE_REG,
5482 0 : 952 => Opcode::LDRBi12,
5483 0 : 953 => Opcode::LDRBrs,
5484 0 : 954 => Opcode::LDRD,
5485 0 : 955 => Opcode::LDRD_POST,
5486 0 : 956 => Opcode::LDRD_PRE,
5487 0 : 957 => Opcode::LDREX,
5488 0 : 958 => Opcode::LDREXB,
5489 0 : 959 => Opcode::LDREXD,
5490 0 : 960 => Opcode::LDREXH,
5491 0 : 961 => Opcode::LDRH,
5492 0 : 962 => Opcode::LDRHTi,
5493 0 : 963 => Opcode::LDRHTr,
5494 0 : 964 => Opcode::LDRH_POST,
5495 0 : 965 => Opcode::LDRH_PRE,
5496 0 : 966 => Opcode::LDRSB,
5497 0 : 967 => Opcode::LDRSBTi,
5498 0 : 968 => Opcode::LDRSBTr,
5499 0 : 969 => Opcode::LDRSB_POST,
5500 0 : 970 => Opcode::LDRSB_PRE,
5501 0 : 971 => Opcode::LDRSH,
5502 0 : 972 => Opcode::LDRSHTi,
5503 0 : 973 => Opcode::LDRSHTr,
5504 0 : 974 => Opcode::LDRSH_POST,
5505 0 : 975 => Opcode::LDRSH_PRE,
5506 0 : 976 => Opcode::LDRT_POST_IMM,
5507 0 : 977 => Opcode::LDRT_POST_REG,
5508 0 : 978 => Opcode::LDR_POST_IMM,
5509 0 : 979 => Opcode::LDR_POST_REG,
5510 0 : 980 => Opcode::LDR_PRE_IMM,
5511 0 : 981 => Opcode::LDR_PRE_REG,
5512 0 : 982 => Opcode::LDRcp,
5513 0 : 983 => Opcode::LDRi12,
5514 0 : 984 => Opcode::LDRrs,
5515 0 : 985 => Opcode::MCR,
5516 0 : 986 => Opcode::MCR2,
5517 0 : 987 => Opcode::MCRR,
5518 0 : 988 => Opcode::MCRR2,
5519 0 : 989 => Opcode::MLA,
5520 0 : 990 => Opcode::MLS,
5521 0 : 991 => Opcode::MOVPCLR,
5522 0 : 992 => Opcode::MOVTi16,
5523 0 : 993 => Opcode::MOVi,
5524 0 : 994 => Opcode::MOVi16,
5525 0 : 995 => Opcode::MOVr,
5526 0 : 996 => Opcode::MOVr_TC,
5527 0 : 997 => Opcode::MOVsi,
5528 0 : 998 => Opcode::MOVsr,
5529 0 : 999 => Opcode::MRC,
5530 0 : 1000 => Opcode::MRC2,
5531 0 : 1001 => Opcode::MRRC,
5532 0 : 1002 => Opcode::MRRC2,
5533 0 : 1003 => Opcode::MRS,
5534 0 : 1004 => Opcode::MRSbanked,
5535 0 : 1005 => Opcode::MRSsys,
5536 0 : 1006 => Opcode::MSR,
5537 0 : 1007 => Opcode::MSRbanked,
5538 0 : 1008 => Opcode::MSRi,
5539 0 : 1009 => Opcode::MUL,
5540 0 : 1010 => Opcode::MVE_ASRLi,
5541 0 : 1011 => Opcode::MVE_ASRLr,
5542 0 : 1012 => Opcode::MVE_DLSTP_16,
5543 0 : 1013 => Opcode::MVE_DLSTP_32,
5544 0 : 1014 => Opcode::MVE_DLSTP_64,
5545 0 : 1015 => Opcode::MVE_DLSTP_8,
5546 0 : 1016 => Opcode::MVE_LCTP,
5547 0 : 1017 => Opcode::MVE_LETP,
5548 0 : 1018 => Opcode::MVE_LSLLi,
5549 0 : 1019 => Opcode::MVE_LSLLr,
5550 0 : 1020 => Opcode::MVE_LSRL,
5551 0 : 1021 => Opcode::MVE_SQRSHR,
5552 0 : 1022 => Opcode::MVE_SQRSHRL,
5553 0 : 1023 => Opcode::MVE_SQSHL,
5554 0 : 1024 => Opcode::MVE_SQSHLL,
5555 0 : 1025 => Opcode::MVE_SRSHR,
5556 0 : 1026 => Opcode::MVE_SRSHRL,
5557 0 : 1027 => Opcode::MVE_UQRSHL,
5558 0 : 1028 => Opcode::MVE_UQRSHLL,
5559 0 : 1029 => Opcode::MVE_UQSHL,
5560 0 : 1030 => Opcode::MVE_UQSHLL,
5561 0 : 1031 => Opcode::MVE_URSHR,
5562 0 : 1032 => Opcode::MVE_URSHRL,
5563 0 : 1033 => Opcode::MVE_VABAVs16,
5564 0 : 1034 => Opcode::MVE_VABAVs32,
5565 0 : 1035 => Opcode::MVE_VABAVs8,
5566 0 : 1036 => Opcode::MVE_VABAVu16,
5567 0 : 1037 => Opcode::MVE_VABAVu32,
5568 0 : 1038 => Opcode::MVE_VABAVu8,
5569 0 : 1039 => Opcode::MVE_VABDf16,
5570 0 : 1040 => Opcode::MVE_VABDf32,
5571 0 : 1041 => Opcode::MVE_VABDs16,
5572 0 : 1042 => Opcode::MVE_VABDs32,
5573 0 : 1043 => Opcode::MVE_VABDs8,
5574 0 : 1044 => Opcode::MVE_VABDu16,
5575 0 : 1045 => Opcode::MVE_VABDu32,
5576 0 : 1046 => Opcode::MVE_VABDu8,
5577 0 : 1047 => Opcode::MVE_VABSf16,
5578 0 : 1048 => Opcode::MVE_VABSf32,
5579 0 : 1049 => Opcode::MVE_VABSs16,
5580 0 : 1050 => Opcode::MVE_VABSs32,
5581 0 : 1051 => Opcode::MVE_VABSs8,
5582 0 : 1052 => Opcode::MVE_VADC,
5583 0 : 1053 => Opcode::MVE_VADCI,
5584 0 : 1054 => Opcode::MVE_VADDLVs32acc,
5585 0 : 1055 => Opcode::MVE_VADDLVs32no_acc,
5586 0 : 1056 => Opcode::MVE_VADDLVu32acc,
5587 0 : 1057 => Opcode::MVE_VADDLVu32no_acc,
5588 0 : 1058 => Opcode::MVE_VADDVs16acc,
5589 0 : 1059 => Opcode::MVE_VADDVs16no_acc,
5590 0 : 1060 => Opcode::MVE_VADDVs32acc,
5591 0 : 1061 => Opcode::MVE_VADDVs32no_acc,
5592 0 : 1062 => Opcode::MVE_VADDVs8acc,
5593 0 : 1063 => Opcode::MVE_VADDVs8no_acc,
5594 0 : 1064 => Opcode::MVE_VADDVu16acc,
5595 0 : 1065 => Opcode::MVE_VADDVu16no_acc,
5596 0 : 1066 => Opcode::MVE_VADDVu32acc,
5597 0 : 1067 => Opcode::MVE_VADDVu32no_acc,
5598 0 : 1068 => Opcode::MVE_VADDVu8acc,
5599 0 : 1069 => Opcode::MVE_VADDVu8no_acc,
5600 0 : 1070 => Opcode::MVE_VADD_qr_f16,
5601 0 : 1071 => Opcode::MVE_VADD_qr_f32,
5602 0 : 1072 => Opcode::MVE_VADD_qr_i16,
5603 0 : 1073 => Opcode::MVE_VADD_qr_i32,
5604 0 : 1074 => Opcode::MVE_VADD_qr_i8,
5605 0 : 1075 => Opcode::MVE_VADDf16,
5606 0 : 1076 => Opcode::MVE_VADDf32,
5607 0 : 1077 => Opcode::MVE_VADDi16,
5608 0 : 1078 => Opcode::MVE_VADDi32,
5609 0 : 1079 => Opcode::MVE_VADDi8,
5610 0 : 1080 => Opcode::MVE_VAND,
5611 0 : 1081 => Opcode::MVE_VBIC,
5612 0 : 1082 => Opcode::MVE_VBICimmi16,
5613 0 : 1083 => Opcode::MVE_VBICimmi32,
5614 0 : 1084 => Opcode::MVE_VBRSR16,
5615 0 : 1085 => Opcode::MVE_VBRSR32,
5616 0 : 1086 => Opcode::MVE_VBRSR8,
5617 0 : 1087 => Opcode::MVE_VCADDf16,
5618 0 : 1088 => Opcode::MVE_VCADDf32,
5619 0 : 1089 => Opcode::MVE_VCADDi16,
5620 0 : 1090 => Opcode::MVE_VCADDi32,
5621 0 : 1091 => Opcode::MVE_VCADDi8,
5622 0 : 1092 => Opcode::MVE_VCLSs16,
5623 0 : 1093 => Opcode::MVE_VCLSs32,
5624 0 : 1094 => Opcode::MVE_VCLSs8,
5625 0 : 1095 => Opcode::MVE_VCLZs16,
5626 0 : 1096 => Opcode::MVE_VCLZs32,
5627 0 : 1097 => Opcode::MVE_VCLZs8,
5628 0 : 1098 => Opcode::MVE_VCMLAf16,
5629 0 : 1099 => Opcode::MVE_VCMLAf32,
5630 0 : 1100 => Opcode::MVE_VCMPf16,
5631 0 : 1101 => Opcode::MVE_VCMPf16r,
5632 0 : 1102 => Opcode::MVE_VCMPf32,
5633 0 : 1103 => Opcode::MVE_VCMPf32r,
5634 0 : 1104 => Opcode::MVE_VCMPi16,
5635 0 : 1105 => Opcode::MVE_VCMPi16r,
5636 0 : 1106 => Opcode::MVE_VCMPi32,
5637 0 : 1107 => Opcode::MVE_VCMPi32r,
5638 0 : 1108 => Opcode::MVE_VCMPi8,
5639 0 : 1109 => Opcode::MVE_VCMPi8r,
5640 0 : 1110 => Opcode::MVE_VCMPs16,
5641 0 : 1111 => Opcode::MVE_VCMPs16r,
5642 0 : 1112 => Opcode::MVE_VCMPs32,
5643 0 : 1113 => Opcode::MVE_VCMPs32r,
5644 0 : 1114 => Opcode::MVE_VCMPs8,
5645 0 : 1115 => Opcode::MVE_VCMPs8r,
5646 0 : 1116 => Opcode::MVE_VCMPu16,
5647 0 : 1117 => Opcode::MVE_VCMPu16r,
5648 0 : 1118 => Opcode::MVE_VCMPu32,
5649 0 : 1119 => Opcode::MVE_VCMPu32r,
5650 0 : 1120 => Opcode::MVE_VCMPu8,
5651 0 : 1121 => Opcode::MVE_VCMPu8r,
5652 0 : 1122 => Opcode::MVE_VCMULf16,
5653 0 : 1123 => Opcode::MVE_VCMULf32,
5654 0 : 1124 => Opcode::MVE_VCTP16,
5655 0 : 1125 => Opcode::MVE_VCTP32,
5656 0 : 1126 => Opcode::MVE_VCTP64,
5657 0 : 1127 => Opcode::MVE_VCTP8,
5658 0 : 1128 => Opcode::MVE_VCVTf16f32bh,
5659 0 : 1129 => Opcode::MVE_VCVTf16f32th,
5660 0 : 1130 => Opcode::MVE_VCVTf16s16_fix,
5661 0 : 1131 => Opcode::MVE_VCVTf16s16n,
5662 0 : 1132 => Opcode::MVE_VCVTf16u16_fix,
5663 0 : 1133 => Opcode::MVE_VCVTf16u16n,
5664 0 : 1134 => Opcode::MVE_VCVTf32f16bh,
5665 0 : 1135 => Opcode::MVE_VCVTf32f16th,
5666 0 : 1136 => Opcode::MVE_VCVTf32s32_fix,
5667 0 : 1137 => Opcode::MVE_VCVTf32s32n,
5668 0 : 1138 => Opcode::MVE_VCVTf32u32_fix,
5669 0 : 1139 => Opcode::MVE_VCVTf32u32n,
5670 0 : 1140 => Opcode::MVE_VCVTs16f16_fix,
5671 0 : 1141 => Opcode::MVE_VCVTs16f16a,
5672 0 : 1142 => Opcode::MVE_VCVTs16f16m,
5673 0 : 1143 => Opcode::MVE_VCVTs16f16n,
5674 0 : 1144 => Opcode::MVE_VCVTs16f16p,
5675 0 : 1145 => Opcode::MVE_VCVTs16f16z,
5676 0 : 1146 => Opcode::MVE_VCVTs32f32_fix,
5677 0 : 1147 => Opcode::MVE_VCVTs32f32a,
5678 0 : 1148 => Opcode::MVE_VCVTs32f32m,
5679 0 : 1149 => Opcode::MVE_VCVTs32f32n,
5680 0 : 1150 => Opcode::MVE_VCVTs32f32p,
5681 0 : 1151 => Opcode::MVE_VCVTs32f32z,
5682 0 : 1152 => Opcode::MVE_VCVTu16f16_fix,
5683 0 : 1153 => Opcode::MVE_VCVTu16f16a,
5684 0 : 1154 => Opcode::MVE_VCVTu16f16m,
5685 0 : 1155 => Opcode::MVE_VCVTu16f16n,
5686 0 : 1156 => Opcode::MVE_VCVTu16f16p,
5687 0 : 1157 => Opcode::MVE_VCVTu16f16z,
5688 0 : 1158 => Opcode::MVE_VCVTu32f32_fix,
5689 0 : 1159 => Opcode::MVE_VCVTu32f32a,
5690 0 : 1160 => Opcode::MVE_VCVTu32f32m,
5691 0 : 1161 => Opcode::MVE_VCVTu32f32n,
5692 0 : 1162 => Opcode::MVE_VCVTu32f32p,
5693 0 : 1163 => Opcode::MVE_VCVTu32f32z,
5694 0 : 1164 => Opcode::MVE_VDDUPu16,
5695 0 : 1165 => Opcode::MVE_VDDUPu32,
5696 0 : 1166 => Opcode::MVE_VDDUPu8,
5697 0 : 1167 => Opcode::MVE_VDUP16,
5698 0 : 1168 => Opcode::MVE_VDUP32,
5699 0 : 1169 => Opcode::MVE_VDUP8,
5700 0 : 1170 => Opcode::MVE_VDWDUPu16,
5701 0 : 1171 => Opcode::MVE_VDWDUPu32,
5702 0 : 1172 => Opcode::MVE_VDWDUPu8,
5703 0 : 1173 => Opcode::MVE_VEOR,
5704 0 : 1174 => Opcode::MVE_VFMA_qr_Sf16,
5705 0 : 1175 => Opcode::MVE_VFMA_qr_Sf32,
5706 0 : 1176 => Opcode::MVE_VFMA_qr_f16,
5707 0 : 1177 => Opcode::MVE_VFMA_qr_f32,
5708 0 : 1178 => Opcode::MVE_VFMAf16,
5709 0 : 1179 => Opcode::MVE_VFMAf32,
5710 0 : 1180 => Opcode::MVE_VFMSf16,
5711 0 : 1181 => Opcode::MVE_VFMSf32,
5712 0 : 1182 => Opcode::MVE_VHADD_qr_s16,
5713 0 : 1183 => Opcode::MVE_VHADD_qr_s32,
5714 0 : 1184 => Opcode::MVE_VHADD_qr_s8,
5715 0 : 1185 => Opcode::MVE_VHADD_qr_u16,
5716 0 : 1186 => Opcode::MVE_VHADD_qr_u32,
5717 0 : 1187 => Opcode::MVE_VHADD_qr_u8,
5718 0 : 1188 => Opcode::MVE_VHADDs16,
5719 0 : 1189 => Opcode::MVE_VHADDs32,
5720 0 : 1190 => Opcode::MVE_VHADDs8,
5721 0 : 1191 => Opcode::MVE_VHADDu16,
5722 0 : 1192 => Opcode::MVE_VHADDu32,
5723 0 : 1193 => Opcode::MVE_VHADDu8,
5724 0 : 1194 => Opcode::MVE_VHCADDs16,
5725 0 : 1195 => Opcode::MVE_VHCADDs32,
5726 0 : 1196 => Opcode::MVE_VHCADDs8,
5727 0 : 1197 => Opcode::MVE_VHSUB_qr_s16,
5728 0 : 1198 => Opcode::MVE_VHSUB_qr_s32,
5729 0 : 1199 => Opcode::MVE_VHSUB_qr_s8,
5730 0 : 1200 => Opcode::MVE_VHSUB_qr_u16,
5731 0 : 1201 => Opcode::MVE_VHSUB_qr_u32,
5732 0 : 1202 => Opcode::MVE_VHSUB_qr_u8,
5733 0 : 1203 => Opcode::MVE_VHSUBs16,
5734 0 : 1204 => Opcode::MVE_VHSUBs32,
5735 0 : 1205 => Opcode::MVE_VHSUBs8,
5736 0 : 1206 => Opcode::MVE_VHSUBu16,
5737 0 : 1207 => Opcode::MVE_VHSUBu32,
5738 0 : 1208 => Opcode::MVE_VHSUBu8,
5739 0 : 1209 => Opcode::MVE_VIDUPu16,
5740 0 : 1210 => Opcode::MVE_VIDUPu32,
5741 0 : 1211 => Opcode::MVE_VIDUPu8,
5742 0 : 1212 => Opcode::MVE_VIWDUPu16,
5743 0 : 1213 => Opcode::MVE_VIWDUPu32,
5744 0 : 1214 => Opcode::MVE_VIWDUPu8,
5745 0 : 1215 => Opcode::MVE_VLD20_16,
5746 0 : 1216 => Opcode::MVE_VLD20_16_wb,
5747 0 : 1217 => Opcode::MVE_VLD20_32,
5748 0 : 1218 => Opcode::MVE_VLD20_32_wb,
5749 0 : 1219 => Opcode::MVE_VLD20_8,
5750 0 : 1220 => Opcode::MVE_VLD20_8_wb,
5751 0 : 1221 => Opcode::MVE_VLD21_16,
5752 0 : 1222 => Opcode::MVE_VLD21_16_wb,
5753 0 : 1223 => Opcode::MVE_VLD21_32,
5754 0 : 1224 => Opcode::MVE_VLD21_32_wb,
5755 0 : 1225 => Opcode::MVE_VLD21_8,
5756 0 : 1226 => Opcode::MVE_VLD21_8_wb,
5757 0 : 1227 => Opcode::MVE_VLD40_16,
5758 0 : 1228 => Opcode::MVE_VLD40_16_wb,
5759 0 : 1229 => Opcode::MVE_VLD40_32,
5760 0 : 1230 => Opcode::MVE_VLD40_32_wb,
5761 0 : 1231 => Opcode::MVE_VLD40_8,
5762 0 : 1232 => Opcode::MVE_VLD40_8_wb,
5763 0 : 1233 => Opcode::MVE_VLD41_16,
5764 0 : 1234 => Opcode::MVE_VLD41_16_wb,
5765 0 : 1235 => Opcode::MVE_VLD41_32,
5766 0 : 1236 => Opcode::MVE_VLD41_32_wb,
5767 0 : 1237 => Opcode::MVE_VLD41_8,
5768 0 : 1238 => Opcode::MVE_VLD41_8_wb,
5769 0 : 1239 => Opcode::MVE_VLD42_16,
5770 0 : 1240 => Opcode::MVE_VLD42_16_wb,
5771 0 : 1241 => Opcode::MVE_VLD42_32,
5772 0 : 1242 => Opcode::MVE_VLD42_32_wb,
5773 0 : 1243 => Opcode::MVE_VLD42_8,
5774 0 : 1244 => Opcode::MVE_VLD42_8_wb,
5775 0 : 1245 => Opcode::MVE_VLD43_16,
5776 0 : 1246 => Opcode::MVE_VLD43_16_wb,
5777 0 : 1247 => Opcode::MVE_VLD43_32,
5778 0 : 1248 => Opcode::MVE_VLD43_32_wb,
5779 0 : 1249 => Opcode::MVE_VLD43_8,
5780 0 : 1250 => Opcode::MVE_VLD43_8_wb,
5781 0 : 1251 => Opcode::MVE_VLDRBS16,
5782 0 : 1252 => Opcode::MVE_VLDRBS16_post,
5783 0 : 1253 => Opcode::MVE_VLDRBS16_pre,
5784 0 : 1254 => Opcode::MVE_VLDRBS16_rq,
5785 0 : 1255 => Opcode::MVE_VLDRBS32,
5786 0 : 1256 => Opcode::MVE_VLDRBS32_post,
5787 0 : 1257 => Opcode::MVE_VLDRBS32_pre,
5788 0 : 1258 => Opcode::MVE_VLDRBS32_rq,
5789 0 : 1259 => Opcode::MVE_VLDRBU16,
5790 0 : 1260 => Opcode::MVE_VLDRBU16_post,
5791 0 : 1261 => Opcode::MVE_VLDRBU16_pre,
5792 0 : 1262 => Opcode::MVE_VLDRBU16_rq,
5793 0 : 1263 => Opcode::MVE_VLDRBU32,
5794 0 : 1264 => Opcode::MVE_VLDRBU32_post,
5795 0 : 1265 => Opcode::MVE_VLDRBU32_pre,
5796 0 : 1266 => Opcode::MVE_VLDRBU32_rq,
5797 0 : 1267 => Opcode::MVE_VLDRBU8,
5798 0 : 1268 => Opcode::MVE_VLDRBU8_post,
5799 0 : 1269 => Opcode::MVE_VLDRBU8_pre,
5800 0 : 1270 => Opcode::MVE_VLDRBU8_rq,
5801 0 : 1271 => Opcode::MVE_VLDRDU64_qi,
5802 0 : 1272 => Opcode::MVE_VLDRDU64_qi_pre,
5803 0 : 1273 => Opcode::MVE_VLDRDU64_rq,
5804 0 : 1274 => Opcode::MVE_VLDRDU64_rq_u,
5805 0 : 1275 => Opcode::MVE_VLDRHS32,
5806 0 : 1276 => Opcode::MVE_VLDRHS32_post,
5807 0 : 1277 => Opcode::MVE_VLDRHS32_pre,
5808 0 : 1278 => Opcode::MVE_VLDRHS32_rq,
5809 0 : 1279 => Opcode::MVE_VLDRHS32_rq_u,
5810 0 : 1280 => Opcode::MVE_VLDRHU16,
5811 0 : 1281 => Opcode::MVE_VLDRHU16_post,
5812 0 : 1282 => Opcode::MVE_VLDRHU16_pre,
5813 0 : 1283 => Opcode::MVE_VLDRHU16_rq,
5814 0 : 1284 => Opcode::MVE_VLDRHU16_rq_u,
5815 0 : 1285 => Opcode::MVE_VLDRHU32,
5816 0 : 1286 => Opcode::MVE_VLDRHU32_post,
5817 0 : 1287 => Opcode::MVE_VLDRHU32_pre,
5818 0 : 1288 => Opcode::MVE_VLDRHU32_rq,
5819 0 : 1289 => Opcode::MVE_VLDRHU32_rq_u,
5820 0 : 1290 => Opcode::MVE_VLDRWU32,
5821 0 : 1291 => Opcode::MVE_VLDRWU32_post,
5822 0 : 1292 => Opcode::MVE_VLDRWU32_pre,
5823 0 : 1293 => Opcode::MVE_VLDRWU32_qi,
5824 0 : 1294 => Opcode::MVE_VLDRWU32_qi_pre,
5825 0 : 1295 => Opcode::MVE_VLDRWU32_rq,
5826 0 : 1296 => Opcode::MVE_VLDRWU32_rq_u,
5827 0 : 1297 => Opcode::MVE_VMAXAVs16,
5828 0 : 1298 => Opcode::MVE_VMAXAVs32,
5829 0 : 1299 => Opcode::MVE_VMAXAVs8,
5830 0 : 1300 => Opcode::MVE_VMAXAs16,
5831 0 : 1301 => Opcode::MVE_VMAXAs32,
5832 0 : 1302 => Opcode::MVE_VMAXAs8,
5833 0 : 1303 => Opcode::MVE_VMAXNMAVf16,
5834 0 : 1304 => Opcode::MVE_VMAXNMAVf32,
5835 0 : 1305 => Opcode::MVE_VMAXNMAf16,
5836 0 : 1306 => Opcode::MVE_VMAXNMAf32,
5837 0 : 1307 => Opcode::MVE_VMAXNMVf16,
5838 0 : 1308 => Opcode::MVE_VMAXNMVf32,
5839 0 : 1309 => Opcode::MVE_VMAXNMf16,
5840 0 : 1310 => Opcode::MVE_VMAXNMf32,
5841 0 : 1311 => Opcode::MVE_VMAXVs16,
5842 0 : 1312 => Opcode::MVE_VMAXVs32,
5843 0 : 1313 => Opcode::MVE_VMAXVs8,
5844 0 : 1314 => Opcode::MVE_VMAXVu16,
5845 0 : 1315 => Opcode::MVE_VMAXVu32,
5846 0 : 1316 => Opcode::MVE_VMAXVu8,
5847 0 : 1317 => Opcode::MVE_VMAXs16,
5848 0 : 1318 => Opcode::MVE_VMAXs32,
5849 0 : 1319 => Opcode::MVE_VMAXs8,
5850 0 : 1320 => Opcode::MVE_VMAXu16,
5851 0 : 1321 => Opcode::MVE_VMAXu32,
5852 0 : 1322 => Opcode::MVE_VMAXu8,
5853 0 : 1323 => Opcode::MVE_VMINAVs16,
5854 0 : 1324 => Opcode::MVE_VMINAVs32,
5855 0 : 1325 => Opcode::MVE_VMINAVs8,
5856 0 : 1326 => Opcode::MVE_VMINAs16,
5857 0 : 1327 => Opcode::MVE_VMINAs32,
5858 0 : 1328 => Opcode::MVE_VMINAs8,
5859 0 : 1329 => Opcode::MVE_VMINNMAVf16,
5860 0 : 1330 => Opcode::MVE_VMINNMAVf32,
5861 0 : 1331 => Opcode::MVE_VMINNMAf16,
5862 0 : 1332 => Opcode::MVE_VMINNMAf32,
5863 0 : 1333 => Opcode::MVE_VMINNMVf16,
5864 0 : 1334 => Opcode::MVE_VMINNMVf32,
5865 0 : 1335 => Opcode::MVE_VMINNMf16,
5866 0 : 1336 => Opcode::MVE_VMINNMf32,
5867 0 : 1337 => Opcode::MVE_VMINVs16,
5868 0 : 1338 => Opcode::MVE_VMINVs32,
5869 0 : 1339 => Opcode::MVE_VMINVs8,
5870 0 : 1340 => Opcode::MVE_VMINVu16,
5871 0 : 1341 => Opcode::MVE_VMINVu32,
5872 0 : 1342 => Opcode::MVE_VMINVu8,
5873 0 : 1343 => Opcode::MVE_VMINs16,
5874 0 : 1344 => Opcode::MVE_VMINs32,
5875 0 : 1345 => Opcode::MVE_VMINs8,
5876 0 : 1346 => Opcode::MVE_VMINu16,
5877 0 : 1347 => Opcode::MVE_VMINu32,
5878 0 : 1348 => Opcode::MVE_VMINu8,
5879 0 : 1349 => Opcode::MVE_VMLADAVas16,
5880 0 : 1350 => Opcode::MVE_VMLADAVas32,
5881 0 : 1351 => Opcode::MVE_VMLADAVas8,
5882 0 : 1352 => Opcode::MVE_VMLADAVau16,
5883 0 : 1353 => Opcode::MVE_VMLADAVau32,
5884 0 : 1354 => Opcode::MVE_VMLADAVau8,
5885 0 : 1355 => Opcode::MVE_VMLADAVaxs16,
5886 0 : 1356 => Opcode::MVE_VMLADAVaxs32,
5887 0 : 1357 => Opcode::MVE_VMLADAVaxs8,
5888 0 : 1358 => Opcode::MVE_VMLADAVs16,
5889 0 : 1359 => Opcode::MVE_VMLADAVs32,
5890 0 : 1360 => Opcode::MVE_VMLADAVs8,
5891 0 : 1361 => Opcode::MVE_VMLADAVu16,
5892 0 : 1362 => Opcode::MVE_VMLADAVu32,
5893 0 : 1363 => Opcode::MVE_VMLADAVu8,
5894 0 : 1364 => Opcode::MVE_VMLADAVxs16,
5895 0 : 1365 => Opcode::MVE_VMLADAVxs32,
5896 0 : 1366 => Opcode::MVE_VMLADAVxs8,
5897 0 : 1367 => Opcode::MVE_VMLALDAVas16,
5898 0 : 1368 => Opcode::MVE_VMLALDAVas32,
5899 0 : 1369 => Opcode::MVE_VMLALDAVau16,
5900 0 : 1370 => Opcode::MVE_VMLALDAVau32,
5901 0 : 1371 => Opcode::MVE_VMLALDAVaxs16,
5902 0 : 1372 => Opcode::MVE_VMLALDAVaxs32,
5903 0 : 1373 => Opcode::MVE_VMLALDAVs16,
5904 0 : 1374 => Opcode::MVE_VMLALDAVs32,
5905 0 : 1375 => Opcode::MVE_VMLALDAVu16,
5906 0 : 1376 => Opcode::MVE_VMLALDAVu32,
5907 0 : 1377 => Opcode::MVE_VMLALDAVxs16,
5908 0 : 1378 => Opcode::MVE_VMLALDAVxs32,
5909 0 : 1379 => Opcode::MVE_VMLAS_qr_i16,
5910 0 : 1380 => Opcode::MVE_VMLAS_qr_i32,
5911 0 : 1381 => Opcode::MVE_VMLAS_qr_i8,
5912 0 : 1382 => Opcode::MVE_VMLA_qr_i16,
5913 0 : 1383 => Opcode::MVE_VMLA_qr_i32,
5914 0 : 1384 => Opcode::MVE_VMLA_qr_i8,
5915 0 : 1385 => Opcode::MVE_VMLSDAVas16,
5916 0 : 1386 => Opcode::MVE_VMLSDAVas32,
5917 0 : 1387 => Opcode::MVE_VMLSDAVas8,
5918 0 : 1388 => Opcode::MVE_VMLSDAVaxs16,
5919 0 : 1389 => Opcode::MVE_VMLSDAVaxs32,
5920 0 : 1390 => Opcode::MVE_VMLSDAVaxs8,
5921 0 : 1391 => Opcode::MVE_VMLSDAVs16,
5922 0 : 1392 => Opcode::MVE_VMLSDAVs32,
5923 0 : 1393 => Opcode::MVE_VMLSDAVs8,
5924 0 : 1394 => Opcode::MVE_VMLSDAVxs16,
5925 0 : 1395 => Opcode::MVE_VMLSDAVxs32,
5926 0 : 1396 => Opcode::MVE_VMLSDAVxs8,
5927 0 : 1397 => Opcode::MVE_VMLSLDAVas16,
5928 0 : 1398 => Opcode::MVE_VMLSLDAVas32,
5929 0 : 1399 => Opcode::MVE_VMLSLDAVaxs16,
5930 0 : 1400 => Opcode::MVE_VMLSLDAVaxs32,
5931 0 : 1401 => Opcode::MVE_VMLSLDAVs16,
5932 0 : 1402 => Opcode::MVE_VMLSLDAVs32,
5933 0 : 1403 => Opcode::MVE_VMLSLDAVxs16,
5934 0 : 1404 => Opcode::MVE_VMLSLDAVxs32,
5935 0 : 1405 => Opcode::MVE_VMOVLs16bh,
5936 0 : 1406 => Opcode::MVE_VMOVLs16th,
5937 0 : 1407 => Opcode::MVE_VMOVLs8bh,
5938 0 : 1408 => Opcode::MVE_VMOVLs8th,
5939 0 : 1409 => Opcode::MVE_VMOVLu16bh,
5940 0 : 1410 => Opcode::MVE_VMOVLu16th,
5941 0 : 1411 => Opcode::MVE_VMOVLu8bh,
5942 0 : 1412 => Opcode::MVE_VMOVLu8th,
5943 0 : 1413 => Opcode::MVE_VMOVNi16bh,
5944 0 : 1414 => Opcode::MVE_VMOVNi16th,
5945 0 : 1415 => Opcode::MVE_VMOVNi32bh,
5946 0 : 1416 => Opcode::MVE_VMOVNi32th,
5947 0 : 1417 => Opcode::MVE_VMOV_from_lane_32,
5948 0 : 1418 => Opcode::MVE_VMOV_from_lane_s16,
5949 0 : 1419 => Opcode::MVE_VMOV_from_lane_s8,
5950 0 : 1420 => Opcode::MVE_VMOV_from_lane_u16,
5951 0 : 1421 => Opcode::MVE_VMOV_from_lane_u8,
5952 0 : 1422 => Opcode::MVE_VMOV_q_rr,
5953 0 : 1423 => Opcode::MVE_VMOV_rr_q,
5954 0 : 1424 => Opcode::MVE_VMOV_to_lane_16,
5955 0 : 1425 => Opcode::MVE_VMOV_to_lane_32,
5956 0 : 1426 => Opcode::MVE_VMOV_to_lane_8,
5957 0 : 1427 => Opcode::MVE_VMOVimmf32,
5958 0 : 1428 => Opcode::MVE_VMOVimmi16,
5959 0 : 1429 => Opcode::MVE_VMOVimmi32,
5960 0 : 1430 => Opcode::MVE_VMOVimmi64,
5961 0 : 1431 => Opcode::MVE_VMOVimmi8,
5962 0 : 1432 => Opcode::MVE_VMULHs16,
5963 0 : 1433 => Opcode::MVE_VMULHs32,
5964 0 : 1434 => Opcode::MVE_VMULHs8,
5965 0 : 1435 => Opcode::MVE_VMULHu16,
5966 0 : 1436 => Opcode::MVE_VMULHu32,
5967 0 : 1437 => Opcode::MVE_VMULHu8,
5968 0 : 1438 => Opcode::MVE_VMULLBp16,
5969 0 : 1439 => Opcode::MVE_VMULLBp8,
5970 0 : 1440 => Opcode::MVE_VMULLBs16,
5971 0 : 1441 => Opcode::MVE_VMULLBs32,
5972 0 : 1442 => Opcode::MVE_VMULLBs8,
5973 0 : 1443 => Opcode::MVE_VMULLBu16,
5974 0 : 1444 => Opcode::MVE_VMULLBu32,
5975 0 : 1445 => Opcode::MVE_VMULLBu8,
5976 0 : 1446 => Opcode::MVE_VMULLTp16,
5977 0 : 1447 => Opcode::MVE_VMULLTp8,
5978 0 : 1448 => Opcode::MVE_VMULLTs16,
5979 0 : 1449 => Opcode::MVE_VMULLTs32,
5980 0 : 1450 => Opcode::MVE_VMULLTs8,
5981 0 : 1451 => Opcode::MVE_VMULLTu16,
5982 0 : 1452 => Opcode::MVE_VMULLTu32,
5983 0 : 1453 => Opcode::MVE_VMULLTu8,
5984 0 : 1454 => Opcode::MVE_VMUL_qr_f16,
5985 0 : 1455 => Opcode::MVE_VMUL_qr_f32,
5986 0 : 1456 => Opcode::MVE_VMUL_qr_i16,
5987 0 : 1457 => Opcode::MVE_VMUL_qr_i32,
5988 0 : 1458 => Opcode::MVE_VMUL_qr_i8,
5989 0 : 1459 => Opcode::MVE_VMULf16,
5990 0 : 1460 => Opcode::MVE_VMULf32,
5991 0 : 1461 => Opcode::MVE_VMULi16,
5992 0 : 1462 => Opcode::MVE_VMULi32,
5993 0 : 1463 => Opcode::MVE_VMULi8,
5994 0 : 1464 => Opcode::MVE_VMVN,
5995 0 : 1465 => Opcode::MVE_VMVNimmi16,
5996 0 : 1466 => Opcode::MVE_VMVNimmi32,
5997 0 : 1467 => Opcode::MVE_VNEGf16,
5998 0 : 1468 => Opcode::MVE_VNEGf32,
5999 0 : 1469 => Opcode::MVE_VNEGs16,
6000 0 : 1470 => Opcode::MVE_VNEGs32,
6001 0 : 1471 => Opcode::MVE_VNEGs8,
6002 0 : 1472 => Opcode::MVE_VORN,
6003 0 : 1473 => Opcode::MVE_VORR,
6004 0 : 1474 => Opcode::MVE_VORRimmi16,
6005 0 : 1475 => Opcode::MVE_VORRimmi32,
6006 0 : 1476 => Opcode::MVE_VPNOT,
6007 0 : 1477 => Opcode::MVE_VPSEL,
6008 0 : 1478 => Opcode::MVE_VPST,
6009 0 : 1479 => Opcode::MVE_VPTv16i8,
6010 0 : 1480 => Opcode::MVE_VPTv16i8r,
6011 0 : 1481 => Opcode::MVE_VPTv16s8,
6012 0 : 1482 => Opcode::MVE_VPTv16s8r,
6013 0 : 1483 => Opcode::MVE_VPTv16u8,
6014 0 : 1484 => Opcode::MVE_VPTv16u8r,
6015 0 : 1485 => Opcode::MVE_VPTv4f32,
6016 0 : 1486 => Opcode::MVE_VPTv4f32r,
6017 0 : 1487 => Opcode::MVE_VPTv4i32,
6018 0 : 1488 => Opcode::MVE_VPTv4i32r,
6019 0 : 1489 => Opcode::MVE_VPTv4s32,
6020 0 : 1490 => Opcode::MVE_VPTv4s32r,
6021 0 : 1491 => Opcode::MVE_VPTv4u32,
6022 0 : 1492 => Opcode::MVE_VPTv4u32r,
6023 0 : 1493 => Opcode::MVE_VPTv8f16,
6024 0 : 1494 => Opcode::MVE_VPTv8f16r,
6025 0 : 1495 => Opcode::MVE_VPTv8i16,
6026 0 : 1496 => Opcode::MVE_VPTv8i16r,
6027 0 : 1497 => Opcode::MVE_VPTv8s16,
6028 0 : 1498 => Opcode::MVE_VPTv8s16r,
6029 0 : 1499 => Opcode::MVE_VPTv8u16,
6030 0 : 1500 => Opcode::MVE_VPTv8u16r,
6031 0 : 1501 => Opcode::MVE_VQABSs16,
6032 0 : 1502 => Opcode::MVE_VQABSs32,
6033 0 : 1503 => Opcode::MVE_VQABSs8,
6034 0 : 1504 => Opcode::MVE_VQADD_qr_s16,
6035 0 : 1505 => Opcode::MVE_VQADD_qr_s32,
6036 0 : 1506 => Opcode::MVE_VQADD_qr_s8,
6037 0 : 1507 => Opcode::MVE_VQADD_qr_u16,
6038 0 : 1508 => Opcode::MVE_VQADD_qr_u32,
6039 0 : 1509 => Opcode::MVE_VQADD_qr_u8,
6040 0 : 1510 => Opcode::MVE_VQADDs16,
6041 0 : 1511 => Opcode::MVE_VQADDs32,
6042 0 : 1512 => Opcode::MVE_VQADDs8,
6043 0 : 1513 => Opcode::MVE_VQADDu16,
6044 0 : 1514 => Opcode::MVE_VQADDu32,
6045 0 : 1515 => Opcode::MVE_VQADDu8,
6046 0 : 1516 => Opcode::MVE_VQDMLADHXs16,
6047 0 : 1517 => Opcode::MVE_VQDMLADHXs32,
6048 0 : 1518 => Opcode::MVE_VQDMLADHXs8,
6049 0 : 1519 => Opcode::MVE_VQDMLADHs16,
6050 0 : 1520 => Opcode::MVE_VQDMLADHs32,
6051 0 : 1521 => Opcode::MVE_VQDMLADHs8,
6052 0 : 1522 => Opcode::MVE_VQDMLAH_qrs16,
6053 0 : 1523 => Opcode::MVE_VQDMLAH_qrs32,
6054 0 : 1524 => Opcode::MVE_VQDMLAH_qrs8,
6055 0 : 1525 => Opcode::MVE_VQDMLASH_qrs16,
6056 0 : 1526 => Opcode::MVE_VQDMLASH_qrs32,
6057 0 : 1527 => Opcode::MVE_VQDMLASH_qrs8,
6058 0 : 1528 => Opcode::MVE_VQDMLSDHXs16,
6059 0 : 1529 => Opcode::MVE_VQDMLSDHXs32,
6060 0 : 1530 => Opcode::MVE_VQDMLSDHXs8,
6061 0 : 1531 => Opcode::MVE_VQDMLSDHs16,
6062 0 : 1532 => Opcode::MVE_VQDMLSDHs32,
6063 0 : 1533 => Opcode::MVE_VQDMLSDHs8,
6064 0 : 1534 => Opcode::MVE_VQDMULH_qr_s16,
6065 0 : 1535 => Opcode::MVE_VQDMULH_qr_s32,
6066 0 : 1536 => Opcode::MVE_VQDMULH_qr_s8,
6067 0 : 1537 => Opcode::MVE_VQDMULHi16,
6068 0 : 1538 => Opcode::MVE_VQDMULHi32,
6069 0 : 1539 => Opcode::MVE_VQDMULHi8,
6070 0 : 1540 => Opcode::MVE_VQDMULL_qr_s16bh,
6071 0 : 1541 => Opcode::MVE_VQDMULL_qr_s16th,
6072 0 : 1542 => Opcode::MVE_VQDMULL_qr_s32bh,
6073 0 : 1543 => Opcode::MVE_VQDMULL_qr_s32th,
6074 0 : 1544 => Opcode::MVE_VQDMULLs16bh,
6075 0 : 1545 => Opcode::MVE_VQDMULLs16th,
6076 0 : 1546 => Opcode::MVE_VQDMULLs32bh,
6077 0 : 1547 => Opcode::MVE_VQDMULLs32th,
6078 0 : 1548 => Opcode::MVE_VQMOVNs16bh,
6079 0 : 1549 => Opcode::MVE_VQMOVNs16th,
6080 0 : 1550 => Opcode::MVE_VQMOVNs32bh,
6081 0 : 1551 => Opcode::MVE_VQMOVNs32th,
6082 0 : 1552 => Opcode::MVE_VQMOVNu16bh,
6083 0 : 1553 => Opcode::MVE_VQMOVNu16th,
6084 0 : 1554 => Opcode::MVE_VQMOVNu32bh,
6085 0 : 1555 => Opcode::MVE_VQMOVNu32th,
6086 0 : 1556 => Opcode::MVE_VQMOVUNs16bh,
6087 0 : 1557 => Opcode::MVE_VQMOVUNs16th,
6088 0 : 1558 => Opcode::MVE_VQMOVUNs32bh,
6089 0 : 1559 => Opcode::MVE_VQMOVUNs32th,
6090 0 : 1560 => Opcode::MVE_VQNEGs16,
6091 0 : 1561 => Opcode::MVE_VQNEGs32,
6092 0 : 1562 => Opcode::MVE_VQNEGs8,
6093 0 : 1563 => Opcode::MVE_VQRDMLADHXs16,
6094 0 : 1564 => Opcode::MVE_VQRDMLADHXs32,
6095 0 : 1565 => Opcode::MVE_VQRDMLADHXs8,
6096 0 : 1566 => Opcode::MVE_VQRDMLADHs16,
6097 0 : 1567 => Opcode::MVE_VQRDMLADHs32,
6098 0 : 1568 => Opcode::MVE_VQRDMLADHs8,
6099 0 : 1569 => Opcode::MVE_VQRDMLAH_qrs16,
6100 0 : 1570 => Opcode::MVE_VQRDMLAH_qrs32,
6101 0 : 1571 => Opcode::MVE_VQRDMLAH_qrs8,
6102 0 : 1572 => Opcode::MVE_VQRDMLASH_qrs16,
6103 0 : 1573 => Opcode::MVE_VQRDMLASH_qrs32,
6104 0 : 1574 => Opcode::MVE_VQRDMLASH_qrs8,
6105 0 : 1575 => Opcode::MVE_VQRDMLSDHXs16,
6106 0 : 1576 => Opcode::MVE_VQRDMLSDHXs32,
6107 0 : 1577 => Opcode::MVE_VQRDMLSDHXs8,
6108 0 : 1578 => Opcode::MVE_VQRDMLSDHs16,
6109 0 : 1579 => Opcode::MVE_VQRDMLSDHs32,
6110 0 : 1580 => Opcode::MVE_VQRDMLSDHs8,
6111 0 : 1581 => Opcode::MVE_VQRDMULH_qr_s16,
6112 0 : 1582 => Opcode::MVE_VQRDMULH_qr_s32,
6113 0 : 1583 => Opcode::MVE_VQRDMULH_qr_s8,
6114 0 : 1584 => Opcode::MVE_VQRDMULHi16,
6115 0 : 1585 => Opcode::MVE_VQRDMULHi32,
6116 0 : 1586 => Opcode::MVE_VQRDMULHi8,
6117 0 : 1587 => Opcode::MVE_VQRSHL_by_vecs16,
6118 0 : 1588 => Opcode::MVE_VQRSHL_by_vecs32,
6119 0 : 1589 => Opcode::MVE_VQRSHL_by_vecs8,
6120 0 : 1590 => Opcode::MVE_VQRSHL_by_vecu16,
6121 0 : 1591 => Opcode::MVE_VQRSHL_by_vecu32,
6122 0 : 1592 => Opcode::MVE_VQRSHL_by_vecu8,
6123 0 : 1593 => Opcode::MVE_VQRSHL_qrs16,
6124 0 : 1594 => Opcode::MVE_VQRSHL_qrs32,
6125 0 : 1595 => Opcode::MVE_VQRSHL_qrs8,
6126 0 : 1596 => Opcode::MVE_VQRSHL_qru16,
6127 0 : 1597 => Opcode::MVE_VQRSHL_qru32,
6128 0 : 1598 => Opcode::MVE_VQRSHL_qru8,
6129 0 : 1599 => Opcode::MVE_VQRSHRNbhs16,
6130 0 : 1600 => Opcode::MVE_VQRSHRNbhs32,
6131 0 : 1601 => Opcode::MVE_VQRSHRNbhu16,
6132 0 : 1602 => Opcode::MVE_VQRSHRNbhu32,
6133 0 : 1603 => Opcode::MVE_VQRSHRNths16,
6134 0 : 1604 => Opcode::MVE_VQRSHRNths32,
6135 0 : 1605 => Opcode::MVE_VQRSHRNthu16,
6136 0 : 1606 => Opcode::MVE_VQRSHRNthu32,
6137 0 : 1607 => Opcode::MVE_VQRSHRUNs16bh,
6138 0 : 1608 => Opcode::MVE_VQRSHRUNs16th,
6139 0 : 1609 => Opcode::MVE_VQRSHRUNs32bh,
6140 0 : 1610 => Opcode::MVE_VQRSHRUNs32th,
6141 0 : 1611 => Opcode::MVE_VQSHLU_imms16,
6142 0 : 1612 => Opcode::MVE_VQSHLU_imms32,
6143 0 : 1613 => Opcode::MVE_VQSHLU_imms8,
6144 0 : 1614 => Opcode::MVE_VQSHL_by_vecs16,
6145 0 : 1615 => Opcode::MVE_VQSHL_by_vecs32,
6146 0 : 1616 => Opcode::MVE_VQSHL_by_vecs8,
6147 0 : 1617 => Opcode::MVE_VQSHL_by_vecu16,
6148 0 : 1618 => Opcode::MVE_VQSHL_by_vecu32,
6149 0 : 1619 => Opcode::MVE_VQSHL_by_vecu8,
6150 0 : 1620 => Opcode::MVE_VQSHL_qrs16,
6151 0 : 1621 => Opcode::MVE_VQSHL_qrs32,
6152 0 : 1622 => Opcode::MVE_VQSHL_qrs8,
6153 0 : 1623 => Opcode::MVE_VQSHL_qru16,
6154 0 : 1624 => Opcode::MVE_VQSHL_qru32,
6155 0 : 1625 => Opcode::MVE_VQSHL_qru8,
6156 0 : 1626 => Opcode::MVE_VQSHLimms16,
6157 0 : 1627 => Opcode::MVE_VQSHLimms32,
6158 0 : 1628 => Opcode::MVE_VQSHLimms8,
6159 0 : 1629 => Opcode::MVE_VQSHLimmu16,
6160 0 : 1630 => Opcode::MVE_VQSHLimmu32,
6161 0 : 1631 => Opcode::MVE_VQSHLimmu8,
6162 0 : 1632 => Opcode::MVE_VQSHRNbhs16,
6163 0 : 1633 => Opcode::MVE_VQSHRNbhs32,
6164 0 : 1634 => Opcode::MVE_VQSHRNbhu16,
6165 0 : 1635 => Opcode::MVE_VQSHRNbhu32,
6166 0 : 1636 => Opcode::MVE_VQSHRNths16,
6167 0 : 1637 => Opcode::MVE_VQSHRNths32,
6168 0 : 1638 => Opcode::MVE_VQSHRNthu16,
6169 0 : 1639 => Opcode::MVE_VQSHRNthu32,
6170 0 : 1640 => Opcode::MVE_VQSHRUNs16bh,
6171 0 : 1641 => Opcode::MVE_VQSHRUNs16th,
6172 0 : 1642 => Opcode::MVE_VQSHRUNs32bh,
6173 0 : 1643 => Opcode::MVE_VQSHRUNs32th,
6174 0 : 1644 => Opcode::MVE_VQSUB_qr_s16,
6175 0 : 1645 => Opcode::MVE_VQSUB_qr_s32,
6176 0 : 1646 => Opcode::MVE_VQSUB_qr_s8,
6177 0 : 1647 => Opcode::MVE_VQSUB_qr_u16,
6178 0 : 1648 => Opcode::MVE_VQSUB_qr_u32,
6179 0 : 1649 => Opcode::MVE_VQSUB_qr_u8,
6180 0 : 1650 => Opcode::MVE_VQSUBs16,
6181 0 : 1651 => Opcode::MVE_VQSUBs32,
6182 0 : 1652 => Opcode::MVE_VQSUBs8,
6183 0 : 1653 => Opcode::MVE_VQSUBu16,
6184 0 : 1654 => Opcode::MVE_VQSUBu32,
6185 0 : 1655 => Opcode::MVE_VQSUBu8,
6186 0 : 1656 => Opcode::MVE_VREV16_8,
6187 0 : 1657 => Opcode::MVE_VREV32_16,
6188 0 : 1658 => Opcode::MVE_VREV32_8,
6189 0 : 1659 => Opcode::MVE_VREV64_16,
6190 0 : 1660 => Opcode::MVE_VREV64_32,
6191 0 : 1661 => Opcode::MVE_VREV64_8,
6192 0 : 1662 => Opcode::MVE_VRHADDs16,
6193 0 : 1663 => Opcode::MVE_VRHADDs32,
6194 0 : 1664 => Opcode::MVE_VRHADDs8,
6195 0 : 1665 => Opcode::MVE_VRHADDu16,
6196 0 : 1666 => Opcode::MVE_VRHADDu32,
6197 0 : 1667 => Opcode::MVE_VRHADDu8,
6198 0 : 1668 => Opcode::MVE_VRINTf16A,
6199 0 : 1669 => Opcode::MVE_VRINTf16M,
6200 0 : 1670 => Opcode::MVE_VRINTf16N,
6201 0 : 1671 => Opcode::MVE_VRINTf16P,
6202 0 : 1672 => Opcode::MVE_VRINTf16X,
6203 0 : 1673 => Opcode::MVE_VRINTf16Z,
6204 0 : 1674 => Opcode::MVE_VRINTf32A,
6205 0 : 1675 => Opcode::MVE_VRINTf32M,
6206 0 : 1676 => Opcode::MVE_VRINTf32N,
6207 0 : 1677 => Opcode::MVE_VRINTf32P,
6208 0 : 1678 => Opcode::MVE_VRINTf32X,
6209 0 : 1679 => Opcode::MVE_VRINTf32Z,
6210 0 : 1680 => Opcode::MVE_VRMLALDAVHas32,
6211 0 : 1681 => Opcode::MVE_VRMLALDAVHau32,
6212 0 : 1682 => Opcode::MVE_VRMLALDAVHaxs32,
6213 0 : 1683 => Opcode::MVE_VRMLALDAVHs32,
6214 0 : 1684 => Opcode::MVE_VRMLALDAVHu32,
6215 0 : 1685 => Opcode::MVE_VRMLALDAVHxs32,
6216 0 : 1686 => Opcode::MVE_VRMLSLDAVHas32,
6217 0 : 1687 => Opcode::MVE_VRMLSLDAVHaxs32,
6218 0 : 1688 => Opcode::MVE_VRMLSLDAVHs32,
6219 0 : 1689 => Opcode::MVE_VRMLSLDAVHxs32,
6220 0 : 1690 => Opcode::MVE_VRMULHs16,
6221 0 : 1691 => Opcode::MVE_VRMULHs32,
6222 0 : 1692 => Opcode::MVE_VRMULHs8,
6223 0 : 1693 => Opcode::MVE_VRMULHu16,
6224 0 : 1694 => Opcode::MVE_VRMULHu32,
6225 0 : 1695 => Opcode::MVE_VRMULHu8,
6226 0 : 1696 => Opcode::MVE_VRSHL_by_vecs16,
6227 0 : 1697 => Opcode::MVE_VRSHL_by_vecs32,
6228 0 : 1698 => Opcode::MVE_VRSHL_by_vecs8,
6229 0 : 1699 => Opcode::MVE_VRSHL_by_vecu16,
6230 0 : 1700 => Opcode::MVE_VRSHL_by_vecu32,
6231 0 : 1701 => Opcode::MVE_VRSHL_by_vecu8,
6232 0 : 1702 => Opcode::MVE_VRSHL_qrs16,
6233 0 : 1703 => Opcode::MVE_VRSHL_qrs32,
6234 0 : 1704 => Opcode::MVE_VRSHL_qrs8,
6235 0 : 1705 => Opcode::MVE_VRSHL_qru16,
6236 0 : 1706 => Opcode::MVE_VRSHL_qru32,
6237 0 : 1707 => Opcode::MVE_VRSHL_qru8,
6238 0 : 1708 => Opcode::MVE_VRSHRNi16bh,
6239 0 : 1709 => Opcode::MVE_VRSHRNi16th,
6240 0 : 1710 => Opcode::MVE_VRSHRNi32bh,
6241 0 : 1711 => Opcode::MVE_VRSHRNi32th,
6242 0 : 1712 => Opcode::MVE_VRSHR_imms16,
6243 0 : 1713 => Opcode::MVE_VRSHR_imms32,
6244 0 : 1714 => Opcode::MVE_VRSHR_imms8,
6245 0 : 1715 => Opcode::MVE_VRSHR_immu16,
6246 0 : 1716 => Opcode::MVE_VRSHR_immu32,
6247 0 : 1717 => Opcode::MVE_VRSHR_immu8,
6248 0 : 1718 => Opcode::MVE_VSBC,
6249 0 : 1719 => Opcode::MVE_VSBCI,
6250 0 : 1720 => Opcode::MVE_VSHLC,
6251 0 : 1721 => Opcode::MVE_VSHLL_imms16bh,
6252 0 : 1722 => Opcode::MVE_VSHLL_imms16th,
6253 0 : 1723 => Opcode::MVE_VSHLL_imms8bh,
6254 0 : 1724 => Opcode::MVE_VSHLL_imms8th,
6255 0 : 1725 => Opcode::MVE_VSHLL_immu16bh,
6256 0 : 1726 => Opcode::MVE_VSHLL_immu16th,
6257 0 : 1727 => Opcode::MVE_VSHLL_immu8bh,
6258 0 : 1728 => Opcode::MVE_VSHLL_immu8th,
6259 0 : 1729 => Opcode::MVE_VSHLL_lws16bh,
6260 0 : 1730 => Opcode::MVE_VSHLL_lws16th,
6261 0 : 1731 => Opcode::MVE_VSHLL_lws8bh,
6262 0 : 1732 => Opcode::MVE_VSHLL_lws8th,
6263 0 : 1733 => Opcode::MVE_VSHLL_lwu16bh,
6264 0 : 1734 => Opcode::MVE_VSHLL_lwu16th,
6265 0 : 1735 => Opcode::MVE_VSHLL_lwu8bh,
6266 0 : 1736 => Opcode::MVE_VSHLL_lwu8th,
6267 0 : 1737 => Opcode::MVE_VSHL_by_vecs16,
6268 0 : 1738 => Opcode::MVE_VSHL_by_vecs32,
6269 0 : 1739 => Opcode::MVE_VSHL_by_vecs8,
6270 0 : 1740 => Opcode::MVE_VSHL_by_vecu16,
6271 0 : 1741 => Opcode::MVE_VSHL_by_vecu32,
6272 0 : 1742 => Opcode::MVE_VSHL_by_vecu8,
6273 0 : 1743 => Opcode::MVE_VSHL_immi16,
6274 0 : 1744 => Opcode::MVE_VSHL_immi32,
6275 0 : 1745 => Opcode::MVE_VSHL_immi8,
6276 0 : 1746 => Opcode::MVE_VSHL_qrs16,
6277 0 : 1747 => Opcode::MVE_VSHL_qrs32,
6278 0 : 1748 => Opcode::MVE_VSHL_qrs8,
6279 0 : 1749 => Opcode::MVE_VSHL_qru16,
6280 0 : 1750 => Opcode::MVE_VSHL_qru32,
6281 0 : 1751 => Opcode::MVE_VSHL_qru8,
6282 0 : 1752 => Opcode::MVE_VSHRNi16bh,
6283 0 : 1753 => Opcode::MVE_VSHRNi16th,
6284 0 : 1754 => Opcode::MVE_VSHRNi32bh,
6285 0 : 1755 => Opcode::MVE_VSHRNi32th,
6286 0 : 1756 => Opcode::MVE_VSHR_imms16,
6287 0 : 1757 => Opcode::MVE_VSHR_imms32,
6288 0 : 1758 => Opcode::MVE_VSHR_imms8,
6289 0 : 1759 => Opcode::MVE_VSHR_immu16,
6290 0 : 1760 => Opcode::MVE_VSHR_immu32,
6291 0 : 1761 => Opcode::MVE_VSHR_immu8,
6292 0 : 1762 => Opcode::MVE_VSLIimm16,
6293 0 : 1763 => Opcode::MVE_VSLIimm32,
6294 0 : 1764 => Opcode::MVE_VSLIimm8,
6295 0 : 1765 => Opcode::MVE_VSRIimm16,
6296 0 : 1766 => Opcode::MVE_VSRIimm32,
6297 0 : 1767 => Opcode::MVE_VSRIimm8,
6298 0 : 1768 => Opcode::MVE_VST20_16,
6299 0 : 1769 => Opcode::MVE_VST20_16_wb,
6300 0 : 1770 => Opcode::MVE_VST20_32,
6301 0 : 1771 => Opcode::MVE_VST20_32_wb,
6302 0 : 1772 => Opcode::MVE_VST20_8,
6303 0 : 1773 => Opcode::MVE_VST20_8_wb,
6304 0 : 1774 => Opcode::MVE_VST21_16,
6305 0 : 1775 => Opcode::MVE_VST21_16_wb,
6306 0 : 1776 => Opcode::MVE_VST21_32,
6307 0 : 1777 => Opcode::MVE_VST21_32_wb,
6308 0 : 1778 => Opcode::MVE_VST21_8,
6309 0 : 1779 => Opcode::MVE_VST21_8_wb,
6310 0 : 1780 => Opcode::MVE_VST40_16,
6311 0 : 1781 => Opcode::MVE_VST40_16_wb,
6312 0 : 1782 => Opcode::MVE_VST40_32,
6313 0 : 1783 => Opcode::MVE_VST40_32_wb,
6314 0 : 1784 => Opcode::MVE_VST40_8,
6315 0 : 1785 => Opcode::MVE_VST40_8_wb,
6316 0 : 1786 => Opcode::MVE_VST41_16,
6317 0 : 1787 => Opcode::MVE_VST41_16_wb,
6318 0 : 1788 => Opcode::MVE_VST41_32,
6319 0 : 1789 => Opcode::MVE_VST41_32_wb,
6320 0 : 1790 => Opcode::MVE_VST41_8,
6321 0 : 1791 => Opcode::MVE_VST41_8_wb,
6322 0 : 1792 => Opcode::MVE_VST42_16,
6323 0 : 1793 => Opcode::MVE_VST42_16_wb,
6324 0 : 1794 => Opcode::MVE_VST42_32,
6325 0 : 1795 => Opcode::MVE_VST42_32_wb,
6326 0 : 1796 => Opcode::MVE_VST42_8,
6327 0 : 1797 => Opcode::MVE_VST42_8_wb,
6328 0 : 1798 => Opcode::MVE_VST43_16,
6329 0 : 1799 => Opcode::MVE_VST43_16_wb,
6330 0 : 1800 => Opcode::MVE_VST43_32,
6331 0 : 1801 => Opcode::MVE_VST43_32_wb,
6332 0 : 1802 => Opcode::MVE_VST43_8,
6333 0 : 1803 => Opcode::MVE_VST43_8_wb,
6334 0 : 1804 => Opcode::MVE_VSTRB16,
6335 0 : 1805 => Opcode::MVE_VSTRB16_post,
6336 0 : 1806 => Opcode::MVE_VSTRB16_pre,
6337 0 : 1807 => Opcode::MVE_VSTRB16_rq,
6338 0 : 1808 => Opcode::MVE_VSTRB32,
6339 0 : 1809 => Opcode::MVE_VSTRB32_post,
6340 0 : 1810 => Opcode::MVE_VSTRB32_pre,
6341 0 : 1811 => Opcode::MVE_VSTRB32_rq,
6342 0 : 1812 => Opcode::MVE_VSTRB8_rq,
6343 0 : 1813 => Opcode::MVE_VSTRBU8,
6344 0 : 1814 => Opcode::MVE_VSTRBU8_post,
6345 0 : 1815 => Opcode::MVE_VSTRBU8_pre,
6346 0 : 1816 => Opcode::MVE_VSTRD64_qi,
6347 0 : 1817 => Opcode::MVE_VSTRD64_qi_pre,
6348 0 : 1818 => Opcode::MVE_VSTRD64_rq,
6349 0 : 1819 => Opcode::MVE_VSTRD64_rq_u,
6350 0 : 1820 => Opcode::MVE_VSTRH16_rq,
6351 0 : 1821 => Opcode::MVE_VSTRH16_rq_u,
6352 0 : 1822 => Opcode::MVE_VSTRH32,
6353 0 : 1823 => Opcode::MVE_VSTRH32_post,
6354 0 : 1824 => Opcode::MVE_VSTRH32_pre,
6355 0 : 1825 => Opcode::MVE_VSTRH32_rq,
6356 0 : 1826 => Opcode::MVE_VSTRH32_rq_u,
6357 0 : 1827 => Opcode::MVE_VSTRHU16,
6358 0 : 1828 => Opcode::MVE_VSTRHU16_post,
6359 0 : 1829 => Opcode::MVE_VSTRHU16_pre,
6360 0 : 1830 => Opcode::MVE_VSTRW32_qi,
6361 0 : 1831 => Opcode::MVE_VSTRW32_qi_pre,
6362 0 : 1832 => Opcode::MVE_VSTRW32_rq,
6363 0 : 1833 => Opcode::MVE_VSTRW32_rq_u,
6364 0 : 1834 => Opcode::MVE_VSTRWU32,
6365 0 : 1835 => Opcode::MVE_VSTRWU32_post,
6366 0 : 1836 => Opcode::MVE_VSTRWU32_pre,
6367 0 : 1837 => Opcode::MVE_VSUB_qr_f16,
6368 0 : 1838 => Opcode::MVE_VSUB_qr_f32,
6369 0 : 1839 => Opcode::MVE_VSUB_qr_i16,
6370 0 : 1840 => Opcode::MVE_VSUB_qr_i32,
6371 0 : 1841 => Opcode::MVE_VSUB_qr_i8,
6372 0 : 1842 => Opcode::MVE_VSUBf16,
6373 0 : 1843 => Opcode::MVE_VSUBf32,
6374 0 : 1844 => Opcode::MVE_VSUBi16,
6375 0 : 1845 => Opcode::MVE_VSUBi32,
6376 0 : 1846 => Opcode::MVE_VSUBi8,
6377 0 : 1847 => Opcode::MVE_WLSTP_16,
6378 0 : 1848 => Opcode::MVE_WLSTP_32,
6379 0 : 1849 => Opcode::MVE_WLSTP_64,
6380 0 : 1850 => Opcode::MVE_WLSTP_8,
6381 0 : 1851 => Opcode::MVNi,
6382 0 : 1852 => Opcode::MVNr,
6383 0 : 1853 => Opcode::MVNsi,
6384 0 : 1854 => Opcode::MVNsr,
6385 0 : 1855 => Opcode::NEON_VMAXNMNDf,
6386 0 : 1856 => Opcode::NEON_VMAXNMNDh,
6387 0 : 1857 => Opcode::NEON_VMAXNMNQf,
6388 0 : 1858 => Opcode::NEON_VMAXNMNQh,
6389 0 : 1859 => Opcode::NEON_VMINNMNDf,
6390 0 : 1860 => Opcode::NEON_VMINNMNDh,
6391 0 : 1861 => Opcode::NEON_VMINNMNQf,
6392 0 : 1862 => Opcode::NEON_VMINNMNQh,
6393 0 : 1863 => Opcode::ORRri,
6394 0 : 1864 => Opcode::ORRrr,
6395 0 : 1865 => Opcode::ORRrsi,
6396 0 : 1866 => Opcode::ORRrsr,
6397 0 : 1867 => Opcode::PKHBT,
6398 0 : 1868 => Opcode::PKHTB,
6399 0 : 1869 => Opcode::PLDWi12,
6400 0 : 1870 => Opcode::PLDWrs,
6401 0 : 1871 => Opcode::PLDi12,
6402 0 : 1872 => Opcode::PLDrs,
6403 0 : 1873 => Opcode::PLIi12,
6404 0 : 1874 => Opcode::PLIrs,
6405 0 : 1875 => Opcode::QADD,
6406 0 : 1876 => Opcode::QADD16,
6407 0 : 1877 => Opcode::QADD8,
6408 0 : 1878 => Opcode::QASX,
6409 0 : 1879 => Opcode::QDADD,
6410 0 : 1880 => Opcode::QDSUB,
6411 0 : 1881 => Opcode::QSAX,
6412 0 : 1882 => Opcode::QSUB,
6413 0 : 1883 => Opcode::QSUB16,
6414 0 : 1884 => Opcode::QSUB8,
6415 0 : 1885 => Opcode::RBIT,
6416 0 : 1886 => Opcode::REV,
6417 0 : 1887 => Opcode::REV16,
6418 0 : 1888 => Opcode::REVSH,
6419 0 : 1889 => Opcode::RFEDA,
6420 0 : 1890 => Opcode::RFEDA_UPD,
6421 0 : 1891 => Opcode::RFEDB,
6422 0 : 1892 => Opcode::RFEDB_UPD,
6423 0 : 1893 => Opcode::RFEIA,
6424 0 : 1894 => Opcode::RFEIA_UPD,
6425 0 : 1895 => Opcode::RFEIB,
6426 0 : 1896 => Opcode::RFEIB_UPD,
6427 0 : 1897 => Opcode::RSBri,
6428 0 : 1898 => Opcode::RSBrr,
6429 0 : 1899 => Opcode::RSBrsi,
6430 0 : 1900 => Opcode::RSBrsr,
6431 0 : 1901 => Opcode::RSCri,
6432 0 : 1902 => Opcode::RSCrr,
6433 0 : 1903 => Opcode::RSCrsi,
6434 0 : 1904 => Opcode::RSCrsr,
6435 0 : 1905 => Opcode::SADD16,
6436 0 : 1906 => Opcode::SADD8,
6437 0 : 1907 => Opcode::SASX,
6438 0 : 1908 => Opcode::SB,
6439 0 : 1909 => Opcode::SBCri,
6440 0 : 1910 => Opcode::SBCrr,
6441 0 : 1911 => Opcode::SBCrsi,
6442 0 : 1912 => Opcode::SBCrsr,
6443 0 : 1913 => Opcode::SBFX,
6444 0 : 1914 => Opcode::SDIV,
6445 0 : 1915 => Opcode::SEL,
6446 0 : 1916 => Opcode::SETEND,
6447 0 : 1917 => Opcode::SETPAN,
6448 0 : 1918 => Opcode::SHA1C,
6449 0 : 1919 => Opcode::SHA1H,
6450 0 : 1920 => Opcode::SHA1M,
6451 0 : 1921 => Opcode::SHA1P,
6452 0 : 1922 => Opcode::SHA1SU0,
6453 0 : 1923 => Opcode::SHA1SU1,
6454 0 : 1924 => Opcode::SHA256H,
6455 0 : 1925 => Opcode::SHA256H2,
6456 0 : 1926 => Opcode::SHA256SU0,
6457 0 : 1927 => Opcode::SHA256SU1,
6458 0 : 1928 => Opcode::SHADD16,
6459 0 : 1929 => Opcode::SHADD8,
6460 0 : 1930 => Opcode::SHASX,
6461 0 : 1931 => Opcode::SHSAX,
6462 0 : 1932 => Opcode::SHSUB16,
6463 0 : 1933 => Opcode::SHSUB8,
6464 0 : 1934 => Opcode::SMC,
6465 0 : 1935 => Opcode::SMLABB,
6466 0 : 1936 => Opcode::SMLABT,
6467 0 : 1937 => Opcode::SMLAD,
6468 0 : 1938 => Opcode::SMLADX,
6469 0 : 1939 => Opcode::SMLAL,
6470 0 : 1940 => Opcode::SMLALBB,
6471 0 : 1941 => Opcode::SMLALBT,
6472 0 : 1942 => Opcode::SMLALD,
6473 0 : 1943 => Opcode::SMLALDX,
6474 0 : 1944 => Opcode::SMLALTB,
6475 0 : 1945 => Opcode::SMLALTT,
6476 0 : 1946 => Opcode::SMLATB,
6477 0 : 1947 => Opcode::SMLATT,
6478 0 : 1948 => Opcode::SMLAWB,
6479 0 : 1949 => Opcode::SMLAWT,
6480 0 : 1950 => Opcode::SMLSD,
6481 0 : 1951 => Opcode::SMLSDX,
6482 0 : 1952 => Opcode::SMLSLD,
6483 0 : 1953 => Opcode::SMLSLDX,
6484 0 : 1954 => Opcode::SMMLA,
6485 0 : 1955 => Opcode::SMMLAR,
6486 0 : 1956 => Opcode::SMMLS,
6487 0 : 1957 => Opcode::SMMLSR,
6488 0 : 1958 => Opcode::SMMUL,
6489 0 : 1959 => Opcode::SMMULR,
6490 0 : 1960 => Opcode::SMUAD,
6491 0 : 1961 => Opcode::SMUADX,
6492 0 : 1962 => Opcode::SMULBB,
6493 0 : 1963 => Opcode::SMULBT,
6494 0 : 1964 => Opcode::SMULL,
6495 0 : 1965 => Opcode::SMULTB,
6496 0 : 1966 => Opcode::SMULTT,
6497 0 : 1967 => Opcode::SMULWB,
6498 0 : 1968 => Opcode::SMULWT,
6499 0 : 1969 => Opcode::SMUSD,
6500 0 : 1970 => Opcode::SMUSDX,
6501 0 : 1971 => Opcode::SRSDA,
6502 0 : 1972 => Opcode::SRSDA_UPD,
6503 0 : 1973 => Opcode::SRSDB,
6504 0 : 1974 => Opcode::SRSDB_UPD,
6505 0 : 1975 => Opcode::SRSIA,
6506 0 : 1976 => Opcode::SRSIA_UPD,
6507 0 : 1977 => Opcode::SRSIB,
6508 0 : 1978 => Opcode::SRSIB_UPD,
6509 0 : 1979 => Opcode::SSAT,
6510 0 : 1980 => Opcode::SSAT16,
6511 0 : 1981 => Opcode::SSAX,
6512 0 : 1982 => Opcode::SSUB16,
6513 0 : 1983 => Opcode::SSUB8,
6514 0 : 1984 => Opcode::STC2L_OFFSET,
6515 0 : 1985 => Opcode::STC2L_OPTION,
6516 0 : 1986 => Opcode::STC2L_POST,
6517 0 : 1987 => Opcode::STC2L_PRE,
6518 0 : 1988 => Opcode::STC2_OFFSET,
6519 0 : 1989 => Opcode::STC2_OPTION,
6520 0 : 1990 => Opcode::STC2_POST,
6521 0 : 1991 => Opcode::STC2_PRE,
6522 0 : 1992 => Opcode::STCL_OFFSET,
6523 0 : 1993 => Opcode::STCL_OPTION,
6524 0 : 1994 => Opcode::STCL_POST,
6525 0 : 1995 => Opcode::STCL_PRE,
6526 0 : 1996 => Opcode::STC_OFFSET,
6527 0 : 1997 => Opcode::STC_OPTION,
6528 0 : 1998 => Opcode::STC_POST,
6529 0 : 1999 => Opcode::STC_PRE,
6530 0 : 2000 => Opcode::STL,
6531 0 : 2001 => Opcode::STLB,
6532 0 : 2002 => Opcode::STLEX,
6533 0 : 2003 => Opcode::STLEXB,
6534 0 : 2004 => Opcode::STLEXD,
6535 0 : 2005 => Opcode::STLEXH,
6536 0 : 2006 => Opcode::STLH,
6537 0 : 2007 => Opcode::STMDA,
6538 0 : 2008 => Opcode::STMDA_UPD,
6539 0 : 2009 => Opcode::STMDB,
6540 0 : 2010 => Opcode::STMDB_UPD,
6541 0 : 2011 => Opcode::STMIA,
6542 0 : 2012 => Opcode::STMIA_UPD,
6543 0 : 2013 => Opcode::STMIB,
6544 0 : 2014 => Opcode::STMIB_UPD,
6545 0 : 2015 => Opcode::STRBT_POST_IMM,
6546 0 : 2016 => Opcode::STRBT_POST_REG,
6547 0 : 2017 => Opcode::STRB_POST_IMM,
6548 0 : 2018 => Opcode::STRB_POST_REG,
6549 0 : 2019 => Opcode::STRB_PRE_IMM,
6550 0 : 2020 => Opcode::STRB_PRE_REG,
6551 0 : 2021 => Opcode::STRBi12,
6552 0 : 2022 => Opcode::STRBrs,
6553 0 : 2023 => Opcode::STRD,
6554 0 : 2024 => Opcode::STRD_POST,
6555 0 : 2025 => Opcode::STRD_PRE,
6556 0 : 2026 => Opcode::STREX,
6557 0 : 2027 => Opcode::STREXB,
6558 0 : 2028 => Opcode::STREXD,
6559 0 : 2029 => Opcode::STREXH,
6560 0 : 2030 => Opcode::STRH,
6561 0 : 2031 => Opcode::STRHTi,
6562 0 : 2032 => Opcode::STRHTr,
6563 0 : 2033 => Opcode::STRH_POST,
6564 0 : 2034 => Opcode::STRH_PRE,
6565 0 : 2035 => Opcode::STRT_POST_IMM,
6566 0 : 2036 => Opcode::STRT_POST_REG,
6567 0 : 2037 => Opcode::STR_POST_IMM,
6568 0 : 2038 => Opcode::STR_POST_REG,
6569 0 : 2039 => Opcode::STR_PRE_IMM,
6570 0 : 2040 => Opcode::STR_PRE_REG,
6571 0 : 2041 => Opcode::STRi12,
6572 0 : 2042 => Opcode::STRrs,
6573 0 : 2043 => Opcode::SUBri,
6574 0 : 2044 => Opcode::SUBrr,
6575 0 : 2045 => Opcode::SUBrsi,
6576 0 : 2046 => Opcode::SUBrsr,
6577 0 : 2047 => Opcode::SVC,
6578 0 : 2048 => Opcode::SWP,
6579 0 : 2049 => Opcode::SWPB,
6580 0 : 2050 => Opcode::SXTAB,
6581 0 : 2051 => Opcode::SXTAB16,
6582 0 : 2052 => Opcode::SXTAH,
6583 0 : 2053 => Opcode::SXTB,
6584 0 : 2054 => Opcode::SXTB16,
6585 0 : 2055 => Opcode::SXTH,
6586 0 : 2056 => Opcode::TEQri,
6587 0 : 2057 => Opcode::TEQrr,
6588 0 : 2058 => Opcode::TEQrsi,
6589 0 : 2059 => Opcode::TEQrsr,
6590 0 : 2060 => Opcode::TRAP,
6591 0 : 2061 => Opcode::TSB,
6592 0 : 2062 => Opcode::TSTri,
6593 0 : 2063 => Opcode::TSTrr,
6594 0 : 2064 => Opcode::TSTrsi,
6595 0 : 2065 => Opcode::TSTrsr,
6596 0 : 2066 => Opcode::UADD16,
6597 0 : 2067 => Opcode::UADD8,
6598 0 : 2068 => Opcode::UASX,
6599 0 : 2069 => Opcode::UBFX,
6600 0 : 2070 => Opcode::UDF,
6601 0 : 2071 => Opcode::UDIV,
6602 0 : 2072 => Opcode::UHADD16,
6603 0 : 2073 => Opcode::UHADD8,
6604 0 : 2074 => Opcode::UHASX,
6605 0 : 2075 => Opcode::UHSAX,
6606 0 : 2076 => Opcode::UHSUB16,
6607 0 : 2077 => Opcode::UHSUB8,
6608 0 : 2078 => Opcode::UMAAL,
6609 0 : 2079 => Opcode::UMLAL,
6610 0 : 2080 => Opcode::UMULL,
6611 0 : 2081 => Opcode::UQADD16,
6612 0 : 2082 => Opcode::UQADD8,
6613 0 : 2083 => Opcode::UQASX,
6614 0 : 2084 => Opcode::UQSAX,
6615 0 : 2085 => Opcode::UQSUB16,
6616 0 : 2086 => Opcode::UQSUB8,
6617 0 : 2087 => Opcode::USAD8,
6618 0 : 2088 => Opcode::USADA8,
6619 0 : 2089 => Opcode::USAT,
6620 0 : 2090 => Opcode::USAT16,
6621 0 : 2091 => Opcode::USAX,
6622 0 : 2092 => Opcode::USUB16,
6623 0 : 2093 => Opcode::USUB8,
6624 0 : 2094 => Opcode::UXTAB,
6625 0 : 2095 => Opcode::UXTAB16,
6626 0 : 2096 => Opcode::UXTAH,
6627 0 : 2097 => Opcode::UXTB,
6628 0 : 2098 => Opcode::UXTB16,
6629 0 : 2099 => Opcode::UXTH,
6630 0 : 2100 => Opcode::VABALsv2i64,
6631 0 : 2101 => Opcode::VABALsv4i32,
6632 0 : 2102 => Opcode::VABALsv8i16,
6633 0 : 2103 => Opcode::VABALuv2i64,
6634 0 : 2104 => Opcode::VABALuv4i32,
6635 0 : 2105 => Opcode::VABALuv8i16,
6636 0 : 2106 => Opcode::VABAsv16i8,
6637 0 : 2107 => Opcode::VABAsv2i32,
6638 0 : 2108 => Opcode::VABAsv4i16,
6639 0 : 2109 => Opcode::VABAsv4i32,
6640 0 : 2110 => Opcode::VABAsv8i16,
6641 0 : 2111 => Opcode::VABAsv8i8,
6642 0 : 2112 => Opcode::VABAuv16i8,
6643 0 : 2113 => Opcode::VABAuv2i32,
6644 0 : 2114 => Opcode::VABAuv4i16,
6645 0 : 2115 => Opcode::VABAuv4i32,
6646 0 : 2116 => Opcode::VABAuv8i16,
6647 0 : 2117 => Opcode::VABAuv8i8,
6648 0 : 2118 => Opcode::VABDLsv2i64,
6649 0 : 2119 => Opcode::VABDLsv4i32,
6650 0 : 2120 => Opcode::VABDLsv8i16,
6651 0 : 2121 => Opcode::VABDLuv2i64,
6652 0 : 2122 => Opcode::VABDLuv4i32,
6653 0 : 2123 => Opcode::VABDLuv8i16,
6654 0 : 2124 => Opcode::VABDfd,
6655 0 : 2125 => Opcode::VABDfq,
6656 0 : 2126 => Opcode::VABDhd,
6657 0 : 2127 => Opcode::VABDhq,
6658 0 : 2128 => Opcode::VABDsv16i8,
6659 0 : 2129 => Opcode::VABDsv2i32,
6660 0 : 2130 => Opcode::VABDsv4i16,
6661 0 : 2131 => Opcode::VABDsv4i32,
6662 0 : 2132 => Opcode::VABDsv8i16,
6663 0 : 2133 => Opcode::VABDsv8i8,
6664 0 : 2134 => Opcode::VABDuv16i8,
6665 0 : 2135 => Opcode::VABDuv2i32,
6666 0 : 2136 => Opcode::VABDuv4i16,
6667 0 : 2137 => Opcode::VABDuv4i32,
6668 0 : 2138 => Opcode::VABDuv8i16,
6669 0 : 2139 => Opcode::VABDuv8i8,
6670 0 : 2140 => Opcode::VABSD,
6671 0 : 2141 => Opcode::VABSH,
6672 0 : 2142 => Opcode::VABSS,
6673 0 : 2143 => Opcode::VABSfd,
6674 0 : 2144 => Opcode::VABSfq,
6675 0 : 2145 => Opcode::VABShd,
6676 0 : 2146 => Opcode::VABShq,
6677 0 : 2147 => Opcode::VABSv16i8,
6678 0 : 2148 => Opcode::VABSv2i32,
6679 0 : 2149 => Opcode::VABSv4i16,
6680 0 : 2150 => Opcode::VABSv4i32,
6681 0 : 2151 => Opcode::VABSv8i16,
6682 0 : 2152 => Opcode::VABSv8i8,
6683 0 : 2153 => Opcode::VACGEfd,
6684 0 : 2154 => Opcode::VACGEfq,
6685 0 : 2155 => Opcode::VACGEhd,
6686 0 : 2156 => Opcode::VACGEhq,
6687 0 : 2157 => Opcode::VACGTfd,
6688 0 : 2158 => Opcode::VACGTfq,
6689 0 : 2159 => Opcode::VACGThd,
6690 0 : 2160 => Opcode::VACGThq,
6691 0 : 2161 => Opcode::VADDD,
6692 0 : 2162 => Opcode::VADDH,
6693 0 : 2163 => Opcode::VADDHNv2i32,
6694 0 : 2164 => Opcode::VADDHNv4i16,
6695 0 : 2165 => Opcode::VADDHNv8i8,
6696 0 : 2166 => Opcode::VADDLsv2i64,
6697 0 : 2167 => Opcode::VADDLsv4i32,
6698 0 : 2168 => Opcode::VADDLsv8i16,
6699 0 : 2169 => Opcode::VADDLuv2i64,
6700 0 : 2170 => Opcode::VADDLuv4i32,
6701 0 : 2171 => Opcode::VADDLuv8i16,
6702 0 : 2172 => Opcode::VADDS,
6703 0 : 2173 => Opcode::VADDWsv2i64,
6704 0 : 2174 => Opcode::VADDWsv4i32,
6705 0 : 2175 => Opcode::VADDWsv8i16,
6706 0 : 2176 => Opcode::VADDWuv2i64,
6707 0 : 2177 => Opcode::VADDWuv4i32,
6708 0 : 2178 => Opcode::VADDWuv8i16,
6709 0 : 2179 => Opcode::VADDfd,
6710 0 : 2180 => Opcode::VADDfq,
6711 0 : 2181 => Opcode::VADDhd,
6712 0 : 2182 => Opcode::VADDhq,
6713 0 : 2183 => Opcode::VADDv16i8,
6714 0 : 2184 => Opcode::VADDv1i64,
6715 0 : 2185 => Opcode::VADDv2i32,
6716 0 : 2186 => Opcode::VADDv2i64,
6717 0 : 2187 => Opcode::VADDv4i16,
6718 0 : 2188 => Opcode::VADDv4i32,
6719 0 : 2189 => Opcode::VADDv8i16,
6720 0 : 2190 => Opcode::VADDv8i8,
6721 0 : 2191 => Opcode::VANDd,
6722 0 : 2192 => Opcode::VANDq,
6723 0 : 2193 => Opcode::VBF16MALBQ,
6724 0 : 2194 => Opcode::VBF16MALBQI,
6725 0 : 2195 => Opcode::VBF16MALTQ,
6726 0 : 2196 => Opcode::VBF16MALTQI,
6727 0 : 2197 => Opcode::VBICd,
6728 0 : 2198 => Opcode::VBICiv2i32,
6729 0 : 2199 => Opcode::VBICiv4i16,
6730 0 : 2200 => Opcode::VBICiv4i32,
6731 0 : 2201 => Opcode::VBICiv8i16,
6732 0 : 2202 => Opcode::VBICq,
6733 0 : 2203 => Opcode::VBIFd,
6734 0 : 2204 => Opcode::VBIFq,
6735 0 : 2205 => Opcode::VBITd,
6736 0 : 2206 => Opcode::VBITq,
6737 0 : 2207 => Opcode::VBSLd,
6738 0 : 2208 => Opcode::VBSLq,
6739 0 : 2209 => Opcode::VBSPd,
6740 0 : 2210 => Opcode::VBSPq,
6741 0 : 2211 => Opcode::VCADDv2f32,
6742 0 : 2212 => Opcode::VCADDv4f16,
6743 0 : 2213 => Opcode::VCADDv4f32,
6744 0 : 2214 => Opcode::VCADDv8f16,
6745 0 : 2215 => Opcode::VCEQfd,
6746 0 : 2216 => Opcode::VCEQfq,
6747 0 : 2217 => Opcode::VCEQhd,
6748 0 : 2218 => Opcode::VCEQhq,
6749 0 : 2219 => Opcode::VCEQv16i8,
6750 0 : 2220 => Opcode::VCEQv2i32,
6751 0 : 2221 => Opcode::VCEQv4i16,
6752 0 : 2222 => Opcode::VCEQv4i32,
6753 0 : 2223 => Opcode::VCEQv8i16,
6754 0 : 2224 => Opcode::VCEQv8i8,
6755 0 : 2225 => Opcode::VCEQzv16i8,
6756 0 : 2226 => Opcode::VCEQzv2f32,
6757 0 : 2227 => Opcode::VCEQzv2i32,
6758 0 : 2228 => Opcode::VCEQzv4f16,
6759 0 : 2229 => Opcode::VCEQzv4f32,
6760 0 : 2230 => Opcode::VCEQzv4i16,
6761 0 : 2231 => Opcode::VCEQzv4i32,
6762 0 : 2232 => Opcode::VCEQzv8f16,
6763 0 : 2233 => Opcode::VCEQzv8i16,
6764 0 : 2234 => Opcode::VCEQzv8i8,
6765 0 : 2235 => Opcode::VCGEfd,
6766 0 : 2236 => Opcode::VCGEfq,
6767 0 : 2237 => Opcode::VCGEhd,
6768 0 : 2238 => Opcode::VCGEhq,
6769 0 : 2239 => Opcode::VCGEsv16i8,
6770 0 : 2240 => Opcode::VCGEsv2i32,
6771 0 : 2241 => Opcode::VCGEsv4i16,
6772 0 : 2242 => Opcode::VCGEsv4i32,
6773 0 : 2243 => Opcode::VCGEsv8i16,
6774 0 : 2244 => Opcode::VCGEsv8i8,
6775 0 : 2245 => Opcode::VCGEuv16i8,
6776 0 : 2246 => Opcode::VCGEuv2i32,
6777 0 : 2247 => Opcode::VCGEuv4i16,
6778 0 : 2248 => Opcode::VCGEuv4i32,
6779 0 : 2249 => Opcode::VCGEuv8i16,
6780 0 : 2250 => Opcode::VCGEuv8i8,
6781 0 : 2251 => Opcode::VCGEzv16i8,
6782 0 : 2252 => Opcode::VCGEzv2f32,
6783 0 : 2253 => Opcode::VCGEzv2i32,
6784 0 : 2254 => Opcode::VCGEzv4f16,
6785 0 : 2255 => Opcode::VCGEzv4f32,
6786 0 : 2256 => Opcode::VCGEzv4i16,
6787 0 : 2257 => Opcode::VCGEzv4i32,
6788 0 : 2258 => Opcode::VCGEzv8f16,
6789 0 : 2259 => Opcode::VCGEzv8i16,
6790 0 : 2260 => Opcode::VCGEzv8i8,
6791 0 : 2261 => Opcode::VCGTfd,
6792 0 : 2262 => Opcode::VCGTfq,
6793 0 : 2263 => Opcode::VCGThd,
6794 0 : 2264 => Opcode::VCGThq,
6795 0 : 2265 => Opcode::VCGTsv16i8,
6796 0 : 2266 => Opcode::VCGTsv2i32,
6797 0 : 2267 => Opcode::VCGTsv4i16,
6798 0 : 2268 => Opcode::VCGTsv4i32,
6799 0 : 2269 => Opcode::VCGTsv8i16,
6800 0 : 2270 => Opcode::VCGTsv8i8,
6801 0 : 2271 => Opcode::VCGTuv16i8,
6802 0 : 2272 => Opcode::VCGTuv2i32,
6803 0 : 2273 => Opcode::VCGTuv4i16,
6804 0 : 2274 => Opcode::VCGTuv4i32,
6805 0 : 2275 => Opcode::VCGTuv8i16,
6806 0 : 2276 => Opcode::VCGTuv8i8,
6807 0 : 2277 => Opcode::VCGTzv16i8,
6808 0 : 2278 => Opcode::VCGTzv2f32,
6809 0 : 2279 => Opcode::VCGTzv2i32,
6810 0 : 2280 => Opcode::VCGTzv4f16,
6811 0 : 2281 => Opcode::VCGTzv4f32,
6812 0 : 2282 => Opcode::VCGTzv4i16,
6813 0 : 2283 => Opcode::VCGTzv4i32,
6814 0 : 2284 => Opcode::VCGTzv8f16,
6815 0 : 2285 => Opcode::VCGTzv8i16,
6816 0 : 2286 => Opcode::VCGTzv8i8,
6817 0 : 2287 => Opcode::VCLEzv16i8,
6818 0 : 2288 => Opcode::VCLEzv2f32,
6819 0 : 2289 => Opcode::VCLEzv2i32,
6820 0 : 2290 => Opcode::VCLEzv4f16,
6821 0 : 2291 => Opcode::VCLEzv4f32,
6822 0 : 2292 => Opcode::VCLEzv4i16,
6823 0 : 2293 => Opcode::VCLEzv4i32,
6824 0 : 2294 => Opcode::VCLEzv8f16,
6825 0 : 2295 => Opcode::VCLEzv8i16,
6826 0 : 2296 => Opcode::VCLEzv8i8,
6827 0 : 2297 => Opcode::VCLSv16i8,
6828 0 : 2298 => Opcode::VCLSv2i32,
6829 0 : 2299 => Opcode::VCLSv4i16,
6830 0 : 2300 => Opcode::VCLSv4i32,
6831 0 : 2301 => Opcode::VCLSv8i16,
6832 0 : 2302 => Opcode::VCLSv8i8,
6833 0 : 2303 => Opcode::VCLTzv16i8,
6834 0 : 2304 => Opcode::VCLTzv2f32,
6835 0 : 2305 => Opcode::VCLTzv2i32,
6836 0 : 2306 => Opcode::VCLTzv4f16,
6837 0 : 2307 => Opcode::VCLTzv4f32,
6838 0 : 2308 => Opcode::VCLTzv4i16,
6839 0 : 2309 => Opcode::VCLTzv4i32,
6840 0 : 2310 => Opcode::VCLTzv8f16,
6841 0 : 2311 => Opcode::VCLTzv8i16,
6842 0 : 2312 => Opcode::VCLTzv8i8,
6843 0 : 2313 => Opcode::VCLZv16i8,
6844 0 : 2314 => Opcode::VCLZv2i32,
6845 0 : 2315 => Opcode::VCLZv4i16,
6846 0 : 2316 => Opcode::VCLZv4i32,
6847 0 : 2317 => Opcode::VCLZv8i16,
6848 0 : 2318 => Opcode::VCLZv8i8,
6849 0 : 2319 => Opcode::VCMLAv2f32,
6850 0 : 2320 => Opcode::VCMLAv2f32_indexed,
6851 0 : 2321 => Opcode::VCMLAv4f16,
6852 0 : 2322 => Opcode::VCMLAv4f16_indexed,
6853 0 : 2323 => Opcode::VCMLAv4f32,
6854 0 : 2324 => Opcode::VCMLAv4f32_indexed,
6855 0 : 2325 => Opcode::VCMLAv8f16,
6856 0 : 2326 => Opcode::VCMLAv8f16_indexed,
6857 0 : 2327 => Opcode::VCMPD,
6858 0 : 2328 => Opcode::VCMPED,
6859 0 : 2329 => Opcode::VCMPEH,
6860 0 : 2330 => Opcode::VCMPES,
6861 0 : 2331 => Opcode::VCMPEZD,
6862 0 : 2332 => Opcode::VCMPEZH,
6863 0 : 2333 => Opcode::VCMPEZS,
6864 0 : 2334 => Opcode::VCMPH,
6865 0 : 2335 => Opcode::VCMPS,
6866 0 : 2336 => Opcode::VCMPZD,
6867 0 : 2337 => Opcode::VCMPZH,
6868 0 : 2338 => Opcode::VCMPZS,
6869 0 : 2339 => Opcode::VCNTd,
6870 0 : 2340 => Opcode::VCNTq,
6871 0 : 2341 => Opcode::VCVTANSDf,
6872 0 : 2342 => Opcode::VCVTANSDh,
6873 0 : 2343 => Opcode::VCVTANSQf,
6874 0 : 2344 => Opcode::VCVTANSQh,
6875 0 : 2345 => Opcode::VCVTANUDf,
6876 0 : 2346 => Opcode::VCVTANUDh,
6877 0 : 2347 => Opcode::VCVTANUQf,
6878 0 : 2348 => Opcode::VCVTANUQh,
6879 0 : 2349 => Opcode::VCVTASD,
6880 0 : 2350 => Opcode::VCVTASH,
6881 0 : 2351 => Opcode::VCVTASS,
6882 0 : 2352 => Opcode::VCVTAUD,
6883 0 : 2353 => Opcode::VCVTAUH,
6884 0 : 2354 => Opcode::VCVTAUS,
6885 0 : 2355 => Opcode::VCVTBDH,
6886 0 : 2356 => Opcode::VCVTBHD,
6887 0 : 2357 => Opcode::VCVTBHS,
6888 0 : 2358 => Opcode::VCVTBSH,
6889 0 : 2359 => Opcode::VCVTDS,
6890 0 : 2360 => Opcode::VCVTMNSDf,
6891 0 : 2361 => Opcode::VCVTMNSDh,
6892 0 : 2362 => Opcode::VCVTMNSQf,
6893 0 : 2363 => Opcode::VCVTMNSQh,
6894 0 : 2364 => Opcode::VCVTMNUDf,
6895 0 : 2365 => Opcode::VCVTMNUDh,
6896 0 : 2366 => Opcode::VCVTMNUQf,
6897 0 : 2367 => Opcode::VCVTMNUQh,
6898 0 : 2368 => Opcode::VCVTMSD,
6899 0 : 2369 => Opcode::VCVTMSH,
6900 0 : 2370 => Opcode::VCVTMSS,
6901 0 : 2371 => Opcode::VCVTMUD,
6902 0 : 2372 => Opcode::VCVTMUH,
6903 0 : 2373 => Opcode::VCVTMUS,
6904 0 : 2374 => Opcode::VCVTNNSDf,
6905 0 : 2375 => Opcode::VCVTNNSDh,
6906 0 : 2376 => Opcode::VCVTNNSQf,
6907 0 : 2377 => Opcode::VCVTNNSQh,
6908 0 : 2378 => Opcode::VCVTNNUDf,
6909 0 : 2379 => Opcode::VCVTNNUDh,
6910 0 : 2380 => Opcode::VCVTNNUQf,
6911 0 : 2381 => Opcode::VCVTNNUQh,
6912 0 : 2382 => Opcode::VCVTNSD,
6913 0 : 2383 => Opcode::VCVTNSH,
6914 0 : 2384 => Opcode::VCVTNSS,
6915 0 : 2385 => Opcode::VCVTNUD,
6916 0 : 2386 => Opcode::VCVTNUH,
6917 0 : 2387 => Opcode::VCVTNUS,
6918 0 : 2388 => Opcode::VCVTPNSDf,
6919 0 : 2389 => Opcode::VCVTPNSDh,
6920 0 : 2390 => Opcode::VCVTPNSQf,
6921 0 : 2391 => Opcode::VCVTPNSQh,
6922 0 : 2392 => Opcode::VCVTPNUDf,
6923 0 : 2393 => Opcode::VCVTPNUDh,
6924 0 : 2394 => Opcode::VCVTPNUQf,
6925 0 : 2395 => Opcode::VCVTPNUQh,
6926 0 : 2396 => Opcode::VCVTPSD,
6927 0 : 2397 => Opcode::VCVTPSH,
6928 0 : 2398 => Opcode::VCVTPSS,
6929 0 : 2399 => Opcode::VCVTPUD,
6930 0 : 2400 => Opcode::VCVTPUH,
6931 0 : 2401 => Opcode::VCVTPUS,
6932 0 : 2402 => Opcode::VCVTSD,
6933 0 : 2403 => Opcode::VCVTTDH,
6934 0 : 2404 => Opcode::VCVTTHD,
6935 0 : 2405 => Opcode::VCVTTHS,
6936 0 : 2406 => Opcode::VCVTTSH,
6937 0 : 2407 => Opcode::VCVTf2h,
6938 0 : 2408 => Opcode::VCVTf2sd,
6939 0 : 2409 => Opcode::VCVTf2sq,
6940 0 : 2410 => Opcode::VCVTf2ud,
6941 0 : 2411 => Opcode::VCVTf2uq,
6942 0 : 2412 => Opcode::VCVTf2xsd,
6943 0 : 2413 => Opcode::VCVTf2xsq,
6944 0 : 2414 => Opcode::VCVTf2xud,
6945 0 : 2415 => Opcode::VCVTf2xuq,
6946 0 : 2416 => Opcode::VCVTh2f,
6947 0 : 2417 => Opcode::VCVTh2sd,
6948 0 : 2418 => Opcode::VCVTh2sq,
6949 0 : 2419 => Opcode::VCVTh2ud,
6950 0 : 2420 => Opcode::VCVTh2uq,
6951 0 : 2421 => Opcode::VCVTh2xsd,
6952 0 : 2422 => Opcode::VCVTh2xsq,
6953 0 : 2423 => Opcode::VCVTh2xud,
6954 0 : 2424 => Opcode::VCVTh2xuq,
6955 0 : 2425 => Opcode::VCVTs2fd,
6956 0 : 2426 => Opcode::VCVTs2fq,
6957 0 : 2427 => Opcode::VCVTs2hd,
6958 0 : 2428 => Opcode::VCVTs2hq,
6959 0 : 2429 => Opcode::VCVTu2fd,
6960 0 : 2430 => Opcode::VCVTu2fq,
6961 0 : 2431 => Opcode::VCVTu2hd,
6962 0 : 2432 => Opcode::VCVTu2hq,
6963 0 : 2433 => Opcode::VCVTxs2fd,
6964 0 : 2434 => Opcode::VCVTxs2fq,
6965 0 : 2435 => Opcode::VCVTxs2hd,
6966 0 : 2436 => Opcode::VCVTxs2hq,
6967 0 : 2437 => Opcode::VCVTxu2fd,
6968 0 : 2438 => Opcode::VCVTxu2fq,
6969 0 : 2439 => Opcode::VCVTxu2hd,
6970 0 : 2440 => Opcode::VCVTxu2hq,
6971 0 : 2441 => Opcode::VDIVD,
6972 0 : 2442 => Opcode::VDIVH,
6973 0 : 2443 => Opcode::VDIVS,
6974 0 : 2444 => Opcode::VDUP16d,
6975 0 : 2445 => Opcode::VDUP16q,
6976 0 : 2446 => Opcode::VDUP32d,
6977 0 : 2447 => Opcode::VDUP32q,
6978 0 : 2448 => Opcode::VDUP8d,
6979 0 : 2449 => Opcode::VDUP8q,
6980 0 : 2450 => Opcode::VDUPLN16d,
6981 0 : 2451 => Opcode::VDUPLN16q,
6982 0 : 2452 => Opcode::VDUPLN32d,
6983 0 : 2453 => Opcode::VDUPLN32q,
6984 0 : 2454 => Opcode::VDUPLN8d,
6985 0 : 2455 => Opcode::VDUPLN8q,
6986 0 : 2456 => Opcode::VEORd,
6987 0 : 2457 => Opcode::VEORq,
6988 0 : 2458 => Opcode::VEXTd16,
6989 0 : 2459 => Opcode::VEXTd32,
6990 0 : 2460 => Opcode::VEXTd8,
6991 0 : 2461 => Opcode::VEXTq16,
6992 0 : 2462 => Opcode::VEXTq32,
6993 0 : 2463 => Opcode::VEXTq64,
6994 0 : 2464 => Opcode::VEXTq8,
6995 0 : 2465 => Opcode::VFMAD,
6996 0 : 2466 => Opcode::VFMAH,
6997 0 : 2467 => Opcode::VFMALD,
6998 0 : 2468 => Opcode::VFMALDI,
6999 0 : 2469 => Opcode::VFMALQ,
7000 0 : 2470 => Opcode::VFMALQI,
7001 0 : 2471 => Opcode::VFMAS,
7002 0 : 2472 => Opcode::VFMAfd,
7003 0 : 2473 => Opcode::VFMAfq,
7004 0 : 2474 => Opcode::VFMAhd,
7005 0 : 2475 => Opcode::VFMAhq,
7006 0 : 2476 => Opcode::VFMSD,
7007 0 : 2477 => Opcode::VFMSH,
7008 0 : 2478 => Opcode::VFMSLD,
7009 0 : 2479 => Opcode::VFMSLDI,
7010 0 : 2480 => Opcode::VFMSLQ,
7011 0 : 2481 => Opcode::VFMSLQI,
7012 0 : 2482 => Opcode::VFMSS,
7013 0 : 2483 => Opcode::VFMSfd,
7014 0 : 2484 => Opcode::VFMSfq,
7015 0 : 2485 => Opcode::VFMShd,
7016 0 : 2486 => Opcode::VFMShq,
7017 0 : 2487 => Opcode::VFNMAD,
7018 0 : 2488 => Opcode::VFNMAH,
7019 0 : 2489 => Opcode::VFNMAS,
7020 0 : 2490 => Opcode::VFNMSD,
7021 0 : 2491 => Opcode::VFNMSH,
7022 0 : 2492 => Opcode::VFNMSS,
7023 0 : 2493 => Opcode::VFP_VMAXNMD,
7024 0 : 2494 => Opcode::VFP_VMAXNMH,
7025 0 : 2495 => Opcode::VFP_VMAXNMS,
7026 0 : 2496 => Opcode::VFP_VMINNMD,
7027 0 : 2497 => Opcode::VFP_VMINNMH,
7028 0 : 2498 => Opcode::VFP_VMINNMS,
7029 0 : 2499 => Opcode::VGETLNi32,
7030 0 : 2500 => Opcode::VGETLNs16,
7031 0 : 2501 => Opcode::VGETLNs8,
7032 0 : 2502 => Opcode::VGETLNu16,
7033 0 : 2503 => Opcode::VGETLNu8,
7034 0 : 2504 => Opcode::VHADDsv16i8,
7035 0 : 2505 => Opcode::VHADDsv2i32,
7036 0 : 2506 => Opcode::VHADDsv4i16,
7037 0 : 2507 => Opcode::VHADDsv4i32,
7038 0 : 2508 => Opcode::VHADDsv8i16,
7039 0 : 2509 => Opcode::VHADDsv8i8,
7040 0 : 2510 => Opcode::VHADDuv16i8,
7041 0 : 2511 => Opcode::VHADDuv2i32,
7042 0 : 2512 => Opcode::VHADDuv4i16,
7043 0 : 2513 => Opcode::VHADDuv4i32,
7044 0 : 2514 => Opcode::VHADDuv8i16,
7045 0 : 2515 => Opcode::VHADDuv8i8,
7046 0 : 2516 => Opcode::VHSUBsv16i8,
7047 0 : 2517 => Opcode::VHSUBsv2i32,
7048 0 : 2518 => Opcode::VHSUBsv4i16,
7049 0 : 2519 => Opcode::VHSUBsv4i32,
7050 0 : 2520 => Opcode::VHSUBsv8i16,
7051 0 : 2521 => Opcode::VHSUBsv8i8,
7052 0 : 2522 => Opcode::VHSUBuv16i8,
7053 0 : 2523 => Opcode::VHSUBuv2i32,
7054 0 : 2524 => Opcode::VHSUBuv4i16,
7055 0 : 2525 => Opcode::VHSUBuv4i32,
7056 0 : 2526 => Opcode::VHSUBuv8i16,
7057 0 : 2527 => Opcode::VHSUBuv8i8,
7058 0 : 2528 => Opcode::VINSH,
7059 0 : 2529 => Opcode::VJCVT,
7060 0 : 2530 => Opcode::VLD1DUPd16,
7061 0 : 2531 => Opcode::VLD1DUPd16wb_fixed,
7062 0 : 2532 => Opcode::VLD1DUPd16wb_register,
7063 0 : 2533 => Opcode::VLD1DUPd32,
7064 0 : 2534 => Opcode::VLD1DUPd32wb_fixed,
7065 0 : 2535 => Opcode::VLD1DUPd32wb_register,
7066 0 : 2536 => Opcode::VLD1DUPd8,
7067 0 : 2537 => Opcode::VLD1DUPd8wb_fixed,
7068 0 : 2538 => Opcode::VLD1DUPd8wb_register,
7069 0 : 2539 => Opcode::VLD1DUPq16,
7070 0 : 2540 => Opcode::VLD1DUPq16wb_fixed,
7071 0 : 2541 => Opcode::VLD1DUPq16wb_register,
7072 0 : 2542 => Opcode::VLD1DUPq32,
7073 0 : 2543 => Opcode::VLD1DUPq32wb_fixed,
7074 0 : 2544 => Opcode::VLD1DUPq32wb_register,
7075 0 : 2545 => Opcode::VLD1DUPq8,
7076 0 : 2546 => Opcode::VLD1DUPq8wb_fixed,
7077 0 : 2547 => Opcode::VLD1DUPq8wb_register,
7078 0 : 2548 => Opcode::VLD1LNd16,
7079 0 : 2549 => Opcode::VLD1LNd16_UPD,
7080 0 : 2550 => Opcode::VLD1LNd32,
7081 0 : 2551 => Opcode::VLD1LNd32_UPD,
7082 0 : 2552 => Opcode::VLD1LNd8,
7083 0 : 2553 => Opcode::VLD1LNd8_UPD,
7084 0 : 2554 => Opcode::VLD1LNq16Pseudo,
7085 0 : 2555 => Opcode::VLD1LNq16Pseudo_UPD,
7086 0 : 2556 => Opcode::VLD1LNq32Pseudo,
7087 0 : 2557 => Opcode::VLD1LNq32Pseudo_UPD,
7088 0 : 2558 => Opcode::VLD1LNq8Pseudo,
7089 0 : 2559 => Opcode::VLD1LNq8Pseudo_UPD,
7090 0 : 2560 => Opcode::VLD1d16,
7091 0 : 2561 => Opcode::VLD1d16Q,
7092 0 : 2562 => Opcode::VLD1d16QPseudo,
7093 0 : 2563 => Opcode::VLD1d16QPseudoWB_fixed,
7094 0 : 2564 => Opcode::VLD1d16QPseudoWB_register,
7095 0 : 2565 => Opcode::VLD1d16Qwb_fixed,
7096 0 : 2566 => Opcode::VLD1d16Qwb_register,
7097 0 : 2567 => Opcode::VLD1d16T,
7098 0 : 2568 => Opcode::VLD1d16TPseudo,
7099 0 : 2569 => Opcode::VLD1d16TPseudoWB_fixed,
7100 0 : 2570 => Opcode::VLD1d16TPseudoWB_register,
7101 0 : 2571 => Opcode::VLD1d16Twb_fixed,
7102 0 : 2572 => Opcode::VLD1d16Twb_register,
7103 0 : 2573 => Opcode::VLD1d16wb_fixed,
7104 0 : 2574 => Opcode::VLD1d16wb_register,
7105 0 : 2575 => Opcode::VLD1d32,
7106 0 : 2576 => Opcode::VLD1d32Q,
7107 0 : 2577 => Opcode::VLD1d32QPseudo,
7108 0 : 2578 => Opcode::VLD1d32QPseudoWB_fixed,
7109 0 : 2579 => Opcode::VLD1d32QPseudoWB_register,
7110 0 : 2580 => Opcode::VLD1d32Qwb_fixed,
7111 0 : 2581 => Opcode::VLD1d32Qwb_register,
7112 0 : 2582 => Opcode::VLD1d32T,
7113 0 : 2583 => Opcode::VLD1d32TPseudo,
7114 0 : 2584 => Opcode::VLD1d32TPseudoWB_fixed,
7115 0 : 2585 => Opcode::VLD1d32TPseudoWB_register,
7116 0 : 2586 => Opcode::VLD1d32Twb_fixed,
7117 0 : 2587 => Opcode::VLD1d32Twb_register,
7118 0 : 2588 => Opcode::VLD1d32wb_fixed,
7119 0 : 2589 => Opcode::VLD1d32wb_register,
7120 0 : 2590 => Opcode::VLD1d64,
7121 0 : 2591 => Opcode::VLD1d64Q,
7122 0 : 2592 => Opcode::VLD1d64QPseudo,
7123 0 : 2593 => Opcode::VLD1d64QPseudoWB_fixed,
7124 0 : 2594 => Opcode::VLD1d64QPseudoWB_register,
7125 0 : 2595 => Opcode::VLD1d64Qwb_fixed,
7126 0 : 2596 => Opcode::VLD1d64Qwb_register,
7127 0 : 2597 => Opcode::VLD1d64T,
7128 0 : 2598 => Opcode::VLD1d64TPseudo,
7129 0 : 2599 => Opcode::VLD1d64TPseudoWB_fixed,
7130 0 : 2600 => Opcode::VLD1d64TPseudoWB_register,
7131 0 : 2601 => Opcode::VLD1d64Twb_fixed,
7132 0 : 2602 => Opcode::VLD1d64Twb_register,
7133 0 : 2603 => Opcode::VLD1d64wb_fixed,
7134 0 : 2604 => Opcode::VLD1d64wb_register,
7135 0 : 2605 => Opcode::VLD1d8,
7136 0 : 2606 => Opcode::VLD1d8Q,
7137 0 : 2607 => Opcode::VLD1d8QPseudo,
7138 0 : 2608 => Opcode::VLD1d8QPseudoWB_fixed,
7139 0 : 2609 => Opcode::VLD1d8QPseudoWB_register,
7140 0 : 2610 => Opcode::VLD1d8Qwb_fixed,
7141 0 : 2611 => Opcode::VLD1d8Qwb_register,
7142 0 : 2612 => Opcode::VLD1d8T,
7143 0 : 2613 => Opcode::VLD1d8TPseudo,
7144 0 : 2614 => Opcode::VLD1d8TPseudoWB_fixed,
7145 0 : 2615 => Opcode::VLD1d8TPseudoWB_register,
7146 0 : 2616 => Opcode::VLD1d8Twb_fixed,
7147 0 : 2617 => Opcode::VLD1d8Twb_register,
7148 0 : 2618 => Opcode::VLD1d8wb_fixed,
7149 0 : 2619 => Opcode::VLD1d8wb_register,
7150 0 : 2620 => Opcode::VLD1q16,
7151 0 : 2621 => Opcode::VLD1q16HighQPseudo,
7152 0 : 2622 => Opcode::VLD1q16HighQPseudo_UPD,
7153 0 : 2623 => Opcode::VLD1q16HighTPseudo,
7154 0 : 2624 => Opcode::VLD1q16HighTPseudo_UPD,
7155 0 : 2625 => Opcode::VLD1q16LowQPseudo_UPD,
7156 0 : 2626 => Opcode::VLD1q16LowTPseudo_UPD,
7157 0 : 2627 => Opcode::VLD1q16wb_fixed,
7158 0 : 2628 => Opcode::VLD1q16wb_register,
7159 0 : 2629 => Opcode::VLD1q32,
7160 0 : 2630 => Opcode::VLD1q32HighQPseudo,
7161 0 : 2631 => Opcode::VLD1q32HighQPseudo_UPD,
7162 0 : 2632 => Opcode::VLD1q32HighTPseudo,
7163 0 : 2633 => Opcode::VLD1q32HighTPseudo_UPD,
7164 0 : 2634 => Opcode::VLD1q32LowQPseudo_UPD,
7165 0 : 2635 => Opcode::VLD1q32LowTPseudo_UPD,
7166 0 : 2636 => Opcode::VLD1q32wb_fixed,
7167 0 : 2637 => Opcode::VLD1q32wb_register,
7168 0 : 2638 => Opcode::VLD1q64,
7169 0 : 2639 => Opcode::VLD1q64HighQPseudo,
7170 0 : 2640 => Opcode::VLD1q64HighQPseudo_UPD,
7171 0 : 2641 => Opcode::VLD1q64HighTPseudo,
7172 0 : 2642 => Opcode::VLD1q64HighTPseudo_UPD,
7173 0 : 2643 => Opcode::VLD1q64LowQPseudo_UPD,
7174 0 : 2644 => Opcode::VLD1q64LowTPseudo_UPD,
7175 0 : 2645 => Opcode::VLD1q64wb_fixed,
7176 0 : 2646 => Opcode::VLD1q64wb_register,
7177 0 : 2647 => Opcode::VLD1q8,
7178 0 : 2648 => Opcode::VLD1q8HighQPseudo,
7179 0 : 2649 => Opcode::VLD1q8HighQPseudo_UPD,
7180 0 : 2650 => Opcode::VLD1q8HighTPseudo,
7181 0 : 2651 => Opcode::VLD1q8HighTPseudo_UPD,
7182 0 : 2652 => Opcode::VLD1q8LowQPseudo_UPD,
7183 0 : 2653 => Opcode::VLD1q8LowTPseudo_UPD,
7184 0 : 2654 => Opcode::VLD1q8wb_fixed,
7185 0 : 2655 => Opcode::VLD1q8wb_register,
7186 0 : 2656 => Opcode::VLD2DUPd16,
7187 0 : 2657 => Opcode::VLD2DUPd16wb_fixed,
7188 0 : 2658 => Opcode::VLD2DUPd16wb_register,
7189 0 : 2659 => Opcode::VLD2DUPd16x2,
7190 0 : 2660 => Opcode::VLD2DUPd16x2wb_fixed,
7191 0 : 2661 => Opcode::VLD2DUPd16x2wb_register,
7192 0 : 2662 => Opcode::VLD2DUPd32,
7193 0 : 2663 => Opcode::VLD2DUPd32wb_fixed,
7194 0 : 2664 => Opcode::VLD2DUPd32wb_register,
7195 0 : 2665 => Opcode::VLD2DUPd32x2,
7196 0 : 2666 => Opcode::VLD2DUPd32x2wb_fixed,
7197 0 : 2667 => Opcode::VLD2DUPd32x2wb_register,
7198 0 : 2668 => Opcode::VLD2DUPd8,
7199 0 : 2669 => Opcode::VLD2DUPd8wb_fixed,
7200 0 : 2670 => Opcode::VLD2DUPd8wb_register,
7201 0 : 2671 => Opcode::VLD2DUPd8x2,
7202 0 : 2672 => Opcode::VLD2DUPd8x2wb_fixed,
7203 0 : 2673 => Opcode::VLD2DUPd8x2wb_register,
7204 0 : 2674 => Opcode::VLD2DUPq16EvenPseudo,
7205 0 : 2675 => Opcode::VLD2DUPq16OddPseudo,
7206 0 : 2676 => Opcode::VLD2DUPq16OddPseudoWB_fixed,
7207 0 : 2677 => Opcode::VLD2DUPq16OddPseudoWB_register,
7208 0 : 2678 => Opcode::VLD2DUPq32EvenPseudo,
7209 0 : 2679 => Opcode::VLD2DUPq32OddPseudo,
7210 0 : 2680 => Opcode::VLD2DUPq32OddPseudoWB_fixed,
7211 0 : 2681 => Opcode::VLD2DUPq32OddPseudoWB_register,
7212 0 : 2682 => Opcode::VLD2DUPq8EvenPseudo,
7213 0 : 2683 => Opcode::VLD2DUPq8OddPseudo,
7214 0 : 2684 => Opcode::VLD2DUPq8OddPseudoWB_fixed,
7215 0 : 2685 => Opcode::VLD2DUPq8OddPseudoWB_register,
7216 0 : 2686 => Opcode::VLD2LNd16,
7217 0 : 2687 => Opcode::VLD2LNd16Pseudo,
7218 0 : 2688 => Opcode::VLD2LNd16Pseudo_UPD,
7219 0 : 2689 => Opcode::VLD2LNd16_UPD,
7220 0 : 2690 => Opcode::VLD2LNd32,
7221 0 : 2691 => Opcode::VLD2LNd32Pseudo,
7222 0 : 2692 => Opcode::VLD2LNd32Pseudo_UPD,
7223 0 : 2693 => Opcode::VLD2LNd32_UPD,
7224 0 : 2694 => Opcode::VLD2LNd8,
7225 0 : 2695 => Opcode::VLD2LNd8Pseudo,
7226 0 : 2696 => Opcode::VLD2LNd8Pseudo_UPD,
7227 0 : 2697 => Opcode::VLD2LNd8_UPD,
7228 0 : 2698 => Opcode::VLD2LNq16,
7229 0 : 2699 => Opcode::VLD2LNq16Pseudo,
7230 0 : 2700 => Opcode::VLD2LNq16Pseudo_UPD,
7231 0 : 2701 => Opcode::VLD2LNq16_UPD,
7232 0 : 2702 => Opcode::VLD2LNq32,
7233 0 : 2703 => Opcode::VLD2LNq32Pseudo,
7234 0 : 2704 => Opcode::VLD2LNq32Pseudo_UPD,
7235 0 : 2705 => Opcode::VLD2LNq32_UPD,
7236 0 : 2706 => Opcode::VLD2b16,
7237 0 : 2707 => Opcode::VLD2b16wb_fixed,
7238 0 : 2708 => Opcode::VLD2b16wb_register,
7239 0 : 2709 => Opcode::VLD2b32,
7240 0 : 2710 => Opcode::VLD2b32wb_fixed,
7241 0 : 2711 => Opcode::VLD2b32wb_register,
7242 0 : 2712 => Opcode::VLD2b8,
7243 0 : 2713 => Opcode::VLD2b8wb_fixed,
7244 0 : 2714 => Opcode::VLD2b8wb_register,
7245 0 : 2715 => Opcode::VLD2d16,
7246 0 : 2716 => Opcode::VLD2d16wb_fixed,
7247 0 : 2717 => Opcode::VLD2d16wb_register,
7248 0 : 2718 => Opcode::VLD2d32,
7249 0 : 2719 => Opcode::VLD2d32wb_fixed,
7250 0 : 2720 => Opcode::VLD2d32wb_register,
7251 0 : 2721 => Opcode::VLD2d8,
7252 0 : 2722 => Opcode::VLD2d8wb_fixed,
7253 0 : 2723 => Opcode::VLD2d8wb_register,
7254 0 : 2724 => Opcode::VLD2q16,
7255 0 : 2725 => Opcode::VLD2q16Pseudo,
7256 0 : 2726 => Opcode::VLD2q16PseudoWB_fixed,
7257 0 : 2727 => Opcode::VLD2q16PseudoWB_register,
7258 0 : 2728 => Opcode::VLD2q16wb_fixed,
7259 0 : 2729 => Opcode::VLD2q16wb_register,
7260 0 : 2730 => Opcode::VLD2q32,
7261 0 : 2731 => Opcode::VLD2q32Pseudo,
7262 0 : 2732 => Opcode::VLD2q32PseudoWB_fixed,
7263 0 : 2733 => Opcode::VLD2q32PseudoWB_register,
7264 0 : 2734 => Opcode::VLD2q32wb_fixed,
7265 0 : 2735 => Opcode::VLD2q32wb_register,
7266 0 : 2736 => Opcode::VLD2q8,
7267 0 : 2737 => Opcode::VLD2q8Pseudo,
7268 0 : 2738 => Opcode::VLD2q8PseudoWB_fixed,
7269 0 : 2739 => Opcode::VLD2q8PseudoWB_register,
7270 0 : 2740 => Opcode::VLD2q8wb_fixed,
7271 0 : 2741 => Opcode::VLD2q8wb_register,
7272 0 : 2742 => Opcode::VLD3DUPd16,
7273 0 : 2743 => Opcode::VLD3DUPd16Pseudo,
7274 0 : 2744 => Opcode::VLD3DUPd16Pseudo_UPD,
7275 0 : 2745 => Opcode::VLD3DUPd16_UPD,
7276 0 : 2746 => Opcode::VLD3DUPd32,
7277 0 : 2747 => Opcode::VLD3DUPd32Pseudo,
7278 0 : 2748 => Opcode::VLD3DUPd32Pseudo_UPD,
7279 0 : 2749 => Opcode::VLD3DUPd32_UPD,
7280 0 : 2750 => Opcode::VLD3DUPd8,
7281 0 : 2751 => Opcode::VLD3DUPd8Pseudo,
7282 0 : 2752 => Opcode::VLD3DUPd8Pseudo_UPD,
7283 0 : 2753 => Opcode::VLD3DUPd8_UPD,
7284 0 : 2754 => Opcode::VLD3DUPq16,
7285 0 : 2755 => Opcode::VLD3DUPq16EvenPseudo,
7286 0 : 2756 => Opcode::VLD3DUPq16OddPseudo,
7287 0 : 2757 => Opcode::VLD3DUPq16OddPseudo_UPD,
7288 0 : 2758 => Opcode::VLD3DUPq16_UPD,
7289 0 : 2759 => Opcode::VLD3DUPq32,
7290 0 : 2760 => Opcode::VLD3DUPq32EvenPseudo,
7291 0 : 2761 => Opcode::VLD3DUPq32OddPseudo,
7292 0 : 2762 => Opcode::VLD3DUPq32OddPseudo_UPD,
7293 0 : 2763 => Opcode::VLD3DUPq32_UPD,
7294 0 : 2764 => Opcode::VLD3DUPq8,
7295 0 : 2765 => Opcode::VLD3DUPq8EvenPseudo,
7296 0 : 2766 => Opcode::VLD3DUPq8OddPseudo,
7297 0 : 2767 => Opcode::VLD3DUPq8OddPseudo_UPD,
7298 0 : 2768 => Opcode::VLD3DUPq8_UPD,
7299 0 : 2769 => Opcode::VLD3LNd16,
7300 0 : 2770 => Opcode::VLD3LNd16Pseudo,
7301 0 : 2771 => Opcode::VLD3LNd16Pseudo_UPD,
7302 0 : 2772 => Opcode::VLD3LNd16_UPD,
7303 0 : 2773 => Opcode::VLD3LNd32,
7304 0 : 2774 => Opcode::VLD3LNd32Pseudo,
7305 0 : 2775 => Opcode::VLD3LNd32Pseudo_UPD,
7306 0 : 2776 => Opcode::VLD3LNd32_UPD,
7307 0 : 2777 => Opcode::VLD3LNd8,
7308 0 : 2778 => Opcode::VLD3LNd8Pseudo,
7309 0 : 2779 => Opcode::VLD3LNd8Pseudo_UPD,
7310 0 : 2780 => Opcode::VLD3LNd8_UPD,
7311 0 : 2781 => Opcode::VLD3LNq16,
7312 0 : 2782 => Opcode::VLD3LNq16Pseudo,
7313 0 : 2783 => Opcode::VLD3LNq16Pseudo_UPD,
7314 0 : 2784 => Opcode::VLD3LNq16_UPD,
7315 0 : 2785 => Opcode::VLD3LNq32,
7316 0 : 2786 => Opcode::VLD3LNq32Pseudo,
7317 0 : 2787 => Opcode::VLD3LNq32Pseudo_UPD,
7318 0 : 2788 => Opcode::VLD3LNq32_UPD,
7319 0 : 2789 => Opcode::VLD3d16,
7320 0 : 2790 => Opcode::VLD3d16Pseudo,
7321 0 : 2791 => Opcode::VLD3d16Pseudo_UPD,
7322 0 : 2792 => Opcode::VLD3d16_UPD,
7323 0 : 2793 => Opcode::VLD3d32,
7324 0 : 2794 => Opcode::VLD3d32Pseudo,
7325 0 : 2795 => Opcode::VLD3d32Pseudo_UPD,
7326 0 : 2796 => Opcode::VLD3d32_UPD,
7327 0 : 2797 => Opcode::VLD3d8,
7328 0 : 2798 => Opcode::VLD3d8Pseudo,
7329 0 : 2799 => Opcode::VLD3d8Pseudo_UPD,
7330 0 : 2800 => Opcode::VLD3d8_UPD,
7331 0 : 2801 => Opcode::VLD3q16,
7332 0 : 2802 => Opcode::VLD3q16Pseudo_UPD,
7333 0 : 2803 => Opcode::VLD3q16_UPD,
7334 0 : 2804 => Opcode::VLD3q16oddPseudo,
7335 0 : 2805 => Opcode::VLD3q16oddPseudo_UPD,
7336 0 : 2806 => Opcode::VLD3q32,
7337 0 : 2807 => Opcode::VLD3q32Pseudo_UPD,
7338 0 : 2808 => Opcode::VLD3q32_UPD,
7339 0 : 2809 => Opcode::VLD3q32oddPseudo,
7340 0 : 2810 => Opcode::VLD3q32oddPseudo_UPD,
7341 0 : 2811 => Opcode::VLD3q8,
7342 0 : 2812 => Opcode::VLD3q8Pseudo_UPD,
7343 0 : 2813 => Opcode::VLD3q8_UPD,
7344 0 : 2814 => Opcode::VLD3q8oddPseudo,
7345 0 : 2815 => Opcode::VLD3q8oddPseudo_UPD,
7346 0 : 2816 => Opcode::VLD4DUPd16,
7347 0 : 2817 => Opcode::VLD4DUPd16Pseudo,
7348 0 : 2818 => Opcode::VLD4DUPd16Pseudo_UPD,
7349 0 : 2819 => Opcode::VLD4DUPd16_UPD,
7350 0 : 2820 => Opcode::VLD4DUPd32,
7351 0 : 2821 => Opcode::VLD4DUPd32Pseudo,
7352 0 : 2822 => Opcode::VLD4DUPd32Pseudo_UPD,
7353 0 : 2823 => Opcode::VLD4DUPd32_UPD,
7354 0 : 2824 => Opcode::VLD4DUPd8,
7355 0 : 2825 => Opcode::VLD4DUPd8Pseudo,
7356 0 : 2826 => Opcode::VLD4DUPd8Pseudo_UPD,
7357 0 : 2827 => Opcode::VLD4DUPd8_UPD,
7358 0 : 2828 => Opcode::VLD4DUPq16,
7359 0 : 2829 => Opcode::VLD4DUPq16EvenPseudo,
7360 0 : 2830 => Opcode::VLD4DUPq16OddPseudo,
7361 0 : 2831 => Opcode::VLD4DUPq16OddPseudo_UPD,
7362 0 : 2832 => Opcode::VLD4DUPq16_UPD,
7363 0 : 2833 => Opcode::VLD4DUPq32,
7364 0 : 2834 => Opcode::VLD4DUPq32EvenPseudo,
7365 0 : 2835 => Opcode::VLD4DUPq32OddPseudo,
7366 0 : 2836 => Opcode::VLD4DUPq32OddPseudo_UPD,
7367 0 : 2837 => Opcode::VLD4DUPq32_UPD,
7368 0 : 2838 => Opcode::VLD4DUPq8,
7369 0 : 2839 => Opcode::VLD4DUPq8EvenPseudo,
7370 0 : 2840 => Opcode::VLD4DUPq8OddPseudo,
7371 0 : 2841 => Opcode::VLD4DUPq8OddPseudo_UPD,
7372 0 : 2842 => Opcode::VLD4DUPq8_UPD,
7373 0 : 2843 => Opcode::VLD4LNd16,
7374 0 : 2844 => Opcode::VLD4LNd16Pseudo,
7375 0 : 2845 => Opcode::VLD4LNd16Pseudo_UPD,
7376 0 : 2846 => Opcode::VLD4LNd16_UPD,
7377 0 : 2847 => Opcode::VLD4LNd32,
7378 0 : 2848 => Opcode::VLD4LNd32Pseudo,
7379 0 : 2849 => Opcode::VLD4LNd32Pseudo_UPD,
7380 0 : 2850 => Opcode::VLD4LNd32_UPD,
7381 0 : 2851 => Opcode::VLD4LNd8,
7382 0 : 2852 => Opcode::VLD4LNd8Pseudo,
7383 0 : 2853 => Opcode::VLD4LNd8Pseudo_UPD,
7384 0 : 2854 => Opcode::VLD4LNd8_UPD,
7385 0 : 2855 => Opcode::VLD4LNq16,
7386 0 : 2856 => Opcode::VLD4LNq16Pseudo,
7387 0 : 2857 => Opcode::VLD4LNq16Pseudo_UPD,
7388 0 : 2858 => Opcode::VLD4LNq16_UPD,
7389 0 : 2859 => Opcode::VLD4LNq32,
7390 0 : 2860 => Opcode::VLD4LNq32Pseudo,
7391 0 : 2861 => Opcode::VLD4LNq32Pseudo_UPD,
7392 0 : 2862 => Opcode::VLD4LNq32_UPD,
7393 0 : 2863 => Opcode::VLD4d16,
7394 0 : 2864 => Opcode::VLD4d16Pseudo,
7395 0 : 2865 => Opcode::VLD4d16Pseudo_UPD,
7396 0 : 2866 => Opcode::VLD4d16_UPD,
7397 0 : 2867 => Opcode::VLD4d32,
7398 0 : 2868 => Opcode::VLD4d32Pseudo,
7399 0 : 2869 => Opcode::VLD4d32Pseudo_UPD,
7400 0 : 2870 => Opcode::VLD4d32_UPD,
7401 0 : 2871 => Opcode::VLD4d8,
7402 0 : 2872 => Opcode::VLD4d8Pseudo,
7403 0 : 2873 => Opcode::VLD4d8Pseudo_UPD,
7404 0 : 2874 => Opcode::VLD4d8_UPD,
7405 0 : 2875 => Opcode::VLD4q16,
7406 0 : 2876 => Opcode::VLD4q16Pseudo_UPD,
7407 0 : 2877 => Opcode::VLD4q16_UPD,
7408 0 : 2878 => Opcode::VLD4q16oddPseudo,
7409 0 : 2879 => Opcode::VLD4q16oddPseudo_UPD,
7410 0 : 2880 => Opcode::VLD4q32,
7411 0 : 2881 => Opcode::VLD4q32Pseudo_UPD,
7412 0 : 2882 => Opcode::VLD4q32_UPD,
7413 0 : 2883 => Opcode::VLD4q32oddPseudo,
7414 0 : 2884 => Opcode::VLD4q32oddPseudo_UPD,
7415 0 : 2885 => Opcode::VLD4q8,
7416 0 : 2886 => Opcode::VLD4q8Pseudo_UPD,
7417 0 : 2887 => Opcode::VLD4q8_UPD,
7418 0 : 2888 => Opcode::VLD4q8oddPseudo,
7419 0 : 2889 => Opcode::VLD4q8oddPseudo_UPD,
7420 0 : 2890 => Opcode::VLDMDDB_UPD,
7421 0 : 2891 => Opcode::VLDMDIA,
7422 0 : 2892 => Opcode::VLDMDIA_UPD,
7423 0 : 2893 => Opcode::VLDMQIA,
7424 0 : 2894 => Opcode::VLDMSDB_UPD,
7425 0 : 2895 => Opcode::VLDMSIA,
7426 0 : 2896 => Opcode::VLDMSIA_UPD,
7427 0 : 2897 => Opcode::VLDRD,
7428 0 : 2898 => Opcode::VLDRH,
7429 0 : 2899 => Opcode::VLDRS,
7430 0 : 2900 => Opcode::VLDR_FPCXTNS_off,
7431 0 : 2901 => Opcode::VLDR_FPCXTNS_post,
7432 0 : 2902 => Opcode::VLDR_FPCXTNS_pre,
7433 0 : 2903 => Opcode::VLDR_FPCXTS_off,
7434 0 : 2904 => Opcode::VLDR_FPCXTS_post,
7435 0 : 2905 => Opcode::VLDR_FPCXTS_pre,
7436 0 : 2906 => Opcode::VLDR_FPSCR_NZCVQC_off,
7437 0 : 2907 => Opcode::VLDR_FPSCR_NZCVQC_post,
7438 0 : 2908 => Opcode::VLDR_FPSCR_NZCVQC_pre,
7439 0 : 2909 => Opcode::VLDR_FPSCR_off,
7440 0 : 2910 => Opcode::VLDR_FPSCR_post,
7441 0 : 2911 => Opcode::VLDR_FPSCR_pre,
7442 0 : 2912 => Opcode::VLDR_P0_off,
7443 0 : 2913 => Opcode::VLDR_P0_post,
7444 0 : 2914 => Opcode::VLDR_P0_pre,
7445 0 : 2915 => Opcode::VLDR_VPR_off,
7446 0 : 2916 => Opcode::VLDR_VPR_post,
7447 0 : 2917 => Opcode::VLDR_VPR_pre,
7448 0 : 2918 => Opcode::VLLDM,
7449 0 : 2919 => Opcode::VLLDM_T2,
7450 0 : 2920 => Opcode::VLSTM,
7451 0 : 2921 => Opcode::VLSTM_T2,
7452 0 : 2922 => Opcode::VMAXfd,
7453 0 : 2923 => Opcode::VMAXfq,
7454 0 : 2924 => Opcode::VMAXhd,
7455 0 : 2925 => Opcode::VMAXhq,
7456 0 : 2926 => Opcode::VMAXsv16i8,
7457 0 : 2927 => Opcode::VMAXsv2i32,
7458 0 : 2928 => Opcode::VMAXsv4i16,
7459 0 : 2929 => Opcode::VMAXsv4i32,
7460 0 : 2930 => Opcode::VMAXsv8i16,
7461 0 : 2931 => Opcode::VMAXsv8i8,
7462 0 : 2932 => Opcode::VMAXuv16i8,
7463 0 : 2933 => Opcode::VMAXuv2i32,
7464 0 : 2934 => Opcode::VMAXuv4i16,
7465 0 : 2935 => Opcode::VMAXuv4i32,
7466 0 : 2936 => Opcode::VMAXuv8i16,
7467 0 : 2937 => Opcode::VMAXuv8i8,
7468 0 : 2938 => Opcode::VMINfd,
7469 0 : 2939 => Opcode::VMINfq,
7470 0 : 2940 => Opcode::VMINhd,
7471 0 : 2941 => Opcode::VMINhq,
7472 0 : 2942 => Opcode::VMINsv16i8,
7473 0 : 2943 => Opcode::VMINsv2i32,
7474 0 : 2944 => Opcode::VMINsv4i16,
7475 0 : 2945 => Opcode::VMINsv4i32,
7476 0 : 2946 => Opcode::VMINsv8i16,
7477 0 : 2947 => Opcode::VMINsv8i8,
7478 0 : 2948 => Opcode::VMINuv16i8,
7479 0 : 2949 => Opcode::VMINuv2i32,
7480 0 : 2950 => Opcode::VMINuv4i16,
7481 0 : 2951 => Opcode::VMINuv4i32,
7482 0 : 2952 => Opcode::VMINuv8i16,
7483 0 : 2953 => Opcode::VMINuv8i8,
7484 0 : 2954 => Opcode::VMLAD,
7485 0 : 2955 => Opcode::VMLAH,
7486 0 : 2956 => Opcode::VMLALslsv2i32,
7487 0 : 2957 => Opcode::VMLALslsv4i16,
7488 0 : 2958 => Opcode::VMLALsluv2i32,
7489 0 : 2959 => Opcode::VMLALsluv4i16,
7490 0 : 2960 => Opcode::VMLALsv2i64,
7491 0 : 2961 => Opcode::VMLALsv4i32,
7492 0 : 2962 => Opcode::VMLALsv8i16,
7493 0 : 2963 => Opcode::VMLALuv2i64,
7494 0 : 2964 => Opcode::VMLALuv4i32,
7495 0 : 2965 => Opcode::VMLALuv8i16,
7496 0 : 2966 => Opcode::VMLAS,
7497 0 : 2967 => Opcode::VMLAfd,
7498 0 : 2968 => Opcode::VMLAfq,
7499 0 : 2969 => Opcode::VMLAhd,
7500 0 : 2970 => Opcode::VMLAhq,
7501 0 : 2971 => Opcode::VMLAslfd,
7502 0 : 2972 => Opcode::VMLAslfq,
7503 0 : 2973 => Opcode::VMLAslhd,
7504 0 : 2974 => Opcode::VMLAslhq,
7505 0 : 2975 => Opcode::VMLAslv2i32,
7506 0 : 2976 => Opcode::VMLAslv4i16,
7507 0 : 2977 => Opcode::VMLAslv4i32,
7508 0 : 2978 => Opcode::VMLAslv8i16,
7509 0 : 2979 => Opcode::VMLAv16i8,
7510 0 : 2980 => Opcode::VMLAv2i32,
7511 0 : 2981 => Opcode::VMLAv4i16,
7512 0 : 2982 => Opcode::VMLAv4i32,
7513 0 : 2983 => Opcode::VMLAv8i16,
7514 0 : 2984 => Opcode::VMLAv8i8,
7515 0 : 2985 => Opcode::VMLSD,
7516 0 : 2986 => Opcode::VMLSH,
7517 0 : 2987 => Opcode::VMLSLslsv2i32,
7518 0 : 2988 => Opcode::VMLSLslsv4i16,
7519 0 : 2989 => Opcode::VMLSLsluv2i32,
7520 0 : 2990 => Opcode::VMLSLsluv4i16,
7521 0 : 2991 => Opcode::VMLSLsv2i64,
7522 0 : 2992 => Opcode::VMLSLsv4i32,
7523 0 : 2993 => Opcode::VMLSLsv8i16,
7524 0 : 2994 => Opcode::VMLSLuv2i64,
7525 0 : 2995 => Opcode::VMLSLuv4i32,
7526 0 : 2996 => Opcode::VMLSLuv8i16,
7527 0 : 2997 => Opcode::VMLSS,
7528 0 : 2998 => Opcode::VMLSfd,
7529 0 : 2999 => Opcode::VMLSfq,
7530 0 : 3000 => Opcode::VMLShd,
7531 0 : 3001 => Opcode::VMLShq,
7532 0 : 3002 => Opcode::VMLSslfd,
7533 0 : 3003 => Opcode::VMLSslfq,
7534 0 : 3004 => Opcode::VMLSslhd,
7535 0 : 3005 => Opcode::VMLSslhq,
7536 0 : 3006 => Opcode::VMLSslv2i32,
7537 0 : 3007 => Opcode::VMLSslv4i16,
7538 0 : 3008 => Opcode::VMLSslv4i32,
7539 0 : 3009 => Opcode::VMLSslv8i16,
7540 0 : 3010 => Opcode::VMLSv16i8,
7541 0 : 3011 => Opcode::VMLSv2i32,
7542 0 : 3012 => Opcode::VMLSv4i16,
7543 0 : 3013 => Opcode::VMLSv4i32,
7544 0 : 3014 => Opcode::VMLSv8i16,
7545 0 : 3015 => Opcode::VMLSv8i8,
7546 0 : 3016 => Opcode::VMMLA,
7547 0 : 3017 => Opcode::VMOVD,
7548 0 : 3018 => Opcode::VMOVDRR,
7549 0 : 3019 => Opcode::VMOVH,
7550 0 : 3020 => Opcode::VMOVHR,
7551 0 : 3021 => Opcode::VMOVLsv2i64,
7552 0 : 3022 => Opcode::VMOVLsv4i32,
7553 0 : 3023 => Opcode::VMOVLsv8i16,
7554 0 : 3024 => Opcode::VMOVLuv2i64,
7555 0 : 3025 => Opcode::VMOVLuv4i32,
7556 0 : 3026 => Opcode::VMOVLuv8i16,
7557 0 : 3027 => Opcode::VMOVNv2i32,
7558 0 : 3028 => Opcode::VMOVNv4i16,
7559 0 : 3029 => Opcode::VMOVNv8i8,
7560 0 : 3030 => Opcode::VMOVRH,
7561 0 : 3031 => Opcode::VMOVRRD,
7562 0 : 3032 => Opcode::VMOVRRS,
7563 0 : 3033 => Opcode::VMOVRS,
7564 0 : 3034 => Opcode::VMOVS,
7565 0 : 3035 => Opcode::VMOVSR,
7566 0 : 3036 => Opcode::VMOVSRR,
7567 0 : 3037 => Opcode::VMOVv16i8,
7568 0 : 3038 => Opcode::VMOVv1i64,
7569 0 : 3039 => Opcode::VMOVv2f32,
7570 0 : 3040 => Opcode::VMOVv2i32,
7571 0 : 3041 => Opcode::VMOVv2i64,
7572 0 : 3042 => Opcode::VMOVv4f32,
7573 0 : 3043 => Opcode::VMOVv4i16,
7574 0 : 3044 => Opcode::VMOVv4i32,
7575 0 : 3045 => Opcode::VMOVv8i16,
7576 0 : 3046 => Opcode::VMOVv8i8,
7577 0 : 3047 => Opcode::VMRS,
7578 0 : 3048 => Opcode::VMRS_FPCXTNS,
7579 0 : 3049 => Opcode::VMRS_FPCXTS,
7580 0 : 3050 => Opcode::VMRS_FPEXC,
7581 0 : 3051 => Opcode::VMRS_FPINST,
7582 0 : 3052 => Opcode::VMRS_FPINST2,
7583 0 : 3053 => Opcode::VMRS_FPSCR_NZCVQC,
7584 0 : 3054 => Opcode::VMRS_FPSID,
7585 0 : 3055 => Opcode::VMRS_MVFR0,
7586 0 : 3056 => Opcode::VMRS_MVFR1,
7587 0 : 3057 => Opcode::VMRS_MVFR2,
7588 0 : 3058 => Opcode::VMRS_P0,
7589 0 : 3059 => Opcode::VMRS_VPR,
7590 0 : 3060 => Opcode::VMSR,
7591 0 : 3061 => Opcode::VMSR_FPCXTNS,
7592 0 : 3062 => Opcode::VMSR_FPCXTS,
7593 0 : 3063 => Opcode::VMSR_FPEXC,
7594 0 : 3064 => Opcode::VMSR_FPINST,
7595 0 : 3065 => Opcode::VMSR_FPINST2,
7596 0 : 3066 => Opcode::VMSR_FPSCR_NZCVQC,
7597 0 : 3067 => Opcode::VMSR_FPSID,
7598 0 : 3068 => Opcode::VMSR_P0,
7599 0 : 3069 => Opcode::VMSR_VPR,
7600 0 : 3070 => Opcode::VMULD,
7601 0 : 3071 => Opcode::VMULH,
7602 0 : 3072 => Opcode::VMULLp64,
7603 0 : 3073 => Opcode::VMULLp8,
7604 0 : 3074 => Opcode::VMULLslsv2i32,
7605 0 : 3075 => Opcode::VMULLslsv4i16,
7606 0 : 3076 => Opcode::VMULLsluv2i32,
7607 0 : 3077 => Opcode::VMULLsluv4i16,
7608 0 : 3078 => Opcode::VMULLsv2i64,
7609 0 : 3079 => Opcode::VMULLsv4i32,
7610 0 : 3080 => Opcode::VMULLsv8i16,
7611 0 : 3081 => Opcode::VMULLuv2i64,
7612 0 : 3082 => Opcode::VMULLuv4i32,
7613 0 : 3083 => Opcode::VMULLuv8i16,
7614 0 : 3084 => Opcode::VMULS,
7615 0 : 3085 => Opcode::VMULfd,
7616 0 : 3086 => Opcode::VMULfq,
7617 0 : 3087 => Opcode::VMULhd,
7618 0 : 3088 => Opcode::VMULhq,
7619 0 : 3089 => Opcode::VMULpd,
7620 0 : 3090 => Opcode::VMULpq,
7621 0 : 3091 => Opcode::VMULslfd,
7622 0 : 3092 => Opcode::VMULslfq,
7623 0 : 3093 => Opcode::VMULslhd,
7624 0 : 3094 => Opcode::VMULslhq,
7625 0 : 3095 => Opcode::VMULslv2i32,
7626 0 : 3096 => Opcode::VMULslv4i16,
7627 0 : 3097 => Opcode::VMULslv4i32,
7628 0 : 3098 => Opcode::VMULslv8i16,
7629 0 : 3099 => Opcode::VMULv16i8,
7630 0 : 3100 => Opcode::VMULv2i32,
7631 0 : 3101 => Opcode::VMULv4i16,
7632 0 : 3102 => Opcode::VMULv4i32,
7633 0 : 3103 => Opcode::VMULv8i16,
7634 0 : 3104 => Opcode::VMULv8i8,
7635 0 : 3105 => Opcode::VMVNd,
7636 0 : 3106 => Opcode::VMVNq,
7637 0 : 3107 => Opcode::VMVNv2i32,
7638 0 : 3108 => Opcode::VMVNv4i16,
7639 0 : 3109 => Opcode::VMVNv4i32,
7640 0 : 3110 => Opcode::VMVNv8i16,
7641 0 : 3111 => Opcode::VNEGD,
7642 0 : 3112 => Opcode::VNEGH,
7643 0 : 3113 => Opcode::VNEGS,
7644 0 : 3114 => Opcode::VNEGf32q,
7645 0 : 3115 => Opcode::VNEGfd,
7646 0 : 3116 => Opcode::VNEGhd,
7647 0 : 3117 => Opcode::VNEGhq,
7648 0 : 3118 => Opcode::VNEGs16d,
7649 0 : 3119 => Opcode::VNEGs16q,
7650 0 : 3120 => Opcode::VNEGs32d,
7651 0 : 3121 => Opcode::VNEGs32q,
7652 0 : 3122 => Opcode::VNEGs8d,
7653 0 : 3123 => Opcode::VNEGs8q,
7654 0 : 3124 => Opcode::VNMLAD,
7655 0 : 3125 => Opcode::VNMLAH,
7656 0 : 3126 => Opcode::VNMLAS,
7657 0 : 3127 => Opcode::VNMLSD,
7658 0 : 3128 => Opcode::VNMLSH,
7659 0 : 3129 => Opcode::VNMLSS,
7660 0 : 3130 => Opcode::VNMULD,
7661 0 : 3131 => Opcode::VNMULH,
7662 0 : 3132 => Opcode::VNMULS,
7663 0 : 3133 => Opcode::VORNd,
7664 0 : 3134 => Opcode::VORNq,
7665 0 : 3135 => Opcode::VORRd,
7666 0 : 3136 => Opcode::VORRiv2i32,
7667 0 : 3137 => Opcode::VORRiv4i16,
7668 0 : 3138 => Opcode::VORRiv4i32,
7669 0 : 3139 => Opcode::VORRiv8i16,
7670 0 : 3140 => Opcode::VORRq,
7671 0 : 3141 => Opcode::VPADALsv16i8,
7672 0 : 3142 => Opcode::VPADALsv2i32,
7673 0 : 3143 => Opcode::VPADALsv4i16,
7674 0 : 3144 => Opcode::VPADALsv4i32,
7675 0 : 3145 => Opcode::VPADALsv8i16,
7676 0 : 3146 => Opcode::VPADALsv8i8,
7677 0 : 3147 => Opcode::VPADALuv16i8,
7678 0 : 3148 => Opcode::VPADALuv2i32,
7679 0 : 3149 => Opcode::VPADALuv4i16,
7680 0 : 3150 => Opcode::VPADALuv4i32,
7681 0 : 3151 => Opcode::VPADALuv8i16,
7682 0 : 3152 => Opcode::VPADALuv8i8,
7683 0 : 3153 => Opcode::VPADDLsv16i8,
7684 0 : 3154 => Opcode::VPADDLsv2i32,
7685 0 : 3155 => Opcode::VPADDLsv4i16,
7686 0 : 3156 => Opcode::VPADDLsv4i32,
7687 0 : 3157 => Opcode::VPADDLsv8i16,
7688 0 : 3158 => Opcode::VPADDLsv8i8,
7689 0 : 3159 => Opcode::VPADDLuv16i8,
7690 0 : 3160 => Opcode::VPADDLuv2i32,
7691 0 : 3161 => Opcode::VPADDLuv4i16,
7692 0 : 3162 => Opcode::VPADDLuv4i32,
7693 0 : 3163 => Opcode::VPADDLuv8i16,
7694 0 : 3164 => Opcode::VPADDLuv8i8,
7695 0 : 3165 => Opcode::VPADDf,
7696 0 : 3166 => Opcode::VPADDh,
7697 0 : 3167 => Opcode::VPADDi16,
7698 0 : 3168 => Opcode::VPADDi32,
7699 0 : 3169 => Opcode::VPADDi8,
7700 0 : 3170 => Opcode::VPMAXf,
7701 0 : 3171 => Opcode::VPMAXh,
7702 0 : 3172 => Opcode::VPMAXs16,
7703 0 : 3173 => Opcode::VPMAXs32,
7704 0 : 3174 => Opcode::VPMAXs8,
7705 0 : 3175 => Opcode::VPMAXu16,
7706 0 : 3176 => Opcode::VPMAXu32,
7707 0 : 3177 => Opcode::VPMAXu8,
7708 0 : 3178 => Opcode::VPMINf,
7709 0 : 3179 => Opcode::VPMINh,
7710 0 : 3180 => Opcode::VPMINs16,
7711 0 : 3181 => Opcode::VPMINs32,
7712 0 : 3182 => Opcode::VPMINs8,
7713 0 : 3183 => Opcode::VPMINu16,
7714 0 : 3184 => Opcode::VPMINu32,
7715 0 : 3185 => Opcode::VPMINu8,
7716 0 : 3186 => Opcode::VQABSv16i8,
7717 0 : 3187 => Opcode::VQABSv2i32,
7718 0 : 3188 => Opcode::VQABSv4i16,
7719 0 : 3189 => Opcode::VQABSv4i32,
7720 0 : 3190 => Opcode::VQABSv8i16,
7721 0 : 3191 => Opcode::VQABSv8i8,
7722 0 : 3192 => Opcode::VQADDsv16i8,
7723 0 : 3193 => Opcode::VQADDsv1i64,
7724 0 : 3194 => Opcode::VQADDsv2i32,
7725 0 : 3195 => Opcode::VQADDsv2i64,
7726 0 : 3196 => Opcode::VQADDsv4i16,
7727 0 : 3197 => Opcode::VQADDsv4i32,
7728 0 : 3198 => Opcode::VQADDsv8i16,
7729 0 : 3199 => Opcode::VQADDsv8i8,
7730 0 : 3200 => Opcode::VQADDuv16i8,
7731 0 : 3201 => Opcode::VQADDuv1i64,
7732 0 : 3202 => Opcode::VQADDuv2i32,
7733 0 : 3203 => Opcode::VQADDuv2i64,
7734 0 : 3204 => Opcode::VQADDuv4i16,
7735 0 : 3205 => Opcode::VQADDuv4i32,
7736 0 : 3206 => Opcode::VQADDuv8i16,
7737 0 : 3207 => Opcode::VQADDuv8i8,
7738 0 : 3208 => Opcode::VQDMLALslv2i32,
7739 0 : 3209 => Opcode::VQDMLALslv4i16,
7740 0 : 3210 => Opcode::VQDMLALv2i64,
7741 0 : 3211 => Opcode::VQDMLALv4i32,
7742 0 : 3212 => Opcode::VQDMLSLslv2i32,
7743 0 : 3213 => Opcode::VQDMLSLslv4i16,
7744 0 : 3214 => Opcode::VQDMLSLv2i64,
7745 0 : 3215 => Opcode::VQDMLSLv4i32,
7746 0 : 3216 => Opcode::VQDMULHslv2i32,
7747 0 : 3217 => Opcode::VQDMULHslv4i16,
7748 0 : 3218 => Opcode::VQDMULHslv4i32,
7749 0 : 3219 => Opcode::VQDMULHslv8i16,
7750 0 : 3220 => Opcode::VQDMULHv2i32,
7751 0 : 3221 => Opcode::VQDMULHv4i16,
7752 0 : 3222 => Opcode::VQDMULHv4i32,
7753 0 : 3223 => Opcode::VQDMULHv8i16,
7754 0 : 3224 => Opcode::VQDMULLslv2i32,
7755 0 : 3225 => Opcode::VQDMULLslv4i16,
7756 0 : 3226 => Opcode::VQDMULLv2i64,
7757 0 : 3227 => Opcode::VQDMULLv4i32,
7758 0 : 3228 => Opcode::VQMOVNsuv2i32,
7759 0 : 3229 => Opcode::VQMOVNsuv4i16,
7760 0 : 3230 => Opcode::VQMOVNsuv8i8,
7761 0 : 3231 => Opcode::VQMOVNsv2i32,
7762 0 : 3232 => Opcode::VQMOVNsv4i16,
7763 0 : 3233 => Opcode::VQMOVNsv8i8,
7764 0 : 3234 => Opcode::VQMOVNuv2i32,
7765 0 : 3235 => Opcode::VQMOVNuv4i16,
7766 0 : 3236 => Opcode::VQMOVNuv8i8,
7767 0 : 3237 => Opcode::VQNEGv16i8,
7768 0 : 3238 => Opcode::VQNEGv2i32,
7769 0 : 3239 => Opcode::VQNEGv4i16,
7770 0 : 3240 => Opcode::VQNEGv4i32,
7771 0 : 3241 => Opcode::VQNEGv8i16,
7772 0 : 3242 => Opcode::VQNEGv8i8,
7773 0 : 3243 => Opcode::VQRDMLAHslv2i32,
7774 0 : 3244 => Opcode::VQRDMLAHslv4i16,
7775 0 : 3245 => Opcode::VQRDMLAHslv4i32,
7776 0 : 3246 => Opcode::VQRDMLAHslv8i16,
7777 0 : 3247 => Opcode::VQRDMLAHv2i32,
7778 0 : 3248 => Opcode::VQRDMLAHv4i16,
7779 0 : 3249 => Opcode::VQRDMLAHv4i32,
7780 0 : 3250 => Opcode::VQRDMLAHv8i16,
7781 0 : 3251 => Opcode::VQRDMLSHslv2i32,
7782 0 : 3252 => Opcode::VQRDMLSHslv4i16,
7783 0 : 3253 => Opcode::VQRDMLSHslv4i32,
7784 0 : 3254 => Opcode::VQRDMLSHslv8i16,
7785 0 : 3255 => Opcode::VQRDMLSHv2i32,
7786 0 : 3256 => Opcode::VQRDMLSHv4i16,
7787 0 : 3257 => Opcode::VQRDMLSHv4i32,
7788 0 : 3258 => Opcode::VQRDMLSHv8i16,
7789 0 : 3259 => Opcode::VQRDMULHslv2i32,
7790 0 : 3260 => Opcode::VQRDMULHslv4i16,
7791 0 : 3261 => Opcode::VQRDMULHslv4i32,
7792 0 : 3262 => Opcode::VQRDMULHslv8i16,
7793 0 : 3263 => Opcode::VQRDMULHv2i32,
7794 0 : 3264 => Opcode::VQRDMULHv4i16,
7795 0 : 3265 => Opcode::VQRDMULHv4i32,
7796 0 : 3266 => Opcode::VQRDMULHv8i16,
7797 0 : 3267 => Opcode::VQRSHLsv16i8,
7798 0 : 3268 => Opcode::VQRSHLsv1i64,
7799 0 : 3269 => Opcode::VQRSHLsv2i32,
7800 0 : 3270 => Opcode::VQRSHLsv2i64,
7801 0 : 3271 => Opcode::VQRSHLsv4i16,
7802 0 : 3272 => Opcode::VQRSHLsv4i32,
7803 0 : 3273 => Opcode::VQRSHLsv8i16,
7804 0 : 3274 => Opcode::VQRSHLsv8i8,
7805 0 : 3275 => Opcode::VQRSHLuv16i8,
7806 0 : 3276 => Opcode::VQRSHLuv1i64,
7807 0 : 3277 => Opcode::VQRSHLuv2i32,
7808 0 : 3278 => Opcode::VQRSHLuv2i64,
7809 0 : 3279 => Opcode::VQRSHLuv4i16,
7810 0 : 3280 => Opcode::VQRSHLuv4i32,
7811 0 : 3281 => Opcode::VQRSHLuv8i16,
7812 0 : 3282 => Opcode::VQRSHLuv8i8,
7813 0 : 3283 => Opcode::VQRSHRNsv2i32,
7814 0 : 3284 => Opcode::VQRSHRNsv4i16,
7815 0 : 3285 => Opcode::VQRSHRNsv8i8,
7816 0 : 3286 => Opcode::VQRSHRNuv2i32,
7817 0 : 3287 => Opcode::VQRSHRNuv4i16,
7818 0 : 3288 => Opcode::VQRSHRNuv8i8,
7819 0 : 3289 => Opcode::VQRSHRUNv2i32,
7820 0 : 3290 => Opcode::VQRSHRUNv4i16,
7821 0 : 3291 => Opcode::VQRSHRUNv8i8,
7822 0 : 3292 => Opcode::VQSHLsiv16i8,
7823 0 : 3293 => Opcode::VQSHLsiv1i64,
7824 0 : 3294 => Opcode::VQSHLsiv2i32,
7825 0 : 3295 => Opcode::VQSHLsiv2i64,
7826 0 : 3296 => Opcode::VQSHLsiv4i16,
7827 0 : 3297 => Opcode::VQSHLsiv4i32,
7828 0 : 3298 => Opcode::VQSHLsiv8i16,
7829 0 : 3299 => Opcode::VQSHLsiv8i8,
7830 0 : 3300 => Opcode::VQSHLsuv16i8,
7831 0 : 3301 => Opcode::VQSHLsuv1i64,
7832 0 : 3302 => Opcode::VQSHLsuv2i32,
7833 0 : 3303 => Opcode::VQSHLsuv2i64,
7834 0 : 3304 => Opcode::VQSHLsuv4i16,
7835 0 : 3305 => Opcode::VQSHLsuv4i32,
7836 0 : 3306 => Opcode::VQSHLsuv8i16,
7837 0 : 3307 => Opcode::VQSHLsuv8i8,
7838 0 : 3308 => Opcode::VQSHLsv16i8,
7839 0 : 3309 => Opcode::VQSHLsv1i64,
7840 0 : 3310 => Opcode::VQSHLsv2i32,
7841 0 : 3311 => Opcode::VQSHLsv2i64,
7842 0 : 3312 => Opcode::VQSHLsv4i16,
7843 0 : 3313 => Opcode::VQSHLsv4i32,
7844 0 : 3314 => Opcode::VQSHLsv8i16,
7845 0 : 3315 => Opcode::VQSHLsv8i8,
7846 0 : 3316 => Opcode::VQSHLuiv16i8,
7847 0 : 3317 => Opcode::VQSHLuiv1i64,
7848 0 : 3318 => Opcode::VQSHLuiv2i32,
7849 0 : 3319 => Opcode::VQSHLuiv2i64,
7850 0 : 3320 => Opcode::VQSHLuiv4i16,
7851 0 : 3321 => Opcode::VQSHLuiv4i32,
7852 0 : 3322 => Opcode::VQSHLuiv8i16,
7853 0 : 3323 => Opcode::VQSHLuiv8i8,
7854 0 : 3324 => Opcode::VQSHLuv16i8,
7855 0 : 3325 => Opcode::VQSHLuv1i64,
7856 0 : 3326 => Opcode::VQSHLuv2i32,
7857 0 : 3327 => Opcode::VQSHLuv2i64,
7858 0 : 3328 => Opcode::VQSHLuv4i16,
7859 0 : 3329 => Opcode::VQSHLuv4i32,
7860 0 : 3330 => Opcode::VQSHLuv8i16,
7861 0 : 3331 => Opcode::VQSHLuv8i8,
7862 0 : 3332 => Opcode::VQSHRNsv2i32,
7863 0 : 3333 => Opcode::VQSHRNsv4i16,
7864 0 : 3334 => Opcode::VQSHRNsv8i8,
7865 0 : 3335 => Opcode::VQSHRNuv2i32,
7866 0 : 3336 => Opcode::VQSHRNuv4i16,
7867 0 : 3337 => Opcode::VQSHRNuv8i8,
7868 0 : 3338 => Opcode::VQSHRUNv2i32,
7869 0 : 3339 => Opcode::VQSHRUNv4i16,
7870 0 : 3340 => Opcode::VQSHRUNv8i8,
7871 0 : 3341 => Opcode::VQSUBsv16i8,
7872 0 : 3342 => Opcode::VQSUBsv1i64,
7873 0 : 3343 => Opcode::VQSUBsv2i32,
7874 0 : 3344 => Opcode::VQSUBsv2i64,
7875 0 : 3345 => Opcode::VQSUBsv4i16,
7876 0 : 3346 => Opcode::VQSUBsv4i32,
7877 0 : 3347 => Opcode::VQSUBsv8i16,
7878 0 : 3348 => Opcode::VQSUBsv8i8,
7879 0 : 3349 => Opcode::VQSUBuv16i8,
7880 0 : 3350 => Opcode::VQSUBuv1i64,
7881 0 : 3351 => Opcode::VQSUBuv2i32,
7882 0 : 3352 => Opcode::VQSUBuv2i64,
7883 0 : 3353 => Opcode::VQSUBuv4i16,
7884 0 : 3354 => Opcode::VQSUBuv4i32,
7885 0 : 3355 => Opcode::VQSUBuv8i16,
7886 0 : 3356 => Opcode::VQSUBuv8i8,
7887 0 : 3357 => Opcode::VRADDHNv2i32,
7888 0 : 3358 => Opcode::VRADDHNv4i16,
7889 0 : 3359 => Opcode::VRADDHNv8i8,
7890 0 : 3360 => Opcode::VRECPEd,
7891 0 : 3361 => Opcode::VRECPEfd,
7892 0 : 3362 => Opcode::VRECPEfq,
7893 0 : 3363 => Opcode::VRECPEhd,
7894 0 : 3364 => Opcode::VRECPEhq,
7895 0 : 3365 => Opcode::VRECPEq,
7896 0 : 3366 => Opcode::VRECPSfd,
7897 0 : 3367 => Opcode::VRECPSfq,
7898 0 : 3368 => Opcode::VRECPShd,
7899 0 : 3369 => Opcode::VRECPShq,
7900 0 : 3370 => Opcode::VREV16d8,
7901 0 : 3371 => Opcode::VREV16q8,
7902 0 : 3372 => Opcode::VREV32d16,
7903 0 : 3373 => Opcode::VREV32d8,
7904 0 : 3374 => Opcode::VREV32q16,
7905 0 : 3375 => Opcode::VREV32q8,
7906 0 : 3376 => Opcode::VREV64d16,
7907 0 : 3377 => Opcode::VREV64d32,
7908 0 : 3378 => Opcode::VREV64d8,
7909 0 : 3379 => Opcode::VREV64q16,
7910 0 : 3380 => Opcode::VREV64q32,
7911 0 : 3381 => Opcode::VREV64q8,
7912 0 : 3382 => Opcode::VRHADDsv16i8,
7913 0 : 3383 => Opcode::VRHADDsv2i32,
7914 0 : 3384 => Opcode::VRHADDsv4i16,
7915 0 : 3385 => Opcode::VRHADDsv4i32,
7916 0 : 3386 => Opcode::VRHADDsv8i16,
7917 0 : 3387 => Opcode::VRHADDsv8i8,
7918 0 : 3388 => Opcode::VRHADDuv16i8,
7919 0 : 3389 => Opcode::VRHADDuv2i32,
7920 0 : 3390 => Opcode::VRHADDuv4i16,
7921 0 : 3391 => Opcode::VRHADDuv4i32,
7922 0 : 3392 => Opcode::VRHADDuv8i16,
7923 0 : 3393 => Opcode::VRHADDuv8i8,
7924 0 : 3394 => Opcode::VRINTAD,
7925 0 : 3395 => Opcode::VRINTAH,
7926 0 : 3396 => Opcode::VRINTANDf,
7927 0 : 3397 => Opcode::VRINTANDh,
7928 0 : 3398 => Opcode::VRINTANQf,
7929 0 : 3399 => Opcode::VRINTANQh,
7930 0 : 3400 => Opcode::VRINTAS,
7931 0 : 3401 => Opcode::VRINTMD,
7932 0 : 3402 => Opcode::VRINTMH,
7933 0 : 3403 => Opcode::VRINTMNDf,
7934 0 : 3404 => Opcode::VRINTMNDh,
7935 0 : 3405 => Opcode::VRINTMNQf,
7936 0 : 3406 => Opcode::VRINTMNQh,
7937 0 : 3407 => Opcode::VRINTMS,
7938 0 : 3408 => Opcode::VRINTND,
7939 0 : 3409 => Opcode::VRINTNH,
7940 0 : 3410 => Opcode::VRINTNNDf,
7941 0 : 3411 => Opcode::VRINTNNDh,
7942 0 : 3412 => Opcode::VRINTNNQf,
7943 0 : 3413 => Opcode::VRINTNNQh,
7944 0 : 3414 => Opcode::VRINTNS,
7945 0 : 3415 => Opcode::VRINTPD,
7946 0 : 3416 => Opcode::VRINTPH,
7947 0 : 3417 => Opcode::VRINTPNDf,
7948 0 : 3418 => Opcode::VRINTPNDh,
7949 0 : 3419 => Opcode::VRINTPNQf,
7950 0 : 3420 => Opcode::VRINTPNQh,
7951 0 : 3421 => Opcode::VRINTPS,
7952 0 : 3422 => Opcode::VRINTRD,
7953 0 : 3423 => Opcode::VRINTRH,
7954 0 : 3424 => Opcode::VRINTRS,
7955 0 : 3425 => Opcode::VRINTXD,
7956 0 : 3426 => Opcode::VRINTXH,
7957 0 : 3427 => Opcode::VRINTXNDf,
7958 0 : 3428 => Opcode::VRINTXNDh,
7959 0 : 3429 => Opcode::VRINTXNQf,
7960 0 : 3430 => Opcode::VRINTXNQh,
7961 0 : 3431 => Opcode::VRINTXS,
7962 0 : 3432 => Opcode::VRINTZD,
7963 0 : 3433 => Opcode::VRINTZH,
7964 0 : 3434 => Opcode::VRINTZNDf,
7965 0 : 3435 => Opcode::VRINTZNDh,
7966 0 : 3436 => Opcode::VRINTZNQf,
7967 0 : 3437 => Opcode::VRINTZNQh,
7968 0 : 3438 => Opcode::VRINTZS,
7969 0 : 3439 => Opcode::VRSHLsv16i8,
7970 0 : 3440 => Opcode::VRSHLsv1i64,
7971 0 : 3441 => Opcode::VRSHLsv2i32,
7972 0 : 3442 => Opcode::VRSHLsv2i64,
7973 0 : 3443 => Opcode::VRSHLsv4i16,
7974 0 : 3444 => Opcode::VRSHLsv4i32,
7975 0 : 3445 => Opcode::VRSHLsv8i16,
7976 0 : 3446 => Opcode::VRSHLsv8i8,
7977 0 : 3447 => Opcode::VRSHLuv16i8,
7978 0 : 3448 => Opcode::VRSHLuv1i64,
7979 0 : 3449 => Opcode::VRSHLuv2i32,
7980 0 : 3450 => Opcode::VRSHLuv2i64,
7981 0 : 3451 => Opcode::VRSHLuv4i16,
7982 0 : 3452 => Opcode::VRSHLuv4i32,
7983 0 : 3453 => Opcode::VRSHLuv8i16,
7984 0 : 3454 => Opcode::VRSHLuv8i8,
7985 0 : 3455 => Opcode::VRSHRNv2i32,
7986 0 : 3456 => Opcode::VRSHRNv4i16,
7987 0 : 3457 => Opcode::VRSHRNv8i8,
7988 0 : 3458 => Opcode::VRSHRsv16i8,
7989 0 : 3459 => Opcode::VRSHRsv1i64,
7990 0 : 3460 => Opcode::VRSHRsv2i32,
7991 0 : 3461 => Opcode::VRSHRsv2i64,
7992 0 : 3462 => Opcode::VRSHRsv4i16,
7993 0 : 3463 => Opcode::VRSHRsv4i32,
7994 0 : 3464 => Opcode::VRSHRsv8i16,
7995 0 : 3465 => Opcode::VRSHRsv8i8,
7996 0 : 3466 => Opcode::VRSHRuv16i8,
7997 0 : 3467 => Opcode::VRSHRuv1i64,
7998 0 : 3468 => Opcode::VRSHRuv2i32,
7999 0 : 3469 => Opcode::VRSHRuv2i64,
8000 0 : 3470 => Opcode::VRSHRuv4i16,
8001 0 : 3471 => Opcode::VRSHRuv4i32,
8002 0 : 3472 => Opcode::VRSHRuv8i16,
8003 0 : 3473 => Opcode::VRSHRuv8i8,
8004 0 : 3474 => Opcode::VRSQRTEd,
8005 0 : 3475 => Opcode::VRSQRTEfd,
8006 0 : 3476 => Opcode::VRSQRTEfq,
8007 0 : 3477 => Opcode::VRSQRTEhd,
8008 0 : 3478 => Opcode::VRSQRTEhq,
8009 0 : 3479 => Opcode::VRSQRTEq,
8010 0 : 3480 => Opcode::VRSQRTSfd,
8011 0 : 3481 => Opcode::VRSQRTSfq,
8012 0 : 3482 => Opcode::VRSQRTShd,
8013 0 : 3483 => Opcode::VRSQRTShq,
8014 0 : 3484 => Opcode::VRSRAsv16i8,
8015 0 : 3485 => Opcode::VRSRAsv1i64,
8016 0 : 3486 => Opcode::VRSRAsv2i32,
8017 0 : 3487 => Opcode::VRSRAsv2i64,
8018 0 : 3488 => Opcode::VRSRAsv4i16,
8019 0 : 3489 => Opcode::VRSRAsv4i32,
8020 0 : 3490 => Opcode::VRSRAsv8i16,
8021 0 : 3491 => Opcode::VRSRAsv8i8,
8022 0 : 3492 => Opcode::VRSRAuv16i8,
8023 0 : 3493 => Opcode::VRSRAuv1i64,
8024 0 : 3494 => Opcode::VRSRAuv2i32,
8025 0 : 3495 => Opcode::VRSRAuv2i64,
8026 0 : 3496 => Opcode::VRSRAuv4i16,
8027 0 : 3497 => Opcode::VRSRAuv4i32,
8028 0 : 3498 => Opcode::VRSRAuv8i16,
8029 0 : 3499 => Opcode::VRSRAuv8i8,
8030 0 : 3500 => Opcode::VRSUBHNv2i32,
8031 0 : 3501 => Opcode::VRSUBHNv4i16,
8032 0 : 3502 => Opcode::VRSUBHNv8i8,
8033 0 : 3503 => Opcode::VSCCLRMD,
8034 0 : 3504 => Opcode::VSCCLRMS,
8035 0 : 3505 => Opcode::VSDOTD,
8036 0 : 3506 => Opcode::VSDOTDI,
8037 0 : 3507 => Opcode::VSDOTQ,
8038 0 : 3508 => Opcode::VSDOTQI,
8039 0 : 3509 => Opcode::VSELEQD,
8040 0 : 3510 => Opcode::VSELEQH,
8041 0 : 3511 => Opcode::VSELEQS,
8042 0 : 3512 => Opcode::VSELGED,
8043 0 : 3513 => Opcode::VSELGEH,
8044 0 : 3514 => Opcode::VSELGES,
8045 0 : 3515 => Opcode::VSELGTD,
8046 0 : 3516 => Opcode::VSELGTH,
8047 0 : 3517 => Opcode::VSELGTS,
8048 0 : 3518 => Opcode::VSELVSD,
8049 0 : 3519 => Opcode::VSELVSH,
8050 0 : 3520 => Opcode::VSELVSS,
8051 0 : 3521 => Opcode::VSETLNi16,
8052 0 : 3522 => Opcode::VSETLNi32,
8053 0 : 3523 => Opcode::VSETLNi8,
8054 0 : 3524 => Opcode::VSHLLi16,
8055 0 : 3525 => Opcode::VSHLLi32,
8056 0 : 3526 => Opcode::VSHLLi8,
8057 0 : 3527 => Opcode::VSHLLsv2i64,
8058 0 : 3528 => Opcode::VSHLLsv4i32,
8059 0 : 3529 => Opcode::VSHLLsv8i16,
8060 0 : 3530 => Opcode::VSHLLuv2i64,
8061 0 : 3531 => Opcode::VSHLLuv4i32,
8062 0 : 3532 => Opcode::VSHLLuv8i16,
8063 0 : 3533 => Opcode::VSHLiv16i8,
8064 0 : 3534 => Opcode::VSHLiv1i64,
8065 0 : 3535 => Opcode::VSHLiv2i32,
8066 0 : 3536 => Opcode::VSHLiv2i64,
8067 0 : 3537 => Opcode::VSHLiv4i16,
8068 0 : 3538 => Opcode::VSHLiv4i32,
8069 0 : 3539 => Opcode::VSHLiv8i16,
8070 0 : 3540 => Opcode::VSHLiv8i8,
8071 0 : 3541 => Opcode::VSHLsv16i8,
8072 0 : 3542 => Opcode::VSHLsv1i64,
8073 0 : 3543 => Opcode::VSHLsv2i32,
8074 0 : 3544 => Opcode::VSHLsv2i64,
8075 0 : 3545 => Opcode::VSHLsv4i16,
8076 0 : 3546 => Opcode::VSHLsv4i32,
8077 0 : 3547 => Opcode::VSHLsv8i16,
8078 0 : 3548 => Opcode::VSHLsv8i8,
8079 0 : 3549 => Opcode::VSHLuv16i8,
8080 0 : 3550 => Opcode::VSHLuv1i64,
8081 0 : 3551 => Opcode::VSHLuv2i32,
8082 0 : 3552 => Opcode::VSHLuv2i64,
8083 0 : 3553 => Opcode::VSHLuv4i16,
8084 0 : 3554 => Opcode::VSHLuv4i32,
8085 0 : 3555 => Opcode::VSHLuv8i16,
8086 0 : 3556 => Opcode::VSHLuv8i8,
8087 0 : 3557 => Opcode::VSHRNv2i32,
8088 0 : 3558 => Opcode::VSHRNv4i16,
8089 0 : 3559 => Opcode::VSHRNv8i8,
8090 0 : 3560 => Opcode::VSHRsv16i8,
8091 0 : 3561 => Opcode::VSHRsv1i64,
8092 0 : 3562 => Opcode::VSHRsv2i32,
8093 0 : 3563 => Opcode::VSHRsv2i64,
8094 0 : 3564 => Opcode::VSHRsv4i16,
8095 0 : 3565 => Opcode::VSHRsv4i32,
8096 0 : 3566 => Opcode::VSHRsv8i16,
8097 0 : 3567 => Opcode::VSHRsv8i8,
8098 0 : 3568 => Opcode::VSHRuv16i8,
8099 0 : 3569 => Opcode::VSHRuv1i64,
8100 0 : 3570 => Opcode::VSHRuv2i32,
8101 0 : 3571 => Opcode::VSHRuv2i64,
8102 0 : 3572 => Opcode::VSHRuv4i16,
8103 0 : 3573 => Opcode::VSHRuv4i32,
8104 0 : 3574 => Opcode::VSHRuv8i16,
8105 0 : 3575 => Opcode::VSHRuv8i8,
8106 0 : 3576 => Opcode::VSHTOD,
8107 0 : 3577 => Opcode::VSHTOH,
8108 0 : 3578 => Opcode::VSHTOS,
8109 0 : 3579 => Opcode::VSITOD,
8110 0 : 3580 => Opcode::VSITOH,
8111 0 : 3581 => Opcode::VSITOS,
8112 0 : 3582 => Opcode::VSLIv16i8,
8113 0 : 3583 => Opcode::VSLIv1i64,
8114 0 : 3584 => Opcode::VSLIv2i32,
8115 0 : 3585 => Opcode::VSLIv2i64,
8116 0 : 3586 => Opcode::VSLIv4i16,
8117 0 : 3587 => Opcode::VSLIv4i32,
8118 0 : 3588 => Opcode::VSLIv8i16,
8119 0 : 3589 => Opcode::VSLIv8i8,
8120 0 : 3590 => Opcode::VSLTOD,
8121 0 : 3591 => Opcode::VSLTOH,
8122 0 : 3592 => Opcode::VSLTOS,
8123 0 : 3593 => Opcode::VSMMLA,
8124 0 : 3594 => Opcode::VSQRTD,
8125 0 : 3595 => Opcode::VSQRTH,
8126 0 : 3596 => Opcode::VSQRTS,
8127 0 : 3597 => Opcode::VSRAsv16i8,
8128 0 : 3598 => Opcode::VSRAsv1i64,
8129 0 : 3599 => Opcode::VSRAsv2i32,
8130 0 : 3600 => Opcode::VSRAsv2i64,
8131 0 : 3601 => Opcode::VSRAsv4i16,
8132 0 : 3602 => Opcode::VSRAsv4i32,
8133 0 : 3603 => Opcode::VSRAsv8i16,
8134 0 : 3604 => Opcode::VSRAsv8i8,
8135 0 : 3605 => Opcode::VSRAuv16i8,
8136 0 : 3606 => Opcode::VSRAuv1i64,
8137 0 : 3607 => Opcode::VSRAuv2i32,
8138 0 : 3608 => Opcode::VSRAuv2i64,
8139 0 : 3609 => Opcode::VSRAuv4i16,
8140 0 : 3610 => Opcode::VSRAuv4i32,
8141 0 : 3611 => Opcode::VSRAuv8i16,
8142 0 : 3612 => Opcode::VSRAuv8i8,
8143 0 : 3613 => Opcode::VSRIv16i8,
8144 0 : 3614 => Opcode::VSRIv1i64,
8145 0 : 3615 => Opcode::VSRIv2i32,
8146 0 : 3616 => Opcode::VSRIv2i64,
8147 0 : 3617 => Opcode::VSRIv4i16,
8148 0 : 3618 => Opcode::VSRIv4i32,
8149 0 : 3619 => Opcode::VSRIv8i16,
8150 0 : 3620 => Opcode::VSRIv8i8,
8151 0 : 3621 => Opcode::VST1LNd16,
8152 0 : 3622 => Opcode::VST1LNd16_UPD,
8153 0 : 3623 => Opcode::VST1LNd32,
8154 0 : 3624 => Opcode::VST1LNd32_UPD,
8155 0 : 3625 => Opcode::VST1LNd8,
8156 0 : 3626 => Opcode::VST1LNd8_UPD,
8157 0 : 3627 => Opcode::VST1LNq16Pseudo,
8158 0 : 3628 => Opcode::VST1LNq16Pseudo_UPD,
8159 0 : 3629 => Opcode::VST1LNq32Pseudo,
8160 0 : 3630 => Opcode::VST1LNq32Pseudo_UPD,
8161 0 : 3631 => Opcode::VST1LNq8Pseudo,
8162 0 : 3632 => Opcode::VST1LNq8Pseudo_UPD,
8163 0 : 3633 => Opcode::VST1d16,
8164 0 : 3634 => Opcode::VST1d16Q,
8165 0 : 3635 => Opcode::VST1d16QPseudo,
8166 0 : 3636 => Opcode::VST1d16QPseudoWB_fixed,
8167 0 : 3637 => Opcode::VST1d16QPseudoWB_register,
8168 0 : 3638 => Opcode::VST1d16Qwb_fixed,
8169 0 : 3639 => Opcode::VST1d16Qwb_register,
8170 0 : 3640 => Opcode::VST1d16T,
8171 0 : 3641 => Opcode::VST1d16TPseudo,
8172 0 : 3642 => Opcode::VST1d16TPseudoWB_fixed,
8173 0 : 3643 => Opcode::VST1d16TPseudoWB_register,
8174 0 : 3644 => Opcode::VST1d16Twb_fixed,
8175 0 : 3645 => Opcode::VST1d16Twb_register,
8176 0 : 3646 => Opcode::VST1d16wb_fixed,
8177 0 : 3647 => Opcode::VST1d16wb_register,
8178 0 : 3648 => Opcode::VST1d32,
8179 0 : 3649 => Opcode::VST1d32Q,
8180 0 : 3650 => Opcode::VST1d32QPseudo,
8181 0 : 3651 => Opcode::VST1d32QPseudoWB_fixed,
8182 0 : 3652 => Opcode::VST1d32QPseudoWB_register,
8183 0 : 3653 => Opcode::VST1d32Qwb_fixed,
8184 0 : 3654 => Opcode::VST1d32Qwb_register,
8185 0 : 3655 => Opcode::VST1d32T,
8186 0 : 3656 => Opcode::VST1d32TPseudo,
8187 0 : 3657 => Opcode::VST1d32TPseudoWB_fixed,
8188 0 : 3658 => Opcode::VST1d32TPseudoWB_register,
8189 0 : 3659 => Opcode::VST1d32Twb_fixed,
8190 0 : 3660 => Opcode::VST1d32Twb_register,
8191 0 : 3661 => Opcode::VST1d32wb_fixed,
8192 0 : 3662 => Opcode::VST1d32wb_register,
8193 0 : 3663 => Opcode::VST1d64,
8194 0 : 3664 => Opcode::VST1d64Q,
8195 0 : 3665 => Opcode::VST1d64QPseudo,
8196 0 : 3666 => Opcode::VST1d64QPseudoWB_fixed,
8197 0 : 3667 => Opcode::VST1d64QPseudoWB_register,
8198 0 : 3668 => Opcode::VST1d64Qwb_fixed,
8199 0 : 3669 => Opcode::VST1d64Qwb_register,
8200 0 : 3670 => Opcode::VST1d64T,
8201 0 : 3671 => Opcode::VST1d64TPseudo,
8202 0 : 3672 => Opcode::VST1d64TPseudoWB_fixed,
8203 0 : 3673 => Opcode::VST1d64TPseudoWB_register,
8204 0 : 3674 => Opcode::VST1d64Twb_fixed,
8205 0 : 3675 => Opcode::VST1d64Twb_register,
8206 0 : 3676 => Opcode::VST1d64wb_fixed,
8207 0 : 3677 => Opcode::VST1d64wb_register,
8208 0 : 3678 => Opcode::VST1d8,
8209 0 : 3679 => Opcode::VST1d8Q,
8210 0 : 3680 => Opcode::VST1d8QPseudo,
8211 0 : 3681 => Opcode::VST1d8QPseudoWB_fixed,
8212 0 : 3682 => Opcode::VST1d8QPseudoWB_register,
8213 0 : 3683 => Opcode::VST1d8Qwb_fixed,
8214 0 : 3684 => Opcode::VST1d8Qwb_register,
8215 0 : 3685 => Opcode::VST1d8T,
8216 0 : 3686 => Opcode::VST1d8TPseudo,
8217 0 : 3687 => Opcode::VST1d8TPseudoWB_fixed,
8218 0 : 3688 => Opcode::VST1d8TPseudoWB_register,
8219 0 : 3689 => Opcode::VST1d8Twb_fixed,
8220 0 : 3690 => Opcode::VST1d8Twb_register,
8221 0 : 3691 => Opcode::VST1d8wb_fixed,
8222 0 : 3692 => Opcode::VST1d8wb_register,
8223 0 : 3693 => Opcode::VST1q16,
8224 0 : 3694 => Opcode::VST1q16HighQPseudo,
8225 0 : 3695 => Opcode::VST1q16HighQPseudo_UPD,
8226 0 : 3696 => Opcode::VST1q16HighTPseudo,
8227 0 : 3697 => Opcode::VST1q16HighTPseudo_UPD,
8228 0 : 3698 => Opcode::VST1q16LowQPseudo_UPD,
8229 0 : 3699 => Opcode::VST1q16LowTPseudo_UPD,
8230 0 : 3700 => Opcode::VST1q16wb_fixed,
8231 0 : 3701 => Opcode::VST1q16wb_register,
8232 0 : 3702 => Opcode::VST1q32,
8233 0 : 3703 => Opcode::VST1q32HighQPseudo,
8234 0 : 3704 => Opcode::VST1q32HighQPseudo_UPD,
8235 0 : 3705 => Opcode::VST1q32HighTPseudo,
8236 0 : 3706 => Opcode::VST1q32HighTPseudo_UPD,
8237 0 : 3707 => Opcode::VST1q32LowQPseudo_UPD,
8238 0 : 3708 => Opcode::VST1q32LowTPseudo_UPD,
8239 0 : 3709 => Opcode::VST1q32wb_fixed,
8240 0 : 3710 => Opcode::VST1q32wb_register,
8241 0 : 3711 => Opcode::VST1q64,
8242 0 : 3712 => Opcode::VST1q64HighQPseudo,
8243 0 : 3713 => Opcode::VST1q64HighQPseudo_UPD,
8244 0 : 3714 => Opcode::VST1q64HighTPseudo,
8245 0 : 3715 => Opcode::VST1q64HighTPseudo_UPD,
8246 0 : 3716 => Opcode::VST1q64LowQPseudo_UPD,
8247 0 : 3717 => Opcode::VST1q64LowTPseudo_UPD,
8248 0 : 3718 => Opcode::VST1q64wb_fixed,
8249 0 : 3719 => Opcode::VST1q64wb_register,
8250 0 : 3720 => Opcode::VST1q8,
8251 0 : 3721 => Opcode::VST1q8HighQPseudo,
8252 0 : 3722 => Opcode::VST1q8HighQPseudo_UPD,
8253 0 : 3723 => Opcode::VST1q8HighTPseudo,
8254 0 : 3724 => Opcode::VST1q8HighTPseudo_UPD,
8255 0 : 3725 => Opcode::VST1q8LowQPseudo_UPD,
8256 0 : 3726 => Opcode::VST1q8LowTPseudo_UPD,
8257 0 : 3727 => Opcode::VST1q8wb_fixed,
8258 0 : 3728 => Opcode::VST1q8wb_register,
8259 0 : 3729 => Opcode::VST2LNd16,
8260 0 : 3730 => Opcode::VST2LNd16Pseudo,
8261 0 : 3731 => Opcode::VST2LNd16Pseudo_UPD,
8262 0 : 3732 => Opcode::VST2LNd16_UPD,
8263 0 : 3733 => Opcode::VST2LNd32,
8264 0 : 3734 => Opcode::VST2LNd32Pseudo,
8265 0 : 3735 => Opcode::VST2LNd32Pseudo_UPD,
8266 0 : 3736 => Opcode::VST2LNd32_UPD,
8267 0 : 3737 => Opcode::VST2LNd8,
8268 0 : 3738 => Opcode::VST2LNd8Pseudo,
8269 0 : 3739 => Opcode::VST2LNd8Pseudo_UPD,
8270 0 : 3740 => Opcode::VST2LNd8_UPD,
8271 0 : 3741 => Opcode::VST2LNq16,
8272 0 : 3742 => Opcode::VST2LNq16Pseudo,
8273 0 : 3743 => Opcode::VST2LNq16Pseudo_UPD,
8274 0 : 3744 => Opcode::VST2LNq16_UPD,
8275 0 : 3745 => Opcode::VST2LNq32,
8276 0 : 3746 => Opcode::VST2LNq32Pseudo,
8277 0 : 3747 => Opcode::VST2LNq32Pseudo_UPD,
8278 0 : 3748 => Opcode::VST2LNq32_UPD,
8279 0 : 3749 => Opcode::VST2b16,
8280 0 : 3750 => Opcode::VST2b16wb_fixed,
8281 0 : 3751 => Opcode::VST2b16wb_register,
8282 0 : 3752 => Opcode::VST2b32,
8283 0 : 3753 => Opcode::VST2b32wb_fixed,
8284 0 : 3754 => Opcode::VST2b32wb_register,
8285 0 : 3755 => Opcode::VST2b8,
8286 0 : 3756 => Opcode::VST2b8wb_fixed,
8287 0 : 3757 => Opcode::VST2b8wb_register,
8288 0 : 3758 => Opcode::VST2d16,
8289 0 : 3759 => Opcode::VST2d16wb_fixed,
8290 0 : 3760 => Opcode::VST2d16wb_register,
8291 0 : 3761 => Opcode::VST2d32,
8292 0 : 3762 => Opcode::VST2d32wb_fixed,
8293 0 : 3763 => Opcode::VST2d32wb_register,
8294 0 : 3764 => Opcode::VST2d8,
8295 0 : 3765 => Opcode::VST2d8wb_fixed,
8296 0 : 3766 => Opcode::VST2d8wb_register,
8297 0 : 3767 => Opcode::VST2q16,
8298 0 : 3768 => Opcode::VST2q16Pseudo,
8299 0 : 3769 => Opcode::VST2q16PseudoWB_fixed,
8300 0 : 3770 => Opcode::VST2q16PseudoWB_register,
8301 0 : 3771 => Opcode::VST2q16wb_fixed,
8302 0 : 3772 => Opcode::VST2q16wb_register,
8303 0 : 3773 => Opcode::VST2q32,
8304 0 : 3774 => Opcode::VST2q32Pseudo,
8305 0 : 3775 => Opcode::VST2q32PseudoWB_fixed,
8306 0 : 3776 => Opcode::VST2q32PseudoWB_register,
8307 0 : 3777 => Opcode::VST2q32wb_fixed,
8308 0 : 3778 => Opcode::VST2q32wb_register,
8309 0 : 3779 => Opcode::VST2q8,
8310 0 : 3780 => Opcode::VST2q8Pseudo,
8311 0 : 3781 => Opcode::VST2q8PseudoWB_fixed,
8312 0 : 3782 => Opcode::VST2q8PseudoWB_register,
8313 0 : 3783 => Opcode::VST2q8wb_fixed,
8314 0 : 3784 => Opcode::VST2q8wb_register,
8315 0 : 3785 => Opcode::VST3LNd16,
8316 0 : 3786 => Opcode::VST3LNd16Pseudo,
8317 0 : 3787 => Opcode::VST3LNd16Pseudo_UPD,
8318 0 : 3788 => Opcode::VST3LNd16_UPD,
8319 0 : 3789 => Opcode::VST3LNd32,
8320 0 : 3790 => Opcode::VST3LNd32Pseudo,
8321 0 : 3791 => Opcode::VST3LNd32Pseudo_UPD,
8322 0 : 3792 => Opcode::VST3LNd32_UPD,
8323 0 : 3793 => Opcode::VST3LNd8,
8324 0 : 3794 => Opcode::VST3LNd8Pseudo,
8325 0 : 3795 => Opcode::VST3LNd8Pseudo_UPD,
8326 0 : 3796 => Opcode::VST3LNd8_UPD,
8327 0 : 3797 => Opcode::VST3LNq16,
8328 0 : 3798 => Opcode::VST3LNq16Pseudo,
8329 0 : 3799 => Opcode::VST3LNq16Pseudo_UPD,
8330 0 : 3800 => Opcode::VST3LNq16_UPD,
8331 0 : 3801 => Opcode::VST3LNq32,
8332 0 : 3802 => Opcode::VST3LNq32Pseudo,
8333 0 : 3803 => Opcode::VST3LNq32Pseudo_UPD,
8334 0 : 3804 => Opcode::VST3LNq32_UPD,
8335 0 : 3805 => Opcode::VST3d16,
8336 0 : 3806 => Opcode::VST3d16Pseudo,
8337 0 : 3807 => Opcode::VST3d16Pseudo_UPD,
8338 0 : 3808 => Opcode::VST3d16_UPD,
8339 0 : 3809 => Opcode::VST3d32,
8340 0 : 3810 => Opcode::VST3d32Pseudo,
8341 0 : 3811 => Opcode::VST3d32Pseudo_UPD,
8342 0 : 3812 => Opcode::VST3d32_UPD,
8343 0 : 3813 => Opcode::VST3d8,
8344 0 : 3814 => Opcode::VST3d8Pseudo,
8345 0 : 3815 => Opcode::VST3d8Pseudo_UPD,
8346 0 : 3816 => Opcode::VST3d8_UPD,
8347 0 : 3817 => Opcode::VST3q16,
8348 0 : 3818 => Opcode::VST3q16Pseudo_UPD,
8349 0 : 3819 => Opcode::VST3q16_UPD,
8350 0 : 3820 => Opcode::VST3q16oddPseudo,
8351 0 : 3821 => Opcode::VST3q16oddPseudo_UPD,
8352 0 : 3822 => Opcode::VST3q32,
8353 0 : 3823 => Opcode::VST3q32Pseudo_UPD,
8354 0 : 3824 => Opcode::VST3q32_UPD,
8355 0 : 3825 => Opcode::VST3q32oddPseudo,
8356 0 : 3826 => Opcode::VST3q32oddPseudo_UPD,
8357 0 : 3827 => Opcode::VST3q8,
8358 0 : 3828 => Opcode::VST3q8Pseudo_UPD,
8359 0 : 3829 => Opcode::VST3q8_UPD,
8360 0 : 3830 => Opcode::VST3q8oddPseudo,
8361 0 : 3831 => Opcode::VST3q8oddPseudo_UPD,
8362 0 : 3832 => Opcode::VST4LNd16,
8363 0 : 3833 => Opcode::VST4LNd16Pseudo,
8364 0 : 3834 => Opcode::VST4LNd16Pseudo_UPD,
8365 0 : 3835 => Opcode::VST4LNd16_UPD,
8366 0 : 3836 => Opcode::VST4LNd32,
8367 0 : 3837 => Opcode::VST4LNd32Pseudo,
8368 0 : 3838 => Opcode::VST4LNd32Pseudo_UPD,
8369 0 : 3839 => Opcode::VST4LNd32_UPD,
8370 0 : 3840 => Opcode::VST4LNd8,
8371 0 : 3841 => Opcode::VST4LNd8Pseudo,
8372 0 : 3842 => Opcode::VST4LNd8Pseudo_UPD,
8373 0 : 3843 => Opcode::VST4LNd8_UPD,
8374 0 : 3844 => Opcode::VST4LNq16,
8375 0 : 3845 => Opcode::VST4LNq16Pseudo,
8376 0 : 3846 => Opcode::VST4LNq16Pseudo_UPD,
8377 0 : 3847 => Opcode::VST4LNq16_UPD,
8378 0 : 3848 => Opcode::VST4LNq32,
8379 0 : 3849 => Opcode::VST4LNq32Pseudo,
8380 0 : 3850 => Opcode::VST4LNq32Pseudo_UPD,
8381 0 : 3851 => Opcode::VST4LNq32_UPD,
8382 0 : 3852 => Opcode::VST4d16,
8383 0 : 3853 => Opcode::VST4d16Pseudo,
8384 0 : 3854 => Opcode::VST4d16Pseudo_UPD,
8385 0 : 3855 => Opcode::VST4d16_UPD,
8386 0 : 3856 => Opcode::VST4d32,
8387 0 : 3857 => Opcode::VST4d32Pseudo,
8388 0 : 3858 => Opcode::VST4d32Pseudo_UPD,
8389 0 : 3859 => Opcode::VST4d32_UPD,
8390 0 : 3860 => Opcode::VST4d8,
8391 0 : 3861 => Opcode::VST4d8Pseudo,
8392 0 : 3862 => Opcode::VST4d8Pseudo_UPD,
8393 0 : 3863 => Opcode::VST4d8_UPD,
8394 0 : 3864 => Opcode::VST4q16,
8395 0 : 3865 => Opcode::VST4q16Pseudo_UPD,
8396 0 : 3866 => Opcode::VST4q16_UPD,
8397 0 : 3867 => Opcode::VST4q16oddPseudo,
8398 0 : 3868 => Opcode::VST4q16oddPseudo_UPD,
8399 0 : 3869 => Opcode::VST4q32,
8400 0 : 3870 => Opcode::VST4q32Pseudo_UPD,
8401 0 : 3871 => Opcode::VST4q32_UPD,
8402 0 : 3872 => Opcode::VST4q32oddPseudo,
8403 0 : 3873 => Opcode::VST4q32oddPseudo_UPD,
8404 0 : 3874 => Opcode::VST4q8,
8405 0 : 3875 => Opcode::VST4q8Pseudo_UPD,
8406 0 : 3876 => Opcode::VST4q8_UPD,
8407 0 : 3877 => Opcode::VST4q8oddPseudo,
8408 0 : 3878 => Opcode::VST4q8oddPseudo_UPD,
8409 0 : 3879 => Opcode::VSTMDDB_UPD,
8410 0 : 3880 => Opcode::VSTMDIA,
8411 0 : 3881 => Opcode::VSTMDIA_UPD,
8412 0 : 3882 => Opcode::VSTMQIA,
8413 0 : 3883 => Opcode::VSTMSDB_UPD,
8414 0 : 3884 => Opcode::VSTMSIA,
8415 0 : 3885 => Opcode::VSTMSIA_UPD,
8416 0 : 3886 => Opcode::VSTRD,
8417 0 : 3887 => Opcode::VSTRH,
8418 0 : 3888 => Opcode::VSTRS,
8419 0 : 3889 => Opcode::VSTR_FPCXTNS_off,
8420 0 : 3890 => Opcode::VSTR_FPCXTNS_post,
8421 0 : 3891 => Opcode::VSTR_FPCXTNS_pre,
8422 0 : 3892 => Opcode::VSTR_FPCXTS_off,
8423 0 : 3893 => Opcode::VSTR_FPCXTS_post,
8424 0 : 3894 => Opcode::VSTR_FPCXTS_pre,
8425 0 : 3895 => Opcode::VSTR_FPSCR_NZCVQC_off,
8426 0 : 3896 => Opcode::VSTR_FPSCR_NZCVQC_post,
8427 0 : 3897 => Opcode::VSTR_FPSCR_NZCVQC_pre,
8428 0 : 3898 => Opcode::VSTR_FPSCR_off,
8429 0 : 3899 => Opcode::VSTR_FPSCR_post,
8430 0 : 3900 => Opcode::VSTR_FPSCR_pre,
8431 0 : 3901 => Opcode::VSTR_P0_off,
8432 0 : 3902 => Opcode::VSTR_P0_post,
8433 0 : 3903 => Opcode::VSTR_P0_pre,
8434 0 : 3904 => Opcode::VSTR_VPR_off,
8435 0 : 3905 => Opcode::VSTR_VPR_post,
8436 0 : 3906 => Opcode::VSTR_VPR_pre,
8437 0 : 3907 => Opcode::VSUBD,
8438 0 : 3908 => Opcode::VSUBH,
8439 0 : 3909 => Opcode::VSUBHNv2i32,
8440 0 : 3910 => Opcode::VSUBHNv4i16,
8441 0 : 3911 => Opcode::VSUBHNv8i8,
8442 0 : 3912 => Opcode::VSUBLsv2i64,
8443 0 : 3913 => Opcode::VSUBLsv4i32,
8444 0 : 3914 => Opcode::VSUBLsv8i16,
8445 0 : 3915 => Opcode::VSUBLuv2i64,
8446 0 : 3916 => Opcode::VSUBLuv4i32,
8447 0 : 3917 => Opcode::VSUBLuv8i16,
8448 0 : 3918 => Opcode::VSUBS,
8449 0 : 3919 => Opcode::VSUBWsv2i64,
8450 0 : 3920 => Opcode::VSUBWsv4i32,
8451 0 : 3921 => Opcode::VSUBWsv8i16,
8452 0 : 3922 => Opcode::VSUBWuv2i64,
8453 0 : 3923 => Opcode::VSUBWuv4i32,
8454 0 : 3924 => Opcode::VSUBWuv8i16,
8455 0 : 3925 => Opcode::VSUBfd,
8456 0 : 3926 => Opcode::VSUBfq,
8457 0 : 3927 => Opcode::VSUBhd,
8458 0 : 3928 => Opcode::VSUBhq,
8459 0 : 3929 => Opcode::VSUBv16i8,
8460 0 : 3930 => Opcode::VSUBv1i64,
8461 0 : 3931 => Opcode::VSUBv2i32,
8462 0 : 3932 => Opcode::VSUBv2i64,
8463 0 : 3933 => Opcode::VSUBv4i16,
8464 0 : 3934 => Opcode::VSUBv4i32,
8465 0 : 3935 => Opcode::VSUBv8i16,
8466 0 : 3936 => Opcode::VSUBv8i8,
8467 0 : 3937 => Opcode::VSUDOTDI,
8468 0 : 3938 => Opcode::VSUDOTQI,
8469 0 : 3939 => Opcode::VSWPd,
8470 0 : 3940 => Opcode::VSWPq,
8471 0 : 3941 => Opcode::VTBL1,
8472 0 : 3942 => Opcode::VTBL2,
8473 0 : 3943 => Opcode::VTBL3,
8474 0 : 3944 => Opcode::VTBL3Pseudo,
8475 0 : 3945 => Opcode::VTBL4,
8476 0 : 3946 => Opcode::VTBL4Pseudo,
8477 0 : 3947 => Opcode::VTBX1,
8478 0 : 3948 => Opcode::VTBX2,
8479 0 : 3949 => Opcode::VTBX3,
8480 0 : 3950 => Opcode::VTBX3Pseudo,
8481 0 : 3951 => Opcode::VTBX4,
8482 0 : 3952 => Opcode::VTBX4Pseudo,
8483 0 : 3953 => Opcode::VTOSHD,
8484 0 : 3954 => Opcode::VTOSHH,
8485 0 : 3955 => Opcode::VTOSHS,
8486 0 : 3956 => Opcode::VTOSIRD,
8487 0 : 3957 => Opcode::VTOSIRH,
8488 0 : 3958 => Opcode::VTOSIRS,
8489 0 : 3959 => Opcode::VTOSIZD,
8490 0 : 3960 => Opcode::VTOSIZH,
8491 0 : 3961 => Opcode::VTOSIZS,
8492 0 : 3962 => Opcode::VTOSLD,
8493 0 : 3963 => Opcode::VTOSLH,
8494 0 : 3964 => Opcode::VTOSLS,
8495 0 : 3965 => Opcode::VTOUHD,
8496 0 : 3966 => Opcode::VTOUHH,
8497 0 : 3967 => Opcode::VTOUHS,
8498 0 : 3968 => Opcode::VTOUIRD,
8499 0 : 3969 => Opcode::VTOUIRH,
8500 0 : 3970 => Opcode::VTOUIRS,
8501 0 : 3971 => Opcode::VTOUIZD,
8502 0 : 3972 => Opcode::VTOUIZH,
8503 0 : 3973 => Opcode::VTOUIZS,
8504 0 : 3974 => Opcode::VTOULD,
8505 0 : 3975 => Opcode::VTOULH,
8506 0 : 3976 => Opcode::VTOULS,
8507 0 : 3977 => Opcode::VTRNd16,
8508 0 : 3978 => Opcode::VTRNd32,
8509 0 : 3979 => Opcode::VTRNd8,
8510 0 : 3980 => Opcode::VTRNq16,
8511 0 : 3981 => Opcode::VTRNq32,
8512 0 : 3982 => Opcode::VTRNq8,
8513 0 : 3983 => Opcode::VTSTv16i8,
8514 0 : 3984 => Opcode::VTSTv2i32,
8515 0 : 3985 => Opcode::VTSTv4i16,
8516 0 : 3986 => Opcode::VTSTv4i32,
8517 0 : 3987 => Opcode::VTSTv8i16,
8518 0 : 3988 => Opcode::VTSTv8i8,
8519 0 : 3989 => Opcode::VUDOTD,
8520 0 : 3990 => Opcode::VUDOTDI,
8521 0 : 3991 => Opcode::VUDOTQ,
8522 0 : 3992 => Opcode::VUDOTQI,
8523 0 : 3993 => Opcode::VUHTOD,
8524 0 : 3994 => Opcode::VUHTOH,
8525 0 : 3995 => Opcode::VUHTOS,
8526 0 : 3996 => Opcode::VUITOD,
8527 0 : 3997 => Opcode::VUITOH,
8528 0 : 3998 => Opcode::VUITOS,
8529 0 : 3999 => Opcode::VULTOD,
8530 0 : 4000 => Opcode::VULTOH,
8531 0 : 4001 => Opcode::VULTOS,
8532 0 : 4002 => Opcode::VUMMLA,
8533 0 : 4003 => Opcode::VUSDOTD,
8534 0 : 4004 => Opcode::VUSDOTDI,
8535 0 : 4005 => Opcode::VUSDOTQ,
8536 0 : 4006 => Opcode::VUSDOTQI,
8537 0 : 4007 => Opcode::VUSMMLA,
8538 0 : 4008 => Opcode::VUZPd16,
8539 0 : 4009 => Opcode::VUZPd8,
8540 0 : 4010 => Opcode::VUZPq16,
8541 0 : 4011 => Opcode::VUZPq32,
8542 0 : 4012 => Opcode::VUZPq8,
8543 0 : 4013 => Opcode::VZIPd16,
8544 0 : 4014 => Opcode::VZIPd8,
8545 0 : 4015 => Opcode::VZIPq16,
8546 0 : 4016 => Opcode::VZIPq32,
8547 0 : 4017 => Opcode::VZIPq8,
8548 0 : 4018 => Opcode::sysLDMDA,
8549 0 : 4019 => Opcode::sysLDMDA_UPD,
8550 0 : 4020 => Opcode::sysLDMDB,
8551 0 : 4021 => Opcode::sysLDMDB_UPD,
8552 0 : 4022 => Opcode::sysLDMIA,
8553 0 : 4023 => Opcode::sysLDMIA_UPD,
8554 0 : 4024 => Opcode::sysLDMIB,
8555 0 : 4025 => Opcode::sysLDMIB_UPD,
8556 0 : 4026 => Opcode::sysSTMDA,
8557 0 : 4027 => Opcode::sysSTMDA_UPD,
8558 0 : 4028 => Opcode::sysSTMDB,
8559 0 : 4029 => Opcode::sysSTMDB_UPD,
8560 0 : 4030 => Opcode::sysSTMIA,
8561 0 : 4031 => Opcode::sysSTMIA_UPD,
8562 0 : 4032 => Opcode::sysSTMIB,
8563 0 : 4033 => Opcode::sysSTMIB_UPD,
8564 0 : 4034 => Opcode::t2ADCri,
8565 0 : 4035 => Opcode::t2ADCrr,
8566 0 : 4036 => Opcode::t2ADCrs,
8567 0 : 4037 => Opcode::t2ADDri,
8568 0 : 4038 => Opcode::t2ADDri12,
8569 0 : 4039 => Opcode::t2ADDrr,
8570 0 : 4040 => Opcode::t2ADDrs,
8571 0 : 4041 => Opcode::t2ADDspImm,
8572 0 : 4042 => Opcode::t2ADDspImm12,
8573 0 : 4043 => Opcode::t2ADR,
8574 0 : 4044 => Opcode::t2ANDri,
8575 0 : 4045 => Opcode::t2ANDrr,
8576 0 : 4046 => Opcode::t2ANDrs,
8577 0 : 4047 => Opcode::t2ASRri,
8578 0 : 4048 => Opcode::t2ASRrr,
8579 0 : 4049 => Opcode::t2ASRs1,
8580 0 : 4050 => Opcode::t2AUT,
8581 0 : 4051 => Opcode::t2AUTG,
8582 0 : 4052 => Opcode::t2B,
8583 0 : 4053 => Opcode::t2BFC,
8584 0 : 4054 => Opcode::t2BFI,
8585 0 : 4055 => Opcode::t2BFLi,
8586 0 : 4056 => Opcode::t2BFLr,
8587 0 : 4057 => Opcode::t2BFi,
8588 0 : 4058 => Opcode::t2BFic,
8589 0 : 4059 => Opcode::t2BFr,
8590 0 : 4060 => Opcode::t2BICri,
8591 0 : 4061 => Opcode::t2BICrr,
8592 0 : 4062 => Opcode::t2BICrs,
8593 0 : 4063 => Opcode::t2BTI,
8594 0 : 4064 => Opcode::t2BXAUT,
8595 0 : 4065 => Opcode::t2BXJ,
8596 0 : 4066 => Opcode::t2Bcc,
8597 0 : 4067 => Opcode::t2CDP,
8598 0 : 4068 => Opcode::t2CDP2,
8599 0 : 4069 => Opcode::t2CLREX,
8600 0 : 4070 => Opcode::t2CLRM,
8601 0 : 4071 => Opcode::t2CLZ,
8602 0 : 4072 => Opcode::t2CMNri,
8603 0 : 4073 => Opcode::t2CMNzrr,
8604 0 : 4074 => Opcode::t2CMNzrs,
8605 0 : 4075 => Opcode::t2CMPri,
8606 0 : 4076 => Opcode::t2CMPrr,
8607 0 : 4077 => Opcode::t2CMPrs,
8608 0 : 4078 => Opcode::t2CPS1p,
8609 0 : 4079 => Opcode::t2CPS2p,
8610 0 : 4080 => Opcode::t2CPS3p,
8611 0 : 4081 => Opcode::t2CRC32B,
8612 0 : 4082 => Opcode::t2CRC32CB,
8613 0 : 4083 => Opcode::t2CRC32CH,
8614 0 : 4084 => Opcode::t2CRC32CW,
8615 0 : 4085 => Opcode::t2CRC32H,
8616 0 : 4086 => Opcode::t2CRC32W,
8617 0 : 4087 => Opcode::t2CSEL,
8618 0 : 4088 => Opcode::t2CSINC,
8619 0 : 4089 => Opcode::t2CSINV,
8620 0 : 4090 => Opcode::t2CSNEG,
8621 0 : 4091 => Opcode::t2DBG,
8622 0 : 4092 => Opcode::t2DCPS1,
8623 0 : 4093 => Opcode::t2DCPS2,
8624 0 : 4094 => Opcode::t2DCPS3,
8625 0 : 4095 => Opcode::t2DLS,
8626 0 : 4096 => Opcode::t2DMB,
8627 0 : 4097 => Opcode::t2DSB,
8628 0 : 4098 => Opcode::t2EORri,
8629 0 : 4099 => Opcode::t2EORrr,
8630 0 : 4100 => Opcode::t2EORrs,
8631 0 : 4101 => Opcode::t2HINT,
8632 0 : 4102 => Opcode::t2HVC,
8633 0 : 4103 => Opcode::t2ISB,
8634 0 : 4104 => Opcode::t2IT,
8635 0 : 4105 => Opcode::t2Int_eh_sjlj_setjmp,
8636 0 : 4106 => Opcode::t2Int_eh_sjlj_setjmp_nofp,
8637 0 : 4107 => Opcode::t2LDA,
8638 0 : 4108 => Opcode::t2LDAB,
8639 0 : 4109 => Opcode::t2LDAEX,
8640 0 : 4110 => Opcode::t2LDAEXB,
8641 0 : 4111 => Opcode::t2LDAEXD,
8642 0 : 4112 => Opcode::t2LDAEXH,
8643 0 : 4113 => Opcode::t2LDAH,
8644 0 : 4114 => Opcode::t2LDC2L_OFFSET,
8645 0 : 4115 => Opcode::t2LDC2L_OPTION,
8646 0 : 4116 => Opcode::t2LDC2L_POST,
8647 0 : 4117 => Opcode::t2LDC2L_PRE,
8648 0 : 4118 => Opcode::t2LDC2_OFFSET,
8649 0 : 4119 => Opcode::t2LDC2_OPTION,
8650 0 : 4120 => Opcode::t2LDC2_POST,
8651 0 : 4121 => Opcode::t2LDC2_PRE,
8652 0 : 4122 => Opcode::t2LDCL_OFFSET,
8653 0 : 4123 => Opcode::t2LDCL_OPTION,
8654 0 : 4124 => Opcode::t2LDCL_POST,
8655 0 : 4125 => Opcode::t2LDCL_PRE,
8656 0 : 4126 => Opcode::t2LDC_OFFSET,
8657 0 : 4127 => Opcode::t2LDC_OPTION,
8658 0 : 4128 => Opcode::t2LDC_POST,
8659 0 : 4129 => Opcode::t2LDC_PRE,
8660 0 : 4130 => Opcode::t2LDMDB,
8661 0 : 4131 => Opcode::t2LDMDB_UPD,
8662 0 : 4132 => Opcode::t2LDMIA,
8663 0 : 4133 => Opcode::t2LDMIA_UPD,
8664 0 : 4134 => Opcode::t2LDRBT,
8665 0 : 4135 => Opcode::t2LDRB_POST,
8666 0 : 4136 => Opcode::t2LDRB_PRE,
8667 0 : 4137 => Opcode::t2LDRBi12,
8668 0 : 4138 => Opcode::t2LDRBi8,
8669 0 : 4139 => Opcode::t2LDRBpci,
8670 0 : 4140 => Opcode::t2LDRBs,
8671 0 : 4141 => Opcode::t2LDRD_POST,
8672 0 : 4142 => Opcode::t2LDRD_PRE,
8673 0 : 4143 => Opcode::t2LDRDi8,
8674 0 : 4144 => Opcode::t2LDREX,
8675 0 : 4145 => Opcode::t2LDREXB,
8676 0 : 4146 => Opcode::t2LDREXD,
8677 0 : 4147 => Opcode::t2LDREXH,
8678 0 : 4148 => Opcode::t2LDRHT,
8679 0 : 4149 => Opcode::t2LDRH_POST,
8680 0 : 4150 => Opcode::t2LDRH_PRE,
8681 0 : 4151 => Opcode::t2LDRHi12,
8682 0 : 4152 => Opcode::t2LDRHi8,
8683 0 : 4153 => Opcode::t2LDRHpci,
8684 0 : 4154 => Opcode::t2LDRHs,
8685 0 : 4155 => Opcode::t2LDRSBT,
8686 0 : 4156 => Opcode::t2LDRSB_POST,
8687 0 : 4157 => Opcode::t2LDRSB_PRE,
8688 0 : 4158 => Opcode::t2LDRSBi12,
8689 0 : 4159 => Opcode::t2LDRSBi8,
8690 0 : 4160 => Opcode::t2LDRSBpci,
8691 0 : 4161 => Opcode::t2LDRSBs,
8692 0 : 4162 => Opcode::t2LDRSHT,
8693 0 : 4163 => Opcode::t2LDRSH_POST,
8694 0 : 4164 => Opcode::t2LDRSH_PRE,
8695 0 : 4165 => Opcode::t2LDRSHi12,
8696 0 : 4166 => Opcode::t2LDRSHi8,
8697 0 : 4167 => Opcode::t2LDRSHpci,
8698 0 : 4168 => Opcode::t2LDRSHs,
8699 0 : 4169 => Opcode::t2LDRT,
8700 0 : 4170 => Opcode::t2LDR_POST,
8701 0 : 4171 => Opcode::t2LDR_PRE,
8702 0 : 4172 => Opcode::t2LDRi12,
8703 0 : 4173 => Opcode::t2LDRi8,
8704 0 : 4174 => Opcode::t2LDRpci,
8705 0 : 4175 => Opcode::t2LDRs,
8706 0 : 4176 => Opcode::t2LE,
8707 0 : 4177 => Opcode::t2LEUpdate,
8708 0 : 4178 => Opcode::t2LSLri,
8709 0 : 4179 => Opcode::t2LSLrr,
8710 0 : 4180 => Opcode::t2LSRri,
8711 0 : 4181 => Opcode::t2LSRrr,
8712 0 : 4182 => Opcode::t2LSRs1,
8713 0 : 4183 => Opcode::t2MCR,
8714 0 : 4184 => Opcode::t2MCR2,
8715 0 : 4185 => Opcode::t2MCRR,
8716 0 : 4186 => Opcode::t2MCRR2,
8717 0 : 4187 => Opcode::t2MLA,
8718 0 : 4188 => Opcode::t2MLS,
8719 0 : 4189 => Opcode::t2MOVTi16,
8720 0 : 4190 => Opcode::t2MOVi,
8721 0 : 4191 => Opcode::t2MOVi16,
8722 0 : 4192 => Opcode::t2MOVr,
8723 0 : 4193 => Opcode::t2MRC,
8724 0 : 4194 => Opcode::t2MRC2,
8725 0 : 4195 => Opcode::t2MRRC,
8726 0 : 4196 => Opcode::t2MRRC2,
8727 0 : 4197 => Opcode::t2MRS_AR,
8728 0 : 4198 => Opcode::t2MRS_M,
8729 0 : 4199 => Opcode::t2MRSbanked,
8730 0 : 4200 => Opcode::t2MRSsys_AR,
8731 0 : 4201 => Opcode::t2MSR_AR,
8732 0 : 4202 => Opcode::t2MSR_M,
8733 0 : 4203 => Opcode::t2MSRbanked,
8734 0 : 4204 => Opcode::t2MUL,
8735 0 : 4205 => Opcode::t2MVNi,
8736 0 : 4206 => Opcode::t2MVNr,
8737 0 : 4207 => Opcode::t2MVNs,
8738 0 : 4208 => Opcode::t2ORNri,
8739 0 : 4209 => Opcode::t2ORNrr,
8740 0 : 4210 => Opcode::t2ORNrs,
8741 0 : 4211 => Opcode::t2ORRri,
8742 0 : 4212 => Opcode::t2ORRrr,
8743 0 : 4213 => Opcode::t2ORRrs,
8744 0 : 4214 => Opcode::t2PAC,
8745 0 : 4215 => Opcode::t2PACBTI,
8746 0 : 4216 => Opcode::t2PACG,
8747 0 : 4217 => Opcode::t2PKHBT,
8748 0 : 4218 => Opcode::t2PKHTB,
8749 0 : 4219 => Opcode::t2PLDWi12,
8750 0 : 4220 => Opcode::t2PLDWi8,
8751 0 : 4221 => Opcode::t2PLDWs,
8752 0 : 4222 => Opcode::t2PLDi12,
8753 0 : 4223 => Opcode::t2PLDi8,
8754 0 : 4224 => Opcode::t2PLDpci,
8755 0 : 4225 => Opcode::t2PLDs,
8756 0 : 4226 => Opcode::t2PLIi12,
8757 0 : 4227 => Opcode::t2PLIi8,
8758 0 : 4228 => Opcode::t2PLIpci,
8759 0 : 4229 => Opcode::t2PLIs,
8760 0 : 4230 => Opcode::t2QADD,
8761 0 : 4231 => Opcode::t2QADD16,
8762 0 : 4232 => Opcode::t2QADD8,
8763 0 : 4233 => Opcode::t2QASX,
8764 0 : 4234 => Opcode::t2QDADD,
8765 0 : 4235 => Opcode::t2QDSUB,
8766 0 : 4236 => Opcode::t2QSAX,
8767 0 : 4237 => Opcode::t2QSUB,
8768 0 : 4238 => Opcode::t2QSUB16,
8769 0 : 4239 => Opcode::t2QSUB8,
8770 0 : 4240 => Opcode::t2RBIT,
8771 0 : 4241 => Opcode::t2REV,
8772 0 : 4242 => Opcode::t2REV16,
8773 0 : 4243 => Opcode::t2REVSH,
8774 0 : 4244 => Opcode::t2RFEDB,
8775 0 : 4245 => Opcode::t2RFEDBW,
8776 0 : 4246 => Opcode::t2RFEIA,
8777 0 : 4247 => Opcode::t2RFEIAW,
8778 0 : 4248 => Opcode::t2RORri,
8779 0 : 4249 => Opcode::t2RORrr,
8780 0 : 4250 => Opcode::t2RRX,
8781 0 : 4251 => Opcode::t2RSBri,
8782 0 : 4252 => Opcode::t2RSBrr,
8783 0 : 4253 => Opcode::t2RSBrs,
8784 0 : 4254 => Opcode::t2SADD16,
8785 0 : 4255 => Opcode::t2SADD8,
8786 0 : 4256 => Opcode::t2SASX,
8787 0 : 4257 => Opcode::t2SB,
8788 0 : 4258 => Opcode::t2SBCri,
8789 0 : 4259 => Opcode::t2SBCrr,
8790 0 : 4260 => Opcode::t2SBCrs,
8791 0 : 4261 => Opcode::t2SBFX,
8792 0 : 4262 => Opcode::t2SDIV,
8793 0 : 4263 => Opcode::t2SEL,
8794 0 : 4264 => Opcode::t2SETPAN,
8795 0 : 4265 => Opcode::t2SG,
8796 0 : 4266 => Opcode::t2SHADD16,
8797 0 : 4267 => Opcode::t2SHADD8,
8798 0 : 4268 => Opcode::t2SHASX,
8799 0 : 4269 => Opcode::t2SHSAX,
8800 0 : 4270 => Opcode::t2SHSUB16,
8801 0 : 4271 => Opcode::t2SHSUB8,
8802 0 : 4272 => Opcode::t2SMC,
8803 0 : 4273 => Opcode::t2SMLABB,
8804 0 : 4274 => Opcode::t2SMLABT,
8805 0 : 4275 => Opcode::t2SMLAD,
8806 0 : 4276 => Opcode::t2SMLADX,
8807 0 : 4277 => Opcode::t2SMLAL,
8808 0 : 4278 => Opcode::t2SMLALBB,
8809 0 : 4279 => Opcode::t2SMLALBT,
8810 0 : 4280 => Opcode::t2SMLALD,
8811 0 : 4281 => Opcode::t2SMLALDX,
8812 0 : 4282 => Opcode::t2SMLALTB,
8813 0 : 4283 => Opcode::t2SMLALTT,
8814 0 : 4284 => Opcode::t2SMLATB,
8815 0 : 4285 => Opcode::t2SMLATT,
8816 0 : 4286 => Opcode::t2SMLAWB,
8817 0 : 4287 => Opcode::t2SMLAWT,
8818 0 : 4288 => Opcode::t2SMLSD,
8819 0 : 4289 => Opcode::t2SMLSDX,
8820 0 : 4290 => Opcode::t2SMLSLD,
8821 0 : 4291 => Opcode::t2SMLSLDX,
8822 0 : 4292 => Opcode::t2SMMLA,
8823 0 : 4293 => Opcode::t2SMMLAR,
8824 0 : 4294 => Opcode::t2SMMLS,
8825 0 : 4295 => Opcode::t2SMMLSR,
8826 0 : 4296 => Opcode::t2SMMUL,
8827 0 : 4297 => Opcode::t2SMMULR,
8828 0 : 4298 => Opcode::t2SMUAD,
8829 0 : 4299 => Opcode::t2SMUADX,
8830 0 : 4300 => Opcode::t2SMULBB,
8831 0 : 4301 => Opcode::t2SMULBT,
8832 0 : 4302 => Opcode::t2SMULL,
8833 0 : 4303 => Opcode::t2SMULTB,
8834 0 : 4304 => Opcode::t2SMULTT,
8835 0 : 4305 => Opcode::t2SMULWB,
8836 0 : 4306 => Opcode::t2SMULWT,
8837 0 : 4307 => Opcode::t2SMUSD,
8838 0 : 4308 => Opcode::t2SMUSDX,
8839 0 : 4309 => Opcode::t2SRSDB,
8840 0 : 4310 => Opcode::t2SRSDB_UPD,
8841 0 : 4311 => Opcode::t2SRSIA,
8842 0 : 4312 => Opcode::t2SRSIA_UPD,
8843 0 : 4313 => Opcode::t2SSAT,
8844 0 : 4314 => Opcode::t2SSAT16,
8845 0 : 4315 => Opcode::t2SSAX,
8846 0 : 4316 => Opcode::t2SSUB16,
8847 0 : 4317 => Opcode::t2SSUB8,
8848 0 : 4318 => Opcode::t2STC2L_OFFSET,
8849 0 : 4319 => Opcode::t2STC2L_OPTION,
8850 0 : 4320 => Opcode::t2STC2L_POST,
8851 0 : 4321 => Opcode::t2STC2L_PRE,
8852 0 : 4322 => Opcode::t2STC2_OFFSET,
8853 0 : 4323 => Opcode::t2STC2_OPTION,
8854 0 : 4324 => Opcode::t2STC2_POST,
8855 0 : 4325 => Opcode::t2STC2_PRE,
8856 0 : 4326 => Opcode::t2STCL_OFFSET,
8857 0 : 4327 => Opcode::t2STCL_OPTION,
8858 0 : 4328 => Opcode::t2STCL_POST,
8859 0 : 4329 => Opcode::t2STCL_PRE,
8860 0 : 4330 => Opcode::t2STC_OFFSET,
8861 0 : 4331 => Opcode::t2STC_OPTION,
8862 0 : 4332 => Opcode::t2STC_POST,
8863 0 : 4333 => Opcode::t2STC_PRE,
8864 0 : 4334 => Opcode::t2STL,
8865 0 : 4335 => Opcode::t2STLB,
8866 0 : 4336 => Opcode::t2STLEX,
8867 0 : 4337 => Opcode::t2STLEXB,
8868 0 : 4338 => Opcode::t2STLEXD,
8869 0 : 4339 => Opcode::t2STLEXH,
8870 0 : 4340 => Opcode::t2STLH,
8871 0 : 4341 => Opcode::t2STMDB,
8872 0 : 4342 => Opcode::t2STMDB_UPD,
8873 0 : 4343 => Opcode::t2STMIA,
8874 0 : 4344 => Opcode::t2STMIA_UPD,
8875 0 : 4345 => Opcode::t2STRBT,
8876 0 : 4346 => Opcode::t2STRB_POST,
8877 0 : 4347 => Opcode::t2STRB_PRE,
8878 0 : 4348 => Opcode::t2STRBi12,
8879 0 : 4349 => Opcode::t2STRBi8,
8880 0 : 4350 => Opcode::t2STRBs,
8881 0 : 4351 => Opcode::t2STRD_POST,
8882 0 : 4352 => Opcode::t2STRD_PRE,
8883 0 : 4353 => Opcode::t2STRDi8,
8884 0 : 4354 => Opcode::t2STREX,
8885 0 : 4355 => Opcode::t2STREXB,
8886 0 : 4356 => Opcode::t2STREXD,
8887 0 : 4357 => Opcode::t2STREXH,
8888 0 : 4358 => Opcode::t2STRHT,
8889 0 : 4359 => Opcode::t2STRH_POST,
8890 0 : 4360 => Opcode::t2STRH_PRE,
8891 0 : 4361 => Opcode::t2STRHi12,
8892 0 : 4362 => Opcode::t2STRHi8,
8893 0 : 4363 => Opcode::t2STRHs,
8894 0 : 4364 => Opcode::t2STRT,
8895 0 : 4365 => Opcode::t2STR_POST,
8896 0 : 4366 => Opcode::t2STR_PRE,
8897 0 : 4367 => Opcode::t2STRi12,
8898 0 : 4368 => Opcode::t2STRi8,
8899 0 : 4369 => Opcode::t2STRs,
8900 0 : 4370 => Opcode::t2SUBS_PC_LR,
8901 0 : 4371 => Opcode::t2SUBri,
8902 0 : 4372 => Opcode::t2SUBri12,
8903 0 : 4373 => Opcode::t2SUBrr,
8904 0 : 4374 => Opcode::t2SUBrs,
8905 0 : 4375 => Opcode::t2SUBspImm,
8906 0 : 4376 => Opcode::t2SUBspImm12,
8907 0 : 4377 => Opcode::t2SXTAB,
8908 0 : 4378 => Opcode::t2SXTAB16,
8909 0 : 4379 => Opcode::t2SXTAH,
8910 0 : 4380 => Opcode::t2SXTB,
8911 0 : 4381 => Opcode::t2SXTB16,
8912 0 : 4382 => Opcode::t2SXTH,
8913 0 : 4383 => Opcode::t2TBB,
8914 0 : 4384 => Opcode::t2TBH,
8915 0 : 4385 => Opcode::t2TEQri,
8916 0 : 4386 => Opcode::t2TEQrr,
8917 0 : 4387 => Opcode::t2TEQrs,
8918 0 : 4388 => Opcode::t2TSB,
8919 0 : 4389 => Opcode::t2TSTri,
8920 0 : 4390 => Opcode::t2TSTrr,
8921 0 : 4391 => Opcode::t2TSTrs,
8922 0 : 4392 => Opcode::t2TT,
8923 0 : 4393 => Opcode::t2TTA,
8924 0 : 4394 => Opcode::t2TTAT,
8925 0 : 4395 => Opcode::t2TTT,
8926 0 : 4396 => Opcode::t2UADD16,
8927 0 : 4397 => Opcode::t2UADD8,
8928 0 : 4398 => Opcode::t2UASX,
8929 0 : 4399 => Opcode::t2UBFX,
8930 0 : 4400 => Opcode::t2UDF,
8931 0 : 4401 => Opcode::t2UDIV,
8932 0 : 4402 => Opcode::t2UHADD16,
8933 0 : 4403 => Opcode::t2UHADD8,
8934 0 : 4404 => Opcode::t2UHASX,
8935 0 : 4405 => Opcode::t2UHSAX,
8936 0 : 4406 => Opcode::t2UHSUB16,
8937 0 : 4407 => Opcode::t2UHSUB8,
8938 0 : 4408 => Opcode::t2UMAAL,
8939 0 : 4409 => Opcode::t2UMLAL,
8940 0 : 4410 => Opcode::t2UMULL,
8941 0 : 4411 => Opcode::t2UQADD16,
8942 0 : 4412 => Opcode::t2UQADD8,
8943 0 : 4413 => Opcode::t2UQASX,
8944 0 : 4414 => Opcode::t2UQSAX,
8945 0 : 4415 => Opcode::t2UQSUB16,
8946 0 : 4416 => Opcode::t2UQSUB8,
8947 0 : 4417 => Opcode::t2USAD8,
8948 0 : 4418 => Opcode::t2USADA8,
8949 0 : 4419 => Opcode::t2USAT,
8950 0 : 4420 => Opcode::t2USAT16,
8951 0 : 4421 => Opcode::t2USAX,
8952 0 : 4422 => Opcode::t2USUB16,
8953 0 : 4423 => Opcode::t2USUB8,
8954 0 : 4424 => Opcode::t2UXTAB,
8955 0 : 4425 => Opcode::t2UXTAB16,
8956 0 : 4426 => Opcode::t2UXTAH,
8957 0 : 4427 => Opcode::t2UXTB,
8958 0 : 4428 => Opcode::t2UXTB16,
8959 0 : 4429 => Opcode::t2UXTH,
8960 0 : 4430 => Opcode::t2WLS,
8961 0 : 4431 => Opcode::tADC,
8962 0 : 4432 => Opcode::tADDhirr,
8963 0 : 4433 => Opcode::tADDi3,
8964 0 : 4434 => Opcode::tADDi8,
8965 0 : 4435 => Opcode::tADDrSP,
8966 0 : 4436 => Opcode::tADDrSPi,
8967 0 : 4437 => Opcode::tADDrr,
8968 0 : 4438 => Opcode::tADDspi,
8969 0 : 4439 => Opcode::tADDspr,
8970 0 : 4440 => Opcode::tADR,
8971 0 : 4441 => Opcode::tAND,
8972 0 : 4442 => Opcode::tASRri,
8973 0 : 4443 => Opcode::tASRrr,
8974 0 : 4444 => Opcode::tB,
8975 0 : 4445 => Opcode::tBIC,
8976 0 : 4446 => Opcode::tBKPT,
8977 0 : 4447 => Opcode::tBL,
8978 0 : 4448 => Opcode::tBLXNSr,
8979 0 : 4449 => Opcode::tBLXi,
8980 0 : 4450 => Opcode::tBLXr,
8981 0 : 4451 => Opcode::tBX,
8982 0 : 4452 => Opcode::tBXNS,
8983 0 : 4453 => Opcode::tBcc,
8984 0 : 4454 => Opcode::tCBNZ,
8985 0 : 4455 => Opcode::tCBZ,
8986 0 : 4456 => Opcode::tCMNz,
8987 0 : 4457 => Opcode::tCMPhir,
8988 0 : 4458 => Opcode::tCMPi8,
8989 0 : 4459 => Opcode::tCMPr,
8990 0 : 4460 => Opcode::tCPS,
8991 0 : 4461 => Opcode::tEOR,
8992 0 : 4462 => Opcode::tHINT,
8993 0 : 4463 => Opcode::tHLT,
8994 0 : 4464 => Opcode::tInt_WIN_eh_sjlj_longjmp,
8995 0 : 4465 => Opcode::tInt_eh_sjlj_longjmp,
8996 0 : 4466 => Opcode::tInt_eh_sjlj_setjmp,
8997 0 : 4467 => Opcode::tLDMIA,
8998 0 : 4468 => Opcode::tLDRBi,
8999 0 : 4469 => Opcode::tLDRBr,
9000 0 : 4470 => Opcode::tLDRHi,
9001 0 : 4471 => Opcode::tLDRHr,
9002 0 : 4472 => Opcode::tLDRSB,
9003 0 : 4473 => Opcode::tLDRSH,
9004 0 : 4474 => Opcode::tLDRi,
9005 0 : 4475 => Opcode::tLDRpci,
9006 0 : 4476 => Opcode::tLDRr,
9007 0 : 4477 => Opcode::tLDRspi,
9008 0 : 4478 => Opcode::tLSLri,
9009 0 : 4479 => Opcode::tLSLrr,
9010 0 : 4480 => Opcode::tLSRri,
9011 0 : 4481 => Opcode::tLSRrr,
9012 0 : 4482 => Opcode::tMOVSr,
9013 0 : 4483 => Opcode::tMOVi8,
9014 0 : 4484 => Opcode::tMOVr,
9015 0 : 4485 => Opcode::tMUL,
9016 0 : 4486 => Opcode::tMVN,
9017 0 : 4487 => Opcode::tORR,
9018 0 : 4488 => Opcode::tPICADD,
9019 0 : 4489 => Opcode::tPOP,
9020 0 : 4490 => Opcode::tPUSH,
9021 0 : 4491 => Opcode::tREV,
9022 0 : 4492 => Opcode::tREV16,
9023 0 : 4493 => Opcode::tREVSH,
9024 0 : 4494 => Opcode::tROR,
9025 0 : 4495 => Opcode::tRSB,
9026 0 : 4496 => Opcode::tSBC,
9027 0 : 4497 => Opcode::tSETEND,
9028 0 : 4498 => Opcode::tSTMIA_UPD,
9029 0 : 4499 => Opcode::tSTRBi,
9030 0 : 4500 => Opcode::tSTRBr,
9031 0 : 4501 => Opcode::tSTRHi,
9032 0 : 4502 => Opcode::tSTRHr,
9033 0 : 4503 => Opcode::tSTRi,
9034 0 : 4504 => Opcode::tSTRr,
9035 0 : 4505 => Opcode::tSTRspi,
9036 0 : 4506 => Opcode::tSUBi3,
9037 0 : 4507 => Opcode::tSUBi8,
9038 0 : 4508 => Opcode::tSUBrr,
9039 0 : 4509 => Opcode::tSUBspi,
9040 0 : 4510 => Opcode::tSVC,
9041 0 : 4511 => Opcode::tSXTB,
9042 0 : 4512 => Opcode::tSXTH,
9043 0 : 4513 => Opcode::tTRAP,
9044 0 : 4514 => Opcode::tTST,
9045 0 : 4515 => Opcode::tUDF,
9046 0 : 4516 => Opcode::tUXTB,
9047 0 : 4517 => Opcode::tUXTH,
9048 0 : 4518 => Opcode::t__brkdiv0,
9049 0 : 4519 => Opcode::INSTRUCTION_LIST_END,
9050 0 : _ => Opcode::UNKNOWN(value),
9051 : }
9052 0 : }
9053 : }
|
